ANALOG DEVICES AD9549 Service Manual
Dual Input Network Clock
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FEATURES
Flexible reference inputs
Input frequencies: 8 kHz to 750 MHz
Two reference inputs
Loss of reference indicators
Auto and manual holdover modes
Auto and manual switchover modes
Smooth A-to-B phase transition on outputs
Excellent stability in holdover mode
Programmable 16 + 1-bit input divider, R
Differential HSTL clock output
Output frequencies to 750 MHz
Low jitter clock doubler for frequencies > 400 MHz
Single-ended CMOS output for frequencies < 150 MHz
Programmable digital loop filter (< 1 Hz to ~100 kHz)
High speed digitally controlled oscillator (DCO) core
DDS with integrated 14-bit DAC
Excellent dynamic performance
Programmable 16 + 1-bit feedback divider, S
Software controlled power-down
64-lead LFCSP package
Generator/Synchronizer
AD9549
APPLICATIONS
Network synchronization
Reference clock jitter cleanup
SONET/SDH clocks up to OC-192, including FEC
Stratum 3/3E reference clocks
Wireless base stations, controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9549 provides synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9549 generates an output clock, synchronized to one of two
external input references. The external references may contain
significant time jitter, also specified as phase noise. Using a
digitally controlled loop and holdover circuitry, the AD9549
continues to generate a clean (low jitter), valid output clock
during a loss of reference condition, even when both references
have failed.
The AD9549 operates over an industrial temperature range of
−40°C t
o +85°C.
REFA_IN
REFB_IN
AD9549
REFERENCE
MONITORS
AND
SWITCHING
SERIAL PORT,
I/O LOGIC
DIGITAL INTERFACE
DIGITAL PLL
R
R, S DIVIDERS
HOLDOVER
SYSTEM CLOCK
MULTIPLIER
Figure 1. Basic Block Diagram
FDBK_IN
DAC_OUT
CLOCK
OUTPUT
DRIVERS
S1 TO S4
FILTER
OUT
OUT_CMOS
06744-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
AD9549
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TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 5
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 12
Input/Output Termination Recommendations.......................... 15
Theory of Operation ...................................................................... 16
Overview...................................................................................... 16
PLL Core (DPLLC)..................................................................... 16
Phase Detector ............................................................................ 20
Digital Loop Filter Coefficients ................................................21
Closed-Loop Phase Offset......................................................... 22
Lock Detection............................................................................23
Reference Monitors.................................................................... 24
Reference Switchover................................................................. 25
Holdover ...................................................................................... 27
Output Frequency Range Control............................................ 30
Reconstruction Filter ................................................................. 30
FDBK Inputs ............................................................................... 30
Reference Inputs......................................................................... 31
SYSCLK Inputs ........................................................................... 31
Harmonic Spur Reduction........................................................ 33
Output Clock Drivers and 2× Frequency Multiplier............. 34
Frequency Slew Limiter............................................................. 35
Frequency Estimator.................................................................. 35
Status and Warnings .................................................................. 36
Thermal Performance.................................................................... 39
AD9549 Power-Up......................................................................... 40
Power-On Reset .......................................................................... 40
Programming Sequence ............................................................ 40
Power Supply Partitioning............................................................. 41
3.3 V Supplies.............................................................................. 41
1.8 V Supplies.............................................................................. 41
Serial Control Port ......................................................................... 42
Serial Control Port Pin Descriptions ....................................... 42
Operation of Serial Control Port.............................................. 42
The Instruction Word (16 Bits) ................................................ 43
MSB/LSB First Transfers ........................................................... 43
I/O Register Map............................................................................ 46
I/O Register Description ............................................................... 51
Serial Port Configuration (Reg 0000 to Reg 0005) ................ 51
Power-Down and Reset (Reg 0010 to Reg 0013) ................... 51
System Clock (Reg 0020 to Reg 0023)..................................... 52
Digital PLL Control and Dividers (Reg 0100 to Reg 0130).. 53
Free-Run (Single-Tone) Mode (Reg 01A0 to Reg 01AD)..... 55
Reference Selector/Holdover (Reg 01C0 to Reg 01C3)......... 56
Doubler and Output Drivers (Reg 0200 to Reg 0201)........... 57
Monitor (Reg 0300 to Reg 0335) .............................................. 57
Calibration (User-Accessible Trim) (Reg 0400 to Reg 0410) 61
Harmonic Spur Reduction (Reg 0500 to Reg 0509).............. 62
Sample Application Circuit........................................................... 64
Outline Dimensions ....................................................................... 65
Ordering Guide .......................................................................... 65
REVISION HISTORY
8/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 68
AD9549
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SPECIFICATIONS
DC SPECIFICATIONS
Unless otherwise noted, AVDD = 1.8 V ± 5%, AVDD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%. AVSS = 0 V,
DVSS = 0 V.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY VOLTAGE
DVDD_I/O (Pin 1) 3.135 3.30 3.465 V
DVDD (Pin 3, Pin 5, Pin 7) 1.71 1.80 1.89 V
AVDD3 (Pin 14, Pin 46, Pin 47, Pin 49) 3.135 3.30 3.465 V
AVDD3 (Pin 37) 1.71 3.30 3.465 V Pin 37 is typically 3.3 V, but can be set to 1.8 V
AVDD (Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29,
Pin 30, Pin 36, Pin 42, Pin 44, Pin 45, Pin 53)
SUPPLY CURRENT
I
(Pin 14) 4.7 5.6 mA REFA, REFB buffers
AVDD3
I
(Pin 37) 3.8 4.5 mA CMOS output clock driver at 3.3 V
AVDD3
I
(Pin 46, Pin 47, Pin 49) 26 29 mA DAC output current source, fS = 1 GSPS
AVDD3
I
(Pin 36, Pin 42) 21 26 mA FDBK in, HSTL output clock driver (output
AVDD
I
(Pin 11) 12 15 mA REFA and REFB input buffer 1.8 V supply
AVDD
I
(Pin 19, Pin 23 to Pin 26, Pin 29,
AVDD
Pin 30, Pin 44, Pin 45)
I
(Pin 53) 41 49 mA DAC power supply
AVDD
I
(Pin 3, Pin 5, Pin 7) 254 265 mA Digital core
DVDD
I
(Pin 1) 4 6 mA Digital I/O (varies dynamically)
DVDD_I/O
LOGIC INPUTS (Except Pin 32) Pin 56 to Pin 61, Pin 64, Pin 9, Pin 10,
Input High Voltage (VIH) 2.0 DVDD_I/O V
Input Low Voltage (VIL) DVSS 0.8 V
Input Current (I
, I
) ±60 ±200 µA At VIN = 0 V and VIN = DVDD_I/O
INH
INL
Maximum Input Capacitance (CIN) 3 pF
CLKMODESEL (Pin 32) LOGIC INPUT Pin 32 only
Input High Voltage (VIH) 1.4 AVDD V
Input Low Voltage (VIL) AVSS 0.4 V
Input Current (I
, I
) −18 −50 µA At VIN = 0 V and VIN = AVDD
INH
INL
Maximum Input Capacitance (CIN) 3 pF
LOGIC OUTPUTS Pin 62 and bidirectional Pin 9, Pin 10,
Output High Voltage (VOH) 2.7 DVDD V IOH = 1 mA
Output Low Voltage (VOL) DVSS 0.4 V IOL = 1 mA
REFERENCE INPUTS Pin 12, Pin 13, Pin 15, Pin 16
Input Capacitance 3 pF
Input Resistance 8.5 11.5 14.5 kΩ Differential at Register 40F[1:0] = 00
Differential Operation
Common Mode Input Voltage1
(Applicable When DC-Coupled)
Differential Input Voltage Swing
1
Single-Ended Operation Register 040F[1:0] = 10
Input Voltage High (VIH) 2.0 AVDD3 V
Input Voltage Low (VIL) AVSS 0.8 V
Threshold Voltage AVDD3 −
Input Current 1 mA Single-ended operation
1.71 1.80 1.89 V
doubler turned on.)
194 255 mA Aggregate analog supply, including
system clock PLL
Pin 54, Pin 55, Pin 63
Pin 54, Pin 55, and Pin 63
1.5 AVDD3 −
0.2
V Differential operation; note that LVDS
signals must be ac-coupled
500 mV p-p Differential operation
0.66
AVDD3 −
0.82
AVDD3 −
0.98
V Register 040F[1:0] = 10 (other settings
possible)
Rev. 0 | Page 3 of 68
AD9549
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Parameter Min Typ Max Unit Test Conditions/Comments
FDBK INPUT Pin 40, Pin 41
Input Capacitance 3 pF
Input Resistance 18 22 26 kΩ Differential
Differential Input Voltage Swing
SYSTEM CLOCK INPUT System clock inputs should always be ac-
SYSCLK PLL Bypassed
Input Capacitance 1.5 pF Single-ended, each pin
Input Resistance 2.4 2.6 2.8 kΩ Differential
Internally Generated DC Bias Voltage
Differential Input Voltage Swing
SYSCLK PLL Enabled
Input Capacitance 3 pF Single-ended, each pin
Input Resistance 2.4 2.6 2.8 kΩ Differential
Internally Generated DC Bias Voltage
Differential Input Voltage Swing
Crystal Resonator with SYSCLK PLL Enabled
Motional Resistance 9 100 Ω 25 MHz, 3.2 mm × 2.5 mm AT cut
CLOCK OUTPUT DRIVERS
HSTL Output Driver
Differential Output Voltage Swing
Common-Mode Output Voltage
CMOS Output Driver
Output Voltage High (VOH) AVDDX = 3.3 V 2.7 V IOH = 1 mA.
Output Voltage Low (VOL) AVDDX = 3.3 V 0.4 V IOL = 1 mA.
Output Voltage High (VOH) AVDDX = 1.8 V 1.4 V IOH = 1 mA.
Output Voltage Low (VOL) AVDDX = 1.8 V 0.4 V IOL = 1 mA.
TOTAL POWER DISSIPATION
All Blocks Running 1010 1250 mW Worst case over supply, temperature,
Power-Down Mode 24 mW Using either the Power-Down and Enable
Digital Power-Down Mode 515 650 mW
Default with SYSCLK PLL Enabled 905 1100 mW After reset or power up with fS = 1 GHz,
Default with SYSCLK PLL Disabled 895 1056 mW After reset or power up with fS = 1 GHz,
With REFA or REFB Power-Down 1046 mW One reference still powered up
With HSTL Clock Driver Power-Down 1036 mW
With CMOS Clock Driver Power-Down 1048 mW
1
Must be ≤ 0 V relative to AVDD3 (Pin 14) and ≥ 0 V relative to AVSS (Pin 33, Pin 43).
2
Relative to AVSS (Pin 33, Pin 43).
3
Must be ≤ 0 V relative to AVDD (Pin 36) and ≥ 0 V relative to AVSS (Pin 33, Pin 43).
2
225 mV p-p −12 dBm into 50 Ω; must be ac-coupled
coupled (both single-ended and differential)
2
3
2
3
0.93 1.17 1.38 V
632 mV p-p 0 dBm into 50 Ω
0.93 1.17 1.38 V
632 mV p-p 0 dBm into 50 Ω
1080 1280 1480 mV
Output driver static, see
Figure 12 for
output swing vs. frequency
2
0.7 0.88 1.06 V
Output driver static, see
Figure 14 for
output swing vs. frequency
process
register or PWRDOWN pin
S4 = 0, S1 to S3 = 1, f
SYSCLK
= 25MHz
S1 to S4 = 1
Rev. 0 | Page 4 of 68
AD9549
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AC SPECIFICATIONS
Unless otherwise noted, fS = 1 GHz. DAC R
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
REFERENCE INPUTS Pin 12, Pin 13, Pin 15, Pin 16
Frequency Range (Sine Wave) 10 750 MHz Minimum recommended slew rate: 40 V/s
Frequency Range (CMOS) 0.008 50 MHz
Frequency Range (LVPECL) 0.008 725 MHz
Frequency Range (LVDS) 0.008 725 MHz LVDS must be ac-coupled; lower frequency bound may
Minimum Slew Rate 0.04 V/ns
Minimum Pulse Width High 620 ps
Minimum Pulse Width Low 620 ps
FDBK INPUT Pin 40, Pin 41
Input Frequency Range 10 400 MHz
Minimum Differential Input Level 225 mV p-p −12 dBm into 50 Ω; must be ac-coupled
Minimum Slew Rate 40 V/s
SYSTEM CLOCK INPUT Pin 27, Pin 28
SYSCLK PLL Bypassed
Input Frequency Range 250 1000 MHz Maximum f
Duty Cycle 45 55 %
Minimum Differential Input Level 632 mV p-p 0 dBm into 50 Ω
SYSCLK PLL Enabled
VCO Frequency Range, Low Band 700 810 MHz When in the range, use the low VCO band exclusively
VCO Frequency Range, Auto Band 810 900 MHz When in the range, use the VCO Auto band select
VCO Frequency Range, High Band 900 1000 MHz When in the range, use the high VCO band exclusively
Maximum Input Rate of System Clock
PFD
Without SYSCLK PLL Doubler
Input Frequency Range 11 200 MHz
Multiplication Range 4 66 Integer multiples of 2, maximum PFD rate and system
Minimum Differential Input Level 632 mV p-p 0 dBm into 50 Ω
With SYSCLK PLL Doubler
Input Frequency Range 6 100 MHz
Multiplication Range 8 132 Integer multiples of 8
Input Duty Cycle 50 % Deviating from 50% duty cycle may adversely affect
Minimum Differential Input Level 632 mV p-p 0 dBm into 50 Ω
Crystal Resonator with SYSCLK PLL
Enabled
Crystal Resonator Frequency Range 10 50 MHz AT cut, fundamental mode resonator
Maximum Crystal Motional Resistance 100 Ω
CLOCK DRIVERS
HSTL Output Driver
Frequency Range 20 725 MHz
Duty Cycle 48 52 %
Rise/Fall Time (20-80%) 115 165 ps 100 Ω termination across OUT/OUTB, 2 pF load
Jitter (12 kHz to 20 MHz) 1.0 ps fIN = 19.44 MHz, f
HSTL Output Driver with 2× Multiplier
Frequency Range 400 725 MHz
Duty Cycle 45 55 %
Rise/Fall Time (20% to 80%) 115 165 ps 100 Ω termination across OUT/OUTB, 2 pF load
Sub-harmonic Spur Level −35 dBc Without correction
Jitter (12 kHz to 20 MHz) 1.1 ps fIN = 19.44 MHz, f
= 10 k. Power supply pins within the range specified in the DC Specifications section.
SET
be higher depending on size of decoupling capacitor
is 0.4 × f
100 MHz
clock frequency must be met
spurious performance.
See the
SYSCLK Inputs section for recommendations
See
Figure 12 for maximum toggle rate
input (see
input (see
Rev. 0 | Page 5 of 68
Figure 3 to Figure 11 for test conditions)
Figure 3 to Figure 11 for test conditions)
OUT
SYSCLK
= 155.52 MHz. 50 MHz system clock
OUT
= 622.08 MHz, 50 MHz system clock
OUT
AD9549
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Parameter Min Typ Max Unit Test Conditions/Comments
CMOS Output Driver
(AVDD3/Pin 37) @ 3.3 V
Frequency Range 0.008 150 MHz
Duty Cycle 45 55 65 % With 20 pF load and up to 150 MHz
Rise/Fall Time (20-80%) 3 4.6 ns With 20 pF load
CMOS Output Driver
(AVDD3/Pin 37) @ 1.8 V
Frequency Range 0.008 40 MHz
Duty Cycle 45 55 65 % With 20 pF load and up to 40 MHz
Rise/Fall Time (20% to 80%) 5 6.8 ns With 20 pF load
HOLDOVER
Frequency Accuracy
OUTPUT FREQUENCY SLEW LIMITER
Slew Rate Resolution 0.54 111 Hz/sec P = 216 for minimum; P = 25 for maximum
Slew Rate Range 0 3 × 10
REFERENCE MONITORS
Loss of Reference Monitor
Operating Frequency Range 7.63 × 103 167 × 106Hz
Minimum Frequency Error for
Continuous REF Present Indication
Minimum Frequency Error for
Continuous REF Present Indication
Maximum Frequency Error for
Continuous REF Lost Indication
Maximum Frequency Error for
Continuous REF Lost Indication
Reference Quality Monitor
Operating Frequency Range 0.008 150 MHz
Frequency Resolution (Normalized) 0.2 ppm f
Frequency Resolution (Normalized) 408 ppm f
Validation Timer
Timing Range 32 × 10
Timing Range 65 × 10
DAC OUTPUT CHARACTERISTICS
DCO Frequency Range (1st Nyquist Zone) 10 450 MHz DPLL loop bandwidth sets lower limit
Output Resistance 50 Ω Single-ended (each pin internally terminated to AVSS)
Output Capacitance 5 pF
Full-Scale Output Current 20 31.7 mA Range depends on DAC R
Gain Error −10 +10 %FS
Output Offset 0.6 A
Voltage Compliance Range AVSS −
DIGITAL PLL
Minimum Open-Loop Bandwidth 0.1 Hz Dependent on the frequency of REFA/REFB, the DAC
Maximum Open-Loop Bandwidth 100 kHz Dependent on the frequency of REFA/REFB, the DAC
Minimum Phase Margin 0 10 Degrees Dependent on the frequency of REFA/REFB, the DAC
Maximum Phase Margin 85 90 Degrees Dependent on the frequency of REFA/REFB, the DAC
PFD Input Frequency Range ~0.008 ~24.5 MHz
Feedforward Divider Ratio 1 131,070 1, 2, …,65,535 or 2, 4, …, 131,070
Feedback Divider Ratio 1 131,070 1, 2, …, 65,535 or 2, 4, …, 131,070
See
Figure 14 for maximum toggle rate
See
Figure 13 for maximum toggle rate
See the
Holdover section
16
Hz/sec P = 216 for minimum; P = 25 for maximum
−16 ppm f
−19 % f
−32 ppm f
−35 % f
= 8 kHz
REF
= 155 MHz
REF
= 8 kHz
REF
= 155 MHz
REF
= 8 kHz; OOL divider = 65,535 for minimum; OOL
REF
divider = 1 for max (see the
Monitor
section)
= 155 MHz; OOL divider = 65,535 for minimum; OOL
REF
divider = 1 for maximum
See the
Reference Validation Timers section
0.50
−9
137 s PIO = 5
−6
2.8 × 105s PIO = 16
+0.5 AVSS +
Outputs not dc-shorted to V
0.50
sample rate, and the P-, R-, and S-divider values
sample rate, and the P-, R-, and S-divider values
sample rate, and the P-, R-, and S-divider values
sample rate, and the P-, R-, and S-divider values
Reference Frequency
resistor
SET
SS
Rev. 0 | Page 6 of 68
AD9549
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Parameter Min Typ Max Unit Test Conditions/Comments
LOCK DETECTION
Phase Lock Detector
Time Threshold Programming Range 0 2097 s FPFD_Gain = 200
Time Threshold Resolution 0.488 ps FPFD_Gain = 200
Lock Time Programming Range 32 × 10−9 275 s In power-of-2 steps
Unlock Time Programming Range 192 × 10−9 67 × 10−3s In power-of-2 steps
Frequency Lock Detector
Normalized Frequency Threshold
Programming Range
Normalized Frequency Threshold
Programming Resolution
Lock Time Programming Range 32 × 10−9 275 s In power-of-2 steps
Unlock Time Programming Range 192 × 10−9 67 × 10−3s In power-of-2 steps
DIGITAL TIMING SPECIFICATIONS
Time Required to Enter Power-Down 15 µs
Time Required to Leave Power-Down 18 µs
Reset Assert to High-Z Time
for S1 to S4 Configuration Pins
Reset Deassert to Low-Z Time
for S1 to S4 Configuration Pins
SERIAL PORT TIMING SPECIFICATIONS
SCLK Clock Rate (1/t
SCLK Pulse Width High, t
SCLK Pulse Width Low, t
SDO/SDIO to SCLK Setup Time, t
SDO/SDIO to SCLK Hold Time, t
) 25 50 MHz
CLK
HI
LO
DS
DH
SCLK Falling Edge to Valid Data on
SDIO/SDO, t
CSB to SCLK Setup Time, t
CSB to SCLK Hold Time, t
CSB Minimum Pulse Width High, t
DV
S
H
PWH
PROPAGATION DELAY
FDBK to HSTL Output Driver 2.8 ns
FDBK to HSTL Output Driver with 2×
Frequency Multiplier Enabled
FDBK to CMOS Output Driver 8.0 ns
FDBK Through S-Divider to CMOS
Output Driver
0 0.0021 FPFD_Gain = 200; normalized to (f
/R)2; see the
REF
Frequency Lock Detection section for details
5 ×
10
FPFD_Gain = 200; normalized to (f
−13
Frequency Lock Detection section for details
/R)2; see the
REF
60 ns Time from rising edge of RESET to high-Z on the S1, S2,
S3, S4 configuration pins
30 ns Time from falling edge of RESET to low-Z on the S1, S2,
S3, S4 configuration pins
Refer to
Figure 58 for all write-related serial port
parameters, maximum SCLK rate for readback is
governed by t
DV
8 ns
8 ns
1.93 ns
1.9 ns
11 ns
Refer to
Figure 56
1.34 ns
−0.4 ns
3 ns
7.3 ns
8.6 ns
Rev. 0 | Page 7 of 68
AD9549
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ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Analog Supply Voltage (AVDD) 2 V
Digital Supply Voltage (DVDD) 2 V
Digital I/O Supply Voltage
(DVDD_I/O)
DAC Supply Voltage (DAC_VDD) 3.6 V
Maximum Digital Input Voltage −0.5 V to DVDD_I/O + 0.5 V
Storage Temperature −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Lead Temperature
(Soldering 10 sec)
Junction Temperature 150°C
Thermal Resistance1
θ
JA
θ
JB
θ
JC
1
The exposed pad on bottom of package must be soldered to ground in
order to achieve the specified thermal performance. See the Thermal
Performance section for more information.
3.6 V
300°C
25.2°C/W typical
13.9°C/W typical
1.7°C/W typical
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 8 of 68
AD9549
T
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
S4S3AVD D
AVSS
DAC_OUTB
DAC_OUT
AVDD3
49
DAC_RSET
48
AVDD3
47
AVDD3
46
AVD D
45
AVD D
44
AVSS
43
AVD D
42
FDBK_IN
41
FDBK_INB
40
AVSS
39
OUT_CMOS
38
AVDD3
37
AVD D
36
OUT
35
OUTB
34
AVSS
33
DVDD_I/O
DVSS
DVDD
DVSS
DVDD
DVSS
DVDD
DVSS
AVD D
REFA_IN
REFA_INB
AVD D3
REFB_IN
REFB_INB
SCLK
SDIO
SDO
CSB
IO_UPDATE
RESET
PWRDOWN
HOLDO VER
646362616059585756555453525150
PIN 1
1
INDICATOR
2
3
4
5
6
7
8
9
S1
10
S2
11
12
13
14
15
16
REFSELEC
AD9549
TOP VIEW
(Not to Scale)
NC = NO CONNECT
171819202122232425262728293031
NC
NC
AVD D
AVD D
AVD D
AVD D
AVD D
AVD D
AVD D
PFD_VRT
PFD_VRB
PFD_RSET
SYSCLK
SYSCLKB
32
LOOP_FILTER
CLKMODESEL
06744-002
Figure 2. 64-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Input/
Ou
Pin No.
tput
Pin Type Mnemonic Description
1 I Power DVDD_I/O I/O Digital Supply.
2, 4, 6, 8 I Power DVSS Digital Ground. Connect to ground.
3, 5, 7 I Power DVDD Digital Supply.
9, 10, 54, 55 I/O 3.3 V CMOS S1, S2, S3, S4
Configurable I/O Pins. These pins are configured under program control (see
the Status and Warnings section) and do not have internal pull-up/pull-down
esistors.
r
11, 19, 23 to
I Power AVDD Analog Supply. Connect to a nominal 1.8 V supply.
26, 29, 30, 36,
42, 44, 45, 53
12 I
Differential
nput
I
REFA_IN
Frequency/Phase Reference A Input. This inter
nally biased input is typically accoupled and, when configured as such, can accept any differential signal with
single-ended swing between 0.4 V and 3.3 V. If dc-coupled, LVPECL or CMOS
input is preferred.
13 I
Differential
nput
I
REFA_INB
Complementary Frequency/Phase Reference A Input. Complementary signal
to the input pr
ovided on Pin 12. If using a single-ended, dc-coupled CMOS
signal into REFA_IN, bypass this pin to ground with a 0.01 F capacitor.
14, 46, 47, 49 I Power AVDD3 Analog Supply. Connect to a nominal 3.3 V supply.
15 I
Differential
nput
I
REFB_IN
Frequency/Phase Reference B Input. This internally biased input is typically accoupled and, when configured as such, can accept any differential signal with
single-ended swing between 0.4 V and 3.3 V. If dc-coupled, LVPECL or CMOS
input is preferred.
16 I
Differential
nput
I
REFB_INB
Complementary Frequency/Phase Reference B Input. Complementary signal to
the input provided on Pin 15. If using a single-ended, dc-coupled CMOS signal
into REFB_IN, bypass this pin to ground with a 0.01 F capacitor.
17, 18 NC No Connect. These are excess, unused pins that can be left floating.
20, 21 O
PFD_VRB,
T
PFD_VR
These pins must be capacitively decoupled. See the Phase Detector Pin
onnections section for details.
C
Rev. 0 | Page 9 of 68
AD9549
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Input/
Pin No.
22 O
27 I
28 I
31 O LOOP_FILTER
32 I 1.8 V CMOS CLKMODESEL
33, 39, 43, 52 O GND AVSS Analog Ground. Connect to ground.
34 O 1.8 V HSTL OUTB
35 O 1.8 V HSTL OUT
37 I Power AVDD3
38 O 3.3 V CMOS OUT_CMOS
40 I
41 I
48 O
50 O
51 O
56 I/O 3.3 V CMOS REFSELECT
57 I/O 3.3 V CMOS HOLDOVER
58 I 3.3 V CMOS PWRDOWN
59 I 3.3 V CMOS RESET
60 I 3.3 V CMOS IO_UPDATE
Output Pin Type Mnemonic Description
Current Set
esistor
R
Differential
nput
I
Differential
nput
I
Differential
nput
I
Differential
nput
I
Current Set
esistor
R
Differential
utput
O
Differential
utput
O
PFD_RSET
SYSCLK
SYSCLKB
FDBK_INB
FDBK_IN
DAC_RSET
DAC_OUT
DAC_OUTB
Connect a 5 kΩ resistor from this pin to ground (see the Phase Detector Pin
onnections section).
C
System Clock Input. The system clock input has internal dc biasing and should
alwa
ys be ac-coupled, except when using a crystal. Single-ended 1.8 V CMOS
can also be used but can introduce a spur caused by an input duty cycle that is
not 50%. When using a crystal, tie the CLKMODESEL pin to AVSS, and connect
crystal directly to this pin and Pin 28.
Complementary System Clock. Complementary signal to the input provided
on P
in 27. Use a 0.01 F capacitor to ground on this pin if the signal provided
on Pin 27 is single-ended.
System Clock Multiplier Loop Filter. When using the fr
drive the system clock, an external loop filter must be constructed and
attached to this pin. This pin is pulled high when the system clock PLL is
bypassed and can be left floating in this mode. See Figure 44 for a diagram of
the system cloc
Clock Mode Select. Set to GND when connecting a crystal to the system clock
in 27 and Pin 28). Pull up to 1.8 V when using either an oscillator or an
input (P
external clock source. This pin can be left floating when the system clock PLL is
bypassed. (See the SYSCLK Inputs section for details on the use of this pin.)
Complementary HSTL Output. See the Specifications and Primary 1.8 V
erential HSTL Driver sections for details.
Diff
HSTL Output. See the Specifications and Primary 1.8 V Differential HSTL Driver
tions for details.
sec
Analog Supply for CMOS Output Driver: This pin
1.8 V. This pin should be powered even if the CMOS driver is not used. See the
Power Supply Partitioning section for power supply partitioning.
CMOS Output. See the Specifications section and the Output Clock Drivers and
requency Multiplier section. This pin is 1.8 V CMOS if Pin 37 is set to 1.8 V.
2× F
Complementary Feedback Input. In standard operating mode, this pin is
c
onnected to the filtered DAC_OUTB output. This internally biased input is
typically ac-coupled, and when configured as such, can accept any differential
signal whose single-ended swing is at least 400 mV.
Feedback Input. In standard operating mode
filtered DAC_OUT output
DAC Output Current Setting Resistor. Connect a resistor (usually 10 kΩ) from
this pin to GND
DAC Output. This signal should be filtered and sent back on chip through
FDBK_IN input. This pin has an internal 50 Ω pull-down resistor.
Complimentary DAC Output. This signal should be filtered and sent back on
chip thr
ough FDBK_INB input. This pin has an internal 50 Ω pull-down resistor.
Reference Select Input. In manual mode, the REFSELECT pin operates as a high
impedanc
output pin. Logic 0 (low) indicates/selects REFA. Logic 1 (high) indicates/selects
REFB. There is no internal pull-up/pull-down resistor on this pin.
Holdover (Active High). In manual holdover mode, this pin is used to force the
AD9549 in
holdover status. There is no internal pull-up/pull-down resistor on this pin.
Power-Down. When this active high pin is asserted, the device becomes
inac
pull-down resistor.
Chip Reset. When this active high pin is a
that on power-up, a 10 s reset pulse is internally generated when the power
supplies reach a threshold and stabilize. This pin has an internal 50 kΩ pulldown resistor.
I/O Update. A logic transition from 0 to 1 on this pin transf
port registers to the control registers (see the Write section). This pin has an
ternal 50 kΩ pull-down resistor.
in
e input pin, while in automatic mode, it operates as a low impedance
to holdover mode. In automatic holdover mode, it indicates
tive and enters the full power-down state. This pin has an internal 50 kΩ
equency multiplier to
k PLL loop filter.
is normally 3.3 V but can be
, this pin is connected to the
. See the DAC Output section.
sserted, the chip goes into reset. Note
ers data from the I/O
Rev. 0 | Page 10 of 68
AD9549
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Input/
Pin No.
61 I 3.3 V CMOS CSB
62 O 3.3 V CMOS SDO
63 I/O 3.3 V CMOS SDIO
64 I 3.3 V CMOS SCLK
Exposed Die
Pad
Output Pin Type Mnemonic Description
Chip Select. Active low. When programming a device, this pin must be held
w. In systems where more than one AD9549 is present, this pin enables
lo
individual programming of each AD9549. This pin has an internal 100 kΩ pullup resistor.
Serial Data Output. When the device is in 3-wire mode, data is r
There is no internal pull-up/pull-down resistor on this pin.
Serial Data Input/Output. When
this pin. In 2-wire mode, data reads and writes both occur on this pin. There is
no internal pull-up/pull-down resistor on this pin.
Serial Programming Clock. Data clock for serial programming. This pin has an
ternal 50 kΩ pull-down resistor.
in
O GND AVSS Analog Ground. Connect to ground.
the device is in 3-wire mode, data is written via
ead on this pin.
Rev. 0 | Page 11 of 68
AD9549
–
–
–
–
–
–
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, AVDD, AVDD3, and DVDD at nominal supply voltage; fS = 1 GHz, DAC R
–80
70
RMS JITTER (12kHz TO 20MHz): 0.18p s
RMS JITTER (50kHz TO 80MHz): 0.24p s
70
–80
= 10 k.
SET
RMS JITTER (12kHz TO 20MHz): 1.09p s
RMS JITTER (50kHz TO 80MHz): 1.14p s
–90
–100
–110
–120
PHASE NOISE (dBc/Hz)
–130
–140
–150
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY OF FSET (Hz)
Figure 3. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
PLL Bypassed), f
(SYSCLK
= 311.04 MHz, DPLL Loop BW = 1 kHz
f
OUT
70
–80
–90
–100
–110
–120
PHASE NOISE (dBc/Hz)
–130
RMS JITT ER (12kHz TO 20MHz): 0.36p s
RMS JITT ER (50kHz TO 80MHz): 0.42p s
= 19.44 MHz,
REF
–90
–100
–110
–120
PHASE NOISE (dBc/Hz)
–130
–140
–150
06744-003
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY OF FSET (Hz)
06744-006
Figure 6. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL
50 MHz), f
Enabled and Driven by R&S SMA100 Signal Generator at
= 19.44 MHz, f
REF
= 622.08 MHz, DPLL Loop BW = 1 kHz,
OUT
System Clock Doubler Enabled, HSTL Doubler Enabled
PHASE NOISE (dBc/Hz)
70
–80
–90
–100
–110
–120
–130
RMS JITT ER (12kHz TO 20MHz): 1.0p s
RMS JITT ER (50kHz TO 80MHz): 1.2p s
–140
–150
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY OF FSET (Hz)
Figure 4. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK
PLL Bypassed), f
= 19.44 MHz, f
REF
= 622.08 MHz,
OUT
DPLL Loop BW = 1 kHz, HSTL Output Doubler Enabled
70
–80
–90
–100
–110
–120
PHASE NOISE (dBc/Hz)
–130
–140
–150
10 100 1k 10k 100k 1M 10M 100M
RMS JITTER (12kHz TO 20MHz): 1.01p s
RMS JITTER (50kHz TO 80MHz): 1.04p s
FREQUENCY OF FSET (Hz)
Figure 5. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL
Enabled Driven by R&S SMA100 Signal Generator at 50 MHz),
= 19.44 MHz, f
f
REF
= 311.04 MHz, DPLL Loop BW = 1 kHz
OUT
06744-004
(SYSCLK PLL
06744-005
Rev. 0 | Page 12 of 68
–140
–150
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY OF FSET (Hz)
Figure 7. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
Enabled and Driven by R&S SMA100 at 50 MHz), f
= 155.52 MHz, SYSCLK Doubler Enabled, DPLL Loop BW =1 kHz
f
OUT
70
–80
–90
–100
–110
–120
PHASE NOISE (dBc/Hz)
–130
–140
–150
10 100 1k 10k 100k 1M 10M 100M
RMS JITT ER (12kHz TO 20MHz): 1.07p s
RMS JITT ER (50kHz TO 80MHz): 1.16p s
FREQUENCY OF FSET (Hz)
= 19.44 MHz,
REF
Figure 8. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL
Enabled and Driven by R&S SMA100 Signal Generator at
50 MHz), f
= 8 kHz, f
REF
= 155.52 MHz, DPLL Loop BW = 10 Hz
OUT
06744-007
06744-008
AD9549
–
–
www.BDTIC.com/ADI
2.0
1.5
1.0
0.5
12kHz TO 20MHz RMS JITTER (ps)
0
10 30 50 70 90
SYSTEM CLOCK PLL INPUT FREQUENCY (MHz)
Figure 9. 12 kHz to 20 MHz RMS Jitter v
SYSCLK = 1 GHz, f
70
–80
–90
–100
–110
= 19.44 MHz, f
REF
RMS JITT ER (12kHz TO 20MHz): 1.26p s
RMS JITT ER (50kHz TO 80MHz): 1.30p s
06744-009
s. System Clock PLL Input Frequency,
= 155.52 MHz
OUT
70
–80
–90
–100
–110
–120
PHASE NOISE (dBc/Hz)
–130
–140
–150
10 100 1k 10k 100k 1M 10M
RMS JITTER (12kHz TO 20M Hz): 4.2ps
FREQUENCY OFFSET (Hz)
06744-011
Figure 11. Additive Phase Noise at HSTL Output Driver, SYSCLK = 500 MHz
(SYSCLK
PLL Disabled), f
= 10.24 MHz, f
REF
= 20.48 MHz,
OUT
DPLL Loop BW = 1 kHz
–120
PHASE NOISE (dBc/Hz)
–130
–140
–150
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY OF FSET (Hz)
Figure 10. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL
Enabled and Driven by a 25 MHz Fox Crystal Oscillator),
f
= 19.44 MHz, f
REF
= 155.52 MHz, DPLL Loop BW = 1 kHz
OUT
06744-010
Rev. 0 | Page 13 of 68
AD9549
www.BDTIC.com/ADI
650
600
0.6
0.4
0.2
550
(mV)
500
NOM SKEW 25°C, 1.8V SUPPLY
SLOW SKEW 90°C, 1. 7V SUPPLY
450
0 200 400 600 800
(MHz)
06744-012
Figure 12. HSTL Output Driver Single-Ended Peak-to-Peak Amplitude vs.
Toggle Rate (100 Ω Across Differential Pair)
2.5
2.0
1.5
(V)
1.0
NOM SKEW 25° C, 1.8V SUPPLY (20pF)
0.5
0
0 1020304
SLOW S KEW 90°C, 1.7V SUPPL Y (20pF )
(MHz)
0
06744-013
Figure 13. CMOS Output Driver Peak-to-Peak Amplitude vs. Toggle Rate
VDD3 = 1.8 V) with 20 pF Load
(A
0
(V)
FREQUENCY= 600MHz
(20→80%) = 104ps
T
–0.2
–0.4
–0.6
0 0.5 1.0 1.5 2.0 2.5
RISE
T
FALL
V p-p = 1. 17V DIFF.
DUTY CYCLE = 50%
(ns)
(80→20%) = 107ps
Figure 15. Typical HSTL Output Waveform, Nominal Conditions,
DC-Coupl
1.8
1.6
1.4
1.2
1.0
0.8
(V)
0.6
0.4
0.2
0
–0.2
0 20 40 60 80 100
Figure 16. Typical CMOS Output Dr
ed, Differential Probe Across 100 Ω load
FREQUENCY= 20MHz
T
(20→80%) = 5.5ns
RISE
T
(80→20%) = 5.9ns
FALL
V p-p = 1.8V
DUTY CYCLE = 53%
(ns)
iver Waveform (@ 1.8 V),
Nominal Conditions, Estimated Capacitance: 5 pF
06744-015
06744-016
3.5
3.0
2.5
2.0
(V)
1.5
1.0
0.5
NOM SKEW 25°C, 3.3V SUPPLY (20pF)
SLOW SKEW 90°C, 3.0V SUPPLY (20pF)
0
0 50 100 150
(MHz)
06744-014
Figure 14. CMOS Output Driver Peak-to-Peak Amplitude vs. Toggle Rate
VDD3 = 3.3 V) with 20 pF Load
(A
Rev. 0 | Page 14 of 68
3.3
2.8
2.3
1.8
(V)
1.3
0.8
0.3
–0.2
0 102030405
FREQUENCY= 40MHz
T
(20→80%) = 2.25ns
RISE
T
FALL
V p-p = 3.3V
DUTY CYCLE = 52%
(ns)
(80→20%) = 2.6ns
0
Figure 17. CMOS Output Driver Waveform (@ 3.3 V), Nominal Conditions,
Esti
mated Capacitance: 5 pF, f
= 20 MHz
OUT
06744-017
AD9549
www.BDTIC.com/ADI
INPUT/OUTPUT TERMINATION RECOMMENDATIONS
0.01µF
AD9549
1.8V
HSTL
OUTPUT
100Ω
0.01µF
DOWNSTREAM
DEVICE
(HIGH-Z)
Figure 18. AC-Coupled HSTL Output Driver
AD9549
1.8V
HSTL
OUTPUT
50Ω
AVDD/2
50Ω
DOWNSTREAM
DEVICE
(HIGH-Z)
Figure 19. DC-Coupled HSTL Output Driver
0.01µF
100Ω
(OPTIONAL)
0.01µF
06744-018
AD9549
SELF-BIASING
REF INPUT
06744-020
Figure 20. Reference Input
0.1µF
100Ω
(OPTIONAL)
0.1µF
06744-019
AD9549
SELF-BIASING
FDBK INPUT
06744-021
Figure 21. FDBK Input
Rev. 0 | Page 15 of 68
AD9549
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THEORY OF OPERATION
OUT_CMOS
REFSELECT
REFA_IN
REFB_IN
S1 TO S4
INPUT
MONITOR
OOL AND LO R
IRQ AND
STATUS
LOGIC
REF
÷R
REF_CNTRL
FREQ
EST.
PROG.
DIGITAL
PFD
LOOP
FILTER
LOCK DETECT
CONTROL
LOGIC
DIGITAL
INTERFACE
Figure 22. Detailed Block Diagram
OVERVIEW
The AD9549 provides a clocking output that is directly related
in phase and frequency to the selected (active) reference (REFA
or REFB) but has a phase noise spectrum primarily governed by
the system clock. A wide band of reference frequencies is supported. Jitter existing on the active reference is greatly reduced
by a programmable digital filter in the digital phase-locked loop
(PLL), which is the core of this product. The AD9549 supports
both manual and automatic holdover. While in holdover, the
AD9549 continues to provide an output as long as the system
clock is maintained. The frequency of the output during holdover is an average of the steady state output frequency prior to
holdover.
Also offered are manual and automatic switchover modes for
nging between the two references, should one become
cha
suspect or lost. A digitally controlled oscillator (DCO) is
implemented using a direct digital synthesizer (DDS) with an
integrated output DAC, clocked by the system clock. A bypassable PLL-based frequency multiplier is present enabling use of
an inexpensive, low frequency source for the system clock. For
best jitter performance, the system clock PLL should be bypassed,
and a low noise, high frequency system clock should be provided
directly. Sampling theory sets an upper bound for the DDS
output frequency at 50% of f
(where fS is the DAC sample rate),
S
2×
÷S
SLEW
HOLDOVER
DIGITAL PLL CORE
FREQUENCY
LIMIT
HOLDOVER SYSCLK
TUNING
WORD
DDS/DAC
LOW NOISE
MULTIPLIER
SYSCLK PORT
but a practical limitation of 40% of f
CLOCK
AMP
OUT
FDBK
EXTERNAL
ANALOG
LOW-PASS
FILTER
is generally recommended
S
to allow for the selectivity of the required off-chip
reconstruction filter. The output signal from the reconstruction
filter is fed back to the AD9549, both to complete the PLL and
to be processed through the output circuitry. The output
circuitry includes HSTL and CMOS output buffers, as well as a
frequency doubler for designs that need to provide frequencies
above the Nyquist level of the DDS.
The individual functional blocks are described in the following
secti
ons.
PLL CORE (DPLLC)
The digital phase-locked loop core (DPLLC) includes the
frequency estimation block and the digital phase lock control
block driving the DDS.
The start of the DPLLC signal chain is the reference signal, f
which appears on REFA or REFB inputs. The frequency of this
signal can be divided by an integer factor of R via the feedforward divider. The output of the feedforward divider is routed to
the phase/frequency detector (PFD). Therefore, the frequency
at the input to the PFD is given by
f
R
=
f
PFD
R
06744-022
,
R
Rev. 0 | Page 16 of 68
AD9549
www.BDTIC.com/ADI
The PFD outputs a time series of digital words that are routed
to the digital loop filter. The digital filter implementation offers
many advantages: The filter response is determined by numeric
coefficients rather than discrete component values. There is no
aging of components and therefore, no drift of component value
over time. There is no thermal noise in the loop filter, and there
is no control node leakage current (which causes reference feedthrough in a traditional analog PLL).
The output of the loop filter is a time series of digital words.
T
hese words are applied to the frequency tuning input of a DDS
to steer the DCO frequency. The DDS provides an analog
output signal via an integrated DAC, effectively mimicking the
operation of an analog VCO.
The DPLLC can be programmed to operate in conjunction
ith an internal frequency estimator to help decrease the time
w
required to achieve lock. When the frequency estimator is
employed, frequency acquisition is accomplished in a two-step
process:
1. An es
timate is made of the frequency of f
. The phase
PFD
lock control loop is essentially inoperative during the
frequency estimation process. Once a frequency estimate is
made, it is delivered to the DDS so that its output frequency
is approximately equal to f
multiplied by S (the modulus
PFD
of the feedback divider).
2. The phas
e lock control loop becomes active and acts as a
servo to acquire and hold phase lock with the reference
signal.
As mentioned in Step 1, the DPLLC includes a feedback divider
hat allows the DCO to operate at an integer multiple (S) of f
t
This establishes a nominal DCO frequency (f
S
⎞
⎛
f
=
⎟
⎜
R
R
⎠
⎝
÷PFD
PHASE
DETECTO R
(TIME-TO-
DIGIT AL
SAMPLES
DELIVERED AT
DIV
THE CLK RAT E
LOOP
FILTER
αβ
FDBK_IN
÷S
Figure 23. AD9549 Digital PLL Block Diagram
÷P
CCI
ץ
PINS
SAMPLES
DELIVERED AT
SYSCLK RATE
EXTERNAL DAC
RECONSTRUCTION
REF
INPUT
÷R
f
CLK
DDS
CONVERTER)
), given by
DDS
DDS
FILTER
SYSCLK
DAC_OUT
PINS
PFD
Feedforward Divider (Divide-by-R)
The feedforward divider is an integer divider that allows
frequency prescaling of the REF source input signal while
maintaining the desired low jitter performance of the AD9549.
The feedforward divider is a programmable modulus divider
th very low jitter injection. The divider is capable of handling
wi
input frequencies as high as 750 MHz. The divider depth is 16-
Rev. 0 | Page 17 of 68
.
06744-023
bits cascaded with an additional divide-by-2. The divider
therefore is capable of integer division from 1 to 65,535 (index
of 1) or 2 to 131,070 (index of 2). The divider is programmed
via the I/O Register Map to trigger on either the rising (default)
or falling edge of the REF source input signal. Note that the
value stored in the R-divider register is one less than the actual
R-divider, so setting the R-divider register to zero results in an R
divider equal to one.
There is a lower bound on the value of R imposed by the phase
f
requency detector within the DPLLC, which has a maximum
operating frequency of f
, as explained in the Fine Phase
PFD[MAX]
Detector section. The R-Divider/2 bit must be set when REFA
r REFB is greater than 400 MHz. The user must also ensure
o
that R is chosen so that it satisfies the inequality
⎛
R
⎜
≥
ceil
⎜
f
⎝
⎞
f
R
⎟
⎟
][
MAXPFD
⎠
The upper bound is
f
⎛
⎞
≤
floor
R
R
⎜
⎟
kHz8
⎝
⎠
where the ceil(x) function yields the nearest integer ≥ x.
For example, if f
=155 MHz and f
R
= 24.5 MHz, then
PFD[MAX]
ceil (155/24.5) = 7, so R must be ≥ 7.
Feedback Divider (Divide-by-S)
The feedback divider is an integer divider allowing frequency
multiplication of the REF signal that appears at the input of the
phase detector. It is capable of handling frequencies well above
the Nyquist limit of the DDS. The divider depth is 16-bits cascaded with an additional divide-by-2. The divider is therefore
capable of integer division from 1 to 65,535 (index of 1) or 2 to
131,070 (index of 2). The divider is programmed via the I/O
Register Map to trigger on either the rising (default) or falling
edge of the feedback signal. Note that the value stored in the SDivider register is one less than the actual R-divider, so setting
the S-Divider register to zero results in an S-divider equal to one.
The feedback divider must be programmed within certain
b
oundaries. The S-Divider/2 bit must be set when FDBK_IN is
greater than 400 MHz. The upper boundary on the feedback
divider is the lesser of the maximum programmable value of
S and the maximum practical output frequency of the DDS
(~ 40% f
divider index of 1 and S
). Two equations are given—S
S
for an index of 2.
max2
⎛
%40
Rf
S
⎜
= 535,65,
MAX1
min
⎜
f
R
⎝
S
for a feedback
max1
⎞
⎟
⎟
⎠
or
⎛
%40
Rf
S
⎜
= 070,131,
S
where
sample rate, and
min
2
MAX
⎜
f
R
⎝
R is the modulus of the feedforward divider, f
f
is the input reference frequency.
R
⎞
⎟
⎟
⎠
is the DAC
S
AD9549
C
www.BDTIC.com/ADI
The DCO has a minimum frequency, f
DCO[MIN]
(see the DAC
Output Characteristics section of the AC Specifications table).
This i
mposes a lower bound, S
, on the feedback divider
MIN
value as well.
⎞
⎞
][RMINDCO
⎟
⎟
⎟
⎟
⎠
⎠
MIN
= 1,max
⎛
⎛
f
⎜
⎜
RS
⎜
⎜
f
⎝
⎝
Note that reduced DCO frequencies result in worse jitter
erformance (a consequence of the reduced slew rate of the
p
sinusoid generated by the DDS).
Forward and Reverse FEC Clock Scaling
The feedforward divider (divide-by-R) and feedback divider
(divide-by-S) enable FEC clock scaling. For instance, to
multiply the incoming signal by 255/237, set the S-divider to
255 and the R-divider to 237. One should be careful to abide by
the limitations on the R- and S-dividers, and make sure the
phase detector input frequency is within specified limits.
Phase Detector
The phase detector is composed of two detectors: a coarse phase
detector and a fine phase detector. The two detectors operate in
parallel. Both detectors measure the duration (t) of the pulses
generated by a conventional three-state phase/frequency detector.
Together, the fine and coarse phase detectors produce a digital
ord that is a time-to-digital conversion of the separation
w
between the edge transitions of the prescaled reference signal
and the feedback signal.
If the fine phase detector is able to produce a valid result, this
r
esult alone serves as the phase error measurement. If the fine
phase detector is either in an overflow or underflow condition,
the phase error measurement uses the coarse phase detector
instead.
Digital Loop Filter
The digital loop filter integrates and low-pass filters the digital
phase error values delivered by the phase detector. The loop
filter response mimics that of a 2
nd
order RC network used to
filter the output of a typical phase detector and charge pump
combination as shown in
LK
PHASE/
FREQUENCY
DETECTOR
Figure 24. Typical Analog PLL Block Diagram
Figure 24.
CHANGE
PUMP
LOOP FILTER
R2
C1
C2
VCO
6744-024
The building blocks implemented on the AD9549, however, are
digital. A time-to-digital converter that produces digital values
proportional to the edge timing error between the CLK and
feedback signals replaces the phase-frequency detector and
charge pump. A digital filter that processes the edge timing
error samples from the time-to-digital converter replaces the
loop filter. A DDS replaces the VCO, which produces a frequency
Rev. 0 | Page 18 of 68
that is linearly related to the digital value provided by the loop
filter. This is shown in
Figure 25 with some additional detail.
The samples provided by the time-to-digital converter are
de
livered to the loop filter at a sample rate equal to the CLK
frequency (that is, f
/R). The loop filter is intended to oversam-
R
ple the time-to-digital converter output at a rate determined by
the P-divider. The value of P is programmable via the I/O
Register Map. It is stored as a 5-bit number, P
. The value of PIO
IO
is related to P by the equation
PIO
P = 2
where 5 ≤ P
≤ 16.
IO
Hence, the P-divider can provide divide ratios between 32 and
65,536 in p
ower-of-2 steps. With a DAC sample rate of 1 GHz,
the loop filter sample rate can range from as low as 15.26 kHz to
a maximum of 31.25 MHz. Coupled to the loop filter is a
cascaded comb integrator (CCI) filter that provides a sample
rate translation between the loop filter sample rate (f
the DDS sample rate, f
.
S
/P) and
S
The choice of P is important because it controls both the
r
esponse of the CCI filter and the sample rate of the loop filter.
In order to understand the method for determining a useful
value for P, it is first necessary to examine the transfer function
of the CCI filter.
2
jω
P
⎡
)(
ωH
CCI
1
=
⎢
1(
⎣
⎤
e
−
−
⎥
− jω
eP
⎦
or
0,1
=
ω
CCI
⎛
)(
=
ωH
−
⎜
⎜
−
p
⎝
2
ωP
ω
⎞
)cos(11
,
⎟
⎟
)cos(1
⎠
0
>
ω
To evaluate the response in terms of absolute frequency, make
e substitution
th
π
2
f
=
ω
f
S
where f
H
is the DAC sample rate and f is the frequency at which
S
is to be evaluated.
CCI
Analysis of this function reveals that the CCI magnitude
r
esponse follows a low-pass characteristic that consists of a
series of P lobes. The lobes are bounded by null points occurring at frequency multiples of f
/P. The peak of each successive
S
lobe is lower that its predecessor over the frequency range
between dc and ½f
response is a reflection about the vertical at ½f
the first lobe (which appears between dc and f
. For frequencies greater than ½fS, the
S
. Furthermore,
S
/P) exhibits a
S
monotonically decreasing response. That is, the magnitude is
unity at dc, and it steadily decreases with frequency until it
vanishes at the first null point (f
/P).
S
The null points imply the existence of transmission zeros placed
a
t finite frequencies. While transmission zeros placed at infinity
yield minimal phase delay, zeros placed closer to dc result in
AD9549
www.BDTIC.com/ADI
increased phase delay. Hence, the position of the first null point
has a significant impact on the phase delay introduced by the
CCI filter. This is an important consideration because excessive
phase delay negatively impacts the overall closed-loop response.
As a rule of thumb, choose a value for P so that the frequency of
the first null point (f
loop bandwidth or 1.5 times the frequency of CLK (f
The value of P thus calculated (P
in practice. Because P is programmed as P
define P
in terms of PIO so that P
MAX
The condition P
/P) is the greater of 80 times the desired
S
) is the largest usable value
MAX
, it is necessary to
IO
can be determined.
IOMAX
IO
≤ P
ensures that the impact of the phase
IOMAX
/R).
R
delay of the CCI filter on the phase margin of the loop does not
exceed 5°. P
=
P
IOMAX
can be expressed as
IOMAX
⎧
⎪
⎨
⎪
⎩
⎡
⎛
⎜
⎢
logfloor,16min,5max
⎜
80
⎢
⎝
⎣
f
f
S
LOOP
⎤
⎡
⎞
⎟
⎥
⎟
⎥
⎠
⎦
⎛
f
2
S
⎜
⎢
logfloor,
22
⎜
f
3
⎢
⎣
REF
⎝
With a properly chosen value for P, the closed-loop response of
the digital PLL is primarily determined by the response of the
digital loop filter. Flexibility in controlling the loop filter
response translates directly into flexibility in the range of
applications satisfied by the architecture of the AD9549.
The AD9549 evaluation software automatically sets the value of
t
he P-divider based on the user’s input criteria. Therefore, the
formulas are provided here mainly to assist in understanding
how the part works.
Direct Digital Synthesizer
One of the primary building blocks of the digital PLL is a direct
digital synthesizer (DDS). The DDS behaves like a sinusoidal
signal generator. The frequency of the sinusoid generated by the
DDS is determined by a frequency tuning word (FTW), which
is a digital (that is, numeric) value. Unlike an analog sinusoidal
generator, a DDS uses digital building blocks and operates as a
sampled system. Thus, it requires a sampling clock (f
) that
S
serves as the DDS's fundamental timing source. The accumulator behaves as a modulo-2
48
counter with a programmable step
size (FTW). A block diagram of the DDS is shown in Figure 25.
The input to the DDS is a 48-bit FTW that provides the accum
ulator with a seed value. On each cycle of f
, the accumulator
S
adds the value of the FTW to the running total of its output.
For example, given an FTW = 5, the accumulator counts by 5s,
incrementing on each f
reaches the upper end of its capacity (2
cycle. Over time, the accumulator
S
48
in this case), at which
point, it rolls over, retaining the excess. The average rate at which
the accumulator rolls over establishes the frequency of the
48-BIT ACCUMULAT OR
48
FREQUENCY
TUNING WO RD
(FTW)
194848
QD
⎤
⎞
⎟
⎥
⎟
⎥
⎠
⎦
PHASE
OFFSET
output sinusoid. The average rollover rate of the accumulator is
given by the next equation and establishes the output frequency
(f
) of the DDS.
DDS
FTW
⎛
=
f
⎞
⎜
⎝
f
⎟
SDDS
48
2
⎠
Solving this equation for FTW yields
⎡
⎢
FTW
=
2round
⎢
⎣
For example, given that f
48
⎤
⎞
⎛
f
DDS
⎟
⎜
⎥
⎟
⎜
f
⎥
S
⎠
⎝
⎦
= 1 GHz and f
S
= 19.44 MHz, then
DDS
FTW = 5,471,873,547,255 (0x04FA05143BF7).
The relative phase of the sinusoid can be controlled numerically,
⎫
⎪
⎬
⎪
⎭
ell. This is accomplished using the phase offset input to the
as w
DDS (a programmable 16-bit value (phase); see the
Map section). The resulting phase offset, Φ (radians), is given by
phase
Δ
⎛
2
Φ
π=Δ
⎜
⎝
⎞
⎟
16
2
⎠
The DDS can be operated in either open-loop or closed-loop
m
ode, via the Close Loop bit in the DPLL Register.
There are two open-loop modes: single tone and holdover. In
gle tone mode, the DDS behaves like a frequency synthesizer,
sin
and uses the value stored in the FTW0 register to determine its
ou tput frequenc y. A l te r n atively, the F T W and phase values
can be determined by the device itself using the frequency
estimator. Because single tone mode ignores the reference
inputs, it is very useful for generating test signals to aid in
debugging. Single tone mode must be activated manually via
register programming.
In holdover mode, the AD9549 uses past tuning words when
he loop is closed to determine its output frequency. Therefore,
t
the loop must have been successfully closed in order for holdover
mode to work. Switching in and out of holdover mode can be
either automatic or manual, depending on register settings.
Typically, the AD9549 operates in closed-loop mode. In closedl
oop mode, the FTW values come from the output of the digital
loop filter and vary with time. The DDS frequency is steered in
a manner similar to a conventional VCO-based PLL.
Note that in closed-loop mode, the DDS phase offset capability
is in
operative.
16
ANGLE TO
AMPLITUDE
CONVERSIO N
1419
DAC
(14-BIT)
I-SET
DAC+
DAC–
I/O Register
Figure 25. DDS Block Diagram
Rev. 0 | Page 19 of 68
f
S
06744-025
AD9549
www.BDTIC.com/ADI
DAC Output
The output of the digital core of the DDS is a time series of
numbers representing a sinusoidal waveform. This series is
translated to an analog signal by means of a digital-to-analog
converter (DAC).
The DAC outputs its signal to two pins driven by a balanced
curr
ent source architecture (see theDAC output diagram in
Figure 26). The peak output current derives from the combinat
ion of two factors. The first is a reference current (I
DAC_REF
)
established at the DAC_RSET pin and the second is a scale
factor programmed into the I/O register map.
AVDD3
49
I
SWITCH
CONTROL
CODE
52
AVSS
FS
CURRENT
SWITCH
ARRAY
IFS/2 – I
CODE
5051
06744-026
)
DAC_REF
IFS/2 + I
The value of I
CURRENT
SWITCH
ARRAY
CODE
DAC_REF
IFS/2 IFS/2
IOUT IOUTB
50Ω 50Ω
Figure 26. DAC Output Pins
is set by connecting a resistor (R
between the DAC_RSET pin and ground. The DAC_RSET pin
is internally connected to a virtual voltage reference of 1.2 V
nominal, so the reference current can be calculated by
I
_
REFDAC
Note that the recommended value of I
leads to a recommended value for R
2.1
=
R
REFDAC
_
is 120 A, which
DAC_REF
of 10 k.
DAC_REF
The scale factor consists of a 10-bit binary number (FSC)
p
rogrammed into the DAC Full-Scale Current register in the
I/O register map. The full-scale DAC output current (I
DAC_FS
) is
given by
FSC
192
⎛
II
__
+=
72
⎜
REFDACFSDAC
⎝
Using the recommended value of R
1024
DAC_REF
⎞
⎟
⎠
, the full-scale DAC
output current can be set with 10-bit granularity over a range of
approximately 8.6 mA to 31.7 mA. 20 mA is the default value.
PHASE DETECTOR
Coarse Phase Detector
The coarse phase detector uses the DAC sample rate (fS) to
determine the edge timing deviation between the REF signal
and the feedback signal generated by the DDS. Hence, f
sets the
S
timing resolution of the coarse phase detector. At the recommended rate of f
= 1 GHz, the coarse phase detector spans a
S
range of over 131 s (sufficient to accommodate REF signal
frequencies as low as 8 kHz).
The phase gain of the coarse phase detector is controlled via the
I/O r
egisters by means of two numeric entries. The first is a 3bit power-of-2 scale factor, PDS. The second is a 6-bit linear
scale factor, PDG.
⎛
⎞
f
PDS
CPD
S
⎜
=
RPhaseGain
⎜
f
R
⎝
62+
⎟
()
PDG
⎟
⎠
Fine Phase Detector
The fine phase detector operates on a divided down version of fS
as its sampling time base. The sample rate of the fine phase
detector is set using a 4-bit word (PFD_Div) in the I/O register
map and is given by
f
S
RateSampleDetectorPhaseFine
=
)_(4 DivPFD
The default value of PFD_Div is 5, so for f
= 1 GHz, the default
S
sample rate of the fine phase detector is 50 MHz. The upper
bound on the maximum allowable input frequency to the phase
detector (f
f
Therefore, f
) is 49% of the sample rate, or
PFD[MAX]
f
MAXPFD
PFD[MAX]
=
][
S
)_(8
DivPFD
is 25 MHz in the preceding example.
The fine phase detector uses a proprietary technique to
det
ermine the phase deviation between the REF signal and
feedback signal.
The phase gain of the fine phase detector is controlled by an 8-
it scale factor (FPFD_Gain) in the I/O register map. The
b
nominal (default) value of FPFD_Gain is 200, and establishes
the phase gain as
710
=
DPhaseGain
FP
×
f
GainFPFDR
)_)(102(
R
Phase Detector Gain Matching
Although the fine and coarse phase detectors use different
means to make a timing measurement, it is essential that both
have equivalent phase gain. Without proper gain matching, the
closed-loop dynamics of the system cannot be properly controlled. Hence, the goal is to make PhaseGain
= PhaseGain
CPD
FPD
This leads to
PDS
+
S
7106
×=
GainFPFDPDGf
_)102()2(
which simplifies to
7
PDS
PDG
2
×
=
GainFPFD
_)1016(
f
S
.
Rev. 0 | Page 20 of 68
AD9549
π−=
{
[
(
(
)
www.BDTIC.com/ADI
Typically, FPFD_Gain is established first and then PDG and
PDS are calculated. The proper choice for PDS is given by
PDS
⎡
⎢
=
loground
⎢
⎣
7
⎛
×
⎜
2
⎜
⎝
_10
f
2
S
⎤
⎞
GainFPFD
⎟
⎥
⎟
⎥
⎠
⎦
The final value of PDS must satisfy 0 ≤ PDS ≤ 7. The proper
hoice for PDG is calculated using the following equation:
c
7
PDG
=
round
⎛
⎜
⎜
⎝
−SPDS
4
2
⎞
GainFPFD
_10
⎟
⎟
f
⎠
The final value of PDG must satisfy 0 ≤ PDG ≤ 63. For example,
let f
= 700 MHz and FPFD_Gain = 200, then PDS = 1 and
S
PDG = 23.
Note that the AD9549 evaluation software calculates register
val
ues that have the phase detector gains already matched.
Phase Detector Pin Connections
There are three pins associated with the phase detector that
must be connected to external components. Figure 27 shows the
ecommended component values and their connections.
r
AD9549
20 21 22
0.1µF
0.1µF
Figure 27. Phase Detector Pin Connections
10µF
PFD_VRT PFD_RSETPFD_VRB
0.1µF
4.99kΩ
06744-027
DIGITAL LOOP FILTER COEFFICIENTS
In order to provide the desired flexibility, the loop filter has
been designed with three programmable coefficients (α, β, and
γ). The coefficients along with P (where P = 2
define the response of the filter, which is given by
jω
2
)(
LoopFilter
⎛
⎜
=
αωH
⎜
⎝
To evaluate the response in terms of absolute frequency,
itute
subst
π
2
Pf
ω
where P
=
is the divide ratio of the P-divider, f
f
S
rate, and f is the frequency at which the function is to be
evaluated.
The loop filter coefficients are determined by the AD9549
valuation software according to three parameters:
e
• Φ is the desired closed-loop phase margin (0 < Φ < π/2 rad).
• f
• f
is the desired open-loop bandwidth (Hz).
LOOP
is the desired output frequency of the DDS (Hz). Note
DDS
that f
can also be expressed as f
DDS
PIO
) completely
−−+
)1(
γβe
jωωj
++−−+
γeγe
is the DAC sample
S
= fR(S/R).
DDS
⎞
⎟
⎟
)1()2(
⎠
Rev. 0 | Page 21 of 68
The three coefficients are calculated according to parameters
he following equations:
via t
)tan(4 ΦPfβ
C
1
=
α
βΦFγ )(
2
−=
⎛
⎜
⎜
⎝
38
π
2
7
⎞
⎟
⎟
GainFPFD
_10
⎠
βΦFff
)(
CDDS
where:
f
LOOP
1
1)(
)sin(
Φ
f
S
f
ΦF +=
C
=
FPFD_Gain is the value of the gain scale factor for the fine
phas
e detector as programmed into the I/O register map.
Note that the range of loop filter coefficients is limited as
fol
lows:
0 < α < 2
23
(~8.39 × 106)
−0.125 < β < 0
−0.125 < γ < 0
The preceding constraints on β and γ constrain the closed-loop
hase margin such that both β and γ assume negative values.
p
Even though β and γ are limited to negative quantities, the
values as programmed are positive. The negative sign is
assumed internally.
Note that the closed-loop phase margin is limited to the range
f 0° < Φ < 90° because β and γ are negative.
o
The three coefficients are implemented as digital elements,
n
ecessitating quantized values. Determination of the
programmed coefficient values in this context follows.
The quantized α coefficient is composed of three factors, where
α
, α1, and α2 are the programmed values for the α coefficient.
0
α
⎞
⎛
α
QUANTIZED
0
=
⎜
2048
⎝
⎟
⎠
The boundary values for each are 0 ≤ α
and 0 ≤ α
≤ 7. The optimal values of α0, α1, and α2 are
2
⎡
=
α
1
=
α
0
⎧
⎢
⎨
⎢
⎩
⎣
⎡
⎧
⎪
⎢
⎨
⎪
⎢
⎩
⎣
αα
−
()(
21
22
⎛
logceil,22min,0max
⎜
⎝
⎛
⎜
logfloor,7min,0max
⎜
⎝
()
)
≤ 4095, 0 ≤ α1 ≤ 22,
0
⎤
⎫
2048
α
⎞
⎟
⎥
4095
4095
×=
⎬
⎠
⎥
⎭
⎦
⎞
⎟
α
⎠
11
+−
αα
12
}
2round,4095min,0max
]
2
⎛
⎜
2 12
⎝
αα
⎤
⎫
⎞
⎪
⎟
−α+
11
⎥
⎬
⎟
⎪
⎥
⎠
⎭
⎦
The magnitude of the quantized β coefficient is composed of
o factors.
tw
)15(2+−
β
1
)
=
where β
ββ
QUANTIZED
and β 1 are the programmed values for the β
0
0
coefficient.
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