ANALOG DEVICES AD9523 Service Manual
Low Jitter Clock Generator with
14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs
FEATURES
Output frequency: <1 MHz to 1 GHz
Start-up frequency accuracy: <±100 ppm (determined by
VCXO reference accuracy)
Zero delay operation
Input-to-output edge timing: <150 ps
14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
14 dedicated output dividers with jitter-free adjustable delay
Adjustable delay: 63 resolution steps of ½ period of VCO
output divider
Output-to-output skew: <50 ps
Duty-cycle correction for odd divider settings
Automatic synchronization of all outputs on power-up
Absolute output jitter: <200 fs at 122.88 MHz
Integration range: 12 kHz to 20 MHz
Distribution phase noise floor: −160 dBc/Hz
Digital lock detect
Nonvolatile EEPROM stores configuration settings
SPI- and I²C-compatible serial control port
Dual PLL architecture
PLL1
Low bandwidth for reference input clock cleanup with
external VCXO
Phase detector rate of 300 kHz to 75 MHz
Redundant reference inputs
Auto and manual reference switchover modes
Revertive and nonrevertive switching
Loss of reference detection with holdover mode
Low noise LVCMOS output from VCXO used for RF/IF
synthesizers
PLL2
Phase detector rate of up to 250 MHz
Integrated low noise VCO
APPLICATIONS
LTE and multicarrier GSM base stations
Wireless and broadband infrastructure
Medical instrumentation
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
and other 10 Gbps protocols
Forward error correction (G.710)
High performance wireless transceivers
ATE and high performance instrumentation
AD9523
FUNCTIONAL BLOCK DIAGRAM
OSC_IN, OSC_IN
REFA,
REFA
REFB,
REFB
REF_TEST
SCLK/SCL
SDIO/SDA
SDO
PLL1
CONTRO L
INTERFACE
(SPI AND I
EEPROM
PLL2
2
C)
ZD_IN, ZD_IN
Figure 1.
ZERO
DELAY
GENERAL DESCRIPTION
The AD9523 provides a low power, multi-output, clock distribution
function with low jitter performance, along with an on-chip PLL
and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz.
The AD9523 is defined to support the clock requirements for
long term evolution (LTE) and multicarrier GSM base station
designs. It relies on an external VCXO to provide the reference
jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.
The input receivers, oscillator, and zero delay receiver provide
both single-ended and differential operation. When connected
to a recovered system reference clock and a VCXO, the device
generates 14 low noise outputs with a range of 1 MHz to 1 GHz,
and one dedicated buffered output from the input PLL (PLL1).
The frequency and phase of one clock output relative to another
clock output can be varied by means of a divider phase select
function that serves as a jitter-free coarse timing adjustment in
increments that are equal to half the period of the signal
coming out of the VCO.
An in-package EEPROM can be programmed through the serial
interface to store user-defined register settings for power-up
and chip reset.
AD9523
14-CLOCK
DISTRIBUTI ON
OUT0,
OUT0
OUT1,
OUT1
OUT12,
OUT12
OUT13,
OUT13
08439-001
Rev. B
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AD9523
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Conditions..................................................................................... 4
Supply Current.............................................................................. 4
Power Dissipation......................................................................... 5
REFA
REFA,
ZD_IN
OSC_CTRL Output Characteristics .......................................... 6
REF_TEST Input Characteristics............................................... 6
PLL1 Output Characteristics ...................................................... 6
Distribution Output Characteristics (OUT0,
OUT13,
Timing Alignment Characteristics............................................. 8
Jitter and Noise Characteristics .................................................. 8
PLL2 Characteristics .................................................................... 9
Logic Input Pins—PD, EEPROM_SEL, REF_SEL,
SYNC
Status Output Pins—STATUS1, STATUS0 ............................... 9
Serial Control Port—SPI Mode................................................ 10
Serial Control Port—IC Mode................................................ 11
Absolute Maximum Ratings.......................................................... 12
Thermal Resistance .................................................................... 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions........................... 13
Typical Performance Characteristics ........................................... 16
, REFB,
Input Characteristics...................................................... 5
OUT13
.............................................................................................. 9
REFB
, OSC_IN,
) .......................................................................... 7
OSC_IN
, and ZD_IN,
OUT0
to
RESET
,
Input/Output Termination Recommendations.......................... 18
Terminology.................................................................................... 19
Theory of Operation ...................................................................... 20
Detailed Block Diagram ............................................................ 20
Overview ..................................................................................... 20
Component Blocks—Input PLL (PLL1).................................. 21
Component Blocks—Output PLL (PLL2) .............................. 22
Clock Distribution ..................................................................... 24
Zero Delay Operation................................................................ 26
Serial Control Port ......................................................................... 27
SPI/IC Port Selection................................................................ 27
IC Serial Port Operation.......................................................... 27
SPI Serial Port Operation.......................................................... 30
SPI Instruction Word (16 Bits)................................................. 31
SPI MSB/LSB First Transfers .................................................... 31
EEPROM Operations..................................................................... 34
Writing to the EEPROM ........................................................... 34
Reading from the EEPROM ..................................................... 34
Programming the EEPROM Buffer Segment......................... 35
Power Dissipation and Thermal Considerations....................... 37
Clock Speed and Driver Mode ................................................. 37
Evaluation of Operating Conditions........................................ 37
Thermally Enhanced Package Mounting Guidelines............ 38
Control Registers............................................................................ 39
Control Register Map ................................................................ 39
Control Register Map Bit Descriptions................................... 44
Outline Dimensions....................................................................... 56
Ordering Guide .......................................................................... 56
Rev. B | Page 2 of 56
AD9523
REVISION HISTORY
3/11—Rev. A to Rev. B
Added Table Summary, Table 8.......................................................7
Cha
o EEPROM Operations Section and Writing to the
nges t
EEPROM Section ............................................................................34
Changes to 0x01A, Bits[4:3], Table 30.......................................... 39
Changes to Bits[4:3], Table 40 .......................................................46
Changes to Table 47, Bit 1 ..............................................................48
11/10—Rev. 0 to Rev. A
Change to General Description....................................................... 1
Changes to Table Summary, Table 1............................................... 3
Change to Input High Voltage and Input Low Voltage
Parameters and Added Input Threshold Voltage Parameter,
Table 4................................................................................................. 4
Change to Junction Temperature Rating, Table 16; Changes
to Thermal Resistance Section ......................................................11
Changes to Table 18 ........................................................................12
Added Figure 14, Renumbered Sequentially............................... 16
Edits to Figure 15, Figure 17, and Figure 19................................ 17
Changes to VCO Calibration Section...........................................22
Changed Output Mode Heading to Multimode Output
Drivers; Changes to Multimode Output Drivers Section;
Added Figure 26.............................................................................. 23
Added Power Dissipation and Thermal Considerations
Section; Added Table 29, Renumbered Sequentially.................. 35
Changes to Table 34, Table 35, Table 36, and Table 38............... 43
Changes to Address 0x192, Table 50 ............................................ 48
Changes to Table 52 ........................................................................49
Changes to Table 54 ........................................................................50
7/10—Revision 0: Initial Version
Rev. B | Page 3 of 56
AD9523
SPECIFICATIONS
f
= 122.88 MHz single ended, REFA and REFB on differential at 30.72 MHz, f
VCXO
power mode off, divider phase =1, unless otherwise noted. Typical is given for VDD = 3.3 V ± 5%, and T
noted. Minimum and maximum values are given over the full VDD, and T
(−40°C to +85°C) variation, as listed in Tabl e 1.
A
CONDITIONS
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY VOLTAGE
VDD3_PLL1, Supply Voltage for PLL1 3.3 V 3.3 V ± 5%
VDD3_PLL2, Supply Voltage for PLL2 3.3 V 3.3 V ± 5%
VDD3_REF, Supply Voltage Clock Output Drivers Reference 3.3 V 3.3 V ± 5%
VDD1.8_PLL2, Supply Voltage for PLL2 1.8 V 1.8 V ± 5%
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 3.3 V 3.3 V ± 5%
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers 1.8 V 1.8 V ± 5%
TEMPERATURE RANGE, TA −40 +25 +85 °C
1
x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0,
respectively) and Supply Voltage Clock Output OUT1,
OUT1
(Pin 65 and Pin 64, respectively).
SUPPLY CURRENT
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS
VDD3_PLL1, Supply Voltage for PLL1 22 25.2 mA Decreases by 9 mA typical if REFB is turned off
VDD3_PLL2, Supply Voltage for PLL2 67 77.7 mA
VDD3_REF, Supply Voltage Clock Output Drivers Reference
LVPECL Mode 5 6 mA
LVDS Mode 4 4.8 mA
HSTL Mode 3 3.6 mA
CMOS Mode 3 3.6 mA
VDD1.8_PLL2, Supply Voltage for PLL2 15 18 mA
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers2 3.5 4.2 mA Current for each divider: f = 245.76 MHz
CLOCK OUTPUT DRIVERS
LVDS Mode, 7 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 16 17.4 mA f = 61.44 MHz
LVDS Mode, 3.5 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 5 6.2 mA f = 245.76 MHz
LVPECL Mode
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 17 18.9 mA f = 122.88 MHz
HSTL Mode, 16 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 21 24.0 mA f = 122.88 MHz
HSTL Mode, 8 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 14 16.3 mA f = 122.88 MHz
CMOS Mode (Single-Ended)
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 2 2.4 mA f = 15.36 MHz, 10 pF Load
1
x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0,
respectively) and Supply Voltage Clock Output OUT1,
2
The current for Pin 63 (VDD1.8_OUT[0:3]) is 2× that of the other VDD1.8_OUT[x:y] pairs.
OUT1
(Pin 65 and Pin 64, respectively).
Rev. B | Page 4 of 56
= 3932.16 MHz, doubler is off, channel control low
VCO
A = 25°C, unless otherwise
OUT0
(Pin 68 and Pin 67,
Only one output driver turned on; for each
additional output that is turned on, the
current increments by 1.2 mA maximum
Only one output driver turned on; for each
additional output that is turned on, the
current increments by 1.2 mA maximum
Values are independent of the number of
outputs turned on
Values are independent of the number of
outputs turned on
OUT0
(Pin 68 and Pin 67,
AD9523
POWER DISSIPATION
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER DISSIPATION Does not include power dissipated in termination resistors
Typical Configuration 891
1047.
1
PD, Power-Down
101 132.2 mW
INCREMENTAL POWER DISSIPATION
Low Power Typical Configuration 367 428.4 mW
Output Distribution, Driver On Incremental power increase (OUT1) from low power typical
LVDS 15.3 18.4 mW Single 3.5 mA LVDS output at 245.76 MHz
47.8 55.4 mW Single 7 mA LVDS output at 61.44 MHz
LVPECL 50.1 54.9 mW Single LVPECL output at 122.88 MHz
HSTL 40.2 46.3 mW Single 8 mA HSTL output at 122.88 MHz
43.7 50.3 mW Single 16 mA HSTL output at 122.88 MHz
CMOS 6.6 7.9 mW Single 3.3 V CMOS output at 15.36 MHz
9.9 11.9 mW Dual complementary 3.3 V CMOS output at 122.88 MHz
9.9 11.9 mW Dual in-phase 3.3 V CMOS output at 122.88 MHz
REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, AND ZD_IN, ZD_IN INPUT CHARACTERISTICS
mW
Clock distribution outputs running as follows: seven LVPECL outputs
at 122.88 MHz, three LVDS outputs (3.5 mA) at 61.44 MHz, three
LVDS outputs (3.5 mA) at 245.76 MHz, one CMOS 10 pF load at
122.88 MHz, and one differential input reference at 30.72 MHz;
f
= 122.88 MHz, f
VCXO
= 3932.16 MHz; PLL2 BW = 530 kHz,
VCO
doubler is off
PD pin pulled low, with typical configuration conditions
Absolute total power with clock distribution; one LVPECL output
running at 122.88 MHz; one differential input reference at
30.72 MHz; f
= 122.88 MHz, f
VCXO
= 3932.16 MHz; doubler is off
VCO
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
DIFFERENTIAL MODE
Input Frequency Range 400 MHz
Input Slew Rate (OSC_IN) 400 V/µs Minimum limit imposed for jitter performance
Common-Mode Internally
0.6 0.7 0.8 V
Generated Input Voltage
Input Common-Mode Range 1.025 1.475 V For dc-coupled LVDS (maximum swing)
Differential Input Voltage,
Sensitivity Frequency < 250 MHz
100 mV p-p
Capacitive coupling required; can accommodate single-ended
input by ac grounding of unused input; the instantaneous voltage
on either pin must not exceed the 1.8 V dc supply rails
Differential Input Voltage,
Sensitivity Frequency > 250 MHz
200 mV p-p
Capacitive coupling required; can accommodate single-ended
input by ac grounding of unused input; the instantaneous voltage
on either pin must not exceed the 1.8 V dc supply rails
Differential Input Resistance 4.8 kΩ
Differential Input Capacitance 1 pF
Duty Cycle Duty cycle bounds are set by pulse width high and pulse width low
Pulse Width Low 1 ns
Pulse Width High 1 ns
CMOS MODE SINGLE-ENDED INPUT
Input Frequency Range 250 MHz
Input High Voltage 1.62 V
Input Low Voltage 0.52 V
Input Threshold Voltage 1.0 V
When ac coupling to the input receiver, the user must dc bias the
input to 1 V; the singl-ended CMOS input is 3.3 V compatible
Input Capacitance 1 pF
Duty Cycle Duty cycle bounds are set by pulse width high and pulse width low
Pulse Width Low 1.6 ns
Pulse Width High 1.6 ns
Rev. B | Page 5 of 56
AD9523
OSC_CTRL OUTPUT CHARACTERISTICS
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
OUTPUT VOLTAGE
High VDD3_PLL1 − 0.15 V R
Low 150 mV
REF_TEST INPUT CHARACTERISTICS
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
REF_TEST INPUT
Input Frequency Range 250 MHz
Input High Voltage 2.0 V
Input Low Voltage 0.8 V
PLL1 OUTPUT CHARACTERISTICS
Table 7.
Parameter1 Min Typ Max Unit Test Conditions/Comments
MAXIMUM OUTPUT FREQUENCY 250 MHz
Rise/Fall Time (20% to 80%) 387 665 ps 15 pF load
Duty Cycle 45 50 55 % f = 250 MHz
OUTPUT VOLTAGE HIGH Output driver static
VDD3_PLL1 − 0.25 V Load current = 10 mA
VDD3_PLL1 − 0.1 V Load current = 1 mA
OUTPUT VOLTAGE LOW Output driver static
0.2 V Load current = 10 mA
0.1 V Load current = 1 mA
1
CMOS driver strength = strong (see Table 51).
LOAD
> 20 kΩ
Rev. B | Page 6 of 56
AD9523
DISTRIBUTION OUTPUT CHARACTERISTICS (OUT0, OUT0 TO OUT13, OUT13)
Duty cycle performance is specified with the invert divider bit set to 1, and the divider phase bits set to 0.5. (For example, for Channel 0,
0x190[7] = 1 and 0x192[7:2] = 1.)
Table 8.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL MODE
Maximum Output Frequency 1 GHz Minimum VCO/maximum dividers
Rise Time/Fall Time (20% to 80%) 117 147 ps 100 Ω termination across output pair
Duty Cycle 47 50 52 % f < 500 MHz
43 48 52 % f = 500 MHz to 800 MHz
40 49 54 % f = 800 MHz to 1 GHz
Differential Output Voltage Magnitude 643 775 924 mV Voltage across pins, output driver static
Common-Mode Output Voltage VDD – 1.5 VDD − 1.4 VDD − 1.25 V Output driver static
SCALED HSTL MODE, 16 mA
Maximum Output Frequency 1 GHz Minimum VCO/maximum dividers
Rise Time/Fall Time (20% to 80%) 112 141 ps 100 Ω termination across output pair
Duty Cycle 47 50 52 % f < 500 MHz
44 48 51 % f = 500 MHz to 800 MHz
40 49 54 % f = 800 MHz to 1 GHz
Differential Output Voltage Magnitude 1.3 1.6 1.7 V
Supply Sensitivity 0.6
Common-Mode Output Voltage VDD − 1.76 VDD − 1.6 VDD − 1.42 V
LVDS MODE, 3.5 mA
Maximum Output Frequency 1 GHz
Rise Time/Fall Time (20% to 80%) 138 161 ps 100 Ω termination across output pair
Duty Cycle 48 51 53 % f < 500 MHz
43 49 53 % f = 500 MHz to 800 MHz
41 49 55 % f = 800 MHz to 1 GHz
Differential Output Voltage Magnitude
Balanced 247 454 mV Voltage across pins; output driver static
Unbalanced 50 mV
Common-Mode Output Voltage 1.125 1.375 V Output driver static
Common-Mode Difference 50 mV
Short-Circuit Output Current 3.5 24 mA Output driver static
CMOS MODE
Maximum Output Frequency 250 MHz
Rise Time/Fall Time (20% to 80%) 387 665 ps 15 pF load
Duty Cycle 45 50 55 % f = 250 MHz
Output Voltage High Output driver static
VDD − 0.25 V Load current = 10 mA
VDD − 0.1 V Load current = 1 mA
Output Voltage Low Output driver static
0.2 V Load current = 10 mA
0.1 V Load current = 1 mA
mV/
mV
Voltage across pins, output driver static;
nominal supply
Change in output swing vs. VDD3_OUT[x:y]
/∆VDD3)
(∆V
OD
Absolute difference between voltage magnitude
of normal pin and inverted pin
Voltage difference between output pins;
output driver static
Rev. B | Page 7 of 56
AD9523
TIMING ALIGNMENT CHARACTERISTICS
Table 9.
Parameter Min Typ Max Unit Test Conditions/Comments
OUTPUT TIMING SKEW
Between Outputs in Same Group1
LVPECL, HSTL, and LVDS
Between LVPECL, HSTL, and LVDS
30 183 ps
Outputs
CMOS
Between CMOS Outputs 100 300 ps Single-ended true phase high-Z mode
Mean Delta Between Groups1 50
Adjustable Delay 0 63 Steps Resolution step; for example, 8 × 0.5/1 GHz
Resolution Step 500 ps ½ period of 1 GHz
Zero Delay
Between Input Clock Edge on REFA or
150 500 ps
REFB to ZD_IN Input Clock Edge,
External Zero Delay Mode
1
There are three groups of outputs. They are as follows: the top outputs group: OUT0, OUT1, OUT2, OUT3; the right outputs group: OUT4, OUT5, OUT6, OUT7, OUT8,
OUT9; and the bottom outputs group: OUT10, OUT11, OUT12, OUT13.
Delay off on all outputs; maximum deviation between rising
edges of outputs; all outputs are on, unless otherwise noted
PLL1 settings: PFD = 7.68 MHz, ICP = 63.5 µA, R
= 10 kΩ,
ZERO
antibacklash pulse width is at maximum, BW = 40 Hz, REFA
and ZD_IN are set to differential mode
JITTER AND NOISE CHARACTERISTICS
Table 10.
Parameter Min Typ Max Unit Test Conditions/Comments
OUTPUT ABSOLUTE RMS TIME JITTER
LVPECL Mode, HSTL Mode, LVDS Mode
125 fs Integrated BW = 200 kHz to 5 MHz
136 fs Integrated BW = 200 kHz to 10 MHz
169 fs Integrated BW = 12 kHz to 20 MHz
212 fs Integrated BW = 10 kHz to 61 MHz
223 fs Integrated BW = 1 kHz to 61 MHz
Application example based on a typical setup (see Table 3);
f = 122.88 MHz
Rev. B | Page 8 of 56
AD9523
PLL2 CHARACTERISTICS
Table 11.
Parameter Min Typ Max Unit Test Conditions/Comments
VCO (ON CHIP)
Frequency Range 3600 4000 MHz
Gain 45 MHz/V
PLL2 FIGURE OF MERIT (FOM) −226 dBc/Hz
MAXIMUM PFD FREQUENCY
Antibacklash Pulse Width
Minimum and Low 250 MHz
Maximum and High 125 MHz
LOGIC INPUT PINS—PD, EEPROM_SEL, REF_SEL, RESET, SYNC
Table 12.
Parameter Min Typ Max Unit Test Conditions/Comments
VOLTAGE
Input High 2.0 V
Input Low 0.8 V
INPUT LOW CURRENT ±80 ±250 µA
CAPACITANCE 3 pF
RESET TIMING
Pulse Width Low 50 ns
Inactive to Start of Register Programming 100 ns
SYNC TIMING
Pulse Width Low 1.5 ns High speed clock is CLK input signal
The minus sign indicates that, due to the
internal pull-up resistor, current is flowing
out of the AD9523
STATUS OUTPUT PINS—STATUS1, STATUS0
Table 13.
Parameter Min Typ Max Unit Test Conditions/Comments
VOLTAGE
Output High 2.94 V
Output Low 0.4 V
Rev. B | Page 9 of 56
AD9523
SERIAL CONTROL PORT—SPI MODE
Table 14.
Parameter Min Typ Max Unit Test Conditions/Comments
CS (INPUT)
Voltage
Input Logic 1 2.0 V
Input Logic 0 0.8 V
Current
Input Logic 1 30 µA
Input Logic 0 −110 µA
Input Capacitance 2 pF
SCLK (INPUT) IN SPI MODE
Voltage
Input Logic 1 2.0 V
Input Logic 0 0.8 V
Current
Input Logic 1 240 µA
Input Logic 0 1 µA
Input Capacitance 2 pF
SDIO (WHEN INPUT IS IN BIDIRECTIONAL MODE)
Voltage
Input Logic 1 2.0 V
Input Logic 0 0.8 V
Current
Input Logic 1 1 µA
Input Logic 0 1 µA
Input Capacitance 2 pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage 2.7 V
Output Logic 0 Voltage 0.4 V
TIMING
Clock Rate (SCLK, 1/t
Pulse Width High, t
Pulse Width Low, t
) 25 MHz
SCLK
8 ns
HIGH
12 ns
LOW
SDIO to SCLK Setup, tDS 3.3 ns
SCLK to SDIO Hold, tDH 0 ns
SCLK to Valid SDIO and SDO, tDV 14 ns
CS to SCLK Setup, tS
CS to SCLK Setup and Hold, tS, tC
CS Minimum Pulse Width High, t
PWH
CS has an internal 40 kΩ pull-up resistor
The minus sign indicates that, due to the
internal pull-up resistor, current is flowing out
of the AD9523
SCLK has an internal 40 kΩ pull-down resistor
in SPI mode but not in I
10 ns
0 ns
6 ns
2
C mode
Rev. B | Page 10 of 56
AD9523
SERIAL CONTROL PORT—I²C MODE
VDD = VDD3_REF, unless otherwise noted.
Table 15.
Parameter Min Typ Max Unit Test Conditions/Comments
SDA, SCL (WHEN INPUTTING DATA)
Input Logic 1 Voltage 0.7 × VDD V
Input Logic 0 Voltage 0.3 × VDD V
Input Current with an Input Voltage Between
0.1 × VDD and 0.9 × VDD
Hysteresis of Schmitt Trigger Inputs 0.015 × VDD V
Pulse Width of Spikes That Must Be
Suppressed by the Input Filter, t
SPIKE
SDA (WHEN OUTPUTTING DATA)
Output Logic 0 Voltage at 3 mA Sink Current 0.4 V
Output Fall Time from VIH
MIN
to VIL
MAX
with
a Bus Capacitance from 10 pF to 400 pF
TIMING
Clock Rate (SCL, f
) 400 kHz
I2C
Bus Free Time Between a Stop and Start
Condition, t
IDLE
Setup Time for a Repeated Start Condition,
t
SET; STR
Hold Time (Repeated) Start Condition, t
Setup Time for Stop Condition, t
Low Period of the SCL Clock, t
High Period of the SCL Clock, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t
20 + 0.1 C
RISE
20 + 0.1 C
FAL L
100 ns
SET; DAT
100 880 ns
HLD; DAT
Capacitive Load for Each Bus Line, C
1
CB is the capacitance of one bus line in picofarads (pF).
2
According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL
falling edge.
HLD; STR
0.6 µs
SET; STP
1.3 µs
LOW
0.6 µs
HIGH
1
400 pF
B
−10 +10 µA
50 ns
1
20 + 0.1 C
250 ns
B
Note that all I
VIH
MIN
1.3 µs
0.6 µs
0.6 µs
After this period, the first clock pulse is
generated
1
300 ns
B
1
300 ns
B
This is a minor deviation from the original I²C
specification of 0 ns minimum2
2
C timing values are referred to
(0.3 × VDD) and VIL
levels (0.7 × VDD)
MAX
Rev. B | Page 11 of 56
AD9523
ABSOLUTE MAXIMUM RATINGS
Table 16.
Parameter Rating
VDD3_PLL1, VDD3_PLL2, VDD3_REF,
−0.3 V to +3.6 V
VDD3_OUT, LDO_VCO to GND
REFA, REFA, REFIN, REFB, REFB to GND
SCLK/SCL, SDIO/SDA, SDO, CS to GND
OUT0, OUT0, OUT1, OUT1, OUT2, OUT2,
OUT3, OUT3
, OUT4, OUT4, OUT5, OUT5,
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
OUT6, OUT6, OUT7, OUT7, OUT8, OUT8,
OUT9, OUT9
, OUT10, OUT10, OUT11,
OUT11, OUT12, OUT12, OUT13, OUT13
to GND
SYNC, RESET, PD to GND
−0.3 V to +3.6 V
STATUS0, STATUS1 to GND −0.3 V to +3.6 V
SP0, SP1, EEPROM_SEL to GND −0.3 V to +3.6 V
VDD1.8_PLL2, VDD1.8_OUT, LDO_PLL1,
2 V
LDO_PLL2 to GND
Junction Temperature1 115°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (10 sec) 300°C
1
See Table 17 for θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 17. Thermal Resistance
Package Type
72-Lead LFCSP,
10 mm ×
10 mm
1
Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.
2
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
For information about power dissipation, refer to the Power
Dissipation and Thermal Considerations section.
ESD CAUTION
Airflow
Velocity
(m/sec) θ
1, 2
1, 3
θ
JA
JC
1, 4
θ
JB
1, 2
Ψ
Unit
JT
0 21.3 1.7 12.6 0.1 °C/W
1.0 20.1 0.2 °C/W
2.5 18.1 0.3 °C/W
Rev. B | Page 12 of 56
AD9523
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PLL1_OUT
ZD_IN
ZD_IN
VDD1.8_PLL2
OUT0
OUT0
VDD3_OUT[0:1]
OUT1
OUT1
VDD1.8_OUT[0: 3]
OUT2
OUT2
VDD3_OUT[2:3]
OUT3
OUT3
EEPROM_SEL
STATUS0/SP0
STATUS1/SP1
7271706968676665646362616059585756
55
LDO_PLL1
VDD3_PLL1
LF1_EXT _CAP
OSC_CTRL
LF2_EXT _CAP
LDO_PLL2
VDD3_PLL2
LDO_VCO
REF_SE L
NOTES
1. THE EXPOSED PADDLE IS THE GROUND CONNECTION ON THE CHIP. IT MUST BE
SOLDERED TO THE ANALOG GRO UND OF THE PCB TO ENSURE PROPER FUNCTI ONALITY
AND HEAT DISSIPATION, NOISE, AND MECHANICA L STRENGTH BENEFITS.
REFA
REFA
REFB
REFB
OSC_IN
OSC_IN
PD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17SYNC
18VDD3_REF
PIN 1
INDICATOR
192021222324252627282930313233
CS
SDO
RESET
SDIO/SDA
SCLK/SCL
REF_TEST
AD9523
(TOP VIEW)
OUT13
OUT13
OUT12
VDD3_OUT[12:13]
VDD1.8_OUT[ 4:5]
54
OUT4
53
OUT4
52
VDD3_OUT[4:5]
51
OUT5
50
OUT5
49
VDD1.8_OUT[ 6:7]
48
OUT6
47
OUT6
46
VDD3_OUT[6:7]
45
OUT7
44
OUT7
43
VDD1.8_OUT[ 8:9]
42
OUT8
41
OUT8
40
VDD3_OUT[8:9]
39
OUT9
38
OUT9
37
35OUT10
36VDD1.8_OUT[10:11]
34
OUT11
OUT11
OUT12
VDD1.8_OUT[ 12:13]
OUT10
VDD3_OUT[10: 11]
08439-002
Figure 2. Pin Configuration
Table 18. Pin Function Descriptions
Pin
No.
Mnemonic Type
1 LDO_PLL1 P/O
1
Description
1.8 V Internal LDO Regulator Decoupling Pin for PLL1. Connect a 0.47 µF decoupling capacitor from
this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in
close proximity to the device.
2 VDD3_PLL1 P 3.3 V Supply PLL1. Use the same supply as VCXO.
3 REFA I
Reference Clock Input A. Along with REFA
, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
4
REFA
I
Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for the
PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3V CMOS input.
5 REFB I
Reference Clock Input B. Along with REFB
, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
6
REFB
I
Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL
reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
7 LF1_EXT_CAP O PLL1 External Loop Filter Capacitor. Connect this pin to ground.
8 OSC_CTRL O Oscillator Control Voltage. Connect this pin to the voltage control pin of the external oscillator.
9 OSC_IN I
PLL1 Oscillator Input. Along with OSC_IN
, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
10
OSC_IN
I
Complementary PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL
reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
11 LF2_EXT_CAP O PLL2 External Loop Filter Capacitor Connection. Connect capacitor to this pin and the LDO_VCO pin.
12 LDO_PLL2 P/O
LDO Decoupling Pin for PLL2 1.8 V Internal Regulator. Connect a 0.47 F decoupling capacitor from
this pin to ground. Note that for best performance, the LDO bypass capacitor must be placed in close
proximity to the device.
13 VDD3_PLL2 P 3.3 V Supply for PLL2.
Rev. B | Page 13 of 56
AD9523
Pin
No. Mnemonic Type
14 LDO_VCO P/O
15
PD
16 REF_SEL I Reference Input Select. This pin has an internal 40 kΩ pull-down resistor.
17
SYNC
18 VDD3_REF P 3.3 V Supply for Output Clock Drivers Reference.
19
20
RESET
CS
21 SCLK/SCL I
22 SDIO/SDA I/O Serial Control Port Bidirectional Serial Data In/Data Out for SPI Mode (SDIO) or I²C Mode (SDA).
23 SDO O
24 REF_TEST I Test Input to PLL1 Phase Detector.
25
OUT13
26 OUT13 O
27 VDD3_OUT[12:13] P 3.3 V Supply for Output 12 and Output 13 Clock Drivers.
28
OUT12
29 OUT12 O
30 VDD1.8_OUT[12:13] P 1.8 V Supply for Output 12 and Output 13 Clock Dividers.
31
OUT11
32 OUT11 O
33 VDD3_OUT[10:11] P 3.3 V Supply for Output 10 and Output 11 Clock Drivers.
34
OUT10
35 OUT10 O
36 VDD1.8_OUT[10:11] P 1.8 V Supply for Output 10 and Output 11 Clock Dividers.
37
OUT9
38 OUT9 O
39 VDD3_OUT[8:9] P 3.3 V Supply for Output 8 and Output 9 Clock Drivers.
40
OUT8
41 OUT8 O
42 VDD1.8_OUT[8:9] P 1.8 V Supply for Output 8 and Output 9 Clock Dividers.
43
OUT7
44 OUT7 O
45 VDD3_OUT[6:7] P 3.3 V Supply for Output 6 and Supply Output 7 Clock Drivers.
46
OUT6
47 OUT6 O
1
Description
2.5 V LDO Internal Regulator Decoupling Pin for VCO. Connect a 0.47 µF decoupling capacitor from
this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in
close proximity to the device.
I Chip Power-Down, Active Low. This pin has an internal 40 kΩ pull-up resistor.
I
Manual Synchronization. This pin initiates a manual synchronization and has an internal 40 kΩ pull-up
resistor.
I
Digital Input, Active Low. Resets internal logic to default states. This pin has an internal 40 kΩ pull-up
resistor.
I Serial Control Port Chip Select, Active Low. This pin has an internal 40 kΩ pull-up resistor.
2
Serial Control Port Clock Signal for SPI Mode (SCLK) or I
C Mode (SCL). Data clock for serial program-
ming. This pin has an internal 40 kΩ pull-down resistor in SPI mode but is high impedance in I²C mode.
Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in 3-wire mode). There
is no internal pull-up/pull-down resistor on this pin.
O
Complementary Square Wave Clocking Output 13. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 13. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
O
Complementary Square Wave Clocking Output 12. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 12. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
O
Complementary Square Wave Clocking Output 11. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 11. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
O
Complementary Square Wave Clocking Output 10. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 10. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
O
Complementary Square Wave Clocking Output 9. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 9. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
O
Complementary Square Wave Clocking Output 8. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 8. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
O
Complementary Square Wave Clocking Output 7. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 7. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
O
Complementary Square Wave Clocking Output 6. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 6. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
Rev. B | Page 14 of 56
AD9523
Pin
No. Mnemonic Type
48 VDD1.8_OUT[6:7] P 1.8 V Supply for Output 6 and Output 7 Clock Dividers.
49
OUT5
50 OUT5 O
51 VDD3_OUT[4:5] P 3.3 V Supply for Output 4 and Output 5 Clock Drivers.
52
OUT4
53 OUT4 O
54 VDD1.8_OUT[4:5] P 1.8 V Supply for Output 4 and Output 5 Clock Dividers.
55 STATUS1/SP1 I/O
56 STATUS0/SP0 I/O
57 EEPROM_SEL I
58
OUT3
59 OUT3 O
60 VDD3_OUT[2:3] P 3.3 V Supply for Output 2 and Output 3 Clock Drivers.
61
OUT2
62 OUT2 O
63 VDD1.8_OUT[0:3] P 1.8 V Supply for Output 0, Output 1, Output 2, and Output 3 Clock Dividers.
64
OUT1
65 OUT1 O
66 VDD3_OUT[0:1] P 3.3 V Supply for Output 0 and Output 1 Clock Drivers.
67
OUT0
68 OUT0 O
69 VDD1.8_PLL2 P 1.8 V Supply for PLL2.
70 ZD_IN I
71
ZD_IN
72 PLL1_OUT O
EP EP, GND GND
1
P = power, I = input, O = output, I/O = input/output, P/O = power/output, GND = ground.
1
Description
O
Complementary Square Wave Clocking Output 5. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 5. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
O
Complementary Square Wave Clocking Output 4. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 4. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
Lock Detect and Other Status Signals (STATUS1)/I
down resistor.
Lock Detect and Other Status Signals (STATUS0)/I
down resistor.
EEPROM Select. Setting this pin high selects the register values stored in the internal EEPROM to be
loaded at reset and/or power-up. Setting this pin low causes the AD9523 to load the hard-coded
default register values at power-up/reset. This pin has an internal 40 kΩ pull-down resistor.
O
Complementary Square Wave Clocking Output 3. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 3. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
O
Complementary Square Wave Clocking Output 2. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 2. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
O
Complementary Square Wave Clocking Output 1. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 1. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
O
Complementary Square Wave Clocking Output 0. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 0. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
External Zero Delay Clock Input. Along with ZD_IN
reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
I
Complementary External Zero Delay Clock Input. Along with ZD_IN, this pin is the differential input
for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
Single-Ended CMOS Output from PLL1. This pin has settings for weak and strong in Register 0x1BA,
Bit 4 (see Table 51).
Exposed Paddle. The exposed paddle is the ground connection on the chip. It must be soldered to
the analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and
mechanical strength benefits.
2
C Address (SP1). This pin has an internal 40 kΩ pull-
2
C Address (SP0). This pin has an internal 40 kΩ pull-
, this pin is the differential input for the PLL
Rev. B | Page 15 of 56
AD9523
A
TYPICAL PERFORMANCE CHARACTERISTICS
f
= 122.88 MHz, REFA differential at 30.72 MHz, f
VCXO
60
50
40
30
CURRENT (mA)
20
HSTL = 16mA
HSTL = 8mA
= 3686.4 MHz, and doubler is off, unless otherwise noted.
VCO
35
30
25
20
15
CURRENT (mA)
10
20pF
10pF
2pF
10
0
0 200 400 600 800 1000 1200
FREQUENCY ( MHz)
08439-003
Figure 3. VDD3_OUT[x:y] Current (Typical) vs. Frequency;
HSTL Mode, 16 mA and 8 mA
45
40
35
30
25
20
CURRENT (mA)
15
10
5
0
0 200 400 600 800 1000 1200
LVD S = 7 mA
LVDS = 3.5mA
08439-004
FREQUENCY ( MHz)
Figure 4. VDD3_OUT[x:y] Current (Typical) vs. Frequency;
LVDS Mode, 7 mA and 3.5 mA
45
40
35
30
25
20
CURRENT (mA)
15
10
5
0
0 200 400 600 800 1000 1200
FREQUENCY ( MHz)
08439-005
Figure 5. VDD3_OUT[x:y] Current (Typical) vs. Frequency, LVPECL Mode
5
0
0 100 200 300 400 500 600
FREQUENCY ( MHz)
08439-006
Figure 6. VDD3_OUT[x:y] Current (Typical) vs. Frequency;
CMOS Mode, 20 pF, 10 pF, and 2 pF Load
3.5
3.0
2.5
2.0
L SWING (V p-p)
1.5
1.0
DIFFERENTI
0.5
0
0 200 400 600 800 1000 1200
HSTL = 16mA
HSTL = 8mA
FREQUENCY ( MHz)
08439-007
Figure 7. Differential Voltage Swing vs. Frequency;
HSTL Mode, 16 mA and 8 mA
1.6
1.4
1.2
1.0
0.8
0.6
0.4
DIFFERENTIAL SWING (V p-p)
0.2
0
0 200 400 600 800 1000 1200
FREQUENCY (MHz)
08439-008
Figure 8. Differential Voltage Swing vs. Frequency,
LVPECL Mode
Rev. B | Page 16 of 56
AD9523
A
–
–
1.4
1.2
LVD S = 7 m A
1.0
0.8
L SWING (V p-p )
0.6
LVD S = 3 . 5m A
0.4
DIFFERENTI
0.2
0
0 200 400 600 800 1000 1200
FREQUENCY ( MHz)
Figure 9. Differential Voltage Swing vs. Frequency;
LVDS Mode, 7 mA and 3.5 mA
08439-009
70
–80
1
–90
–100
–110
–120
–130
–140
PHASE NOISE (dBc/Hz)
–150
–160
–170
100 1k 10k 100k 1M 10M
2
3
4
NOISE:
ANALYSIS RANG E X: BAND M ARKER
ANALYSIS RANG E Y: BAND M ARKER
INTG NOISE: –75.94595dBc/39.99MHz
RMS NOISE: 225.539µRAD
12.9224mdeg
RMS JITTER: 194.746fsec
RESIDUAL FM: 2.81623kHz
1: 100Hz, –85.0688dBc/Hz
2: 1kHz, –113.3955dBc/Hz
3: 8kHz, –125.8719dBc/Hz
4: 16kHz, –129.5942dBc/Hz
5: 100kHz, –134.5017dBc/Hz
6: 1MHz, –145.2872dBc/Hz
7: 10MHz, –156.2706dBc/Hz
8: 40MHz, –157.4153dBc/Hz
x: START 12kHz
CENTER 40.006MHz
SPAN 79.988MHz
5
FREQUENCY (Hz)
Figure 12. Phase Noise, Output = 184.32 MHz
(VCXO = 122.88 MHz, Crystek VCXO CVHD-950)
STOP 80MHz
6
7
8
08439-015
4.0
3.5
3.0
2.5
2pF
10pF
20pF
2.0
1.5
AMPLITUDE (V)
1.0
0.5
0
0 100 200 300 400 500 600
FREQUENCY ( MHz)
Figure 10. Amplitude vs. Frequency and Capacitive Load;
CMOS Mode, 2 pF, 10 pF, and 20 pF
1
70
–80
1
–90
–100
–110
–120
–130
–140
PHASE NOISE (dBc/Hz)
–150
–160
08439-010
–170
100 1k 10k 100k 1M 10M
2
3
NOISE:
ANALYSIS RANG E X: BAND M ARKER
ANALYSIS RANG E Y: BAND M ARKER
INTG NOISE: –78.8099dBc/39.99MHz
RMS NOISE: 162.189µRAD
9.29276mdeg
RMS JITTER: 210.069fsec
RESIDUAL FM: 2.27638kHz
4
FREQUENCY (Hz)
1: 100Hz, –89.0260dBc/Hz
2: 1kHz, –116.9949dBc/Hz
3: 8kHz, –129.5198dBc/Hz
4: 16kHz, –133.3916dBc/Hz
5: 100kHz, –137.7680dBc/Hz
6: 1MHz, –148.3519dBc/Hz
7: 10MHz, –158.3307dBc/Hz
8: 40MHz, 159.1629–dBc/Hz
x: START 12kHz
STOP 80MHz
CENTER 40.006MHz
SPAN 79.988MHz
5
6
7
8
08439-016
Figure 13. Phase Noise, Output = 122.88 MHz
(VCXO = 122.88 MHz, Crystek VCXO CVHD-950; Doubler Is Off)
1
CH1 200mV 2.5ns/DI V
40.0GS/s
A CH1 104mV
Figure 11. Output Waveform (Differential), LVPECL at 122.88 MHz
08439-013
CH1 500mV Ω 2.5ns/DIV
40.0GS/s
A CH1 80mV
08439-049
Figure 14. Output Waveform (Differential), HSTL at 16 mA, 122.88 MHz
Rev. B | Page 17 of 56
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