ANALOG DEVICES AD9518-2 Service Manual

6-Output Clock Generator with

www.BDTIC.com/ADI

FEATURES

Low phase noise, phase-locked loop

On-chip VCO tunes from 2.05 GHz to 2.33 GHz External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Auto and manual reference switchover/holdover modes Autorecover from holdover Accepts references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable

3 pairs of 1.6 GHz LVPECL outputs

Each pair shares 1 to 32 dividers with coarse phase delay Additive output jitter 225 fs rms

Channel-to-channel skew paired outputs <10 ps Automatic synchronization of all outputs on power-up Manual synchronization of outputs as needed Serial control port 48-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure AT E

GENERAL DESCRIPTION

The AD9518-21 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.05 GHz to 2.33 GHz. Optionally, an external VCO/VCXO of up to

2.4 GHz may be used.

The AD9518-2 emphasizes low jitter and phase noise to max

imize data converter performance, and can benefit other

applications with demanding phase noise and jitter requirements.

Integrated 2.2 GHz VCO

AD9518-2

FUNCTIONAL BLOCK DIAGRAM

PLL

LF

VCO

LVPECL

AD9518-2

STATUS

MONITOR

CP

REF1

REFIN

REF2

SWITCHOVER

AND MONITOR

CLK

SERIAL CONT ROL PORT

DIVIDER

AND MUXs

DIV/Φ

AND

DIGITAL LOGIC

Figure 1.

The AD9518-2 features six LVPECL outputs (in three pairs). The LVPECL outputs operate to 1.6 GHz.

Each pair of outputs has dividers that allow both the divide r

atio and coarse delay (or phase) to be set. The range of division

for the LVPECL outputs is 1 to 32.

The AD9518-2 is available in a 48-lead LFCSP and can be op

erated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. A separate LVPECL power supply can be from 2.375 V to 3.6 V.

The AD9518-2 is specified for operation over the industrial ra

nge of −40°C to +85°C.

1

AD9518 is used throughout to refer to all the members of the AD9518

family. However, when AD9518-2 is used, it is referring to that specific member of the AD9518 family.

OUT0 OUT1 OUT2 OUT3 OUT4 OUT5

6431-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9518-2

www.BDTIC.com/ADI

REVISION HISTORY

9/07—Revision 0: Initial Version

Application Notes............................................................................61

Using the AD9518 Outputs for ADC Clock Applications ....61

LVPECL Clock D i s t ribut io n ......................................................61

Outline Dimensions........................................................................62

Ordering Guide...........................................................................62

Rev. 0 | Page 3 of 64

AD9518-2

www.BDTIC.com/ADI

SPECIFICATIONS

Typical (typ) is given for VS = V unless otherwise noted. Minimum (min) and maximum (max) values are given over full V

POWER SUPPLY REQUIREMENTS

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

V

S

V

S_LVPECL

V

CP

3.135 3.3 3.465 V This is 3.3 V ± 5%

2.375 V V

S

RSET Pin Resistor 4.12 kΩ Sets internal biasing currents; connect to ground CPRSET Pin Resistor 5.1 kΩ

BYPASS Pin Capacitor 220 nF Bypass for internal LDO regulator; necessary for LDO stability; connect to ground

PLL CHARACTERISTICS

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

VCO (ON-CHIP)

Frequency Range 2050 2335 MHz See Figure 11 VCO Gain (K Tunin g Volt age (VT) 0.5 VCP − 0.5 V

Frequency Pushing (Open-Loop) 1 MHz/V Phase Noise @ 100 kHz Offset −107 dBc/Hz f = 2175 MHz Phase Noise @ 1 MHz Offset −124 dBc/Hz f = 2175 MHz

REFERENCE INPUTS

Differential Mode (REFIN, REFIN)

Input Frequency 0 250 MHz

Input Sensitivity 250 mV p-p

Self-Bias Voltage, REFIN 1.35 1.60 1.75 V Self-bias voltage of REFIN Self-Bias Voltage, REFIN Input Resistance, REFIN 4.0 4.8 5.9 kΩ Self-biased Input Resistance, REFIN

Dual Single-Ended Mode (REF1, REF2) Two single-ended CMOS-compatible inputs

Input Frequency (AC-Coupled) 20 250 MHz Slew rate > 50 V/μs Input Frequency (DC-Coupled) 0 250 MHz Slew rate > 50 V/μs; CMOS levels Input Sensitivity (AC-Coupled) 0.8 V p-p Should not exceed VS p-p Input Logic High 2.0 V Input Logic Low 0.8 V Input Current −100 +100 μA

Input Capacitance 2 pF

) 50 MHz/V See Figure 6

VCO

= 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; R

S_LVPECL

V This is nominally 2.5 V to 3.3 V ± 5%

S

SET

5.25 V This is nominally 3.3 V to 5.0 V ± 5%

Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);

tual current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground

ac

1.30 1.50 1.60 V

4.4 5.3 6.4 kΩ Self-biased

= 4.12 kΩ; CP and TA (−40°C to +85°C) variation.

S

≤ VS when using internal VCO; outside of

V

CP

= 5.1 kΩ,

RSET

this range, the CP spurs may increase due to CP up/down mismatch

Differential mode (can accommodate singleended input by ac grounding undriven input)

Frequencies below about 1 MHz should be

coupled; be careful to match V

dc-

(self-bias voltage)

CM

PLL figure of merit increases with increasing

te; see Figure 10

slew ra

Self-bias voltage of REFIN

1

Each pin, REFIN/REFIN

1

(REF1/REF2)

Rev. 0 | Page 4 of 64

AD9518-2

www.BDTIC.com/ADI

Parameter Min Typ Max Unit Test Conditions/Comments

PHASE/FREQUENCY DETECTOR (PFD)

PFD Input Frequency 100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns 45 MHz Antibacklash pulse width = 6.0 ns Antibacklash Pulse Width 1.3 ns 0x17<1:0> = 01b

2.9 ns 0x17<1:0> = 00b; 0x17<1:0> = 11b

6.0 ns 0x17<1:0> = 10b

CHARGE PUMP (CP)

ICP Sink/Source Programmable

High Value 4.8 mA With CP

Low Value 0.60 mA

Absolute Accuracy 2.5 % CPV = VCP/2 V

CP

Range 2.7/10 kΩ

RSET

ICP High Impedance Mode Leakage 1 nA Sink-and-Source Current Matching 2 % 0.5 < CPV < VCP − 0.5 V ICP vs. CP ICP vs. Temperature 2 % CPV = VCP/2 V

PRESCALER (PART OF N DIVIDER)

Prescaler Input Frequency

Prescaler Output Frequency 300 MHz

PLL DIVIDER DELAYS 0x19: R<5:3>, N<2:0>; see Tab le 43

000 Off 001 330 ps 010 440 ps 011 550 ps 100 660 ps 101 770 ps 110 880 ps 111 990 ps

NOISE CHARACTERISTICS

In-Band Phase Noise of the Charge Pump/Phase Frequency Detector (In-Band Means Within the LBW of the PLL)

PLL Figure of Merit (FOM) −220 dBc/Hz

V

P = 1 FD 300 MHz

P = 2 FD 600 MHz

P = 3 FD 900 MHz

P = 2 DM (2/3) 600 MHz

P = 4 DM (4/5) 1000 MHz

P = 8 DM (8/9) 2400 MHz

P = 16 DM (16/17) 3000 MHz

P = 32 DM (32/33) 3000 MHz

@ 500 kHz PFD Frequency −165 dBc/Hz

@ 1 MHz PFD Frequency −162 dBc/Hz

@ 10 MHz PFD Frequency −151 dBc/Hz

@ 50 MHz PFD Frequency −143 dBc/Hz

1.5 % 0.5 < CPV < VCP − 0.5 V

A, B counter input frequency (prescaler input fr

The PLL in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the value of the N divider)

Reference slew rate > 0.25 V/ns; FOM + 10 log(f is an approximation of the PFD/CP in-band phase noise (in the flat region) inside the PLL loop bandwidth; when running closed loop, the phase noise, as observed at the VCO output, is increased by 20 log(N)

= 5.1 kΩ

RSET

equency divided by P)

PFD

)

Rev. 0 | Page 5 of 64

AD9518-2

www.BDTIC.com/ADI

Parameter Min Typ Max Unit Test Conditions/Comments

PLL DIGITAL LOCK DETECT WINDOW

Required to Lock (Coincidence of Edges) Selected by 0x17<1:0> and 0x18<4>

Low Range (ABP 1.3 ns, 2.9 ns) 3.5 ns 0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 1b High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns 0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 0b High Range (ABP 6 ns) 3.5 ns 0x17<1:0> = 10b; 0x18<4> = 0b

To Unlock After Lock (Hysteresis)

Low Range (ABP 1.3 ns, 2.9 ns) 7 ns 0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 1b High Range (ABP 1.3 ns, 2.9 ns) 15 ns 0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 0b High Range (ABP 6 ns) 11 ns 0x17<1:0> = 10b; 0x18<4> = 0b

1

REFIN and

2

For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

REFIN

self-bias points are offset slightly to avoid chatter on an open input condition.

CLOCK INPUTS

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

CLOCK INPUTS (CLK, CLK)

Input Frequency 0 0 Input Sensitivity, Differential 150 mV p-p

Input Level, Differential 2 V p-p

Input Common-Mode Voltage, V Input Common-Mode Range, V Input Sensitivity, Single-Ended 150 mV p-p

Input Resistance 3.9 4.7 5.7 kΩ Self-biased Input Capacitance 2 pF

1

Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.

CMR

2

Signal available at LD, STATUS, and REFMON pins when se

lected by appropriate register settings

Differential input

1

2.4 GHz High frequency distribution (VCO divider)

1

1.6 GHz Distribution only (VCO divider bypassed) Measured at 2.4 GHz; jitter performance is improved

w rates > 1 V/ns

with sle Larger voltage swings may turn on the protection

diodes and can degr

CM

1.3 1.57 1.8 V Self-biased; enables ac coupling

ade jitter performance

1.3 1.8 V With 200 mV p-p signal applied; dc-coupled CLK ac-coupled; CLK

ac-bypassed to RF ground

CLOCK OUTPUTS

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL CLOCK OUTPUTS Termination = 50 Ω to VS − 2 V

OUT0, OUT1, OUT2, OUT3, OUT4, OUT5

Differential (OUT, OUT Output Frequency, Maximum 2950 MHz Using direct to output; see Figure 16 Output High Voltage (VOH) VS − 1.12 VS − 0.98 VS − 0.84 V Output Low Voltage (VOL) VS − 2.03 VS − 1.77 VS − 1.49 V Output Differential Voltage (VOD) 550 790 980 mV

Rev. 0 | Page 6 of 64

)

AD9518-2

www.BDTIC.com/ADI

TIMING CHARACTERISTICS

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL Termination = 50 Ω to VS − 2 V; level = 810 mV

Output Rise Time, t Output Fall Time, t

PROPAGATION DELAY, t

High Frequency Clock Distribution Configuration 835 995 1180 ps See Figure 27 Clock Distribution Configuration 773 933 1090 ps See Figure 29 Variation with Temperature 0.8 ps/°C

OUTPUT SKEW, LVPECL OUTPUTS

LVPECL Outputs That Share the Same Divider 5 15 ps LVPECL Outputs on Different Dividers 13 40 ps All LVPECL Outputs Across Multiple Parts 220 ps

1

This is the difference between any two similar delay paths while operating at the same voltage and temperature.

RP

FP

, CLK-TO-LVPECL OUTPUT

PECL

1

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

CLK-TO-LVPECL ADDITIVE PHASE NOISE

CLK = 1 GHz, OUTPUT = 1 GHz Input slew rate > 1 V/ns Divider = 1

@ 10 Hz Offset −109 dBc/Hz @ 100 Hz Offset −118 dBc/Hz @ 1 kHz Offset −130 dBc/Hz @ 10 kHz Offset −139 dBc/Hz @ 100 kHz Offset −144 dBc/Hz @ 1 MHz Offset −146 dBc/Hz

@ 10 MHz Offset −147 dBc/Hz

@ 100 MHz Offset −149 dBc/Hz CLK = 1 GHz, OUTPUT = 200 MHz Input slew rate > 1 V/ns Divider = 5

@ 10 Hz Offset −120 dBc/Hz @ 100 Hz Offset −126 dBc/Hz @ 1 kHz Offset −139 dBc/Hz @ 10 kHz Offset −150 dBc/Hz @ 100 kHz Offset −155 dBc/Hz @ 1 MHz Offset −157 dBc/Hz

>10 MHz Offset −157 dBc/Hz

70 180 ps 20% to 80%, measured differentially 70 180 ps 80% to 20%, measured differentially

Distribution section only; does not include PLL and

VCO

Rev. 0 | Page 7 of 64

AD9518-2

www.BDTIC.com/ADI

CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)

Table 7.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL ABSOLUTE PHASE NOISE Internal VCO; direct to LVPECL output

VCO = 2.335 GHz; OUTPUT = 2.335 GHz

@ 1 kHz Offset −46 dBc/Hz @ 10 kHz Offset −78 dBc/Hz @ 100 kHz Offset −105 dBc/Hz @ 1 MHz Offset −124 dBc/Hz @ 10 MHz Offset −141 dBc/Hz @ 40 MHz Offset −146 dBc/Hz

VCO = 2.175 GHz; OUTPUT = 2.175 GHz

@ 1 kHz Offset −51 dBc/Hz @ 10 kHz Offset −80 dBc/Hz @ 100 kHz Offset −107 dBc/Hz @ 1 MHz Offset −124 dBc/Hz @ 10 MHz Offset −142 dBc/Hz @ 40 MHz Offset −146 dBc/Hz

VCO = 2.05 GHz; OUTPUT = 2.05 GHz

@ 1 kHz Offset −53 dBc/Hz @ 10 kHz Offset −82 dBc/Hz @ 100 kHz Offset −108 dBc/Hz @ 1 MHz Offset −127 dBc/Hz @ 10 MHz Offset −142 dBc/Hz @ 40 MHz Offset −147 dBc/Hz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)

Table 8.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

VCO = 2.21 GHz; LVPECL = 245.76 MHz; PLL LBW = 138 kHz 146 fs rms Integration BW = 200 kHz to 10 MHz 329 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2.21 GHz; LVPECL = 122.88 MHz; PLL LBW = 138 kHz 151 fs rms Integration BW = 200 kHz to 10 MHz 329 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2.21 GHz; LVPECL = 61.44 MHz; PLL LBW = 138 kHz 203 fs rms Integration BW = 200 kHz to 10 MHz 376 fs rms Integration BW = 12 kHz to 20 MHz

Application example based on a typical setup wher clean, so a wider PLL loop bandwidth is used; reference = 15.36 MHz; R = 1

e the reference source is

Rev. 0 | Page 8 of 64

AD9518-2

www.BDTIC.com/ADI

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)

Table 9.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

VCO = 2.18 GHz; LVPECL = 155.52 MHz; PLL LBW = 125 Hz 515 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2.21 GHz; LVPECL = 122.88 MHz; PLL LBW = 125 Hz 570 fs rms Integration BW = 12 kHz to 20 MHz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)

Table 10.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

LVPECL = 245.76 MHz; PLL LBW = 125 Hz 54 fs rms Integration BW = 200 kHz to 5 MHz 77 fs rms Integration BW = 200 kHz to 10 MHz 109 fs rms Integration BW = 12 kHz to 20 MHz LVPECL = 122.88 MHz; PLL LBW = 125 Hz 79 fs rms Integration BW = 200 kHz to 5 MHz 114 fs rms Integration BW = 200 kHz to 10 MHz 163 fs rms Integration BW = 12 kHz to 20 MHz LVPECL = 61.44 MHz; PLL LBW = 125 Hz 124 fs rms Integration BW = 200 kHz to 5 MHz 176 fs rms Integration BW = 200 kHz to 10 MHz 259 fs rms Integration BW = 12 kHz to 20 MHz

Application example based on a typical setup using an

ternal 245.76 MHz VCXO (Toyocom TCO-2112);

ex reference = 15.36 MHz; R = 1

Application example based on a typical setup wher jittery, so a narrower PLL loop bandwidth is used; reference = 10.0 MHz; R = 20

e the reference source is

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

Table 11.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1 40 fs rms BW = 12 kHz to 20 MHz CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4 80 fs rms BW = 12 kHz to 20 MHz CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16 215 fs rms

CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5 245 fs rms Calculated from SNR of ADC method; DCC on

Distribution section only; does not include PLL VCO; uses rising edge of clock signal

Calculated from SNR of ADC method; DCC not used

or even divides

f

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)

Table 12.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz; Divider = 12; Duty-Cycle Correction = Off

210 fs rms Calculated from SNR of ADC method

Distribution section only; does not include PLL and VCO;

ising edge of clock signal

uses r

and

Rev. 0 | Page 9 of 64

AD9518-2

www.BDTIC.com/ADI

SERIAL CONTROL PORT

Table 13.

Parameter Min Typ Max Unit Test Conditions/Comments

CS (INPUT)

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 3 μA Input Logic 0 Current 110 μA Input Capacitance 2 pF

SCLK (INPUT) SCLK has an internal 30 kΩ pull-down resistor

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 110 μA Input Logic 0 Current 1 μA Input Capacitance 2 pF

SDIO (WHEN INPUT)

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 10 nA Input Logic 0 Current 20 nA Input Capacitance 2 pF

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V

TIMING

Clock Rate (SCLK, 1/t Pulse Width High, t Pulse Width Low, t SDIO to SCLK Setup, t SCLK to SDIO Hold, t SCLK to Valid SDIO and SDO, t CS to SCLK Setup and Hold, tS, t

CS Minimum Pulse Width High, t

) 25 MHz

SCLK

HI

LO

DS

DH

DV

H

PWH

16 ns 16 ns 2 ns

1.1 ns 8 ns 2 ns

3 ns

CS has an internal 30 kΩ pull-up resistor

PD, SYNC, AND RESET PINS

Table 14.

Parameter Min Typ Max Unit Test Conditions/Comments

INPUT CHARACTERISTICS These pins each have a 30 kΩ internal pull-up resistor

Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 110 μA Logic 0 Current 1 μA Capacitance 2 pF

RESET TIMING

Pulse Width Low 50 ns

SYNC TIMING

Pulse Width Low 1.5 High speed clock cycles High speed clock is CLK input signal

Rev. 0 | Page 10 of 64

AD9518-2

www.BDTIC.com/ADI

LD, STATUS, AND REFMON PINS

Table 15.

Parameter Min Typ Max Unit Test Conditions/Comments

OUTPUT CHARACTERISTICS

Output Voltage High (VOH) 2.7 V Output Voltage Low (VOL) 0.4 V

MAXIMUM TOGGLE RATE 100 MHz

ANALOG LOCK DETECT

Capacitance 3 pF

REF1, REF2, AND VCO FREQUENCY STATUS MONITOR

Normal Range 1.02 MHz

Extended Range (REF1 and REF2 Only) 8 kHz

LD PIN COMPARATOR

Trip Point 1.6 V Hysteresis 260 mV

When selected as a digital output (CMOS); there are other

in which these pins are not CMOS digital outputs;

modes see Table 43, 0x17, 0x1A, and 0x1B

Applies when mux is set to any divid or PFD up/down pulse; also applies in analog lock detect mode; usually debug mode only; beware that spurs may couple to output when any of these pins are toggling

On-chip capacitance; used to calculate RC time constant

or analog lock detect readback; use a pull-up resistor

f

Frequency above which the monitor indicates the

esence of the reference

pr Frequency above which the monitor indicates the

esence of the reference

pr

er or counter output,

POWER DISSIPATION

Table 16.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER DISSIPATION, CHIP

Power-On Default 0.76 1.0 W

Full Operation 1.1 1.7 W

PD Power-Down

PD Power-Down, Maximum Sleep

VCP Supply 1.5 mW PLL operating; typical closed loop configuration

POWER DELTAS, INDIVIDUAL FUNCTIONS Power delta when a function is enabled/disabled

VCO Divider 30 mW VCO divider not used REFIN (Differential) 20 mW All references off to differential reference enabled REF1, REF2 (Single-Ended) 4 mW

VCO 70 mW CLK input selected to VCO selected PLL 75 mW PLL off to PLL on, normal operation; no reference enabled Channel Divider 30 mW Divider bypassed to divide-by-2 to divide-by-32 LVPECL Channel (Divider Plus Output Driver) 160 mW No LVPECL output on to one LVPECL output on LVPECL Driver 90 mW Second LVPECL output turned on, same channel

75 185 mW

31 mW

No clock; no programming; defa does not include power dissipated in external resistors

PLL on; internal VCO = 2335 MHz; VCO divider = 2;

annel dividers on; six LVPECL outputs @ 584 MHz;

all ch does not include power dissipated in external resistors

PD pin pulled low; does not include power dissipated in terminations

PD pin pulled low; PLL power-down 0x10<1:0> = 01b; SYNC power-down 0x230<2> = 1b; REF for distribution power-down 0x230<1> = 1b

All references off to REF1 or REF2 enabled; differential

ference not enabled

re

ult register values;

Rev. 0 | Page 11 of 64

AD9518-2

K

www.BDTIC.com/ADI

TIMING DIAGRAMS

t

CLK

CL

DIFFERENTIAL

80%

LVPECL

20%

t

PECL

Figure 2. CLK/

CLK

to Clock Output Timing, DIV = 1

t

06431-060

RP

Figure 3. LVPECL Timing, Differential

t

FP

06431-061

Rev. 0 | Page 12 of 64

AD9518-2

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 17.

With

Parameter or Pin

VS, VS_LVPECL GND −0.3 V to +3.6 V VCP GND −0.3 V to +5.8 V REFIN, REFIN REFIN RSET GND −0.3 V to VS + 0.3 V CPRSET GND −0.3 V to VS + 0.3 V CLK, CLK CLK

SCLK, SDIO, SDO, CS OUT0, OUT0, OUT1, OUT1,

OUT2, OUT2 OUT4, OUT4

SYNC REFMON, STATUS, LD GND −0.3 V to VS + 0.3 V Junction Temperature Storage Temperature Range −65°C to +150°C Lead Temperature (10 sec) 300°C

1

See Table 18 for θJA.

, OUT3, OUT3, , OUT5, OUT5

Respec

t To Rating

GND −0.3 V to VS + 0.3 V REFIN

GND −0.3 V to VS + 0.3 V CLK GND −0.3 V to VS + 0.3 V GND −0.3 V to VS + 0.3 V

GND −0.3 V to VS + 0.3 V

1

150°C

−3.3 V to +3.3 V

−1.2 V to +1.2 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

Table 18.

Package Type

48-Lead LFCSP 28.5 °C/W

1

Thermal impedance measurements were taken on a 4-layer board in still air

in accordance with EIA/JESD51-7.

1

θ

JA

Unit

ESD CAUTION

Rev. 0 | Page 13 of 64

AD9518-2

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REFMON

LD

VCP

CP

STATUS

REF_SEL

SYNC

BYPASS

VS

CLK

C

N

=

N

REFIN (REF1)REFIN (REF2)CPRSETVSRSETVSOUT0

4847464544434241403938

1

2

3

4

5

6

7

8

LF

9

10

11

12

O

C

13141516171819

SCLK

N

T

C

E

PIN 1 INDICATO R

CS

SDO

AD9518-2

TOP VIEW

(Not to Scale)

SDIO

RESET

PD

OUT4

OUT0

VS_LVPECL

OUT1

2021222324

OUT4

OUT5

VS_LVPECL

Figure 4. Pin Configuration

Table 19. Pin Function Descriptions

Pin No. Mnemonic Description

10, 24 to 26,

VS 3.3 V Power Pins.

35, 37, 43, 45 21, 30, 31, 40 VS_LVPECL Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins. EPAD, 27, 34 GND 1 REFMON 2 LD 3 VCP 4 CP 5 STATUS 6 REF_SEL 7

SYNC

Ground; External Paddle (EPAD). Reference Monitor (Output). This pin has multiple selectable outputs; see Table 43, 0x1B. Lock Detect (Output). This pin has multiple selectable outputs; see Table 4 3 , 0x1A. Power Supply for Charge Pump (CP); VS < VCP < 5.0 V. Charge Pump (Output). Connects to external loop filter. Status (Output). This pin has multiple selectable outputs; see Table 43, 0x17. Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ pull-down resistor. Manual Synchronizations and Manual Holdover. This pin initiates a manual synchronization and is also used

for manual holdover. Active low. This pin has an internal 30 kΩ pull-up resistor. 8 LF 9 BYPASS 11 CLK

12

CLK 13 SCLK 14

CS

Loop Filter (Input). Connects to VCO control voltage node internally. This pin is for bypassing the LDO to ground with a capacitor. Along with CLK, this is the differential input for the clock distribution section. Along with CLK, this is the differential input for the clock distribution section.

Serial Control Port Data Clock Signal.

Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up resistor. 15 SDO Serial Control Port Unidirectional Serial Data Out. 16 SDIO 17 18

RESET PD

42 OUT0 41

OUT0 39 OUT1 38

OUT1

Serial Control Port Bidirectional Serial Data In/Out. Chip Reset; Active Low. This pin has an internal 30 kΩ pull-up resistor.

Chip Power Down; Active Low. This pin has an internal 30 kΩ pull-up resistor. LVPECL Output; One Side of a Differential LVPECL Output.

LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output.

LVPECL Output; One Side of a Differential LVPECL Output.

VS

37

VS

36

C

N

V

35

S

34

G

N

33

OUT2

32

OUT2

31

VS_LVPECL

30

VS_LVPECL

29

OUT3

28

OUT3

27

G

N

26

V

S

25

S

V

D

06431-003

Rev. 0 | Page 14 of 64

AD9518-2

www.BDTIC.com/ADI

Pin No. Mnemonic Description

33 OUT2 LVPECL Output; One Side of a Differential LVPECL Output. 32 29 OUT3 LVPECL Output; One Side of a Differential LVPECL Output. 28

19 OUT4 LVPECL Output; One Side of a Differential LVPECL Output. 20

22 OUT5 LVPECL Output; One Side of a Differential LVPECL Output. 23 44 RSET Resistor Connected Here Sets Internal Bias Currents. Nominal value = 4.12 kΩ. 46 CPRSET Resistor Connected Here Sets the CP Current Range. Nominal value = 5.1 kΩ. 47

48 REFIN (REF1)

36 NC No Connection.

OUT2

OUT3

OUT4

OUT5

(REF2) Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended

REFIN

LVPECL Output; One Side of a Differential LVPECL Output.

input for REF2. Along with REFIN

input for REF1.

, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended

Rev. 0 | Page 15 of 64

AD9518-2

–

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

300

280

260

240

220

200

180

CURRENT (mA)

160

140

120

100

0 500 1000 1500 2000 2500 3000

Figure 5. Current vs. Frequency, Di

3 CHANNELS—6 LVPECL

3 CHANNELS—3 LVPECL

2 CHANNELS—2 LVPECL

1 CHANNEL—1 LVPECL

FREQUENCY (MHz)

rect-to-Output, LVPECL Outputs

48

46

44

42

40

(MHz/V)

38

VCO

K

36

34

32

30

2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35

VCO FREQUENCY (GHz)

Figure 6. K

VCO

vs. VCO Frequency

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

CURRENT FROM CP PIN (mA)

1.0

0.5

PUMP DOWN PUMP UP

0

0 0.5 1.0 1.5 2.0 2.5 3.0

Figure 7. Charge Pump Characteristics @ V

VOLTAGE ON CP PIN (V)

= 3.3 V

CP

06431-007

06431-010

06431-011

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

CURRENT FROM CP PIN (mA)

1.0

0.5

0

PUMP DOWN PUMP UP

0 0.5 1.0 1.5 2.0 3.0 4.02.5 3.5 5. 04.5

Figure 8. Charge Pump Characteristics @ V

VOLTAGE ON CP PIN (V)

= 5.0 V

CP

140

–145

–150

–155

(dBc/Hz)

–160

–165

PFD PHASE NOI SE REFERRED T O PFD INP UT

–170

0.1 1 10010

PFD FREQUENCY (MHz)

Figure 9. PFD Phase Noise Referred to PFD Input vs. PFD Frequency

210

–212

–214

–216

–218

–220

PLL FIGURE OF MERI T (dBc/Hz)

–222

–224

022.01.51.00.5

Figure 10. PLL Figure

SLEW RATE (V/n s)

of Merit (FOM) vs. Slew Rate at REFIN/

REFIN

06431-012

06431-013

.5

06431-136

Rev. 0 | Page 16 of 64

AD9518-2

www.BDTIC.com/ADI

1.9

1.0

1.8

1.7

1.6

1.5

1.4

VCO TUNING VO LTAGE (V)

1.3

1.2

2.0 2.42.32.22. 1

FREQUENCY (GHz)

Figure 11. VCO Tuning Voltage vs. Frequency

10

0

–10

–20

–30

–40

–50

–60

–70

RELATIVE POWER (dB)

–80

–90

–100

–110

CENTER 122.88MHz SPAN 50MHz5MHz/DIV

Figure 12. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz;

LBW

= 138 kHz; I

10

0

–10

–20

–30

–40

–50

–60

–70

RELATIVE POWER (dB)

–80

–90

–100

–110

CENTER 122. 88MHz SP AN 1MHz100kHz/DIV

= 3.0 mA; f

CP

= 2.21 GHz

VCO

Figure 13. Output Spectrum, LVPECL; 122.88 MHz; PFD = 15.36 MHz;

LBW

= 138 kHz; I

= 3.0 mA; f

CP

= 2.21 GHz

VCO

0.6

0.2

–0.2

DIFFERENT IAL OUTPUT (V)

–0.6

–1.0

022015105

06431-138

TIME (ns)

5

06431-014

Figure 14. LVPECL Output (Differential) @ 100 MHz

1.0

0.6

0.2

–0.2

DIFFERENT IAL OUTPUT (V)

–0.6

–1.0

06431-137

021

TIME (ns)

06431-015

Figure 15. LVPECL Output (Differential) @ 1600 MHz

1600

1400

1200

1000

DIFFERENTIAL SWING (mV p-p)

800

06431-135

0321

FREQUENCY (GHz)

06431-020

Figure 16. LVPECL Differential Swing vs. Frequency

Rev. 0 | Page 17 of 64

AD9518-2

–

www.BDTIC.com/ADI

70

120

–80

–90

–100

–110

–120

PHASE NOISE (dBc/Hz)

–130

–140

–150

10k 100M10M1M100k

FREQUENCY (Hz)

06431-023

Figure 17. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 2335 MHz

80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–125

–130

–135

–140

–145

PHASE NOISE (dBc/Hz)

–150

–155

–160

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 20. Phase Noise (Additive) LV

110

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

PECL @ 245.76 MHz, Divide-by-1

06431-026

–150

10k 100M10M1M100k

FREQUENCY (Hz)

06431-024

Figure 18. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 2175 MHz

80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

10k 100M10M1M100k

FREQUENCY (Hz)

06431-025

Figure 19. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 2050 MHz

–160

10 100M10M1M100k10k1k100

Figure 21. Phase Noise (Additive) LVPECL @ 200 M

FREQUENCY (Hz)

Hz, Divide-by-5

100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 22. Phase Noise (Additive) LVPECL @ 1600 MHz, D

ivide-by-1

06431-027

06431-128

Rev. 0 | Page 18 of 64

AD9518-2

–

www.BDTIC.com/ADI

110

120

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

1k 100M10M1M100k10k

FREQUENCY (Hz)

Figure 23. Phase Noise (Absolute) Clock Generation; Internal VCO @

2.2

1 GHz; PFD = 15.36 MHz; LBW = 138 kHz; LVPECL Output = 122.88 MHz

80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

1k 100M10M1M100k10k

06431-141

Figure 25. Phase Noise (Absolute); Ex

FREQUENCY (Hz)

ternal VCXO (Toyocom TCO-2112)

06431-140

@ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz

–150

–160

1k 100M10M1M100k10k

FREQUENCY (Hz)

Figure 24. Phase Noise (Absolute) Clock Cleanup; Internal VCO @ 2.18 GHz;

P

FD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz

06431-139

Rev. 0 | Page 19 of 64

AD9518-2

www.BDTIC.com/ADI

TERMINOLOGY

Phase Jitter and Phase Noise

An ideal sine wave can be thought of as having a continuous

nd even progression of phase with time from 0° to 360° for

a each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution.

This phase jitter leads to a spreading out of the energy of the sin

e wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given.

It is meaningful to integrate the total power contained within

ome interval of offset frequencies (for example, 10 kHz to

s 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval.

Phase noise has a detrimental effect on the performance of

Cs, DACs, and RF mixers. It lowers the achievable dynamic

AD range of the converters and mixers, although they are affected in somewhat different ways.

Time Jitter

Phase noise is a frequency domain phenomenon. In the time do

main, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings varies. In a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution.

Time jitter that occurs on a sampling clock for a DAC or an

C decreases the signal-to-noise ratio (SNR) and dynamic

AD range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter.

Additive Phase Noise

Additive phase noise is the amount of phase noise that is

ttributable to the device or subsystem being measured. The

a phase noise of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. When there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors.

Additive Time Jitter

Additive time jitter is the amount of time jitter that is

ttributable to the device or subsystem being measured. The

a time jitter of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.

Rev. 0 | Page 20 of 64

ANALOG DEVICES AD9518-2 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

POWER SUPPLY REQUIREMENTS

PLL CHARACTERISTICS

CLOCK INPUTS

CLOCK OUTPUTS

TIMING CHARACTERISTICS

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)

CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)

SERIAL CONTROL PORT

PD, SYNC, AND RESET PINS

LD, STATUS, AND REFMON PINS

POWER DISSIPATION

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY