ANALOG DEVICES AD9517-4 Service Manual

12-Output Clock Generator with

FEATURES

Low phase noise, phase-locked loop (PLL)

On-chip VCO tunes from 1.45 GHz to 1.80 GHz External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic revertive and manual reference

switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable

2 pairs of 1.6 GHz LVPECL outputs

Each output pair shares a 1-to-32 divider with coarse

phase delay Additive output jitter: 225 fs rms Channel-to-channel skew paired outputs of <10 ps

2 pairs of 800 MHz LVDS clock outputs

Each output pair shares two cascaded 1-to-32 dividers

with coarse phase delay Additive output jitter: 275 fs rms Fine delay adjust (Δt) on each LVDS output

Each LVDS output can be reconfigured as two 250 MHz

CMOS outputs

Automatic synchronization of all outputs on power-up Manual output synchronization available Available in a 48-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET,

Synchronous Ethernet, OTU2/3/4

Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation

GENERAL DESCRIPTION

The AD9517-41 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.45 GHz to 1.80 GHz. Optionally, an external VCO/VCXO of up to

2.4 GHz can be used.

The AD9517-4 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.

Integrated 1.6 GHz VCO

AD9517-4

FUNCTIONAL BLOCK DIAGRAM

PLL

∆t

LF

STATUS

MONITOR

VCO

LVPECL

LVDS/CMOS

AD9517-4

CP

REF1

REFIN

REF2

SWITCHOVER

AND MONITOR

CLK

DIV/Φ DIV/Φ

SERIAL CONT ROL PORT

DIVIDER

AND MUXs

DIV/Φ

AND

DIGITAL LOGIC

Figure 1.

The AD9517-4 features four LVPECL outputs (in two pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.

For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs.

Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.

The AD9517-4 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).

The AD9517-4 is specified for operation over the industrial range of −40°C to +85°C.

1

AD9517 is used throughout the data sheet to refer to all the members of the

AD9517 family. However, when AD9517-4 is used, it refers to that specific member of the AD9517 family.

OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7

06428-001

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9517-4

D

REVISION HISTORY

1/12—Rev. C to Rev. D

Changes to Table 62 ........................................................................ 75

5/11—Rev. B to Rev. C

Changes to Features, Applications, and General Description

Sections ............................................................................................... 1

Change to CPRSET Pin Resistor Parameter, Table 1 .................... 4

Changes to Table 2 ............................................................................ 4

Changes to Table 4 ............................................................................ 6

Changes to Logic 1 Current and Logic 0 Current

Parameters, Table 15 ....................................................................... 14

Changes to Table 20 ........................................................................ 18

Change to Caption, Figure 8 .......................................................... 20

Change to Caption, Figure 15 ........................................................ 21

Change to Captions, Figure 25 and Figure 26 ............................. 23

Added Figure 41; Renumbered Sequentially ............................... 25

Changes to On-Chip VCO Section ............................................... 34

Changes to Reference Switchover Section ................................... 35

Changes to Prescaler Section and Change to

Comments/Conditions Column, Table 28 ................................... 36

Changes to Automatic/Internal Holdover Mode Section

and Frequency Status Monitors Section ....................................... 39

Changes to VCO Calibration Section ........................................... 40

Changes to Clock Distribution Section ........................................ 41

Changes to Write Section ............................................................... 51

Change to The Instruction Word (16 Bits) Section .................... 52

Change to Figure 65 ........................................................................ 53

Change to Thermal Performance Section .................................... 55

Changes to Register Address 0x01C, Bits[4:3], Table 52 ............ 56

Changes to Address 0x017, Bits[1:0] and Address 0x018,

Bits[2:0], Table 54 ............................................................................ 62

Changes to Register Address 0x01C, Bits[5:1], Table 54 ............ 64

Change to LVPECL Clock Distribution Section ......................... 77

5/10—Rev. A to Rev. B

Changes to Default Values of LVDS/CMOS Outputs

Section in Table 52 .......................................................................... 56

Changes to Register 0x140, Bit 0; Register 0x142, Bit 0;

Register 0x143, Bit 0 in Table 57 ................................................... 69

Updated Outline Dimensions, Changes to Ordering Guide ..... 78

1/10—Rev. 0 to Rev. A

Added 48-Lead LFCSP Package (CP-48-8) .................... Universal

Changes to Features, Applications, and General Description ..... 1

Change to CPRSET Pin Resistor Parameter .................................. 4

Changes to Table 4 ............................................................................ 6

Changes to V

Changes to Table 19 ........................................................................ 16

Added Exposed Paddle Notation to Figure 6; Changes to

Table 20 ............................................................................................. 17

Change to High Frequency Clock Distribution—CLK or

External VCO > 1600 MHz Section; Change to Table 22 .......... 27

Changes to Table 24 ........................................................................ 29

Change to Configuration and Register Settings Section ........... 31

Change to Phase Frequency Detector (PFD) Section ................ 32

Changes to Charge Pump (CP), On-Chip VCO, PLL

External Loop Filter, and PLL Reference Inputs Sections ......... 33

Change to Figure 46; Added Figure 47 ......................................... 33

Changes to Reference Switchover and VCXO/VCO

Feedback Divider N—P, A, B, R Sections .................................... 34

Changes to Table 28 ........................................................................ 35

Change to Holdover Section .......................................................... 37

Changes to VCO Calibration Section ........................................... 39

Changes to Clock Distribution Section ........................................ 40

Change to Clock Frequency Division Section;

Change to Table 34 .......................................................................... 41

Changes to Channel Dividers—LVDS/CMOS Outputs

Section; Change to Table 39 ........................................................... 43

Change to Write Section ................................................................ 50

Change to MSB/LSB First Transfers ............................................. 51

Change to Figure 64 ........................................................................ 52

Added Thermal Performance Section .......................................... 54

Changes to 0x003 Register Address .............................................. 55

Changes to Table 53 ........................................................................ 58

Changes to Table 54 ........................................................................ 59

Changes to Table 55 ........................................................................ 65

Changes to Table 56 ........................................................................ 67

Changes to Table 57 ........................................................................ 69

Changes to Table 58 ........................................................................ 71

Changes to Table 59 ........................................................................ 72

Changes to Table 60 and Table 61 ................................................. 74

Added Frequency Planning Using the AD9517 Section ............ 75

Changes to Figure 70 and Figure 72; Added Figure 71 .............. 76

Changes to LVDS Clock Distribution Section ............................ 76

Added Exposed Paddle Notation to Outline Dimensions ......... 78

Changes to Ordering Guide ........................................................... 78

7/07—Revision 0: Initial Version

Supply Parameter ................................................. 14

CP

Rev. D | Page 3 of 80

AD9517-4

D

SPECIFICATIONS

Typical is g i v e n for VS = V Minimum and maximum values are given over full V

POWER SUPPLY REQUIREMENTS

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

VS 3.135 3.3 3.465 V 3.3 V ± 5% V

2.375 VS V Nominally 2.5 V to 3.3 V ± 5%

S_LVPECL

VCP V RSET Pin Resistor 4.12 kΩ Sets internal biasing currents; connect to ground CPRSET Pin Resistor 2.7 5.1 10 kΩ Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);

BYPASS Pin Capacitor 220 nF Bypass for internal LDO regulator; necessary for LDO stability;

PLL CHARACTERISTICS

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

VCO (ON-CHIP)

Frequency Range 1450 1800 MHz VCO Gain (K Tuning Voltage (VT) 0.5 VCP −

Frequency Pushing (Open Loop) 1 MHz/V Phase Noise at 100 kHz Offset −109 dBc/Hz f = 1625 MHz Phase Noise at 1 MHz Offset −128 dBc/Hz f = 1625 MHz

REFERENCE INPUTS

Differential Mode (REFIN,

Input Frequency 0 250 MHz Frequencies below about 1 MHz should be dc-coupled; be careful

Input Sensitivity 250 mV p-p PLL figure of merit (FOM) increases with increasing slew rate

Self-Bias Voltage, REFIN 1.35 1.60 1.75 V Self-bias voltage of REFIN1 Self-Bias Voltage, Input Resistance, REFIN 4.0 4.8 5.9 kΩ Input Resistance,

Dual Single-Ended Mode (REF1, REF2) Two single-ended CMOS-compatible inputs

Input Frequency (AC-Coupled) 20 250 MHz Slew rate > 50 V/μs Input Frequency (DC-Coupled) 0 250 MHz Slew rate > 50 V/μs; CMOS levels Input Sensitivity (AC-Coupled) 0.8 V p-p Should not exceed VS p-p Input Logic High 2.0 V Input Logic Low 0.8 V Input Current −100 +100 μA

Pulse Width High/Low 1.8 ns This value determines the allowable input duty cycle and is the

Input Capacitance 2 pF

PHASE/FREQUENCY DETECTOR (PFD)

PFD Input Frequency 100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns 45 MHz Antibacklash pulse width = 6.0 ns Antibacklash Pulse Width 1.3 ns Register 0x017[1:0] = 01b

2.9 ns Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b

6.0 ns Register 0x017[1:0] = 10b

) 50 MHz/V

VCO

REFIN

= 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; R

S_LVPECL

and TA (−40°C to +85°C) variation.

S

5.25 V Nominally 3.3 V to 5.0 V ± 5%

S

0.5

REFIN

)

Differential mode (can accommodate single-ended input by ac

1.30 1.50 1.60 V

4.4 5.3 6.4 kΩ

Rev. | Page 4 of 80

= 4.12 kΩ; CP

SET

= 5.1 kΩ, unless otherwise noted.

RSET

actual current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground

connect to ground

See

Figure 15

See

Figure 10

V VCP ≤ VS when using internal VCO; outside of this range,

the CP spurs may increase due to CP up/down mismatch

grounding undriven input)

to match V

(see

(self-bias voltage)

CM

Figure 14); the input sensitivity is sufficient for ac-coupled

LVDS and LVPECL signals

1

Self-bias voltage of Self-biased Self-biased

1

REFIN

amount of time that a square wave is high/low Each pin, REFIN/

REFIN

(REF1/REF2)

AD9517-4

D

Parameter Min Typ Max Unit Test Conditions/Comments

CHARGE PUMP (CP) CPV is CP pin voltage; VCP is charge pump power supply voltage

ICP Sink/Source Programmable

High Value 4.8 mA With CP Low Value 0.60 mA Absolute Accuracy 2.5 % CPV = VCP/2 V CP

Range 2.7/10 kΩ

RSET

ICP High Impedance Mode Leakage 1 nA Sink-and-Source Current Matching 2 % 0.5 < CPV < VCP − 0.5 V ICP vs. CPV 1.5 % 0.5 < CPV < VCP − 0.5 V ICP vs. Temperature 2 % CPV = VCP/2 V

PRESCALER (PART OF N DIVIDER)

See the

Prescaler Input Frequency

P = 1 FD 300 MHz P = 2 FD 600 MHz P = 3 FD 900 MHz P = 2 DM (2/3) 200 MHz P = 4 DM (4/5) 1000 MHz P = 8 DM (8/9) 2400 MHz P = 16 DM (16/17) 3000 MHz P = 32 DM (32/33) 3000 MHz

Prescaler Output Frequency 300 MHz A, B counter input frequency (prescaler input frequency divided by P)

PLL DIVIDER DELAYS

Register 0x019: R, Bits[5:3]; N, Bits[2:0]; see 000 Off ps 001 330 ps 010 440 ps 011 550 ps 100 660 ps 101 770 ps 110 880 ps 111 990 ps

NOISE CHARACTERISTICS

In-Band Phase Noise of the Charge

Pump/Phase Frequency Detector (In-Band Is Within the LBW of the PLL)

The PLL in-band phase noise floor is estimated by measuring the

in-band phase noise at the output of the VCO and subtracting

20 log(N) (where N is the value of the N divider)

At 500 kHz PFD Frequency −165 dBc/Hz At 1 MHz PFD Frequency −162 dBc/Hz At 10 MHz PFD Frequency −151 dBc/Hz At 50 MHz PFD Frequency −143 dBc/Hz

PLL Figure of Merit (FOM) −220 dBc/Hz Reference slew rate > 0.25 V/ns; FOM +10 log(f

mation of the PFD/CP in-band phase noise (in the flat region)

inside the PLL loop bandwidth; when running closed-loop, the

phase noise, as observed at the VCO output, is increased by

20 log(N)

PLL DIGITAL LOCK DETECT WINDOW2 Signal available at LD, STATUS, and REFMON pins when selected

by appropriate register settings Required to Lock (Coincidence of Edges) Selected by Register 0x017[1:0] and Register 0x018[4]

Low Range (ABP 1.3 ns, 2.9 ns) 3.5 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b High Range (ABP 6.0 ns) 3.5 ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b

To Unlock After Lock (Hysteresis)2

Low Range (ABP 1.3 ns, 2.9 ns) 7 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b High Range (ABP 1.3 ns, 2.9 ns) 15 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b High Range (ABP 6.0 ns) 11 ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b

1

REFIN and

2

For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

REFIN

self-bias points are offset slightly to avoid chatter on an open input condition.

Rev. | Page 5 of 80

= 5.1 kΩ

RSET

VCXO/VCO Feedback Divider N—P, A, B, R section

Tab le 54

) is an approxi-

PFD

AD9517-4

D

CLOCK INPUTS

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

CLOCK INPUTS (CLK, CLK)

Input Frequency 01 2.4 GHz High frequency distribution (VCO divider) 0 Input Sensitivity, Differential 150 mV p-p

Input Level, Differential 2 V p-p

Input Common-Mode Voltage, VCM 1.3 1.57 1.8 V Self-biased; enables ac coupling Input Common-Mode Range, V Input Sensitivity, Single-Ended 150 mV p-p

Input Resistance 3.9 4.7 5.7 kΩ Self-biased Input Capacitance 2 pF

1

Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.

CLOCK OUTPUTS

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL CLOCK OUTPUTS Termination = 50 Ω to VS − 2 V

OUT0, OUT1, OUT2, OUT3

Output Frequency, Maximum 2950 MHz

Output High Voltage (VOH)

Output Low Voltage (VOL)

Output Differential Voltage (VOD) 550 790 980 mV

LVDS CLOCK OUTPUTS Differential termination 100 Ω at 3.5 mA

OUT4, OUT5, OUT6, OUT7

Output Frequency 800 MHz

Output Differential Voltage (VOD) 247 360 454 mV

Delta VOD 25 mV

Output Offset Voltage (VOS) 1.125 1.24 1.375 V (VOH + VOL)/2 across a differential pair Delta VOS 25 mV

Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND

Differential input

1

1.6 GHz Distribution only (VCO divider bypassed) Measured at 2.4 GHz; jitter performance is improved

with slew rates > 1 V/ns Larger voltage swings may turn on the protection

diodes and may degrade jitter performance

1.3 1.8 V With 200 mV p-p signal applied; dc-coupled

CMR

CLK ac-coupled; CLK

Differential (OUT, OUT

ac-bypassed to RF ground

)

Using direct to output; see Figure 25 for peak-to-peak differential amplitude

V

S_LVPECL

1.12 V

S_LVPECL

2.03

−

V

S_LVPECL

0.98 V

S_LVPECL

1.77

−

V

S_LVPECL

0.84 V

S_LVPECL

1.49

V

−

V

−

This is V

− VOL for each leg of a differential pair for

OH

default amplitude setting with driver not toggling; the peak-to-peak amplitude measured using a differential probe across the differential pair with the driver toggling is roughly 2× these values (see Figure 25 for variation over frequency)

Differential (OUT, OUT

)

The AD9517 outputs toggle at higher frequencies, but the output amplitude may not meet the V specification; see Figure 26

− VOL measurement across a differential pair at the

V

OH

default amplitude setting with output driver not toggling; see Figure 26 for variation over frequency

This is the absolute value of the difference between

when the normal output is high vs. when the

V

OD

complementary output is high

This is the absolute value of the difference between

when the normal output is high vs. when the

V

OS

complementary output is high

OD

Rev. | Page 6 of 80

AD9517-4

D

Parameter Min Typ Max Unit Test Conditions/Comments

CMOS CLOCK OUTPUTS

OUT4A, OUT4B, OUT5A, OUT5B,

OUT6A, OUT6B, OUT7A, OUT7B

Output Frequency 250 MHz See Figure 27 Output Voltage

High (VOH) VS − 0.1 V At 1 mA load Low (VOL) 0.1 V At 1 mA load

Source Current Exceeding these values can result in damage to the part

Static 20 mA Dynamic 16 mA

Sink Current Exceeding these values can result in damage to the part

Static 8 mA Dynamic 16 mA

Single-ended; termination = 10 pF

Rev. | Page 7 of 80

AD9517-4

D

TIMING CHARACTERISTICS

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL Termination = 50 Ω to VS − 2 V; level = 810 mV

Output Rise Time, tRP 70 180 ps 20% to 80%, measured differentially Output Fall Time, tFP 70 180 ps 80% to 20%, measured differentially

PROPAGATION DELAY, t

High Frequency Clock Distribution Configuration 835 995 1180 ps Clock Distribution Configuration 773 933 1090 ps Variation with Temperature 0.8 ps/°C

OUTPUT SKEW, LVPECL OUTPUTS1

LVPECL Outputs That Share the Same Divider 5 15 ps LVPECL Outputs on Different Dividers 13 40 ps All LVPECL Outputs Across Multiple Parts 220 ps

LVDS Termination = 100 Ω differential; 3.5 mA

Output Rise Time, tRL 170 350 ps 20% to 80%, measured differentially2 Output Fall Time, tFL 160 350 ps 20% to 80%, measured differentially2

PROPAGATION DELAY, t

For All Divide Values 1.4 1.8 2.1 ns Variation with Temperature 1.25 ps/°C

OUTPUT SKEW, LVDS OUTPUTS1 Delay off on all outputs

LVDS Outputs That Share the Same Divider 6 62 ps LVDS Outputs on Different Dividers 25 150 ps All LVDS Outputs Across Multiple Parts 430 ps

CMOS Termination = open

Output Rise Time, tRC 495 1000 ps 20% to 80%; C Output Fall Time, tFC 475 985 ps 80% to 20%; C

PROPAGATION DELAY, t

For All Divide Values 1.6 2.1 2.6 ns Variation with Temperature 2.6 ps/°C

OUTPUT SKEW, CMOS OUTPUTS1 Fine delay off

CMOS Outputs That Share the Same Divider 4 66 ps All CMOS Outputs on Different Dividers 28 180 ps All CMOS Outputs Across Multiple Parts 675 ps

DELAY ADJUST3 LVDS and CMOS

Shortest Delay Range4 Register 0x0A1 (0x0A4, 0x0A7, 0x0AA), Bits[5:0] = 101111b

Zero Scale 50 315 680 ps Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b Full Scale 540 880 1180 ps Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b

Longest Delay Range4 Register 0x0A1 (0x0A4, 0x0A7, 0x0AA), Bits[5:0] = 000000b

Zero Scale 200 570 950 ps Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b

Quarter Scale 1.72 2.31 2.89 ns Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 001100b

Full Scale 5.7 8.0 10.1 ns Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b

Delay Variation with Temperature

Short Delay Range5

Zero Scale 0.23 ps/°C Full Scale −0.02 ps/°C

Long Delay Range5

Zero Scale 0.3 ps/°C Full Scale 0.24 ps/°C

1

This is the difference between any two similar delay paths while operating at the same voltage and temperature.

2

Corresponding CMOS drivers set to A for noninverting and B for inverting.

3

The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output.

4

Incremental delay; does not include propagation delay.

5

All delays between zero scale and full scale can be estimated by linear interpolation.

, CLK-TO-LVPECL OUTPUT

PECL

See

Figure 43

See

Figure 45

, CLK-TO-LVDS OUTPUT Delay off on all outputs

LVDS

LOAD

, CLK-TO-CMOS OUTPUT Fine delay off

CMOS

= 10 pF = 10 pF

Rev. | Page 8 of 80

AD9517-4

D

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

CLK-TO-LVPECL ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO

CLK = 1 GHz, Output = 1 GHz Input slew rate > 1 V/ns

Divider = 1

At 10 Hz Offset −109 dBc/Hz At 100 Hz Offset −118 dBc/Hz At 1 kHz Offset −130 dBc/Hz At 10 kHz Offset −139 dBc/Hz At 100 kHz Offset −144 dBc/Hz At 1 MHz Offset −146 dBc/Hz At 10 MHz Offset −147 dBc/Hz At 100 MHz Offset −149 dBc/Hz

CLK = 1 GHz, Output = 200 MHz Input slew rate > 1 V/ns

Divider = 5

At 10 Hz Offset −120 dBc/Hz At 100 Hz Offset −126 dBc/Hz At 1 kHz Offset −139 dBc/Hz At 10 kHz Offset −150 dBc/Hz At 100 kHz Offset −155 dBc/Hz At 1 MHz Offset −157 dBc/Hz >10 MHz Offset −157 dBc/Hz

CLK-TO-LVDS ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO

CLK = 1.6 GHz, Output = 800 MHz Input slew rate > 1 V/ns

Divider = 2

At 10 Hz Offset −103 dBc/Hz At 100 Hz Offset −110 dBc/Hz At 1 kHz Offset −120 dBc/Hz At 10 kHz Offset −127 dBc/Hz At 100 kHz Offset −133 dBc/Hz At 1 MHz Offset −138 dBc/Hz At 10 MHz Offset −147 dBc/Hz At 100 MHz Offset −149 dBc/Hz

CLK = 1.6 GHz, Output = 400 MHz Input slew rate > 1 V/ns

Divider = 4

At 10 Hz Offset −114 dBc/Hz At 100 Hz Offset −122 dBc/Hz At 1 kHz Offset −132 dBc/Hz At 10 kHz Offset −140 dBc/Hz At 100 kHz Offset −146 dBc/Hz At 1 MHz Offset −150 dBc/Hz >10 MHz Offset −155 dBc/Hz

CLK-TO-CMOS ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO

CLK = 1 GHz, Output = 250 MHz Input slew rate > 1 V/ns

Divider = 4

At 10 Hz Offset −110 dBc/Hz At 100 Hz Offset −120 dBc/Hz At 1 kHz Offset −127 dBc/Hz At 10 kHz Offset −136 dBc/Hz At 100 kHz Offset −144 dBc/Hz At 1 MHz Offset −147 dBc/Hz >10 MHz Offset −154 dBc/Hz

Rev. | Page 9 of 80

AD9517-4

D

Parameter Min Typ Max Unit Test Conditions/Comments

CLK = 1 GHz, Output = 50 MHz Input slew rate > 1 V/ns

Divider = 20

At 10 Hz Offset −124 dBc/Hz At 100 Hz Offset −134 dBc/Hz At 1 kHz Offset −142 dBc/Hz At 10 kHz Offset −151 dBc/Hz At 100 kHz Offset −157 dBc/Hz At 1 MHz Offset −160 dBc/Hz >10 MHz Offset −163 dBc/Hz

CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)

Table 7.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL ABSOLUTE PHASE NOISE Internal VCO; direct to LVPECL output

VCO = 1800 MHz; Output = 1800 MHz

At 1 kHz Offset −47 dBc/Hz At 10 kHz Offset −82 dBc/Hz At 100 kHz Offset −106 dBc/Hz At 1 MHz Offset −125 dBc/Hz At 10 MHz Offset −142 dBc/Hz At 40 MHz Offset −146 dBc/Hz

VCO = 1625 MHz; Output = 1625 MHz

At 1 kHz Offset −55 dBc/Hz At 10 kHz Offset −85 dBc/Hz At 100 kHz Offset −109 dBc/Hz At 1 MHz Offset −128 dBc/Hz At 10 MHz Offset −143 dBc/Hz At 40 MHz Offset −147 dBc/Hz

VCO = 1450 MHz; Output = 1450 MHz

At 1 kHz Offset −61 dBc/Hz At 10 kHz Offset −90 dBc/Hz At 100 kHz Offset −113 dBc/Hz At 1 MHz Offset −131 dBc/Hz At 10 MHz Offset −144 dBc/Hz At 40 MHz Offset −148 dBc/Hz

Rev. | Page 10 of 80

AD9517-4

D

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)

Table 8.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

VCO = 1475 MHz; LVPECL = 491.52 MHz; PLL LBW = 135 kHz 135 fs rms Integration BW = 200 kHz to 10 MHz 275 fs rms Integration BW = 12 kHz to 20 MHz VCO = 1475 MHz; LVPECL = 122.88 MHz; PLL LBW = 135 kHz 145 fs rms Integration BW = 200 kHz to 10 MHz 275 fs rms Integration BW = 12 kHz to 20 MHz VCO = 1475 MHz; LVPECL = 61.44 MHz; PLL LBW = 135 kHz 170 fs rms Integration BW = 200 kHz to 10 MHz 305 fs rms Integration BW = 12 kHz to 20 MHz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)

Table 9.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

VCO = 1555 MHz; LVPECL = 155.52 MHz; PLL LBW = 500 Hz 500 fs rms Integration BW = 12 kHz to 20 MHz VCO = 1475 MHz; LVPECL = 122.88 MHz; PLL LBW = 500 Hz 400 fs rms Integration BW = 12 kHz to 20 MHz

Application example based on a typical setup where the reference source is clean, so a wider PLL loop bandwidth is used; reference = 15.36 MHz; R = 1

Application example based on a typical setup where the reference source is jittery, so a narrower PLL loop bandwidth is used; reference = 10.0 MHz; R = 20

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)

Table 10.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

LVPECL = 245.76 MHz; PLL LBW = 125 Hz 54 fs rms Integration BW = 200 kHz to 5 MHz 77 fs rms Integration BW = 200 kHz to 10 MHz 109 fs rms Integration BW = 12 kHz to 20 MHz LVPECL = 122.88 MHz; PLL LBW = 125 Hz 79 fs rms Integration BW = 200 kHz to 5 MHz 114 fs rms Integration BW = 200 kHz to 10 MHz 163 fs rms Integration BW = 12 kHz to 20 MHz LVPECL = 61.44 MHz; PLL LBW = 125 Hz 124 fs rms Integration BW = 200 kHz to 5 MHz 176 fs rms Integration BW = 200 kHz to 10 MHz 259 fs rms Integration BW = 12 kHz to 20 MHz

Application example based on a typical setup using an external 245.76 MHz VCXO (Toyocom TCO-2112); reference = 15.36 MHz; R = 1

Rev. | Page 11 of 80

AD9517-4

D

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

Table 11.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1 40 fs rms BW = 12 kHz to 20 MHz CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4 80 fs rms BW = 12 kHz to 20 MHz CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16 215 fs rms

CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5 245 fs rms

LVDS OUTPUT ADDITIVE TIME JITTER

CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2;

VCO Divider Not Used CLK = 1 GHz; LVDS = 200 MHz; Divider = 5 113 fs rms BW = 12 kHz to 20 MHz CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16 280 fs rms

CMOS OUTPUT ADDITIVE TIME JITTER

CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16 365 fs rms

85 fs rms BW = 12 kHz to 20 MHz

Distribution section only; does not include PLL and VCO; uses rising edge of clock signal

Calculated from SNR of ADC method; DCC not used for even divides

Calculated from SNR of ADC method; DCC on

Distribution section only; does not include PLL and VCO; uses rising edge of clock signal

Calculated from SNR of ADC method; DCC not used for even divides

Distribution section only; does not include PLL and VCO; uses rising edge of clock signal

Calculated from SNR of ADC method; DCC not used for even divides

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)

Table 12.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

LVDS OUTPUT ADDITIVE TIME JITTER

CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

CMOS OUTPUT ADDITIVE TIME JITTER

CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

210 fs rms Calculated from SNR of ADC method

285 fs rms Calculated from SNR of ADC method

350 fs rms Calculated from SNR of ADC method

Distribution section only; does not include PLL and VCO; uses rising edge of clock signal

Rev. | Page 12 of 80

AD9517-4

D

DELAY BLOCK ADDITIVE TIME JITTER

Table 13.

Parameter Min Typ Max Unit Test Conditions/Comments

DELAY BLOCK ADDITIVE TIME JITTER1 Incremental additive jitter

100 MHz Output

Delay (1600 μA, 0x1C) Fine Adj. 000000b 0.54 ps rms Delay (1600 μA, 0x1C) Fine Adj. 101111b 0.60 ps rms Delay (800 μA, 0x1C) Fine Adj. 000000b 0.65 ps rms Delay (800 μA, 0x1C) Fine Adj. 101111b 0.85 ps rms Delay (800 μA, 0x4C) Fine Adj. 000000b 0.79 ps rms Delay (800 μA, 0x4C) Fine Adj. 101111b 1.2 ps rms Delay (400 μA, 0x4C) Fine Adj. 000000b 1.2 ps rms Delay (400 μA, 0x4C) Fine Adj. 101111b 2.0 ps rms Delay (200 μA, 0x1C) Fine Adj. 000000b 1.3 ps rms Delay (200 μA, 0x1C) Fine Adj. 101111b 2.5 ps rms Delay (200 μA, 0x4C) Fine Adj. 000000b 1.9 ps rms Delay (200 μA, 0x4C) Fine Adj. 101111b 3.8 ps rms

1

This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter

should be added to this value using the root sum of the squares (RSS) method.

SERIAL CONTROL PORT

Table 14.

Parameter Min Typ Max Unit Test Conditions/Comments

CS (INPUT)

CS has an internal 30 kΩ pull-up resistor Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 3 μA Input Logic 0 Current 110 μA Input Capacitance 2 pF

SCLK (INPUT) SCLK has an internal 30 kΩ pull-down resistor

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 110 μA Input Logic 0 Current 1 μA Input Capacitance 2 pF

SDIO (WHEN INPUT)

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 10 nA Input Logic 0 Current 20 nA Input Capacitance 2 pF

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V

TIMING

Clock Rate (SCLK, 1/t Pulse Width High, t Pulse Width Low, t

) 25 MHz

SCLK

16 ns

HIGH

16 ns

LOW

SDIO to SCLK Setup, tDS 2 ns SCLK to SDIO Hold, tDH 1.1 ns SCLK to Valid SDIO and SDO, tDV 8 ns CS to SCLK Setup and Hold, tS, tH

CS Minimum Pulse Width High, t

PWH

2 ns 3 ns

Rev. | Page 13 of 80

AD9517-4

D

PD, SYNC, AND RESET PINS

Table 15.

Parameter Min Typ Max Unit Test Conditions/Comments

INPUT CHARACTERISTICS

Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 1 μA Logic 0 Current 110 μA Capacitance 2 pF

RESET TIMING

Pulse Width Low 50 ns

SYNC TIMING

Pulse Width Low 1.5

High speed clock cycles

LD, STATUS, AND REFMON PINS

Table 16.

Parameter Min Typ Max Unit Test Conditions/Comments

OUTPUT CHARACTERISTICS

Output Voltage High (VOH) 2.7 V Output Voltage Low (VOL) 0.4 V

MAXIMUM TOGGLE RATE 100 MHz

ANALOG LOCK DETECT

Capacitance 3 pF

REF1, REF2, AND VCO FREQUENCY STATUS MONITOR

Normal Range 1.02 MHz

Extended Range (REF1 and REF2 Only) 8 kHz

LD PIN COMPARATOR

Trip Point 1.6 V Hysteresis 260 mV

These pins each have a 30 kΩ internal pull-up resistor

High speed clock is CLK input signal

When selected as a digital output (CMOS); there are other modes in which these pins are not CMOS digital outputs; see Table 54 , Register 0x017, Register 0x01A, and Register 0x01B

Applies when mux is set to any divider or counter output, or PFD up/down pulse; also applies in analog lock detect mode; usually debug mode only; beware that spurs may couple to output when any of these pins are toggling

On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor

Frequency above which the monitor always indicates the presence of the reference

Rev. | Page 14 of 80

AD9517-4

D

POWER DISSIPATION

Table 17.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER DISSIPATION, CHIP

Power-On Default 1.0 1.2 W

Full Operation; CMOS Outputs at 229 MHz 1.4 2.0 W

Full Operation; LVDS Outputs at 200 MHz 1.4 2.1 W

PD Power-Down

PD Power-Down, Maximum Sleep

VCP Supply 4 4.8 mW PLL operating; typical closed-loop configuration

POWER DELTAS, INDIVIDUAL FUNCTIONS Power delta when a function is enabled/disabled

VCO Divider 30 mW VCO divider bypassed REFIN (Differential) 20 mW All references off to differential reference enabled REF1, REF2 (Single-Ended) 4 mW

VCO 70 mW CLK input selected to VCO selected PLL 75 mW PLL off to PLL on, normal operation; no reference enabled Channel Divider 30 mW Divider bypassed to divide-by-2 to divide-by-32 LVPECL Channel (Divider Plus Output Driver) 160 mW

LVPECL Driver 90 mW Second LVPECL output turned on, same channel LVDS Channel (Divider Plus Output Driver) 120 mW

LVDS Driver 50 mW Second LVDS output turned on, same channel CMOS Channel (Divider Plus Output Driver) 100 mW

CMOS Driver (Second in Pair) 0 mW Static; second CMOS output, same pair, turned on CMOS Driver (First in Second Pair) 30 mW Static; first output, second pair, turned on Fine Delay Block 50 mW Delay block off to delay block enabled; maximum current setting

75 185 mW

31 mW

No clock; no programming; default register values; does not include power dissipated in external resistors

PLL on; internal VCO = 2750 MHz; VCO divider = 2; all channel dividers on; four LVPECL outputs at 687.5 MHz; eight CMOS outputs (10 pF load) at 229 MHz; all fine delay on, maximum current; does not include power dissipated in external resistors

PLL on; internal VCO = 2800 MHz, VCO divider = 2; all channel dividers on; four LVPECL outputs at 700 MHz; four LVDS outputs at 200 MHz; all fine delay on, maximum current; does not include power dissipated in external resistors

PD pin pulled low; does not include power dissipated in terminations

PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b; SYNC power-down, Register 0x230[2] = 1b; REF for distribution power-down, Register 0x230[1] = 1b

All references off to REF1 or REF2 enabled; differential reference not enabled

No LVPECL output on to one LVPECL output on, independent of frequency

No LVDS output on to one LVDS output on; see Figure 8 for dependence on output frequency

Static; no CMOS output on to one CMOS output on; see Figure 9 for variation over output frequency

Rev. | Page 15 of 80

AD9517-4

K

D

TIMING DIAGRAMS

t

CLK

CL

DIFFERENTIAL

80%

20%

t

LVDS

t

PECL

LVDS

t

CMOS

Figure 2. CLK/

DIFFERENTIAL

80%

20%

Figure 3. LVPECL Timing, Differential

CLK

to Clock Output Timing, DIV = 1

LVPECL

t

RP

t

RL

06428-060

Figure 4. LVDS Timing, Differential

SINGL E-ENDE D

80%

CMOS

10pF LOAD

20%

t

FP

06428-061

t

RC

Figure 5. CMOS Timing, Single-Ended, 10 pF Load

t

FL

t

FC

06428-062

06428-063

Rev. | Page 16 of 80

AD9517-4

D

ABSOLUTE MAXIMUM RATINGS

Table 18.

Parameter Rating

VS, VS_LVPECL to GND −0.3 V to +3.6 V VCP to GND −0.3 V to +5.8 V REFIN, REFIN to GND

REFIN to REFIN

−0.3 V to V

−3.3 V to +3.3 V

+ 0.3 V

S

RSET to GND −0.3 V to VS + 0.3 V CPRSET to GND −0.3 V to VS + 0.3 V CLK, CLK to GND

CLK to CLK SCLK, SDIO, SDO, CS to GND OUT0, OUT0, OUT1, OUT1, OUT2, OUT2,

OUT3, OUT3 OUT6, OUT6

,OUT4, OUT4, OUT5, OUT5, , OUT7, OUT7 to GND

SYNC to GND

−0.3 V to V

−1.2 V to +1.2 V

−0.3 V to V

+ 0.3 V

S

+ 0.3 V

S

+ 0.3 V

S

+ 0.3 V

S

REFMON, STATUS, LD to GND −0.3 V to VS + 0.3 V Junction Temperature1 150°C Storage Temperature Range −65°C to +150°C Lead Temperature (10 sec) 300°C

1

See Table 19 for θJA.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

Table 19.

Package Type1 θ

Unit

JA

48-Lead LFCSP 24.7 °C/W

1

Thermal impedance measurements were taken on a 4-layer board in still air

in accordance with EIA/JESD51-2.

ESD CAUTION

Rev. | Page 17 of 80

AD9517-4

D

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REFIN (REF 1)

REFIN (REF 2)

CPRSETVSRSETVSOUT0

4847464544434241403938

OUT0

VS_LVPECL

OUT1

VS

37

REFMON

REF_SEL

BYPASS

NOTES

1. THE EXTERNAL PADDLE ON T HE BOTTO M OF THE PACKAGE MUST BE CONNECTED TO GROUND FO R PROPER OPERAT ION.

LD

VCP

CP

STATUS

SYNC

VS

CLK

1

2

3

4

5

6

7

8

LF

9

10

11

12

PIN 1 INDICATO R

13141516171819

CS

SCLK

Table 20. Pin Function Descriptions

Input/

Pin No.

Output

Pin Type Mnemonic Description

1 O 3.3 V CMOS REFMON

2 O 3.3 V CMOS LD

3 I Power VCP

4 O 3.3 V CMOS CP 5 O 3.3 V CMOS STATUS 6 I 3.3 V CMOS REF_SEL

7 I 3.3 V CMOS

SYNC

8 I Loop filter LF

9 O Loop filter BYPASS 10, 24, 25,

I Power VS 30, 31, 36, 37, 43, 45

11 I

Differential

CLK

clock input

12 I

Differential

Along with CLK, this is the self-biased differential input for the clock distribution

CLK

clock input 13 I 3.3 V CMOS SCLK 14 I 3.3 V CMOS

Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up

CS

36

S

V

35

OUT4 (OUT4A)

34

OUT4 (OUT4B)

33

OUT5 (OUT5A)

32

VS

OUT5 (OUT5B)

31

VS

30

VS

29

OUT7 (OUT7B)

28

OUT7 (OUT7A)

27

OUT6 (OUT6B)

26

OUT6 (OUT6A)

25

V

S

06428-003

AD9517-4

TOP VIEW

(Not to Scale)

SDO

SDIO

RESET

PD

OUT2

2021222324

OUT2

OUT3

VS_LVPECL

Figure 6. Pin Configuration

Reference Monitor (Output). This pin has multiple selectable outputs; see Table 54, Register 0x01B.

Lock Detect (Output). This pin has multiple selectable outputs; see Table 5 4, Register 0x01A.

Power Supply for Charge Pump (CP); V

≤ VCP ≤ 5.0 V. This pin is usually 3.3 V for

S

most applications; but if a 5 V external VCXO is used, this pin should be 5 V. Charge Pump (Output). Connects to external loop filter. Status (Output). This pin has multiple selectable outputs; see Table 54, Register 0x017. Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ

pull-down resistor. Manual Synchronizations and Manual Holdover. This pin initiates a manual

synchronization and is also used for manual holdover. Active low. This pin has an internal 30 kΩ pull-up resistor.

Loop Filter (Input). Connects to VCO control voltage node internally. This pin has 31 pF of internal capacitance to ground, which may influence the loop filter design for large loop bandwidths.

This pin is for bypassing the LDO to ground with a capacitor.

3.3 V Power Pins.

Along with CLK

, this is the self-biased differential input for the clock distribution

section. This pin can be left floating if internal VCO is used.

section. This pin can be left floating if internal VCO is used. Serial Control Port Data Clock Signal.

resistor.

Rev. | Page 18 of 80

AD9517-4

D

Input/

Pin No.

15 O 3.3 V CMOS SDO Serial Control Port. Unidirectional serial data output. 16 I/O 3.3 V CMOS SDIO

17 I 3.3 V CMOS 18 I 3.3 V CMOS 21, 40 I Power VS_LVPECL Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins. 42 O LVPECL OUT0 LVPECL Output; One Side of a Differential LVPECL Output. 41 O LVPECL 39 O LVPECL OUT1 LVPECL Output; One Side of a Differential LVPECL Output. 38 O LVPECL 19 O LVPECL OUT2 LVPECL Output; One Side of a Differential LVPECL Output. 20 O LVPECL 22 O LVPECL OUT3 LVPECL Output; One Side of a Differential LVPECL Output. 23 O LVPECL 35 O

34 O

33 O

32 O

26 O

27 O

28 O

29 O

44 O

46 O

47 I

48 I

EPAD GND GND

Output Pin Type Mnemonic Description

Serial Control Port. Bidirectional serial data input/output and unidirectional serial data input.

Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor. Chip Power Down, Active Low. This pin has an internal 30 kΩ pull-up resistor.

LVPECL Output; One Side of a Differential LVPECL Output.

LVPECL Output; One Side of a Differential LVPECL Output. LVDS/CMOS Output; One Side of a Differential LVDS Output

or a Single-Ended CMOS Output.

or a Single-Ended CMOS Output. LVDS/CMOS Output; One Side of a Differential LVDS Output

or a Single-Ended CMOS Output.

or a Single-Ended CMOS Output. LVDS/CMOS Output; One Side of a Differential LVDS Output

or a Single-Ended CMOS Output.

or a Single-Ended CMOS Output. LVDS/CMOS Output; One Side of a Differential LVDS Output

or a Single-Ended CMOS Output.

Alternatively, this pin is a single-ended input for REF2. Along with REFIN

Alternatively, this pin is a single-ended input for REF1. Ground. The external paddle on the bottom of the package must be connected to

ground for proper operation.

LVDS or CMOS

Current set resistor

Reference input

RESET PD

OUT0

OUT1

OUT2

OUT3 OUT4 (OUT4A)

(OUT4B) LVDS/CMOS Output; One Side of a Differential LVDS Output

OUT4

OUT5 (OUT5A)

(OUT5B) LVDS/CMOS Output; One Side of a Differential LVDS Output

OUT5

OUT6 (OUT6A)

(OUT6B) LVDS/CMOS Output; One Side of a Differential LVDS Output

OUT6

OUT7 (OUT7A)

(OUT7B) LVDS/CMOS Output; One Side of a Differential LVDS Output

OUT7

RSET Resistor connected here sets internal bias currents. Nominal value = 4.12 kΩ.

CPRSET Resistor connected here sets CP current range. Nominal value = 5.1 kΩ.

(REF2) Along with REFIN, this is the self-biased differential input for the PLL reference.

REFIN

REFIN (REF1)

, this is the self-biased differential input for the PLL reference.

Rev. | Page 19 of 80

AD9517-4

D

TYPICAL PERFORMANCE CHARACTERISTICS

240

220

200

180

160

CURRENT (mA)

140

2 CHANNELS—4 LVPE CL

2 CHANNELS—2 LVPE CL

50

45

40

35

(MHz/V)

VCO

K

30

120

100

0 500 1000 1500 2000 2500 3000

1 CHANNEL—1 LVPECL

FREQUENCY (MHz)

Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs

180

2 CHANNELS—4 LVDS

160

140

120

CURRENT (mA)

100

80

0 200 400 600 800

2 CHANNELS—2 LVDS

1 CHANNEL—1 LVDS

FREQUENCY (MHz )

Figure 8. Current vs. Frequency—LVDS Outputs

(Includes Clock Distribution Current Draw)

240

220

200

180

160

140

CURRENT (mA)

120

100

2 CHANNELS—8 CMOS

1 CHANNEL—2 CMOS

80

0220015010050

2 CHANNELS—2 CMOS

1 CHANNEL—1 CMOS

FREQUENCY (MHz )

Figure 9. Current vs. Frequency—CMOS Outputs

25

20

1.45 1.55 1. 65 1.75

06428-007

VCO FREQUENCY ( GHz)

Figure 10. VCO K

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

CURRENT FROM CP P IN (mA)

1.0

0.5

06428-008

PUMP DOWN PUMP UP

0

0 0.5 1.0 1.5 2.0 2.5 3.0

VOLTAGE ON CP PIN (V)

Figure 11. Charge Pump Characteristics at V

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

CURRENT FROM CP P IN (mA)

1.0

0.5

50

06428-009

0

PUMP DOWN PUMP UP

0 0.5 1.0 1.5 2.0 3.0 4.02. 5 3.5 5.04.5

VOLTAGE ON CP PIN (V)

Figure 12. Charge Pump Characteristics at V

vs. Frequency

VCO

= 3.3 V

CP

= 5.0 V

CP

06428-200

06428-011

06428-012

Rev. | Page 20 of 80

AD9517-4

–

D

140

–145

–150

–155

(dBc/Hz)

–160

–165

PFD PHASE NOI SE REFERRED TO PFD INPUT

–170

0.1 1 10010

PFD FREQUENCY (MHz)

Figure 13. PFD Phase Noise Referred to PFD Input vs. PFD Frequency

210

–212

–214

–216

–218

–220

PLL FIGURE OF MERIT (dBc/ Hz)

–222

–224

022.01.51.00. 5

SLEW RATE (V/n s)

Figure 14. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/

2.1

1.9

1.7

1.5

1.3

VCO TUNING V OLTAGE (V)

1.1

0.9

1.45 1.55 1.65 1.751.50 1.60 1.70 1.80

FREQUENCY (GHz)

Figure 15. VCO Tuning Voltage vs. Frequency

(Note that VCO calibration centers the dc tuning voltage

for the PLL setup that is active during calibration.)

10

0

–10

–20

–30

–40

–50

–60

–70

RELATIVE POWER (dB)

–80

–90

–100

–110

CENTER 122.88MHz SPAN 50MHz5MHz/DIV

06428-013

Figure 16. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz;

LBW = 135 kHz; I

10

0

–10

–20

–30

–40

–50

–60

–70

RELATIVE POWER (dB)

–80

–90

–100

–110

.5

06428-136

REFIN

CENTER 122.88MHz SPAN 1MHz100kHz/DIV

Figure 17. Output Spectrum, LVPECL; 122.88 MHz; PFD = 15.36 MHz;

LBW = 135 kHz; I

10

0

–10

–20

–30

–40

–50

–60

–70

RELATIVE POWER (dB)

–80

–90

–100

–110

CENTER 122.88MHz SPAN 1MHz100kHz/DIV

06428-201

Figure 18. Output Spectrum, LVDS; 122.88 MHz; PFD = 15.36 MHz;

LBW = 135 kHz; I

= 3 mA; f

CP

= 3 mA; f

CP

= 3 mA; f

CP

= 1.475 GHz

VCO

= 1.475 GHz

VCO

= 1.475 GHz

VCO

06428-202

06428-203

06428-204

Rev. | Page 21 of 80

AD9517-4

D

1.0

0.4

0.6

0.2

–0.2

DIFFERENTIAL OUTPUT (V)

–0.6

–1.0

022015105

TIME (ns)

Figure 19. LVPECL Output (Differential) at 100 MHz

1.0

0.6

0.2

–0.2

DIFFERENTIAL OUTPUT (V)

–0.6

0.2

0

–0.2

DIFFERENTIAL OUTPUT (V)

–0.4

5

06428-014

021

Figure 22. LVDS Output (Differential) at 800 MHz

2.8

1.8

OUTPUT (V)

0.8

TIME (ns)

06428-017

–1.0

021

TIME (ns)

Figure 20. LVPECL Output (Differential) at 1600 MHz

0.4

0.2

0

–0.2

DIFFERENTIAL OUTPUT (V)

–0.4

022015105

TIME (ns)

Figure 21. LVDS Output (Differential) at 100 MHz

–0.2

0860 1004020

06428-015

Figure 23. CMOS Output at 25 MHz

2.8

1.8

OUTPUT (V)

0.8

–0.2

5

06428-016

08611042

Figure 24. CMOS Output at 250 MHz

TIME (ns)

0

06428-018

2

06428-019

Rev. | Page 22 of 80

AD9517-4

–

D

1600

1400

80

–90

–100

1200

1000

DIFFERENTIAL SWING (mV p-p)

800

0321

FREQUENCY (GHz)

Figure 25. LVPECL Differential Swing vs. Frequency

Using a Differential Probe Across the Output Pair

700

600

DIFFERENTIAL SWING (mV p-p)

500

08700600500400300200100

FREQUENCY (MHz )

Figure 26. LVDS Differential Swing vs. Frequency

Using a Differential Probe Across the Output Pair

3

CL = 2pF

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

10k 100M10M1M100k

06428-020

FREQUENCY (Hz)

Figure 28. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 1800 MHz

80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

00

06428-021

–150

10k 100M10M1M10k

FREQUENCY (Hz)

Figure 29. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 1625 MHz

80

–90

06428-205

06428-206

C

= 10pF

L

2

= 20pF

C

OUTPUT SWING (V)

1

0

0 600500400300200100

OUTPUT FREQUENCY (MHz)

L

Figure 27. CMOS Output Swing vs. Frequency and Capacitive Load

06428-133

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

10k 100M10M1M100k

FREQUENCY (Hz)

06428-207

Figure 30. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 1450 MHz

Rev. | Page 23 of 80

AD9517-4

–

D

120

–125

–130

110

–120

–135

–140

–145

PHASE NOISE (dBc/Hz)

–150

–155

–160

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 31. Phase Noise (Additive) LVPECL at 245.76 MHz, Divide-by-1

110

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 32. Phase Noise (Additive) LVPECL at 200 MHz, Divide-by-5

100

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

10 100M1k 10k 100k 1M 10 M100

06428-026

FREQUENCY (Hz)

06428-142

Figure 34. Phase Noise (Additive) LVDS at 200 MHz, Divide-by-1

100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

10 100M10M1M100k10k1k100

06428-027

FREQUENCY (Hz)

06428-130

Figure 35. Phase Noise (Additive) LVDS at 800 MHz, Divide-by-2

120

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 33. Phase Noise (Additive) LVPECL at 1600 MHz, Divide-by-1

06428-128

–130

–140

–150

PHASE NOISE (dBc/Hz)

–160

–170

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 36. Phase Noise (Additive) CMOS at 50 MHz, Divide-by-20

06428-131

Rev. | Page 24 of 80

ANALOG DEVICES AD9517-4 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

POWER SUPPLY REQUIREMENTS

PLL CHARACTERISTICS

CLOCK INPUTS

CLOCK OUTPUTS

TIMING CHARACTERISTICS

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)

CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)

DELAY BLOCK ADDITIVE TIME JITTER

SERIAL CONTROL PORT

LD, STATUS, AND REFMON PINS

POWER DISSIPATION

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS