ANALOG DEVICES AD9517-2 Service Manual

12-Output Clock Generator with

www.BDTIC.com/ADI

FEATURES

Low phase noise, phase-locked loop

On-chip VCO tunes from 2.05 GHz to 2.33 GHz External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Auto and manual reference switchover/holdover modes Autorecover from holdover Accepts references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable

2 pairs of 1.6 GHz LVPECL outputs

Each pair shares 1 to 32 dividers with coarse phase delay Additive output jitter 225 f Channel-to-channel skew paired outputs <10 ps

2 pairs of 800 MHz LVDS clock outputs

Each pair shares two cascaded 1 to 32 dividers with coarse

phase del

ay Additive output jitter 275 f Fine delay adjust (ΔT) on each LVDS output

Eight 250 MHz CMOS outputs (two per LVDS output) Automatic synchronization of all outputs on power-up Manual synchronization of outputs as needed Serial control port 48-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure AT E

GENERAL DESCRIPTION

The AD9517-21 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.05 GHz to 2.33 GHz. Optionally, an external VCO/VCXO of up to

2.4 GHz can be used.

The AD9517-2 emphasizes low jitter and phase noise to max

imize data converter performance, and it can benefit other

applications with demanding phase noise and jitter requirements.

rms

S

rms

S

Integrated 2.2 GHz VCO

AD9517-2

FUNCTIONAL BLOCK DIAGRAM

PLL

ΔT

LF

STATUS

MONITOR

VCO

LVPECL

LVDS/CMOS

AD9517-2

CP

REF1

REFIN

REF2

SWITCHOVER

AND MONITOR

CLK

DIV/Φ DIV/Φ

SERIAL CONT ROL PORT

DIVIDER

AND MUXs

DIV/Φ

AND

DIGITAL LOGIC

Figure 1.

The AD9517-2 features four LVPECL outputs (in two pairs); four LVDS outputs (in two pairs); and eight CMOS outputs (two per LVDS output). The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.

Each pair of outputs has dividers that allow both the divide

atio and coarse delay (or phase) to be set. The range of division

r for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.

The AD9517-2 is available in a 48-lead LFCSP and can be op

erated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. A separate LVPECL power supply can be from 2.375 V to 3.6 V.

The AD9517-2 is specified for operation over the standard

ustrial range of −40°C to +85°C.

ind

1

AD9517 is used throughout to refer to all the members of the AD9517

family. However, when AD9517-2 is used, it is referring to that specific member of the AD9517 family.

OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7

06426-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9517-2

www.BDTIC.com/ADI

REVISION HISTORY

7/07—Revision 0: Initial Version

Register Map Overview ..................................................................56

Register Map Descriptions.............................................................60

Application Notes............................................................................78

Using the AD9517 Outputs for ADC Clock Applications ....78

LVPECL Clock D i s t ribut io n ......................................................78

LVDS Clock Distribution...........................................................78

CMOS Clock Distribution.........................................................79

Outline Dimensions........................................................................80

Ordering Guide...........................................................................80

Rev. 0 | Page 3 of 80

AD9517-2

www.BDTIC.com/ADI

SPECIFICATIONS

Typical (typ) is given for VS = V unless otherwise noted. Minimum (min) and maximum (max) values are given over full V

POWER SUPPLY REQUIREMENTS

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

V

S

V

S_LVPECL

V

CP

3.135 3.3 3.465 V This is 3.3 V ± 5%

2.375 V V

S

RSET Pin Resistor 4.12 kΩ Sets internal biasing currents; connect to ground CPRSET Pin Resistor 5.1 kΩ

BYPASS Pin Capacitor 220 nF Bypass for internal LDO regulator; necessary for LDO stability; connect to ground

PLL CHARACTERISTICS

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

VCO (ON-CHIP)

Frequency Range 2050 2335 MHz See Figure 15 VCO Gain (K Tunin g Volt age (VT) 0.5 VCP − 0.5 V

Frequency Pushing (Open-Loop) 1 MHz/V Phase Noise @ 100 kHz Offset −107 dBc/Hz f = 2175 MHz Phase Noise @ 1 MHz Offset −124 dBc/Hz f = 2175 MHz

REFERENCE INPUTS

Differential Mode (REFIN, REFIN)

Input Frequency 0 250 MHz

Input Sensitivity 250 mV p-p

Self-Bias Voltage, REFIN 1.35 1.60 1.75 V Self-bias voltage of REFIN Self-Bias Voltage, REFIN Input Resistance, REFIN 4.0 4.8 5.9 kΩ Self-biased Input Resistance, REFIN

Dual Single-Ended Mode (REF1, REF2) Two single-ended CMOS-compatible inputs

Input Frequency (AC-Coupled) 20 250 MHz Slew rate > 50 V/μs Input Frequency (DC-Coupled) 0 250 MHz Slew rate > 50 V/μs; CMOS levels Input Sensitivity (AC-Coupled) 0.8 V p-p Should not exceed VS p-p Input Logic High 2.0 V Input Logic Low 0.8 V Input Current −100 +100 μA

Input Capacitance 2 pF

) 50 MHz/V See Figure 10

VCO

= 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ,

S_LVPECL

and TA (−40°C to +85°C) variation.

S

V This is nominally 2.5 V to 3.3 V ± 5%

S

5.25 V This is nominally 3.3 V to 5.0 V ± 5%

Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);

tual current can be calculated by: CP_lsb = 3.06/CPRSET; connect to ground

ac

≤ VS when using internal VCO; outside of this

V

CP

range, the CP spurs may increase due to CP up/ down mismatch

Differential mode (can accommodate singleended input by ac grounding undriven input)

Frequencies below about 1 MHz should be

coupled; be careful to match V

dcPLL figure of merit increases with increasing

te; see Figure 14

slew ra

1.30 1.50 1.60 V

4.4 5.3 6.4 kΩ Self-biased

Self-bias voltage of REFIN

1

Each pin, REFIN/REFIN

CM

1

(REF1/REF2)

(self-bias voltage)

Rev. 0 | Page 4 of 80

AD9517-2

www.BDTIC.com/ADI

Parameter Min Typ Max Unit Test Conditions/Comments

PHASE/FREQUENCY DETECTOR (PFD)

PFD Input Frequency 100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns 45 MHz Antibacklash pulse width = 6.0 ns Antibacklash Pulse Width 1.3 ns 0x17<1:0> = 01b

2.9 ns 0x17<1:0> = 00b; 0x17<1:0> = 11b

6.0 ns 0x17<1:0> = 10b

CHARGE PUMP (CP)

ICP Sink/Source Programmable

High Value 4.8 mA With CPRSET = 5.1 kΩ

Low Value 0.60 mA

Absolute Accuracy 2.5 % CPV = VCP/2 V

CPRSET Range 2.7/10 kΩ ICP High Impedance Mode Leakage 1 nA Sink-and-Source Current Matching 2 % 0.5 < CPV < VCP − 0.5 V ICP vs. V

CP

ICP vs. Temperature 2 % CPV = VCP /2 V

PRESCALER (PART OF N DIVIDER)

Prescaler Input Frequency

P = 1 FD 300 MHz

P = 2 FD 600 MHz

P = 3 FD 900 MHz

P = 2 DM (2/3) 600 MHz

P = 4 DM (4/5) 1000 MHz

P = 8 DM (8/9) 2400 MHz

P = 16 DM (16/17) 3000 MHz

P = 32 DM (32/33) 3000 MHz Prescaler Output Frequency 300 MHz

PLL DIVIDER DELAYS Register 0x19: R<5:3>, N<2:0>; see Tab le 53

000 Off 001 330 ps 010 440 ps 011 550 ps 100 660 ps 101 770 ps 110 880 ps 111 990 ps

NOISE CHARACTERISTICS

In-Band Phase Noise of the Charge Pump/Phase Frequency Detector (In-Band Means Within the LBW of the PLL)

@ 500 kHz PFD Frequency −165 dBc/Hz

@ 1 MHz PFD Frequency −162 dBc/Hz

@ 10 MHz PFD Frequency −151 dBc/Hz

@ 50 MHz PFD Frequency −143 dBc/Hz PLL Figure of Merit (FOM) −220 dBc/Hz

1.5 % 0.5 < CPV < VCP − 0.5 V

A, B counter input frequency (prescaler

equency divided by P)

input fr

The PLL in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the value of the N divider)

Reference slew rate > 0.25 V/ns. FOM + 10 log(f is an approximation of the PFD/CP in-band phase noise (in the flat region) inside the PLL loop bandwidth; when running closed loop, the phase noise, as observed at the VCO output, is increased by 20 log(N)

PFD

)

Rev. 0 | Page 5 of 80

AD9517-2

www.BDTIC.com/ADI

Parameter Min Typ Max Unit Test Conditions/Comments

PLL DIGITAL LOCK DETECT WINDOW

Required to Lock (Coincidence of Edges) Selected by 0x17<1:0> and 0x18<4>

Low Range (ABP 1.3 ns, 2.9 ns) 3.5 ns 0x17<1:0> = 00b, 01b,11b; 0x18<4> = 1b High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns 0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 0b High Range (ABP 6 ns) 3.5 ns 0x17<1:0> = 10b; 0x18<4> = 0b

To Unlock After Lock (Hysteresis)

Low Range (ABP 1.3 ns, 2.9 ns) 7 ns 0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 1b High Range (ABP 1.3 ns, 2.9 ns) 15 ns 0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 0b High Range (ABP 6 ns) 11 ns 0x17<1:0> = 10b; 0x18<4> = 0b

1

REFIN and

2

For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

REFIN

self-bias points are offset slightly to avoid chatter on an open input condition.

CLOCK INPUTS

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

CLOCK INPUTS (CLK, CLK)

Input Frequency 0 0 Input Sensitivity, Differential 150 mV p-p

Input Level, Differential 2 V p-p

Input Common-Mode Voltage, V Input Common-Mode Range, V Input Sensitivity, Single-Ended 150 mV p-p

Input Resistance 3.9 4.7 5.7 kΩ Self-biased Input Capacitance 2 pF

1

Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.

CMR

2

Signal available at LD, STATUS, and REFMON pins when se

lected by appropriate register settings

Differential input

1

2.4 GHz High frequency distribution (VCO divider)

1

1.6 GHz Distribution only (VCO divider bypassed) Measured at 2.4 GHz; jitter performance is improved

w rates > 1 V/ns

with sle Larger voltage swings may turn on the protection

diodes and can degr

CM

1.3 1.57 1.8 V Self-biased; enables ac coupling

ade jitter performance

1.3 1.8 V With 200 mV p-p signal applied; dc-coupled CLK ac-coupled; CLK

ac-bypassed to RF ground

CLOCK OUTPUTS

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL CLOCK OUTPUTS Termination = 50 Ω to VS − 2 V

OUT0, OUT1, OUT2, OUT3

Differential (OUT, Output Frequency, Maximum 2950 MHz Using direct to output; see Figure 25 Output High Voltage (VOH) VS − 1.12 VS − 0.98 VS − 0.84 V Output Low Voltage (VOL) VS − 2.03 VS − 1.77 VS − 1.49 V Output Differential Voltage (VOD) 550 790 980 mV

LVDS CLOCK OUTPUTS Differential termination 100 Ω @ 3.5 mA

OUT4, OUT5, OUT6, OUT7

Differential (OUT, Output Frequency 800 MHz See Figure 26 Differential Output Voltage (VOD) 247 360 454 mV Delta V

OD

25 mV Output Offset Voltage (VOS) 1.125 1.24 1.375 V Delta V

OS

25 mV Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND

Rev. 0 | Page 6 of 80

OUT

)

AD9517-2

www.BDTIC.com/ADI

Parameter Min Typ Max Unit Test Conditions/Comments

CMOS CLOCK OUTPUTS

OUT4A, OUT4B, OUT5A, OUT5B, OUT6A, OUT6B, OUT7A, OUT7B

Output Frequency 250 MHz See Figure 27 Output Voltage High (VOH) VS − 0.1 V @ 1 mA load Output Voltage Low (VOL) 0.1 V @ 1 mA load

TIMING CHARACTERISTICS

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL Termination = 50 Ω to VS − 2 V; level = 810 mV

Output Rise Time, t Output Fall Time, t

PROPAGATION DELAY, t

High Frequency Clock Distribution Configuration 835 995 1180 ps See Figure 42 Clock Distribution Configuration 773 933 1090 ps See Figure 44 Variation with Temperature 0.8 ps/°C

OUTPUT SKEW, LVPECL OUTPUTS

LVPECL Outputs That Share the Same Divider 5 15 ps LVPECL Outputs on Different Dividers 13 40 ps All LVPECL Outputs Across Multiple Parts 220 ps

LVDS Termination = 100 Ω differential; 3.5 mA

Output Rise Time, t Output Fall Time, t

PROPAGATION DELAY, t

For All Divide Values 1.4 1.8 2.1 ns Variation with Temperature 1.25 ps/°C

OUTPUT SKEW, LVDS OUTPUTS

LVDS Outputs That Share the Same Divider 6 62 ps LVDS Outputs on Different Dividers 25 150 ps All LVDS Outputs Across Multiple Parts 430 ps

CMOS Termination = open

Output Rise Time, t Output Fall Time, t

PROPAGATION DELAY, t

For All Divide Values 1.6 2.1 2.6 ns Variation with Temperature 2.6 ps/°C

OUTPUT SKEW, CMOS OUTPUTS

CMOS Outputs That Share the Same Divider 4 66 ps All CMOS Outputs on Different Dividers 28 180 ps All CMOS Outputs Across Multiple Parts 675 ps

DELAY ADJUST

Shortest Delay Range

Zero Scale 50 315 680 ps 0xA2 (0xA5) (0xA8) (0xAB) <5:0> 000000b Full Scale 540 880 1180 ps 0xA2 (0xA5) (0xA8) (0xAB) <5:0> 101111b

Longest Delay Range

Zero Scale 200 570 950 ps 0xA2 (0xA5) (0xA8) (0xAB) <5:0> 000000b

Quarter Scale 1.72 2.31 2.89 ns 0xA2 (0xA5) (0xA8) (0xAB) <5:0> 001100b

Full Scale 5.7 8.0 10.1 ns 0xA2 (0xA5) (0xA8) (0xAB) <5:0> 101111b

RP

FP

, CLK-TO-LVPECL OUTPUT

PECL

1

RL

FL

, CLK-TO-LVDS OUTPUT Delay off on all outputs

LVDS

1

RC

FC

, CLK-TO-CMOS OUTPUT Fine delay off

CMOS

1

3

4

Single-ended; termination = 10 pF

70 180 ps 20% to 80%, measured differentially 70 180 ps 80% to 20%, measured differentially

170 350 ps 20% to 80%, measured differentially 160 350 ps 20% to 80%, measured differentially

2

Delay off on all outputs

495 1000 ps 20% to 80%, C 475 985 ps 80% to 20%, C

LOAD

= 10 pF = 10 pF

Fine delay off

LVDS and CMOS 0xA1 (0xA4) (0xA7) (0xAA) <5:0> 101111b

0xA1 (0xA4) (0xA7) (0xAA) <5:0> 000000b

Rev. 0 | Page 7 of 80

AD9517-2

www.BDTIC.com/ADI

Parameter Min Typ Max Unit Test Conditions/Comments

Delay Variation with Temperature

Short Delay Range

Zero Scale 0.23 ps/°C Full Scale −0.02 ps/°C

Long Delay Range

Zero Scale 0.3 ps/°C Full Scale 0.24 ps/°C

1

This is the difference between any two similar delay paths while operating at the same voltage and temperature.

2

Corresponding CMOS drivers set to A for noninverting, and B for inverting.

3

The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output.

4

Incremental delay; does not include propagation delay.

5

All delays between zero scale and full scale can be estimated by linear interpolation.

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

CLK-TO-LVPECL ADDITIVE PHASE NOISE

CLK = 1 GHz, OUTPUT = 1 GHz Input slew rate > 1 V/ns Divider = 1

@ 10 Hz Offset −109 dBc/Hz @ 100 Hz Offset −118 dBc/Hz @ 1 kHz Offset −130 dBc/Hz @ 10 kHz Offset −139 dBc/Hz @ 100 kHz Offset −144 dBc/Hz @ 1 MHz Offset −146 dBc/Hz

@ 10 MHz Offset −147 dBc/Hz

@ 100 MHz Offset −149 dBc/Hz CLK = 1 GHz, OUTPUT = 200 MHz Input slew rate > 1 V/ns Divider = 5

@ 10 Hz Offset −120 dBc/Hz @ 100 Hz Offset −126 dBc/Hz @ 1 kHz Offset −139 dBc/Hz @ 10 kHz Offset −150 dBc/Hz @ 100 kHz Offset −155 dBc/Hz @ 1 MHz Offset −157 dBc/Hz

>10 MHz Offset −157 dBc/Hz

CLK-TO-LVDS ADDITIVE PHASE NOISE

CLK = 1.6 GHz, OUTPUT = 800 MHz Input slew rate > 1 V/ns Divider = 2

@ 10 Hz Offset −103 dBc/Hz @ 100 Hz Offset −110 dBc/Hz @ 1 kHz Offset −120 dBc/Hz @ 10 kHz Offset −127 dBc/Hz @ 100 kHz Offset −133 dBc/Hz @ 1 MHz Offset −138 dBc/Hz @ 10 MHz Offset −147 dBc/Hz @ 100 MHz Offset −149 dBc/Hz

5

Distribution section only; does not include PLL and

VCO

Distribution section only; does not include PLL and

VCO

Rev. 0 | Page 8 of 80

AD9517-2

www.BDTIC.com/ADI

Parameter Min Typ Max Unit Test Conditions/Comments

CLK = 1.6 GHz, OUTPUT = 400 MHz Input slew rate > 1 V/ns Divider = 4

@ 10 Hz Offset −114 dBc/Hz @ 100 Hz Offset −122 dBc/Hz @ 1 kHz Offset −132 dBc/Hz @ 10 kHz Offset −140 dBc/Hz @ 100 kHz Offset −146 dBc/Hz @ 1 MHz Offset −150 dBc/Hz >10 MHz Offset −155 dBc/Hz

CLK-TO-CMOS ADDITIVE PHASE NOISE

CLK = 1 GHz, OUTPUT = 250 MHz Input slew rate > 1 V/ns Divider = 4

@ 10 Hz Offset −110 dBc/Hz @ 100 Hz Offset −120 dBc/Hz @ 1 kHz Offset −127 dBc/Hz @ 10 kHz Offset −136 dBc/Hz @ 100 kHz Offset −144 dBc/Hz @ 1 MHz Offset −147 dBc/Hz

>10 MHz Offset −154 dBc/Hz CLK = 1 GHz, OUTPUT = 50 MHz Input slew rate > 1 V/ns Divider = 20

@ 10 Hz Offset −124 dBc/Hz

@ 100 Hz Offset −134 dBc/Hz

@ 1 kHz Offset −142 dBc/Hz

@ 10 kHz Offset −151 dBc/Hz

@ 100 kHz Offset −157 dBc/Hz

@ 1 MHz Offset −160 dBc/Hz

>10 MHz Offset −163 dBc/Hz

Distribution section only; does not include PLL and

VCO

CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)

Table 7.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL ABSOLUTE PHASE NOISE Internal VCO; direct to LVPECL output

VCO = 2.335 GHz; OUTPUT = 2.335 GHz

@ 1 kHz Offset −46 dBc/Hz

@ 10 kHz Offset −78 dBc/Hz

@ 100 kHz Offset −105 dBc/Hz

@ 1 MHz Offset −124 dBc/Hz

@ 10 MHz Offset −141 dBc/Hz

@ 40 MHz Offset −146 dBc/Hz VCO = 2.175 GHz; OUTPUT = 2.175 GHz

@ 1 kHz Offset −51 dBc/Hz

@ 10 kHz Offset −80 dBc/Hz

@ 100 kHz Offset −107 dBc/Hz

@ 1 MHz Offset −124 dBc/Hz

@ 10 MHz Offset −142 dBc/Hz

@ 40 MHz Offset −146 dBc/Hz

Rev. 0 | Page 9 of 80

AD9517-2

www.BDTIC.com/ADI

Parameter Min Typ Max Unit Test Conditions/Comments

VCO = 2.05 GHz; OUTPUT = 2.05 GHz

@ 1 kHz Offset −53 dBc/Hz @ 10 kHz Offset −82 dBc/Hz @ 100 kHz Offset −108 dBc/Hz @ 1 MHz Offset −127 dBc/Hz @ 10 MHz Offset −142 dBc/Hz @ 40 MHz Offset −147 dBc/Hz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)

Table 8.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

VCO = 2.21 GHz; LVPECL = 245.76 MHz; PLL LBW = 138 kHz 146 fS rms Integration BW = 200 kHz to 10 MHz 329 fS rms Integration BW = 12 kHz to 20 MHz VCO = 2.21 GHz; LVPECL = 122.88 MHz; PLL LBW = 138 kHz 151 fS rms Integration BW = 200 kHz to 10 MHz 329 fS rms Integration BW = 12 kHz to 20 MHz VCO = 2.21 GHz; LVPECL = 61.44 MHz; PLL LBW = 138 kHz 203 fS rms Integration BW = 200 kHz to 10 MHz 376 fS rms Integration BW = 12 kHz to 20 MHz

Application example based on a typical setup wher clean, so a wider PLL loop bandwidth is used; reference = 15.36 MHz; R = 1

e the reference source is

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)

Table 9.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

VCO = 2.18 GHz; LVPECL = 155.52 MHz; PLL LBW = 125 Hz 515 fS rms Integration BW = 12 kHz to 20 MHz VCO = 2.21 GHz; LVPECL = 122.88 MHz; PLL LBW = 125 Hz 570 fS rms Integration BW = 12 kHz to 20 MHz

Application example based on a typical setup wher jittery, so a narrower PLL loop bandwidth is used; reference = 10.0 MHz; R = 20

e the reference source is

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)

Table 10.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

LVPECL = 245.76 MHz; PLL LBW = 125 Hz 54 fS rms Integration BW = 200 kHz to 5 MHz 77 fS rms Integration BW = 200 kHz to 10 MHz 109 fS rms Integration BW = 12 kHz to 20 MHz LVPECL = 122.88 MHz; PLL LBW = 125 Hz 79 fS rms Integration BW = 200 kHz to 5 MHz 114 fS rms Integration BW = 200 kHz to 10 MHz 163 fS rms Integration BW = 12 kHz to 20 MHz LVPECL = 61.44 MHz; PLL LBW = 125 Hz 124 fS rms Integration BW = 200 kHz to 5 MHz 176 fS rms Integration BW = 200 kHz to 10 MHz 259 fS rms Integration BW = 12 kHz to 20 MHz

Application example based on a typical setup using an

ternal 245.76 MHz VCXO (Toyocom TCO-2112);

ex reference = 15.36 MHz; R = 1

Rev. 0 | Page 10 of 80

AD9517-2

www.BDTIC.com/ADI

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

Table 11.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1 40 fS rms BW = 12 kHz to 20 MHz CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4 80 fS rms BW = 12 kHz to 20 MHz CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16 215 fS rms

CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5 245 fS rms

LVDS OUTPUT ADDITIVE TIME JITTER

CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2; VCO Divider Not Used 85 fS rms BW = 12 kHz to 20 MHz CLK = 1 GHz; LVDS = 200 MHz; Divider = 5 113 fS rms BW = 12 kHz to 20 MHz CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16 280 fS rms

CMOS OUTPUT ADDITIVE TIME JITTER

CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16 365 fS rms

Distribution section only; does not include PLL and clock signal

Calculated from SNR of ADC method;

C not used for even divides

DC Calculated from SNR of ADC method;

C on

DC Distribution section only; does not

include PLL and clock signal

Calculated from SNR of ADC method;

C not used for even divides

DC Distribution section only; does not

include PLL and clock signal

Calculated from SNR of ADC method;

C not used for even divides

DC

VCO; rising edge of

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)

Table 12.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz; Divider = 12; Duty-Cycle Correction = Off

LVDS OUTPUT ADDITIVE TIME JITTER

CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz; Divider = 12; Duty-Cycle Correction = Off

CMOS OUTPUT ADDITIVE TIME JITTER

CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz; Divider = 12; Duty-Cycle Correction = Off

210 f

285 f

350 f

Distribution section only; does not include PLL and VCO;

ising edge of clock signal

uses r

rms Calculated from SNR of ADC method

S

Distribution section only; does not include PLL and VCO;

ising edge of clock signal

uses r

rms Calculated from SNR of ADC method

S

Distribution section only; does not include PLL and VCO;

ising edge of clock signal

uses r

rms Calculated from SNR of ADC method

S

Rev. 0 | Page 11 of 80

AD9517-2

www.BDTIC.com/ADI

DELAY BLOCK ADDITIVE TIME JITTER

Table 13.

Parameter Min Typ Max Unit Test Conditions/Comments

DELAY BLOCK ADDITIVE TIME JITTER

100 MHz Output

Delay (1600 μA, 1C) Fine Adj. 000000 0.54 ps rms Delay (1600 μA, 1C) Fine Adj. 101111 0.60 ps rms Delay (800 μA, 1C) Fine Adj. 000000 0.65 ps rms Delay (800 μA, 1C) Fine Adj. 101111 0.85 ps rms Delay (800 μA, 4C) Fine Adj. 000000 0.79 ps rms Delay (800 μA, 4C) Fine Adj. 101111 1.2 ps rms Delay (400 μA, 4C) Fine Adj. 000000 1.2 ps rms Delay (400 μA, 4C) Fine Adj. 101111 2.0 ps rms Delay (200 μA, 1C) Fine Adj. 000000 1.3 ps rms Delay (200 μA, 1C) Fine Adj. 101111 2.5 ps rms Delay (200 μA, 4C) Fine Adj. 000000 1.9 ps rms Delay (200 μA, 4C) Fine Adj. 101111 3.8 ps rms

1

This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter

should be added to this value using the root sum of the squares (RSS) method.

1

Incremental additive jitter

SERIAL CONTROL PORT

Table 14.

Parameter Min Typ Max Unit Test Conditions/Comments

CS (INPUT)

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 3 μA Input Logic 0 Current 110 μA Input Capacitance 2 pF

SCLK (INPUT) SCLK has an internal 30 kΩ pull-down resistor

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 110 μA Input Logic 0 Current 1 μA Input Capacitance 2 pF

SDIO (WHEN INPUT)

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 10 nA Input Logic 0 Current 20 nA Input Capacitance 2 pF

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V

CS has an internal 30 kΩ pull-up resistor

Rev. 0 | Page 12 of 80

AD9517-2

www.BDTIC.com/ADI

Parameter Min Typ Max Unit Test Conditions/Comments

TIMING

Clock Rate (SCLK, 1/t Pulse Width High, t Pulse Width Low, t SDIO to SCLK Setup, t SCLK to SDIO Hold, t SCLK to Valid SDIO and SDO, t CS to SCLK Setup and Hold, tS, t CS Minimum Pulse Width High, t

PD

,

SYNC

, AND

Table 15.

Parameter Min Typ Max Unit Test Conditions/Comments

INPUT CHARACTERISTICS These pins each have a 30 kΩ internal pull-up resistor

Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 110 μA Logic 0 Current 1 μA Capacitance 2 pF

RESET TIMING

Pulse Width Low 50 ns

SYNC TIMING

Pulse Width Low 1.5 High speed clock cycles High speed clock is CLK input signal

LD, STATUS, REFMON PINS

) 25 MHz

SCLK

HI

LO

DS

DH

RESET

DV

H

PWH

PINS

16 ns 16 ns 2 ns

1.1 ns 8 ns 2 ns 3 ns

Table 16.

Parameter Min Typ Max Unit Test Conditions/Comments

OUTPUT CHARACTERISTICS

Output Voltage High (VOH) 2.7 V Output Voltage Low (VOL) 0.4 V

MAXIMUM TOGGLE RATE 100 MHz

ANALOG LOCK DETECT

Capacitance 3 pF

REF1, REF2, AND VCO FREQUENCY STATUS MONITOR

Normal Range 1.02 MHz

Extended Range 8 kHz

LD PIN COMPARATOR

Trip Point 1.6 V Hysteresis 260 mV

When selected as a digital output (CMOS); there are other modes in outputs; see Tab le 53, 0x17, 0x1A, and 0x1B

Applies when mux is set to an or PFD up/down pulse; also applies in analog lock detect mode; usually debug mode only; beware that spurs may couple to output when any of these pins are toggling

On-chip capacitance; used to calculate RC time constant

or analog lock detect readback; use a pull-up resistor

f

Frequency above which the monitor indicates the

esence of the reference

pr Frequency above which the monitor indicates the

esence of the reference

pr

which these pins are not CMOS digital

y divider or counter output,

Rev. 0 | Page 13 of 80

AD9517-2

www.BDTIC.com/ADI

POWER DISSIPATION

Table 17.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER DISSIPATION, CHIP

Power-On Default 1.0 1.2 W

Full Operation; CMOS Outputs at 195 MHz 1.4 2.0 W

Full Operation; LVDS Outputs at 195 MHz 1.4 2.1 W

PD

Power-Down

PD

Power-Down, Maximum Sleep

VCP Supply 1.5 mW PLL operating; typical closed-loop configuration

POWER DELTAS, INDIVIDUAL FUNCTIONS Power delta when a function is enabled/disabled

VCO Divider 30 mW VCO divider not used REFIN (Differential) 20 mW All references off to differential reference enabled REF1, REF2 (Single-Ended) 4 mW

VCO 70 mW CLK input selected to VCO selected PLL 75 mW PLL off to PLL on, normal operation; no reference enabled Channel Divider 30 mW Divider bypassed to divide-by-2 to divide-by-32 LVPECL Channel (Divider Plus Output Driver) 160 mW No LVPECL output on to one LVPECL output on LVPECL Driver 90 mW Second LVPECL output turned on, same channel LVDS Channel (Divider Plus Output Driver) 120 mW No LVDS output on to one LVDS output on LVDS Driver 50 mW Second LVDS output turned on, same channel CMOS Channel (Divider Plus Output Driver) 100 mW Static; no CMOS output on to one CMOS output on CMOS Driver (Second in Pair) 0 mW Static; second CMOS output, same pair, turned on CMOS Driver (First in Second Pair) 30 mW Static; first output, second pair, turned on Fine Delay Block 50 mW

75 185 mW

31 mW

No clock; no programming; defa does not include power dissipated in external resistors

PLL on; internal VCO = 2335 MHz; VCO divider = 2;

annel dividers on; six LVPECL outputs @ 584 MHz;

all ch eight CMOS outputs (10 pF load) @ 195 MHz; all fine delay on, maximum current; does not include power dissipated in external resistors

PLL on; internal VCO = 2335 MHz, VCO divider = 2; all channel dividers on; six L four LVDS outputs @ 195 MHz; all fine delay on, maximum current; does not include power dissipated in external resistors

PD

pin pulled low; does not include power dissipated

in terminations PD

pin pulled low; PLL power-down 0x10<1:0> = 01b; SYNC power-down 0x230<2> = 1b; REF for distribution power-down 0x230<1> = 1b

All references off to REF1 or REF2 enabled; differential

ference not enabled

re

Delay block off to delay block enabled; maximum

ent setting

curr

ult register values;

VPECL outputs @ 584 MHz;

Rev. 0 | Page 14 of 80

AD9517-2

K

www.BDTIC.com/ADI

TIMING DIAGRAMS

t

CLK

CL

DIFFERENTIAL

80%

20%

t

LVDS

t

PECL

LVDS

t

CMOS

Figure 2. CLK/

DIFFERENTIAL

80%

20%

Figure 3. LVPECL Timing, Differential

CLK

to Clock Output Timing, DIV = 1

LVPECL

t

RP

t

RL

06426-060

Figure 4. LVDS Timing, Differential

SINGL E-ENDE D

80%

CMOS

10pF LOAD

20%

t

FP

06426-061

t

RC

Figure 5. CMOS Timing, Single-End

t

FL

t

FC

ed, 10 pF Load

06426-062

06426-063

Rev. 0 | Page 15 of 80

AD9517-2

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 18.

With

Parameter or Pin

VS, VS_LVPECL GND −0.3 V to +3.6 V VCP GND −0.3 V to +5.8 V REFIN, REFIN REFIN RSET GND −0.3 V to VS + 0.3 V CPRSET GND −0.3 V to VS + 0.3 V CLK, CLK CLK

SCLK, SDIO, SDO, CS OUT0, OUT0, OUT1, OUT1,

OUT2, OUT2 OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7

SYNC REFMON, STATUS, LD GND −0.3 V to VS + 0.3 V Junction Temperature Storage Temperature Range −65°C to +150°C Lead Temperature (10 sec) 300°C

1

See Table 19 for θJA.

, OUT3, OUT3,

1

Respec

t To Rating

GND −0.3 V to VS + 0.3 V REFIN

GND −0.3 V to VS + 0.3 V CLK GND −0.3 V to VS + 0.3 V GND −0.3 V to VS + 0.3 V

GND −0.3 V to V

150°C

−3.3 V to +3.3 V

−1.2 V to +1.2 V

+ 0.3 V

S

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

Table 19.

Package Type

48-Lead LFCSP 28.5 °C/W

1

Thermal impedance measurements were taken on a 4-layer board in still air

in accordance with EIA/JESD51-7.

1

θ

JA

Unit

ESD CAUTION

Rev. 0 | Page 16 of 80

AD9517-2

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REFIN (REF 1)

REFIN (REF 2)

CPRSETVSRSETVSOUT0

4847464544434241403938

OUT0

VS_LVPECL

OUT1

VS

37

REFMON

LD

VCP

CP

STATUS

REF_SEL

SYNC

BYPASS

VS

CLK

1

PIN 1

2

INDICAT OR

3

4

5

6

7

8

LF

9

10

11

12

AD9517-2

TOP VIEW

(Not to Scale)

13141516171819

CS

SCLK

PD

SDO

SDIO

RESET

2021222324

OUT2

S_LVPECL

OUT3

36

S

V

35

OUT4 (OUT4A)

34

OUT4 (OUT4B)

33

OUT5 (OUT5A)

32

OUT5 (OUT5B)

31

VS

30

VS

29

OUT7 (OUT7B)

28

OUT7 (OUT7A)

27

OUT6 (OUT6B)

26

OUT6 (OUT6A)

25

S

V

VS

OUT3

06426-003

Figure 6. Pin Configuration

Table 20. Pin Function Descriptions

Pin No. Mnemonic Description

1 REFMON Reference Monitor (Output). This pin has multiple selectable outputs; see Tabl e 53 0x1B. 2 LD Lock Detect (Output). This pin has multiple selectable outputs; see Table 5 3 0x1A. 3 VCP 4 CP 5 STATUS 6 REF_SEL 7

SYNC

Power Supply for Charge Pump (CP); VS < VCP < 5.0 V. Charge Pump (Output). Connects to external loop filter. Status (Output). This pin has multiple selectable outputs; see Table 53 0x17. Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ pull-down resistor. Manual Synchronizations and Manual Holdover. This pin initiates a manual synchronization and is

also used for manual holdover. Active low. This pin has an internal 30 kΩ pull-up resistor. 8 LF 9 BYPASS 10, 24, 25, 30, 31,

VS

Loop Filter (Input). Connects to VCO control voltage node internally.

This pin is for bypassing the LDO to ground with a capacitor.

3.3 V Power Pins.

36, 37, 43, 45 11 CLK

12

CLK 13 SCLK 14

CS

Along with CLK Along with CLK, this is the differential input for the clock distribution section. Serial Control Port Data Clock Signal. Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up resistor.

, this is the differential input for the clock distribution section.

15 SDO Serial Control Port Unidirectional Serial Data Out. 16 SDIO 17

18

RESET

PD 21, 40 VS_LVPECL 42 OUT0 41

OUT0 39 OUT1 38

OUT1

Serial Control Port Bidirectional Serial Data In/Out. Chip Reset; Active Low. This pin has an internal 30 kΩ pull-up resistor.

Chip Power Down; Active Low. This pin has an internal 30 kΩ pull-up resistor. Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.

LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output.

19 OUT2 LVPECL Output; One Side of a Differential LVPECL Output.

Rev. 0 | Page 17 of 80

AD9517-2

www.BDTIC.com/ADI

Pin No. Mnemonic Description

20 22 OUT3 LVPECL Output; One Side of a Differential LVPECL Output. 23 35 OUT4 (OUT4A) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output. 34 33 OUT5 (OUT5A) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output. 32 26 OUT6 (OUT6A) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output. 27 28 OUT7 (OUT7A) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output. 29 44 RSET Resistor connected here sets internal bias currents. Nominal value = 4.12 kΩ. 46 CPRSET Resistor connected here sets the CP current range. Nominal value = 5.1 kΩ. 47

48 REFIN (REF1)

EPAD GND Ground; External Paddle (EPAD). This is the only ground for the part.

OUT2

OUT3

(OUT4B)

OUT4

(OUT5B)

OUT5

(OUT6B)

OUT6

(OUT7B)

OUT7

(REF2) Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a

REFIN

LVPECL Output; One Side of a Differential LVPECL Output.

LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output.

single-ended input for REF2. Along with REFIN

single-ended input for REF1.

, this is the differential input for the PLL reference. Alternatively, this pin is a

Rev. 0 | Page 18 of 80

AD9517-2

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

240

220

200

180

160

CURRENT (mA)

140

120

100

0 500 1000 1500 2000 2500 3000

Figure 7. Current vs. Frequency, Direct

2 CHANNELS—4 LVPE CL

2 CHANNELS—2 LVPE CL

1 CHANNEL—1 LVPECL

FREQUENCY (MHz)

to Output, LVPECL Outputs

06426-007

180

2 CHANNELS—4 LVDS

160

140

120

CURRENT (mA)

100

80

0 200 400 600 800

2 CHANNELS—2 LVDS

1 CHANNEL—1 LVDS

FREQUENCY (MHz )

06426-008

Figure 8. Current vs. Frequency—LVDS Outputs

240

220

200

180

160

140

CURRENT (mA)

120

100

2 CHANNELS—8 CMOS

2 CHANNELS—2 CMOS

1 CHANNEL—2 CMOS

80

02

FREQUENCY (MHz )

1 CHANNEL—1 CMOS

010050

5020015

06426-009

Figure 9. Current vs. Frequency—CMOS Outputs

48

46

44

42

40

(MHz/V)

38

VCO

K

36

34

32

30

2.00 2.05 2.10 2.15 2.20 2. 25 2. 30 2. 35

VCO FREQUENCY (GHz)

Figure 10. VCO K

vs. Frequency

VCO

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

CURRENT FROM CP PIN (mA)

1.0

0.5

PUMP DOWN PUMP UP

0

0 0.5 1.0 1.5 2.0 2.5 3.0

VOLTAGE ON CP PIN (V)

Figure 11. Charge Pump Characteristics @ VCP = 3.3 V

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

CURRENT FROM CP PIN (mA)

1.0

0.5

0

PUMP DOWN PUMP UP

0 0.5 1.0 1.5 2.0 3.0 4.02.5 3.5 5. 04.5

VOLTAGE ON CP PIN (V)

Figure 12. Charge Pump Characteristics @ VCP = 5.0 V

06426-010

06426-011

06426-012

Rev. 0 | Page 19 of 80

AD9517-2

–

www.BDTIC.com/ADI

140

–145

–150

–155

(dBc/Hz)

–160

–165

PFD PHASE NOI SE REFERRED T O PFD INP UT

–170

0.1 1 10010

PFD FREQUENCY (MHz)

Figure 13. PFD Phase Noise Referred to PFD Input vs. PFD Frequency

210

–212

–214

–216

–218

–220

PLL FIGURE OF MERI T (dBc/Hz)

–222

–224

02

Figure 14. PLL Figure

SLEW RATE (V/n s)

of Merit (FOM) vs. Slew Rate at REFIN/

1.9

1.8

1.7

1.6

1.5

1.4

VCO TUNING VO LTAGE (V)

1.3

1.2

2.0 2.42.32.22.1

FREQUENCY (GHz)

Figure 15. VCO Tuning Voltage vs. Frequency

REFIN

10

0

–10

–20

–30

–40

–50

–60

–70

RELATIVE POWER (dB)

–80

–90

–100

–110

CENTER 122.88MHz SPAN 50MHz5MHz/DIV

06426-013

06426-137

Figure 16. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz;

LBW

= 138 kHz; I

10

0

–10

–20

–30

–40

–50

–60

–70

RELATIVE POWER (dB)

–80

–90

–100

–110

.52.01.51.00. 5

06426-136

06426-138

CENTER 122. 88MHz SP AN 1MHz100kHz/DIV

Figure 17. Output Spectrum, LVPECL; 122.88 MHz; PFD = 15.36 MHz;

= 138 kHz; I

LBW

10

0

–10

–20

–30

–40

–50

–60

–70

RELATIVE POWER (dB)

–80

–90

–100

–110

CENTER 122.88MHz SPAN 1MHz100kHz/DIV

= 3.0 mA; F

CP

= 3.0 mA; F

CP

= 2.21 GHz

VCO

= 2.21 GHz

VCO

06426-135

06426-134

Figure 18. Output Spectrum, LVDS; 122.88 MHz; PFD = 15.36 MHz;

LBW

= 138 kHz; I

= 3.0 mA; F

CP

= 2.21 GHz

VCO

Rev. 0 | Page 20 of 80

AD9517-2

www.BDTIC.com/ADI

0.4

0.2

0

–0.2

1.0

0.

0.2

6

DIFFERENT IAL OUTPUT (V)

–0.6

–1.0

025

TIME (ns)

2015105

06426-014

Figure 19. LVPECL Output (Differential) @ 100 MHz

–0.2

DIFFERENT IAL OUTPUT (V)

–0.4

021

Figure 22. LVDS Output (Differential) @ 800 MHz

1.0

0.6

0.2

–0.2

DIFFERENT IAL OUTPUT (V)

–0.6

–1.0

021

TIME (ns)

Figure 20. LVPECL Output (Differential) @ 1600 MHz

06426-015

2.8

1.8

OUTPUT (V)

0.8

–0.2

0860 1004020

Figure 23. CMOS Output @ 25 MHz

0.4

TIME (ns)

06426-017

0

06426-018

0.2

0

–0.2

DIFFERENT IAL OUTPUT (V)

–0.4

02

TIME (ns)

2015105

5

06426-016

Figure 21. LVDS Output (Differential) @ 100 MHz

Rev. 0 | Page 21 of 80

OUTPUT (V)

2.8

1.8

0.8

–0.2

086121042

Figure 24. CMOS Output @ 250 MHz

TIME (ns)

06426-019

AD9517-2

–

www.BDTIC.com/ADI

1600

70

–80

1400

1200

1000

DIFFERENTIAL SWING (mV p-p)

800

0321

FREQUENCY (GHz)

Figure 25. LVPECL Differential Swing vs. Frequency

700

600

DIFFERENT IAL SWING (mV p- p)

500

080070060050040

0300200100

FREQUENCY (MHz )

Figure 26. LVDS Differential Swing vs. Frequency

3

CL = 2pF

–90

–100

–110

–120

PHASE NOISE (dBc/Hz)

–130

–140

–150

10k 100M10M1M100k

06426-020

FREQUENCY (Hz)

06426-023

Figure 28. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 2335 MHz

80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

06426-021

10k 100M10M1M100k

FREQUENCY (Hz)

06426-024

Figure 29. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 2175 MHz

80

–90

= 10pF

C

L

2

C

= 20pF

OUTPUT SWING (V)

1

0

0 600500400300200100

OUTPUT FREQUENCY (MHz)

Figure 27. CMOS Output Swing vs. Frequency

L

and Capacitive Load

06426-133

Rev. 0 | Page 22 of 80

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

10k 100M10M1M100k

FREQUENCY (Hz)

06426-025

Figure 30. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 2050 MHz

AD9517-2

–

www.BDTIC.com/ADI

120

–125

–130

110

–120

–135

–140

–145

PHASE NOISE (dBc/Hz)

–150

–155

–160

10 100M10M1M100k10k1k100

Figure 31. Phase Noise (Additive) LV

FREQUENCY (Hz)

PECL @ 245.76 MHz, Divide-by-1

110

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 32. Phase Noise (Additive) LVPECL @ 200 M

100

Hz, Divide-by-5

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

10 100M1k 10k 100k 1M 10M100

06426-026

Figure 34. Phase Noise (Additive) LVD

FREQUENCY (Hz)

S @ 200 MHz, Divide-by-1

06426-142

100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

10 100M10M1M100k10k1k100

06426-027

Figure 35. Phase Noise (Additive) LVD

FREQUENCY (Hz)

S @ 800 MHz, Divide-by-2

06426-130

120

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

10 100M10M1M100k10k1k100

Figure 33. Phase Noise (Additive) LVPECL @ 1600 MHz, D

FREQUENCY (Hz)

ivide-by-1

06426-128

Rev. 0 | Page 23 of 80

–130

–140

–150

PHASE NOISE (dBc/Hz)

–160

–170

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 36. Phase Noise (Additive) CM

OS @ 50 MHz, Divide-by-20

06426-131

AD9517-2

–

www.BDTIC.com/ADI

100

80

–110

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 37. Phase Noise (Additive) CM

110

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

OS @ 250 MHz, Divide-by-4

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

1k 100M10M1M100k10k

06426-132

FREQUENCY (Hz)

06426-139

Figure 39. Phase Noise (Absolute) Clock Cleanup; Internal VCO @ 2.18 GHz;

P

FD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz

120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

1k 100M10M1M100k10k

FREQUENCY (Hz)

Figure 38. Phase Noise (Absolute) Clock Generation; Internal VCO @

2.2

1 GHz; PFD = 15.36 MHz; LBW = 138 kHz; LVPECL Output = 122.88 MHz

–160

1k 100M10M1M100k10k

06426-141

FREQUENCY (Hz)

06426-140

Figure 40. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) @

245.76 M

Hz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz

Rev. 0 | Page 24 of 80

ANALOG DEVICES AD9517-2 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

POWER SUPPLY REQUIREMENTS

PLL CHARACTERISTICS

CLOCK INPUTS

CLOCK OUTPUTS

TIMING CHARACTERISTICS

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)

CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)

DELAY BLOCK ADDITIVE TIME JITTER

SERIAL CONTROL PORT

LD, STATUS, REFMON PINS

POWER DISSIPATION

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS