ANALOG DEVICES AD9516-5 Service Manual

14-Output Clock Generator

FEATURES

Low phase noise, phase-locked loop (PLL)

External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic revertive and manual reference

switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable

Six 1.6 GHz LVPECL outputs, arranged in 3 groups

Each group shares a 1-to-32 divider with coarse phase delay Additive output jitter: 225 fs rms Channel-to-channel skew paired outputs of <10 ps

Four 800 MHz LVDS outputs, arranged in 2 groups

Each group has 2 cascaded 1-to-32 dividers with coarse

phase delay Additive output jitter: 275 fs rms Fine delay adjust (Δt) on each LVDS output Each LVDS output can be reconfigured as two 250 MHz

CMOS outputs

Automatic synchronization of all outputs on power-up Manual output synchronization available Available in 64-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET,

Synchronous Ethernet, OTU2/3/4

Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation

GENERAL DESCRIPTION

The AD9516-51 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO/VCXO of up to 2.4 GHz.

The AD9516-5 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.

AD9516-5

FUNCTIONAL BLOCK DIAGRAM

CP

REF1

REFIN

CLK

REF2

DIV/Φ DIV/Φ

SERIAL CONTRO L PORT

AND

DIGITAL LOGIC

SWITCHOVER

AND MONITOR

DIVIDER

AND MUXes

DIV/Φ

Figure 1.

PLL

∆t

The AD9516-5 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.

Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.

The AD9516-5 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (V LVPECL power supply can be from 2.375 V to 3.6 V (nominal).

The AD9516-5 is specified for operation over the industrial range of −40°C to +85°C.

For applications requiring an integrated EEPROM, or needing additional outputs, the AD9520-5 and AD9522-5 are available.

1

AD9516 is used throughout the data sheet to refer to all members of the AD9516

family. However, when AD9516-5 is used, it refers to that specific member of the

AD9516 family.

STATUS

MONITOR

LVPECL

LVDS/CMOS

AD9516-5

) to 5.5 V. A separate

CP

OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9

07972-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9516-5

REVISION HISTORY

8/11—Rev. 0 to Rev. A

Changes to Features, Applications, and General Description ..... 1

Changes to CPRSET Pin Resistor Parameter, Table 1 .................. 4

Change to P = 2 DM (2/3) Parameter, Table 2 .............................. 5

Changes Test Conditions/Comments, Table 4 .............................. 6

Moved Table 5 to End of Specifications and Renumbered

Sequentially ...................................................................................... 13

Change to Shortest Delay Range Parameter,

Test Conditions/Comments, Table 14 .......................................... 13

Moved Timing Diagrams ............................................................... 14

Change to Endnote, Table 16 ......................................................... 15

Change to Caption, Figure 8 .......................................................... 18

Change to Captions, Figure 20 and Figure 21 ............................. 20

Moved Figure 23 and Figure 24 ..................................................... 21

Added Figure 31; Renumbered Sequentially ............................... 22

Change to Mode 1—Clock Distribution or External VCO <

1600 MHz Section .......................................................................... 25

Changes to Mode 2 (High Frequency Clock Distribution)—

CLK or External VCO > 1600 MHz; Change to Table 22 .......... 26

Change to Charge Pump (CP) Section ......................................... 28

Changes to PLL Reference Inputs and Reference Switchover

Sections ............................................................................................. 29

Changes to Prescaler Section and Table 24 .................................. 30

Changes to A and B Counters, Digital Lock Detect (DLD),

and Current Source Digital Lock Detect (CSDLD) Sections .... 31

Change to Holdover Section .......................................................... 32

Changes to Automatic/Internal Holdover Mode ........................ 34

Changes to Clock Distribution Section ........................................ 35

Changes to Channel Dividers—LVDS/CMOS Outputs

Section .............................................................................................. 37

Change to the Instruction Word (16 Bits) Section ..................... 45

Change to Figure 53 ........................................................................ 46

Changes to θ Changes to Register Address 0x003 and

Register Address 0x01C, Table 47 ................................................. 49

Changes to Register Address 0x003, Table 48 ............................. 52

Changes to Register Address 0x016, Bits[2:0], Table 49 ............ 54

Changes to Register Address 0x01C, Bits[4:3], Table 49 ........... 57

Changes to Register Address 0x191, Register Address 0x194,

and Register Address 0x197, Bit 5, Table 53 ................................ 66

Added Frequency Planning Using the AD9516 Section ............ 71

Changes to LVPECL Clock Distribution and LVDS Clock Distribution Sections; Changes to Figure 59, Figure 60, and

Figure 61 ........................................................................................... 72

1/09—Revision 0: Initial Version

and ΨJT Parameters, Table 46 ............................... 48

JA

Rev. A | Page 3 of 76

AD9516-5

SPECIFICATIONS

Typical is g i v e n for VS = V Minimum and maximum values are given over full V

POWER SUPPLY REQUIREMENTS

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

VS 3.135 3.3 3.465 V 3.3 V ± 5% V

2.375 VS V Nominally 2.5 V to 3.3 V ± 5%

S_LVPECL

VCP V RSET Pin Resistor 4.12 kΩ Sets internal biasing currents; connect to ground CPRSET Pin Resistor 2.7 5.1 10 kΩ

PLL CHARACTERISTICS

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE INPUTS

Differential Mode (REFIN, REFIN)

Input Frequency 0 250 MHz

Input Sensitivity 250 mV p-p

Self-Bias Voltage, REFIN 1.35 1.60 1.75 V Self-bias voltage of REFIN1 Self-Bias Voltage, REFIN Input Resistance, REFIN 4.0 4.8 5.9 kΩ Self-biased1 Input Resistance, REFIN

Dual Single-Ended Mode (REF1, REF2) Two single-ended CMOS-compatible inputs

Input Frequency (AC-Coupled) 20 250 MHz Slew rate > 50 V/μs Input Frequency (DC-Coupled) 0 250 MHz Slew rate > 50 V/μs; CMOS levels Input Sensitivity (AC-Coupled) 0.8 V p-p Should not exceed VS p-p Input Logic High 2.0 V Input Logic Low 0.8 V Input Current −100 +100 μA

Input Capacitance 2 pF

PHASE/FREQUENCY DETECTOR (PFD)

PFD Input Frequency 100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns 45 MHz Antibacklash pulse width = 6.0 ns Antibacklash Pulse Width 1.3 ns Register 0x017[1:0] = 01b

2.9 ns Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b

6.0 ns Register 0x017[1:0] = 10b

CHARGE PUMP (CP)

ICP Sink/Source Programmable

High Value 4.8 mA With CP Low Value 0.60 mA Absolute Accuracy 2.5 % CPV = VCP/2

CPRSET Range 2.7/10 kΩ ICP High Impedance Mode Leakage 1 nA Sink-and-Source Current Matching 2 % 0.5 < CPV < VCP − 0.5 V ICP vs. CPV 1.5 % 0.5 < CPV < VCP − 0.5 V ICP vs. Temperature 2 % VCP = VCP/2 V

= 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; R

S_LVPECL

and TA (−40°C to +85°C) variation.

S

5.25 V Nominally 3.3 V to 5.0 V ± 5%

S

1.30 1.50 1.60 V

4.4 5.3 6.4 kΩ Self-biased

Rev. A | Page 4 of 76

= 4.12 kΩ; CP

SET

= 5.1 kΩ, unless otherwise noted.

RSET

Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA); actual current can be calculated by: CP_lsb = 3.06/CPRSET; connect to ground

Differential mode (can accommodate single-ended input by ac grounding undriven input)

Frequencies below about 1 MHz should be dc-coupled; be careful to match V

(self-bias voltage)

CM

PLL figure of merit (FOM) increases with increasing slew rate; see Figure 13

Self-bias voltage of REFIN1

1

Each pin, REFIN/REFIN

= 5.1 kΩ

RSET

(REF1/REF2)

AD9516-5

Parameter Min Typ Max Unit Test Conditions/Comments

PRESCALER (PART OF N DIVIDER) See the VCXO/VCO Feedback Divider N—P, A, B section

Prescaler Input Frequency

P = 1 FD 300 MHz P = 2 FD 600 MHz P = 3 FD 900 MHz P = 2 DM (2/3) 200 MHz P = 4 DM (4/5) 1000 MHz P = 8 DM (8/9) 2400 MHz P = 16 DM (16/17) 3000 MHz P = 32 DM (32/33) 3000 MHz

Prescaler Output Frequency 300 MHz

PLL DIVIDER DELAYS Register 0x019: R, Bits[5:3]; N, Bits[2:0]; see Table 49

000 Off ps 001 330 ps 010 440 ps 011 550 ps 100 660 ps 101 770 ps 110 880 ps 111 990 ps

NOISE CHARACTERISTICS

In-Band Phase Noise of the Charge Pump/Phase Frequency Detector (In-Band Is Within the LBW of the PLL)

At 500 kHz PFD Frequency −165 dBc/Hz At 1 MHz PFD Frequency −162 dBc/Hz At 10 MHz PFD Frequency −151 dBc/Hz At 50 MHz PFD Frequency −143 dBc/Hz

PLL Figure of Merit (FOM) −220 dBc/Hz

PLL DIGITAL LOCK DETECT WINDOW2

Required to Lock (Coincidence of Edges) Selected by Register 0x017[1:0] and Register 0x018[4]

Low Range (ABP 1.3 ns, 2.9 ns) 3.5 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b High Range (ABP 6.0 ns) 3.5 ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b

To Unlock After Lock (Hysteresis)2

Low Range (ABP 1.3 ns, 2.9 ns) 7 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b High Range (ABP 1.3 ns, 2.9 ns) 15 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b High Range (ABP 6.0 ns) 11 ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b

1

The REFIN and

2

For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

REFIN

self-bias points are offset slightly to avoid chatter on an open input condition.

A, B counter input frequency (prescaler input frequency divided by P)

The PLL in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the value of the N divider)

Reference slew rate > 0.25 V/ns; FOM + 10 log(f

PFD

) is an approximation of the PFD/CP in-band phase noise (in the flat region) inside the PLL loop bandwidth; when running closed-loop, the phase noise, as observed at the VCO output, is increased by 20 log(N)

Signal available at the LD, STATUS, and REFMON pins when selected by appropriate register settings

Rev. A | Page 5 of 76

AD9516-5

CLOCK INPUTS

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

CLOCK INPUTS (CLK,

CLK

) Input Frequency 01 2.4 GHz High frequency distribution (VCO divider enabled) 0

Input Sensitivity, Differential 150 mV p-p Measured at 2.4 GHz; jitter performance is

Input Level, Differential 2 V p-p Larger voltage swings may turn on the

Input Common-Mode Voltage, VCM 1.3 1.57 1.8 V Self-biased; enables ac coupling Input Common-Mode Range, V Input Sensitivity, Single-Ended 150 mV p-p Input Resistance 3.9 4.7 5.7 kΩ Self-biased Input Capacitance 2 pF

1

Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.

CLOCK OUTPUTS

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL CLOCK OUTPUTS Termination = 50 Ω to V

OUT0, OUT1, OUT2, OUT3, OUT4,

OUT5 Output Frequency, Maximum 2400 MHz Using direct to output; see Figure 20 for peak-to-

Output High Voltage (VOH) V

Output Low Voltage (VOL) V

Output Differential Voltage (VOD) 550 790 980 mV VOH − VOL for each leg of a differential pair for

LVDS CLOCK OUTPUTS Differential termination 100 Ω at 3.5 mA

OUT6, OUT7, OUT8, OUT9

Output Frequency, Maximum 800 MHz The AD9516 outputs can toggle at higher

Differential Output Voltage (VOD) 247 360 454 mV VOH − VOL measurement across a differential pair

Delta VOD 25 mV This is the absolute value of the difference between

Output Offset Voltage (VOS) 1.125 1.24 1.375 V (VOH + VOL)/2 across a differential pair at the

Delta VOS 25 mV This is the absolute value of the difference between

Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND

CMOS CLOCK OUTPUTS

OUT6A, OUT6B, OUT7A, OUT7B,

OUT8A, OUT8B, OUT9A, OUT9B Output Frequency 250 MHz See Figure 22 Output Voltage High (VOH) V Output Voltage Low (VOL) 0.1 V At 1 mA load

Differential input

1

1.6 GHz Distribution only (VCO divider bypassed; this is the frequency range supported by the channel divider)

improved with slew rates > 1 V/ns

protection diodes and may degrade jitter performance

1.3 1.8 V With 200 mV p-p signal applied; dc-coupled

CMR

CLK ac-coupled;

Differential (OUT,

CLK

ac-bypassed to RF ground

− 2 V

S_LVPECL

OUT

)

peak differential amplitude

S_LVPECL

− 1.12 V

S_LVPECL

− 0.98 V

− 0.84 V Measured at dc using the default amplitude setting;

S_LVPECL

see Figure 20 for amplitude vs. frequency

S_LVPECL

− 2.03 V

S_LVPECL

− 1.77 V

− 1.49 V Measured at dc using the default amplitude setting;

S_LVPECL

see Figure 20 for amplitude vs. frequency

default amplitude setting with driver not toggling; see Figure 20 for variation over frequency

Differential (OUT,

OUT

)

frequencies, but the output amplitude may not meet the V

specification; see Figure 21

OD

at the default amplitude setting with output driver not toggling; see Figure 21 for variation over frequency

when the normal output is high vs. when the

V

OD

complementary output is high

default amplitude setting with output driver not toggling

when the normal output is high vs. when the

V

OS

complementary output is high

Single-ended; termination = 10 pF

− 0.1 V At 1 mA load

S_LVPECL

Rev. A | Page 6 of 76

AD9516-5

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

CLK-TO-LVPECL ADDITIVE PHASE NOISE Distribution section only; does not include PLL input

CLK = 1 GHz, Output = 1 GHz slew rate > 1 V/ns

Divider = 1

At 10 Hz Offset −109 dBc/Hz At 100 Hz Offset −118 dBc/Hz At 1 kHz Offset −130 dBc/Hz At 10 kHz Offset −139 dBc/Hz At 100 kHz Offset −144 dBc/Hz At 1 MHz Offset −146 dBc/Hz At 10 MHz Offset −147 dBc/Hz At 100 MHz Offset −149 dBc/Hz

CLK = 1 GHz, Output = 200 MHz Input slew rate > 1 V/ns

Divider = 5

At 10 Hz Offset −120 dBc/Hz At 100 Hz Offset −126 dBc/Hz At 1 kHz Offset −139 dBc/Hz At 10 kHz Offset −150 dBc/Hz At 100 kHz Offset −155 dBc/Hz At 1 MHz Offset −157 dBc/Hz >10 MHz Offset −157 dBc/Hz

CLK-TO-LVDS ADDITIVE PHASE NOISE Distribution section only; does not include input slew

CLK = 1.6 GHz, Output = 800 MHz rate > 1 V/ns

Divider = 2

At 10 Hz Offset −103 dBc/Hz At 100 Hz Offset −110 dBc/Hz At 1 kHz Offset −120 dBc/Hz At 10 kHz Offset −127 dBc/Hz At 100 kHz Offset −133 dBc/Hz At 1 MHz Offset −138 dBc/Hz At 10 MHz Offset −147 dBc/Hz At 100 MHz Offset −149 dBc/Hz

CLK = 1.6 GHz, Output = 400 MHz Input slew rate > 1 V/ns

Divider = 4

At 10 Hz Offset −114 dBc/Hz At 100 Hz Offset −122 dBc/Hz At 1 kHz Offset −132 dBc/Hz At 10 kHz Offset −140 dBc/Hz At 100 kHz Offset −146 dBc/Hz At 1 MHz Offset −150 dBc/Hz >10 MHz Offset −155 dBc/Hz

CLK-TO-CMOS ADDITIVE PHASE NOISE Distribution section only; does not include PLL input

CLK = 1 GHz, Output = 250 MHz slew rate > 1 V/ns

Divider = 4

At 10 Hz Offset −110 dBc/Hz At 100 Hz Offset −120 dBc/Hz At 1 kHz Offset −127 dBc/Hz At 10 kHz Offset −136 dBc/Hz At 100 kHz Offset −144 dBc/Hz At 1 MHz Offset −147 dBc/Hz >10 MHz Offset −154 dBc/Hz

Rev. A | Page 7 of 76

AD9516-5

Parameter Min Typ Max Unit Test Conditions/Comments

CLK = 1 GHz, Output = 50 MHz Input slew rate > 1 V/ns

Divider = 20

At 10 Hz Offset −124 dBc/Hz At 100 Hz Offset −134 dBc/Hz At 1 kHz Offset −142 dBc/Hz At 10 kHz Offset −151 dBc/Hz At 100 kHz Offset −157 dBc/Hz At 1 MHz Offset −160 dBc/Hz >10 MHz Offset −163 dBc/Hz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

LVPECL = 245.76 MHz; PLL LBW = 125 Hz 54 fs rms Integration bandwidth = 200 kHz to 5 MHz 77 fs rms Integration bandwidth = 200 kHz to 10 MHz 109 fs rms Integration bandwidth = 12 kHz to 20 MHz LVPECL = 122.88 MHz; PLL LBW = 125 Hz 79 fs rms Integration bandwidth = 200 kHz to 5 MHz 114 fs rms Integration bandwidth = 200 kHz to 10 MHz 163 fs rms Integration bandwidth = 12 kHz to 20 MHz LVPECL = 61.44 MHz; PLL LBW = 125 Hz 124 fs rms Integration bandwidth = 200 kHz to 5 MHz 176 fs rms Integration bandwidth = 200 kHz to 10 MHz 259 fs rms Integration bandwidth = 12 kHz to 20 MHz

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

Application example based on a typical setup using an external 245.76 MHz VCXO (Toyocom TCO-2112); reference = 15.36 MHz; R = 1

Table 7.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

CLK = 622.08 MHz; LVPECL = 622.08 MHz;

Divider = 1

CLK = 622.08 MHz; LVPECL = 155.52 MHz;

Divider = 4

CLK = 1.6 GHz; LVPECL = 100 MHz;

Divider = 16

CLK = 500 MHz; LVPECL = 100 MHz;

Divider = 5

LVDS OUTPUT ADDITIVE TIME JITTER

CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2

(VCO Divider Not Used) CLK = 1 GHz; LVDS = 200 MHz; Divider = 5 113 fs rms Bandwidth = 12 kHz to 20 MHz CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16 280 fs rms

CMOS OUTPUT ADDITIVE TIME JITTER

CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16 365 fs rms

40 fs rms Bandwidth = 12 kHz to 20 MHz

80 fs rms Bandwidth = 12 kHz to 20 MHz

215 fs rms

245 fs rms Calculated from SNR of ADC method; DCC on

85 fs rms Bandwidth = 12 kHz to 20 MHz

Distribution section only; does not include PLL; uses rising edge of clock signal

Calculated from SNR of ADC method; DCC not used for even divides

Distribution section only; does not include PLL; uses rising edge of clock signal

Calculated from SNR of ADC method; DCC not used for even divides

Distribution section only; does not include PLL; uses rising edge of clock signal

Calculated from SNR of ADC method; DCC not used for even divides

Rev. A | Page 8 of 76

AD9516-5

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)

Table 8.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

CLK = 2.4 GHz; VCO Div = 2; LVPECL = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

LVDS OUTPUT ADDITIVE TIME JITTER

CLK = 2.4 GHz; VCO Div = 2; LVDS = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

CMOS OUTPUT ADDITIVE TIME JITTER

CLK = 2.4 GHz; VCO Div = 2; CMOS = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

210 fs rms Calculated from SNR of ADC method

285 fs rms Calculated from SNR of ADC method

350 fs rms Calculated from SNR of ADC method

DELAY BLOCK ADDITIVE TIME JITTER

Table 9.

Parameter Min Typ Max Unit Test Conditions/Comments

DELAY BLOCK ADDITIVE TIME JITTER1 Incremental additive jitter

100 MHz Output

Delay (1600 μA, 0x1C) Fine Adjust 000000b 0.54 ps rms Delay (1600 μA, 0x1C) Fine Adjust 101111b 0.60 ps rms Delay (800 μA, 0x1C) Fine Adjust 000000b 0.65 ps rms Delay (800 μA, 0x1C) Fine Adjust 101111b 0.85 ps rms Delay (800 μA, 0x4C) Fine Adjust 000000b 0.79 ps rms Delay (800 μA, 0x4C) Fine Adjust 101111b 1.2 ps rms Delay (400 μA, 0x4C) Fine Adjust 000000b 1.2 ps rms Delay (400 μA, 0x4C) Fine Adjust 101111b 2.0 ps rms Delay (200 μA, 0x1C) Fine Adjust 000000b 1.3 ps rms Delay (200 μA, 0x1C) Fine Adjust 101111b 2.5 ps rms Delay (200 μA, 0x4C) Fine Adjust 000000b 1.9 ps rms Delay (200 μA, 0x4C) Fine Adjust 101111b 3.8 ps rms

1

This value is incremental; that is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter

should be added to this value using the root sum of the squares (RSS) method.

Distribution section only; does not include PLL; uses rising edge of clock signal

Rev. A | Page 9 of 76

AD9516-5

SERIAL CONTROL PORT

Table 10.

Parameter Min Typ Max Unit Test Conditions/Comments

CS (INPUT)

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 3 μA Input Logic 0 Current 110 μA Input Capacitance 2 pF

SCLK (INPUT) SCLK has an internal 30 kΩ pull-down resistor

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 110 μA Input Logic 0 Current 1 μA Input Capacitance 2 pF

SDIO (WHEN INPUT)

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 10 nA Input Logic 0 Current 20 nA Input Capacitance 2 pF

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V

TIMING

Clock Rate (SCLK, 1/t Pulse Width High, t Pulse Width Low, t

) 25 MHz

SCLK

16 ns

HIGH

16 ns

LOW

SDIO to SCLK Setup, tDS 2 ns SCLK to SDIO Hold, tDH 1.1 ns SCLK to Valid SDIO and SDO, tDV 8 ns CS to SCLK Setup and Hold, tS, tH

CS Minimum Pulse Width High, t

2 ns 3 ns

PWH

CS has an internal 30 kΩ pull-up resistor

PD, RESET, AND SYNC PINS

Table 11.

Parameter Min Typ Max Unit Test Conditions/Comments

INPUT CHARACTERISTICS Each of these pins has an internal 30 kΩ pull-up resistor

Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 110 μA Logic 0 Current 1 μA Capacitance 2 pF

RESET TIMING

Pulse Width Low 50 ns

SYNC TIMING

Pulse Width Low 1.5

High speed

High speed clock is CLK input signal

clock cycles

Rev. A | Page 10 of 76

AD9516-5

LD, STATUS, AND REFMON PINS

Table 12.

Parameter Min Typ Max Unit Test Conditions/Comments

OUTPUT CHARACTERISTICS

Output Voltage High, VOH 2.7 V Output Voltage Low, VOL 0.4 V

MAXIMUM TOGGLE RATE 100 MHz

ANALOG LOCK DETECT

Capacitance 3 pF

REF1, REF2, AND CLK FREQUENCY STATUS

MONITOR Normal Range 1.02 MHz

Extended Range 8 kHz

LD PIN COMPARATOR

Trip Point 1.6 V Hysteresis 260 mV

When selected as a digital output (CMOS); there are other modes in which these pins are not CMOS digital outputs; see Table 49: Register 0x017, Register 0x01A, and Register 0x01B

Applies when mux is set to any divider or counter output or PFD up/down pulse; also applies in analog lock detect mode; usually debug mode only; beware that spurs may couple to output when any of these pins are toggling

On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor

Frequency above which the monitor always indicates the presence of the reference

POWER DISSIPATION

Table 13.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER DISSIPATION, CHIP

Power-On Default 1.0 1.2 W

Full Operation; CMOS Outputs at 225 MHz 1.5 2.1 W

Full Operation; LVDS Outputs at 225 MHz 1.5 2.1 W

PD Power-Down

PD Power-Down, Maximum Sleep

VCP Supply 4 4.8 mW

AD9516 Core 220 mW

75 185 mW

31 mW

The values in this table include all power supplies, unless otherwise noted; the power deltas for individual drivers are at dc; see Figure 7, Figure 8, and Figure 9 for power dissipation vs. output frequency

No clock; no programming; default register values; does not include power dissipated in external resistors; this configuration has the following blocks already powered up: VCO divider, six channel dividers, three LVPECL drivers, and two LVDS drivers

= 2.25 GHz; VCO divider = 2; all channel dividers on; six

f

CLK

LVPECL outputs at 562.5 MHz; eight CMOS outputs (10 pF load) at 225 MHz; all four fine delay blocks on, maximum current; does not include power dissipated in external resistors

= 2.25 GHz; VCO divider = 2; all channel dividers on; six

f

CLK

LVPECL outputs at 562.5 MHz; four LVDS outputs at 225 MHz; all four fine delay blocks on: maximum current; does not include power dissipated in external resistors

PD pin pulled low; does not include power dissipated in terminations

PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b; SYNC power-down, Register 0x230[2] = 1b; REF for distribution power-down, Register 0x230[1] = 1b

PLL operating; typical closed-loop configuration (this number is included in all other power measurements)

AD9516 core only, all drivers off, PLL off, VCO divider off, and

delay blocks off; the power consumption of the configuration of the user can be derived from this number and the power deltas that follow

Rev. A | Page 11 of 76

AD9516-5

Parameter Min Typ Max Unit Test Conditions/Comments

POWER DELTAS, INDIVIDUAL FUNCTIONS Power delta when a function is enabled/disabled

VCO Divider 30 mW VCO divider bypassed REFIN (Differential) 20 mW All references off to differential reference enabled REF1, REF2 (Single-Ended) 4 mW

PLL 75 mW PLL off to PLL on, normal operation; no reference enabled Channel Divider 30 mW Divider bypassed to divide-by-2 to divide-by-32 LVPECL Channel (Divider Plus Output Driver) 120 mW

LVPECL Driver 90 mW

LVDS Channel (Divider Plus Output Driver) 140 mW

LVDS Driver 50 mW

CMOS Channel (Divider Plus Output Driver) 100 mW

CMOS Driver (Second in Pair) 0 mW

CMOS Driver (First in Second Pair) 30 mW

Fine Delay Block 50 mW

All references off to REF1 or REF2 enabled; differential reference not enabled

No LVPECL output on to one LVPECL output on (that is, enabling OUT0 with OUT1 off; Divider 0 enabled), independent of frequency

Second LVPECL output turned on, same channel (that is, enabling OUT0 with OUT1 already on)

No LVDS output on to one LVDS output on (that is, enabling OUT8 with OUT9 off with Divider 4.1 enabled and Divider 4.2 bypassed); see Figure 8 for dependence on output frequency

Second LVDS output turned on, same channel (that is, enabling OUT8 with OUT9 already on)

Static; no CMOS output on to one CMOS output on (that is, enabling OUT8A starting with OUT8 and OUT9 off); see Figure 9 for variation over output frequency

Static; second CMOS output, same pair, turned on (that is, enabling OUT8A with OUT8B already on)

Static; first output, second pair, turned on (that is, enabling OUT9A with OUT9B off and OUT8A and OUT8B already on)

Delay block off to delay block enabled; maximum current setting

Rev. A | Page 12 of 76

AD9516-5

TIMING CHARACTERISTICS

Table 14.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL Termination = 50 Ω to V

(810 mV) Output Rise Time, tRP 70 180 ps 20% to 80%, measured differentially Output Fall Time, tFP 70 180 ps 80% to 20%, measured differentially

PROPAGATION DELAY, t

, CLK-TO-LVPECL OUTPUT

PECL

High Frequency Clock Distribution Configuration 835 995 1180 ps See Figure 34 Clock Distribution Configuration 773 933 1090 ps See Figure 33 Variation with Temperature 0.8 ps/°C

OUTPUT SKEW, LVPECL OUTPUTS1

LVPECL Outputs That Share the Same Divider 5 15 ps LVPECL Outputs on Different Dividers 13 40 ps All LVPECL Outputs Across Multiple Parts 220 ps

LVDS Termination = 100 Ω differential; 3.5 mA setting

Output Rise Time, tRL 170 350 ps 20% to 80%, measured differentially2 Output Fall Time, tFL 160 350 ps 20% to 80%, measured differentially2

PROPAGATION DELAY, t

, CLK-TO-LVDS OUTPUT Delay off on all outputs

LVDS

OUT6, OUT7, OUT8, OUT9

For All Divide Values 1.4 1.8 2.1 ns Variation with Temperature 1.25 ps/°C

OUTPUT SKEW, LVDS OUTPUTS1 Delay off on all outputs

LVDS Outputs That Share the Same Divider 6 62 ps LVDS Outputs on Different Dividers 25 150 ps All LVDS Outputs Across Multiple Parts 430 ps

CMOS Termination = open

Output Rise Time, tRC 495 1000 ps 20% to 80%; C Output Fall Time, tFC 475 985 ps 80% to 20%; C

PROPAGATION DELAY, t

, CLK-TO-CMOS OUTPUT Fine delay off

CMOS

LOAD

= 10 pF = 10 pF

For All Divide Values 1.6 2.1 2.6 ns Variation with Temperature 2.6 ps/°C

OUTPUT SKEW, CMOS OUTPUTS1 Fine delay off

CMOS Outputs That Share the Same Divider 4 66 ps All CMOS Outputs on Different Dividers 28 180 ps All CMOS Outputs Across Multiple Parts 675 ps

DELAY ADJUST3 LVDS and CMOS

Shortest Delay Range4 Register 0x0A1 (0x0A4, 0x0A7, 0x0AA), Bits[5:0] = 101111b

Zero Scale 50 315 680 ps Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b Full Scale 540 880 1180 ps Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b

Longest Delay Range4 Register 0x0A1 (0x0A4, 0x0A7, 0x0AA) Bits[5:0] = 000000b

Zero Scale 200 570 950 ps Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b Quarter Scale 1.72 2.31 2.89 ns Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 001100b Full Scale 5.7 8.0 10.1 ns Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b

Delay Variation with Temperature

Short Delay Range5

Zero Scale 0.23 ps/°C Full Scale −0.02 ps/°C

Long Delay Range5

Zero Scale 0.3 ps/°C Full Scale 0.24 ps/°C

1

This is the difference between any two similar delay paths while operating at the same voltage and temperature.

2

Corresponding CMOS drivers set to OUTxA for noninverting and OUTxB for inverting; x = 6, 7, 8, or 9.

3

The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output.

4

Incremental delay; does not include propagation delay.

5

All delays between zero scale and full scale can be estimated by linear interpolation.

Rev. A | Page 13 of 76

− 2 V; default amplitude setting

S_LVPECL

AD9516-5

K

Timing Diagrams

t

CLK

CL

t

LVDS

t

CMOS

Figure 2. CLK/

DIFFERENTIAL

80%

20%

Figure 3. LVPECL Timing, Differential

PECL

CLK

to Clock Output Timing, Divider = 1

LVPECL

t

RP

07972-060

t

FP

07972-061

DIFFERENTIAL

80%

LVDS

20%

t

RL

t

FL

Figure 4. LVDS Timing, Differential

SINGLE-ENDED

80%

CMOS

10pF LOAD

20%

t

RC

t

FC

Figure 5. CMOS Timing, Single-Ended, 10 pF Load

07972-062

07972-063

Rev. A | Page 14 of 76

AD9516-5

ABSOLUTE MAXIMUM RATINGS

Table 15.

Parameter Rating

VS, VS_LVPECL to GND −0.3 V to +3.6 V VCP to GND −0.3 V to +5.8 V REFIN, REFIN to GND REFIN to REFIN

−0.3 V to VS + 0.3 V

−3.3 V to +3.3 V

RSET to GND −0.3 V to VS + 0.3 V CPRSET to GND −0.3 V to VS + 0.3 V CLK, CLK to GND

CLK to CLK SCLK, SDIO, SDO, CS to GND OUT0, OUT0, OUT1, OUT1, OUT2, OUT2,

OUT3, OUT3 OUT6, OUT6 OUT9, OUT9

SYNC

to GND

, OUT4, OUT4, OUT5, OUT5, , OUT7, OUT7, OUT8, OUT8, to GND

−0.3 V to VS + 0.3 V

−1.2 V to +1.2 V

−0.3 V to VS + 0.3 V

REFMON, STATUS, LD to GND −0.3 V to VS + 0.3 V Temperature

Junction Temperature1 150°C Storage Temperature Range −65°C to +150°C Lead Temperature (10 sec) 300°C

1

See Table 16 for θJA.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

Table 16.

Package Type1 θ

64-Lead LFCSP (CP-64-4) 22 °C/W

1

Thermal impedance measurements were taken on a 4-layer board in still air

in accordance with EIA/JESD51-2.

Unit

JA

ESD CAUTION

Rev. A | Page 15 of 76

AD9516-5

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REFIN (REF 1)

REFIN (REF 2)

CPRSETVSVS

GND

RSETVSOUT0

OUT0

VS_LVPECL

OUT1

OUT1VSVS

646362616059585756555453525150

VS

49

1

VS

REFMON

LD

VCP

CP

STATUS

REF_SEL

SYNC

NC

10

NC

11

VS

12

VS

13

CLK

14

CLK

15

NC

16

SCLK

NOTES

1. NC = NO CONNE CT. DO NO T CONNECT TO THI S PIN.

2. EXPOSED DIE PAD MUST BE CONNECTED TO GND.

PIN 1 INDICATOR

2 3 4 5 6 7 8 9

171819202122232425262728293031

CS

NCNCNC

AD9516-5

TOP VIEW

(Not to Scale)

SDO

SDIO

RESET

Figure 6. Pin Configuration

Table 17. Pin Function Descriptions

Input/

Pin No.

1, 11, 12, 30,

Output Pin Type Mnemonic Description

I Power VS 3.3 V Power Pins. 31, 32, 38, 49, 50, 51, 57, 60, 61

2 O 3.3 V CMOS REFMON

Reference Monitor (Output). This pin has multiple selectable outputs; see Tab le 49, Register 0x01B.

3 O 3.3 V CMOS LD

Lock Detect (Output). This pin has multiple selectable outputs; see Table 4 9,

Register 0x01A. 4 I Power VCP 5 O Loop filter CP

Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.25 V.

Charge Pump (Output). This pin connects to an external loop filter. This pin can

be left unconnected if the PLL is not used. 6 O 3.3 V CMOS STATUS

Status (Output). This pin has multiple selectable outputs; see Table 49,

Register 0x017. 7 I 3.3 V CMOS REF_SEL

Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ

pull-down resistor. 8 I 3.3 V CMOS

SYNC

Manual Synchronizations and Manual Holdover. This pin initiates a manual

synchronization and is also used for manual holdover. Active low. This pin has

an internal 30 kΩ pull-up resistor. 9, 10, 15, 18,

N/A NC NC

No Connection. These pins can be left floating. 19, 20

13 I

Differential

CLK

Along with CLK

clock input

14 I

Differential clock input

Along with CLK, this is the differential input for the clock distribution section.

CLK

If a single-ended input is connected to the CLK pin, connect a 0.1 μF bypass

capacitor from CLK

LVPECL LVPECL

PD

OUT4

OUT5

VS_LVPECL

OUT6 (OUT6A)

48

OUT6 (OUT6B)

47

OUT7 (OUT7A)

46

OUT7 (OUT7B)

45

OUT5

LVDS/CMOS

w/FINE DELAY ADJUST

LVDS/CMOS

w/FI NE DELAY ADJUST

32

VSVSVS

LVPECL LVPECL

GND

44

OUT2

43

OUT2

42

VS_LVPECL

41

OUT3

40

OUT3

39

VS

38

GND

37

OUT9 (OUT9B)

36

OUT9 (OUT9A)

35

OUT8 (OUT8B)

34

OUT8 (OUT8A)

33

07972-003

, this is the differential input for the clock distribution section.

to ground.

Rev. A | Page 16 of 76

AD9516-5

Input/

Pin No.

16 I 3.3 V CMOS SCLK Serial Control Port Data Clock Signal. 17 I 3.3 V CMOS

21 O 3.3 V CMOS SDO Serial Control Port Unidirectional Serial Data Output. 22 I/O 3.3 V CMOS SDIO Serial Control Port Bidirectional Serial Data Input/Output. 23 I 3.3 V CMOS

24 I 3.3 V CMOS 25 O LVPECL OUT4 LVPECL Output; One Side of a Differential LVPECL Output.

26 O LVPECL 27, 41, 54 I Power VS_LVPECL Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins. 28 O LVPECL OUT5 LVPECL Output; One Side of a Differential LVPECL Output. 29 O LVPECL 33 O LVDS or CMOS OUT8 (OUT8A)

34 O LVDS or CMOS

35 O LVDS or CMOS OUT9 (OUT9A)

36 O LVDS or CMOS

37, 44, 59, EPAD

39 O LVPECL 40 O LVPECL OUT3 LVPECL Output; One Side of a Differential LVPECL Output.

42 O LVPECL 43 O LVPECL OUT2 LVPECL Output; One Side of a Differential LVPECL Output. 45 O LVDS or CMOS

46 O LVDS or CMOS OUT7 (OUT7A)

47 O LVDS or CMOS

48 O LVDS or CMOS OUT6 (OUT6A)

52 O LVPECL 53 O LVPECL OUT1 LVPECL Output; One Side of a Differential LVPECL Output.

55 O LVPECL 56 O LVPECL OUT0 LVPECL Output; One Side of a Differential LVPECL Output. 58 O

62 O

63 I

64 I

Output Pin Type Mnemonic Description

Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up

CS

resistor.

RESET PD

OUT4

OUT5

(OUT8B) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

OUT8

(OUT9B) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

OUT9

I GND GND

OUT3

OUT2

(OUT7B) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

OUT7

(OUT6B) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

OUT6

OUT1

OUT0

Current set resistor

Reference input

RSET A resistor connected to this pin sets internal bias currents. Nominal value = 4.12 kΩ.

CPRSET

(REF2) Along with REFIN, this pin is the differential input for the PLL reference.

REFIN

REFIN (REF1)

Chip Reset; Active Low. This pin has an internal 30 kΩ pull-up resistor. Chip Power-Down; Active Low. This pin has an internal 30 kΩ pull-up resistor.

LVPECL Output; One Side of a Differential LVPECL Output.

LVPECL Output; One Side of a Differential LVPECL Output. LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

CMOS Output.

CMOS Output. LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

CMOS Output.

CMOS Output. Ground Pins, Including External Paddle (EPAD). The external die paddle on the

bottom of the package must be connected to ground for proper operation. LVPECL Output; One Side of a Differential LVPECL Output.

LVPECL Output; One Side of a Differential LVPECL Output.

CMOS Output. LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

CMOS Output.

CMOS Output. LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

CMOS Output. LVPECL Output; One Side of a Differential LVPECL Output.

LVPECL Output; One Side of a Differential LVPECL Output.

A resistor connected to this pin sets the CP current range. Nominal value = 5.1 kΩ. This resistor can be omitted if the PLL is not used.

Alternatively, this pin is a single-ended input for REF2. This pin can be left unconnected when the PLL is not used.

Along with REFIN Alternatively, this pin is a single-ended input for REF1. This pin can be left

unconnected when the PLL is not used.

, this pin is the differential input for the PLL reference.

Rev. A | Page 17 of 76

AD9516-5

–

TYPICAL PERFORMANCE CHARACTERISTICS

300

280

260

240

220

200

180

CURRENT (mA)

160

140

120

100

0 500 1000 1500 2000 2500 3000

3 CHANNELS—6 LVPE CL

3 CHANNELS—3 LVPE CL

2 CHANNELS—2 LVPE CL

1 CHANNEL—1 LVPECL

FREQUENCY (MHz)

Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs

07972-007

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

CURRENT FROM CP P IN (mA)

1.0

0.5

PUMP DOWN PUMP UP

0

0 0.5 1.0 1.5 2.0 2.5 3.0

VOLTAGE ON CP PIN (V)

Figure 10. Charge Pump Characteristics at VCP = 3.3 V

07972-011

180

2 CHANNELS—4 LVDS

160

140

120

CURRENT (mA)

100

80

0 200 400 600 800

2 CHANNELS—2 LVDS

1 CHANNEL—1 LVDS

FREQUENCY (MHz )

Figure 8. Current vs. Frequency—LVDS Outputs

(Includes Clock Distribution Current Draw)

240

220

200

180

160

140

CURRENT (mA)

120

100

1 CHANNEL—2 CMOS

80

0220015010050

2 CHANNELS—8 CMOS

2 CHANNELS—2 CMOS

1 CHANNEL—1 CMOS

FREQUENCY (MHz )

Figure 9. Current vs. Frequency—CMOS Outputs with 10 pF Load

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

CURRENT FROM CP P IN (mA)

1.0

0.5

0

07972-008

PUMP DOWN PUMP UP

0 0.5 1.0 1.5 2.0 3.0 4.02.5 3.5 5.04.5

VOLTAGE ON CP PIN (V)

Figure 11. Charge Pump Characteristics at V

140

–145

–150

–155

(dBc/Hz)

–160

–165

PFD PHASE NOI SE REFERRED TO PFD INPUT

50

07972-009

–170

0.1 1 10010

PFD FREQUENCY (MHz)

Figure 12. PFD Phase Noise Referred to PFD Input vs. PFD Frequency

= 5.0 V

CP

07972-012

07972-013

Rev. A | Page 18 of 76

AD9516-5

–

210

–212

–214

–216

–218

0.4

0.2

0

–220

PLL FIGURE OF MERIT (dBc/ Hz)

–222

–224

022.01.51.00.5

SLEW RATE (V/n s)

Figure 13. PLL Figure of Merit vs. Slew Rate at REFIN/

1.0

0.6

0.2

–0.2

DIFFERENTIAL OUTPUT (V)

–0.6

–1.0

022015105

TIME (ns)

Figure 14. LVPECL Output (Differential) at 100 MHz

–0.2

DIFFERENTIAL OUTPUT (V)

–0.4

.5

07972-136

REFIN

5

07972-014

022015105

Figure 16. LVDS Output (Differential) at 100 MHz

0.4

0.2

0

–0.2

DIFFERENTIAL OUTPUT (V)

–0.4

021

Figure 17. LVDS Output (Differential) at 800 MHz

TIME (ns)

5

07972-016

07972-017

1.0

0.6

0.2

–0.2

DIFFERENTIAL OUTPUT (V)

–0.6

–1.0

021

TIME (ns)

Figure 15. LVPECL Output (Differential) at 1600 MHz

07972-015

Rev. A | Page 19 of 76

2.8

1.8

0.8

DIFFERENTIAL OUTPUT (V)

–0.2

0860 1004020

Figure 18. CMOS Output at 25 MHz

TIME (ns)

0

07972-018

AD9516-5

OUTPUT (V)

DIFFERENTIAL SWING (mV p-p)

2.8

1.8

0.8

–0.2

08611042

1600

1400

1200

1000

TIME (ns)

Figure 19. CMOS Output at 250 MHz

DIFFERENTIAL SWING (mV p-p)

2

07972-019

OUTPUT SWING (V)

700

600

500

08700600500400300200100

FREQUENCY (MHz )

Figure 21. LVDS Differential Swing vs. Frequency

(Using a Differential Probe Across the Output Pair)

3

2

1

CL = 2pF

C

= 10pF

L

= 20pF

C

L

00

07972-021

800

0321

FREQUENCY (GHz)

Figure 20. LVPECL Differential Swing vs. Frequency

07972-020

0

0 600500400300200100

OUTPUT FREQUENCY (MHz)

Figure 22. CMOS Output Swing vs. Frequency and Capacitive Load

07972-133

(Using a Differential Probe Across the Output Pair)

Rev. A | Page 20 of 76

AD9516-5

–

120

110

–125

–130

–135

–140

–145

PHASE NOISE (dBc/Hz)

–150

–155

–160

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 23. Phase Noise (Additive) LVPECL at 245.76 MHz, Divide-by-1

110

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

10 100M1k 10k 100k 1M 10M100

07972-026

FREQUENCY (Hz)

07972-142

Figure 26. Phase Noise (Additive) LVDS at 200 MHz, Divide-by-1

100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–160

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 24. Phase Noise (Additive) LVPECL at 200 MHz, Divide-by-5

100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 25. Phase Noise (Additive) LVPECL at 1600 MHz, Divide-by-1

–150

10 100M10M1M100k10k1k100

07972-027

FREQUENCY (Hz)

07972-130

Figure 27. Phase Noise (Additive) LVDS at 800 MHz, Divide-by-2

120

–130

–140

–150

PHASE NOISE (dBc/Hz)

–160

–170

10 100M10M1M100k10k1k100

07972-128

FREQUENCY (Hz)

07972-131

Figure 28. Phase Noise (Additive) CMOS at 50 MHz, Divide-by-20

Rev. A | Page 21 of 76

AD9516-5

–

100

–110

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 29. Phase Noise (Additive) CMOS at 250 MHz, Divide-by-4

07972-132

1000

100

f

OBJ

10

1

NOTE: 375UI MAX AT 10Hz OFFSET IS THE

INPUT JITTER AMPLITUDE (UI p-p)

0.1

0.01 0.1 1 10 100 1000

MAXIMUM JIT TER THAT CAN BE GENERATED BY THE TEST EQUIPMENT. FAILURE POINT IS GREATER THAN 375UI.

JITTER FRE QUENCY (kHz)

OC-48 OBJECTIVE MASK AD9516

Figure 31. GR-253 Jitter Tolerance Plot

07972-148

120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

1k 100M10M1M100k10k

FREQUENCY (Hz)

Figure 30. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)

at 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz

07972-140

Rev. A | Page 22 of 76

AD9516-5

TERMINOLOGY

Phase Jitter and Phase Noise

An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution.

This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in decibels, dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given.

It is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval.

Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways.

Time Jitter

Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings varies. In a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution.

Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the signal-to-noise ratio (SNR) and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter.

Additive Phase Noise

Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. When there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors.

Additive Time Jitter

Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.

Rev. A | Page 23 of 76

AD9516-5

V

DETAILED BLOCK DIAGRAM

REFIN (REF 1)

REFIN (REF 2)

REF1

REF2

REF_ SEL CPRSETVCP

REFERENCE

SWITCHO VER

STATUS

S GND RSET

DISTRIBUT ION

REFERENCE

R

DIVIDER

VCO STATUS

P, P + 1

PRESCALER

N DIVIDER

A/B

COUNTERS

REFMON

PROGRAMMABL E

R DELAY

PROGRAMMABL E

N DELAY

LOCK

DETECT

PHASE

FREQUENCY

DETECTOR

PLL

REFERENCE

CHARGE

PUMP

LD

HOLD

CP

CLK

SYNC

RESET

SCLK

SDIO

SDO

PD

CS

DIGITAL

LOGIC

SERIAL

CONTROL

PORT

AD9516-5

DIVIDE BY

2, 3, 4, 5, OR 6

01

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

∆t

LVPECL

LVDS/CMOS

STATUS

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6 (OUT6A)

OUT6 (OUT6B)

OUT7 (OUT7A)

OUT7 (OUT7B)

OUT8 (OUT8A)

OUT8 (OUT8B)

OUT9 (OUT9A)

OUT9 (OUT9B)

7972-002

Figure 32. Detailed Block Diagram

Rev. A | Page 24 of 76

AD9516-5

V

THEORY OF OPERATION

REFIN (REF1)

REFIN (REF2)

REF1

REF2

REF_SEL CPRSETVCP

REFERENCE

SWITCHOVER

STATUS

S GND RSET

DISTRIBUTI ON

REFERENCE

R

DIVIDER

VCO STATUS

P, P + 1

PRESCALER

N DIVIDER

A/B

COUNTERS

REFMON

PROGRAMMABLE

R DELAY

PROGRAMMABLE

N DELAY

LOCK

DETECT

PHASE

FREQUENCY

DETECT OR

PLL

REFERENCE

CHARGE

PUMP

LD

HOLD

CP

CLK

SYNC

RESET

SCLK

SDIO

SDO

DIVIDE BY

2, 3, 4, 5, OR 6

01

DIVIDE BY

PD

CS

DIGITAL

LOGIC

SERIAL

CONTRO L

PORT

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

AD9516-5

LVPECL

∆t

LVDS/CMOS

∆t

LVDS/CMOS

∆t

STATUS

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6 (OUT6A)

OUT6 (OUT6B)

OUT7 (OUT7A)

OUT7 (OUT7B)

OUT8 (OUT8A)

OUT8 (OUT8B)

OUT9 (OUT9A)

OUT9 (OUT9B)

07972-028

Figure 33. Clock Distribution or External VCO < 1600 MHz (Mode 1)

OPERATIONAL CONFIGURATIONS

The AD9516 can be configured in several ways. These configurations must be set up by loading the control registers (see Tabl e 47 and Ta bl e 48 through Tabl e 5 7 ). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers.

Mode 1—Clock Distribution or External VCO < 1600 MHz

Mode 1 bypasses the VCO divider. Mode 1 can be used only with an external clock source of <1600 MHz, due to the maximum

For clock distribution applications where the external clock is less than 1600 MHz, use the register settings shown in Tab le 1 8.

Table 18. Settings for Clock Distribution < 1600 MHz

Register Description

0x010[1:0] = 01b PLL asynchronous power-down (PLL off) 0x1E1[0] = 1b

Bypass the VCO divider as source for distribution section

When using the internal PLL with an external VCO of <1600 MHz, the PLL must be turned on.

input frequency allowed at the channel dividers.

Rev. A | Page 25 of 76

AD9516-5

Table 19. Settings for Using an Internal PLL with an External VCO < 1600 MHz

Register Description

0x1E1[0] = 1b

0x010[1:0] = 00b

Bypass the VCO divider as source for distribution section

PLL normal operation (PLL on) along with other appropriate PLL settings in Register 0x010 to Register 0x01E

An external VCO/VCXO requires an external loop filter that must be connected between CP and the tuning pin of the VCO/ VCXO. This loop filter determines the loop bandwidth and stability of the PLL. Ensure that the correct PFD polarity is selected for the VCO/VCXO that is being used.

The register settings shown in Table 21 are the default values of these registers at power-up or after a reset operation. If the contents of the registers are altered by prior programming after power-up or reset, these registers can also be set intentionally to these values.

Table 21. Default Settings of Some PLL Registers

Register Description

0x010[1:0] = 01b PLL asynchronous power-down (PLL off). 0x1E0[2:0] = 010b Set VCO divider = 4. 0x1E1[0] = 0b Use the VCO divider.

When using the internal PLL with an external VCO, the PLL must be turned on.

Table 20. Setting the PFD Polarity

Register Description

0x010[7] = 0b

0x010[7] = 1b

PFD polarity positive (higher control voltage produces higher frequency)

PFD polarity negative (higher control voltage produces lower frequency)

After the appropriate register values are programmed, Register 0x232 must be set to 0x01 for the values to take effect.

Mode 2 (High Frequency Clock Distribution)—CLK or External VCO > 1600 MHz

The AD9516 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/ CLK

input is connected to the distribution section through the VCO divider (divide-by-2/divide-by-3/divide-by-4/divide-by-5/ divide-by-6). This is a distribution-only mode that allows for an external input of up to 2400 MHz (see Table 4). For divide ratios other than 1, the maximum frequency that can be applied to the channel dividers is 1600 MHz. Therefore, the VCO divider must be used to divide down input frequencies that are greater than 1600 MHz before the channel dividers can be used for further division. This input routing can also be used for lower input frequencies, but the minimum divide is 2 before the channel dividers.

When the PLL is enabled, this routing also allows the use of the PLL with an external VCO or VCXO with a frequency of <2400 MHz. In this configuration, the external VCO/VCXO feeds directly into the prescaler.

Table 22. Settings When Using an External VCO

Register Description

0x010[1:0] = 00b PLL normal operation (PLL on). 0x010 to 0x01D

0x1E1[1] = 0b CLK selected as the source.

PLL settings. Select and enable a reference input. Set R, N (P, A, B), PFD polarity, and ICP according to the intended loop configuration.

An external VCO requires an external loop filter that must be connected between CP and the tuning pin of the VCO. This loop filter determines the loop bandwidth and stability of the PLL. Ensure that the correct PFD polarity is selected for the VCO that is being used.

Table 23. Setting the PFD Polarity

Register Description

0x010[7] = 0b

0x010[7] = 1b

PFD polarity positive (higher control voltage produces higher frequency).

PFD polarity negative (higher control voltage produces lower frequency).

After the appropriate register values are programmed, Register 0x232 must be set to 0x01 for the values to take effect.

Rev. A | Page 26 of 76

AD9516-5

V

REFIN (REF 1)

REFIN (REF 2)

CLK

PD

SYNC

RESET

SCLK

SDIO

SDO

CS

REF1

REF2

REF_SEL CPRSETVCP

REFERENCE

SWITCHOVER

STATUS

DIGITAL

LOGIC

SERIAL

CONTROL

PORT

S GND RSET

DISTRIBUT ION

REFERENCE

R

DIVIDER

VCO STATUS

P, P + 1

PRESCALER

DIVIDE BY

2, 3, 4, 5, OR 6

01

N DIVIDER

A/B

COUNTERS

REFMON

PROGRAMMABL E

R DELAY

PROGRAMMABL E

N DELAY

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LOCK

DETECT

PHASE

FREQUENCY

DETECTO R

PLL

REFERENCE

CHARGE

PUMP

HOLD

LVPECL

LD

CP

STATUS

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6 (OUT6A)

OUT6 (OUT6B)

OUT7 (OUT7A)

OUT7 (OUT7B)

OUT8 (OUT8A)

OUT8 (OUT8B)

OUT9 (OUT9A)

OUT9 (OUT9B)

07972-029

AD9516-5

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

∆t

LVDS/CMOS

∆t

LVDS/CMOS

∆t

Figure 34. High Frequency Clock Distribution—CLK or External VCO > 1600 MHz (Mode 2)

Rev. A | Page 27 of 76

AD9516-5

VCPV

Phase-Locked Loop (PLL)

REF_SEL

SGND

RSET

REFMON

CPRSET

N DIVIDER

DIST

REF

R DIVIDER

A/B

COUNTERS

REFIN (REF1)

REFIN (REF2)

CLK

REF1

REF2

REFERENCE

SWITCHO VER

STATUS

DIVIDE BY

2, 3, 4, 5, OR 6

P, P + 1

PRESCALER

01

Figure 35. PLL Functional Blocks

The AD9516 includes on-chip PLL blocks that can be used with an external VCO or VCXO to create a complete phase-locked loop. The PLL requires an external loop filter, which usually consists of a small number of capacitors and resistors. The configuration and components of the loop filter help to establish the loop bandwidth and stability of the PLL.

The AD9516 PLL is useful for generating clock frequencies from a supplied reference frequency. This includes conversion of reference frequencies to much higher frequencies for subsequent division and distribution. In addition, the PLL can be exploited to clean up jitter and phase noise on a noisy reference. The exact choices of PLL parameters and loop dynamics are very application specific. The flexibility and depth of the PLL allow the part to be tailored to function in many different applications and signal environments.

Configuration of the PLL

Configuration of the PLL is accomplished by programming the various settings for the R divider, N divider, PFD polarity, and charge pump current. The combination of these settings determines the PLL loop bandwidth. These are managed through programmable register settings (see Table 4 7 and Ta b le 4 9) and by the design of the external loop filter. Successful PLL operation and satisfactory PLL loop performance are highly dependent upon proper configuration of the PLL settings.

The design of the external loop filter is crucial to the proper operation of the PLL. A thorough knowledge of PLL theory and design is helpful.

ADIsimCLK™ (V1.2 or later) is a free program that can help with the design and exploration of the capabilities and features of the AD9516, including the design of the PLL loop filter. It is available at www.analog.com/clocks.

PROGRAMM ABLE

R DELAY

PROGRAMM ABLE

N DELAY

VCO STAT US

0

1

LOCK

DETECT

PHASE

FREQUENCY

DETECTOR

PLL REF

HOLD

CHARGE PUMP

LD

CP

STATUS

07972-064

Phase Frequency Detector (PFD)

The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. The antibacklash pulse width is set by Register 0x017[1:0].

An important limit to keep in mind is the maximum frequency allowed into the PFD, which, in turn, determines the correct antibacklash pulse setting. The antibacklash pulse setting is specified in the phase/frequency detector (PFD) parameter of Tab le 2 .

Charge Pump (CP)

The charge pump is controlled by the PFD. The PFD monitors the phase and frequency relationship between its two inputs, and tells the CP to pump up or pump down to charge or discharge the integrating node (part of the loop filter). The integrated and filtered CP current is transformed into a voltage that drives the tuning node of the external VCO to move the VCO frequency up or down. The CP can be set (via Register 0x010[6:4]) for high impedance (allows holdover operation), for normal operation (attempts to lock the PLL loop), for pump-up, or for pump-down (test modes). The CP current is programmable in eight steps from (nominally) 600 μA to 4.8 mA.

The exact value of the CP current LSB is set by the CPRSET resistor, which is nominally 5.1 kΩ. If the value of the resistor connected to the CP_RSET pin is doubled, the resulting charge pump current range becomes 300 μA to 2.4 mA.

Rev. A | Page 28 of 76

AD9516-5

V

PLL External Loop Filter

An example of an external loop filter for a PLL is shown in

Figure 36. A loop filter must be calculated for each desired PLL

configuration. The values of the components depend on the VCO

frequency, the K

, the PFD frequency, the charge pump current,

VCO

the desired loop bandwidth, and the desired phase margin. The

loop filter affects the phase noise, loop settling time, and loop

stability. A basic knowledge of PLL theory is helpful for under-

standing loop filter design. ADIsimCLK can help with calculation

of a loop filter according to the application requirements.

AD9516-5

CLK/CLK

CP

CHARGE

PUMP

Figure 36. Example of External Loop Filter for PLL

EXTERNAL VCO/VCXO

R2

R1

C1 C2 C3

07972-065

PLL Reference Inputs

The AD9516 features a flexible PLL reference input circuit that

allows a fully differential input or two separate single-ended

inputs. The input frequency range for the reference inputs is

specified in Tabl e 2. Both the differential and the single-ended

inputs are self-biased, allowing for easy ac coupling of input signals.

The differential input and the single-ended inputs share two

pins, REFIN (REF1) and

REFIN

(REF2). The desired reference

input type is selected and controlled by Register 0x01C (see

and ). Tabl e 47 Tab le 4 9

When the differential reference input is selected, the self-bias

level of the two sides is offset slightly (see Tabl e 2) to prevent

chattering of the input buffer when the reference is slow or missing.

The specification for this voltage level is found in Table 2. The input

hysteresis increases the voltage swing required of the driver to

overcome the offset. The differential reference input can be driven

by either ac-coupled LVDS or ac-coupled LVPECL signals.

The single-ended inputs can be driven by either a dc-coupled

CMOS level signal or an ac-coupled sine wave or square wave.

Each single-ended input can be independently powered down

when not needed to increase isolation and reduce power. Either

a differential or a single-ended reference must be specifically

enabled. All PLL reference inputs are off by default.

The differential reference input is powered down whenever the

PLL is powered down, or when the differential reference input

is not selected. The single-ended buffers power down when the

PLL is powered down and when their individual power-down

registers are set. When the differential mode is selected, the

single-ended inputs are powered down.

In differential mode, the reference input pins are internally selfbiased so that they can be ac-coupled via capacitors. It is possible to dc couple to these inputs. If the differential REFIN is driven by a single-ended signal, the unused side ( via a suitable capacitor to a quiet ground. shows the

REFIN

) should be decoupled

Figure 37

equivalent circuit of REFIN.

S

85kΩ

REF1

V

S

07972-066

REFIN

REF2

10kΩ 12kΩ

150Ω

10kΩ 10kΩ

V

S

85kΩ

Figure 37. REFIN Equivalent Circuit

Reference Switchover

The AD9516 supports dual single-ended CMOS inputs, as well as a single differential reference input. In dual single-ended reference mode, automatic and manual PLL reference clock switching between REF1 (Pin REFIN) and REF2 (Pin

REFIN

) is supported. This feature supports networking and other applications that require smooth switching of redundant references. When used in conjunction with the automatic holdover function, the

AD9516

can achieve a worst-case reference input switchover with an output frequency disturbance as low as 10 ppm.

When using reference switchover, the single-ended reference inputs should be dc-coupled CMOS levels that are never allowed to go to high impedance. If the inputs are allowed to go to high impedance, noise may cause the buffer to chatter, causing false detection of the presence of a reference. Reference switchover can be performed manually or automatically. Manual switchover is performed either through Register 0x01C or by using the REF_SEL pin.

Manual switchover requires the presence of a clock on the reference input that is being switched to, or that the deglitching feature be disabled (Register 0x01C[7]). The reference switching logic fails if this condition is not met, and the PLL does not reacquire.

Rev. A | Page 29 of 76

AD9516-5

Automatic revertive switchover relies on the REFMON pin to indicate when REF1 disappears. By programming Register 0x01B = 0xF7 and Register 0x01C = 0x26, the REFMON pin is programmed to be high when REF1 is invalid, which commands the switch to REF2. When REF1 is valid again, the REFMON pin goes low, and the part again locks to REF1. The STATUS pin can also be used for this function, and REF2 can be used as the preferred reference.

A switchover deglitch feature ensures that the PLL does not receive rising edges that are far out of alignment with the newly selected reference. Automatic nonrevertive switching is not supported.

Reference Divider R

The reference inputs are routed to the reference divider, R. R (a 14-bit counter) can be set to any value from 0 to 16,383 by writing to Register 0x011 and Register 0x012. (Both R = 0 and R = 1 give divide-by-1.) The output of the R divider goes to one of the PFD inputs to be compared with the VCO frequency divided by the N divider. The frequency applied to the PFD must not exceed the maximum allowable frequency, which depends on the antibacklash pulse setting (see Tabl e 2 ).

The R counter has its own reset. The R counter can be reset via the shared reset bit of the R, A, and B counters. It can also be reset by a

SYNC

operation.

VCXO/VCO Feedback Divider N—P, A, B

The N divider is a combination of a prescaler (P) and two counters, A and B. The total divider value is

N = (P × B) + A

where P can be 2, 4, 8, 16, or 32.

Prescaler

The prescaler of the AD9516 allows for two modes of operation: a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus (DM) mode where the prescaler divides by P and (P + 1) {2 and 3, 4 and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes of operation are given in Ta bl e 49 , Register 0x016[2:0]. Not all modes are available at all frequencies (see Ta bl e 2).

When operating the AD9516 in dual modulus mode, P/(P + 1), the equation used to relate the input reference frequency to the VCO output frequency is

f

= (f

VCO

/R) × (P × B + A) = f

REF

× N/R

REF

However, when operating the prescaler in FD Mode 1, FD Mode 2, or FD Mode 3, the A counter is not used (A = 0) and the equation simplifies to

f

= (f

VCO

/R) × (P × B) = f

REF

× N/R

When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32, in which case, the previous equation also applies.

By using combinations of DM and FD modes, the AD9516 can achieve values of N all the way down to N = 1 and up to N = 26,2175. Tabl e 24 shows how a 10 MHz reference input can be locked to any integer multiple of N.

Table 24. Using a 10 MHz Reference to Generate Different VCO Frequencies

f

(MHz) R P A B N f

REF

(MHz) Mode Conditions/Comments

VCO

10 1 1 X1 1 1 10 FD P = 1, B = 1 (A and B counters are bypassed). 10 1 2 X1 1 2 20 FD P = 2, B = 1 (A and B counters are bypassed). 10 1 1 X1 3 3 30 FD A counter is bypassed. 10 1 1 X1 4 4 40 FD A counter is bypassed. 10 1 1 X1 5 5 50 FD A counter is bypassed. 10 1 2 X1 3 6 60 FD A counter is bypassed. 10 1 2 0 3 6 60 DM 10 1 2 1 3 7 70 DM

Maximum frequency into prescaler in P = 2/3 mode is 200 MHz. If N = 7 or N = 11 is desired for prescaler input frequency of 200 MHz

to 300 MHz, use P = 1, and N = 7 or 11, respectively. 10 1 2 2 3 8 80 DM 10 1 2 1 4 9 90 DM 10 1 8 6 18 150 1500 DM 10 1 8 7 18 151 1510 DM 10 1 16 7 9 151 1510 DM 10 10 32 6 47 1510 1510 DM 10 1 8 0 25 200 2000 DM 10 1 16 14 16 270 2700 DM P = 8 is not allowed (2700 ÷ 8 > 300 MHz).

P = 32 is not allowed (A > B not allowed). 10 10 32 22 84 2710 2710 DM P = 32, A = 22, B = 84.

P = 16 is also permitted.

1

X = don’t care.

Rev. A | Page 30 of 76

AD9516-5

V

Note that the same value of N can be derived in different ways, as illustrated by the case of N = 12. The user can choose a fixed divide mode of P = 2 with B = 6; use the dual modulus mode of 2/3 with A = 0, B = 6; or use the dual modulus mode of 4/5 with A = 0, B = 3.

A and B Counters

The B counter must be ≥3 or bypassed, and, unlike the R counter, A = 0 is actually zero. When the prescaler is in dual modulus mode, the A counter must be less than the B counter.

The maximum input frequency to the A or B counter is reflected in the maximum prescaler output frequency (~300 MHz) that is specified in Ta ble 2 . This is the prescaler input frequency (external VCO or CLK) divided by P. For example, a dual modulus mode of P = 8/9 mode is not allowed if the external VCO frequency is greater than 2400 MHz because the frequency going to the A or B counter is too high.

When the B counter is bypassed (B = 1), the A counter should be set to 0, and the overall resulting divide is equal to the prescaler setting, P. The possible divide ratios in this mode are 1, 2, 3, 4, 8, 16, and 32. This mode is useful only when an external VCO/VCXO is used because the frequency range of the internal VCO requires an overall feedback divider that is greater than 32.

Although manual reset is not normally required, the A and B counters have their own reset bit. Alternatively, the A and B counters can be reset using the shared reset bit of the R, A, and B counters. Note that these reset bits are not self-clearing.

R, A, and B Counters—

SYNC

Pin Reset

The R, A, and B counters can also be reset simultaneously via

SYNC

the (see ). The Tabl e 49

pin. This function is controlled by Register 0x019[7:6]

SYNC

pin reset is disabled by default.

R and N Divider Delays

Both the R and N dividers feature a programmable delay cell. These delays can be enabled to allow adjustment of the phase relationship between the PLL reference clock and the VCO or CLK. Each delay is controlled by three bits. The total delay range is about 1 ns. See Register 0x019 in Tabl e 49 .

LOCK DETECT

Digital Lock Detect (DLD)

By selecting the proper output through the mux on each pin, the DLD function can be made available at the LD, STATUS, and REFMON pins. The DLD circuit indicates a lock when the time difference of the rising edges at the PFD inputs is less than a specified value (the lock threshold). The loss of a lock is indicated when the time difference exceeds a specified value (the unlock threshold). Note that the unlock threshold is wider than the lock threshold, which allows some phase error in excess of the lock window to occur without chattering on the lock indicator.

The lock detect window timing depends on three settings: the digital lock detect window bit (Register 0x018[4]), the antibacklash pulse width setting (Register 0x017[1:0]), see Tabl e 2), and the

lock detect counter (Register 0x018[6:5]). A lock is not indicated until there is a programmable number of consecutive PFD cycles with a time difference that is less than the lock detect threshold. The lock detect circuit continues to indicate a lock until a time difference greater than the unlock threshold occurs on a single subsequent cycle. For the lock detect to work properly, the period of the PFD frequency must be greater than the unlock threshold. The number of consecutive PFD cycles required for lock is programmable (Register 0x018[6:5]).

Analog Lock Detect (ALD)

The AD9516 provides an ALD function that can be selected for use at the LD pin. There are two versions of ALD, as follows:

• N-channel open-drain lock detect. This signal requires

a pull-up resistor to the positive supply, VS. The output is normally high with short, low going pulses. Lock is indicated by the minimum duty cycle of the low going pulses.

• P-channel open-drain lock detect. This signal requires

a pull-down resistor to GND. The output is normally low with short, high going pulses. Lock is indicated by the minimum duty cycle of the high going pulses.

The analog lock detect function requires an R-C filter to provide a logic level indicating lock/unlock.

S = 3.3V

AD9516-5

LD

ALD

Figure 38. Example of Analog Lock Detect Filter, Using

N-Channel Open-Drain Driver

R2

V

R1

OUT

C

07972-067

Current Source Digital Lock Detect (CSDLD)

During the PLL locking sequence, it is normal for the DLD signal to toggle a number of times before remaining steady when the PLL is completely locked and stable. There may be applications where it is desirable to have DLD asserted only after the PLL is solidly locked. This is made possible by using the current source lock detect function. This function is set when it is selected as the output from the LD pin control (Register 0x01A[5:0]).

The current source lock detect provides a current of 110 μA when DLD is true, and it shorts to ground when DLD is false. If a capacitor is connected to the LD pin, it charges at a rate that is determined by the current source during the DLD true time but is discharged nearly instantly when DLD is false. By monitoring the voltage at the LD pin (top of the capacitor), it is possible to get a logic high level only after the DLD has been true for a sufficiently long time. Any momentary DLD false resets the charging. By selecting a properly sized capacitor, it is possible to delay a lock detect indication until the PLL is locked in a stable condition and the lock detect does not chatter.

Rev. A | Page 31 of 76

AD9516-5

CLKC

The voltage on the capacitor can be sensed by an external comparator connected to the LD pin. However, there is an internal LD pin comparator that can be read at the REFMON pin control (Register 0x01B[4:0]) or the STATUS pin control (Register 0x017[7:2]) as an active high signal. It is also available as an active low signal (REFMON, Register 0x01B[4:0] and STATUS, Register 0x017[7:2]). The internal LD pin comparator trip point and hysteresis are listed in Tab le 1 2.

AD9516-5

110µA

C

V

OUT

CLK

07972-068

)

DLD

LD PIN

COMPARAT OR

Figure 39. Current Source Lock Detect

LD

REFMON OR STATUS

External VCXO/VCO Clock Input (CLK/

CLK is a differential input that can be used to drive the AD9516 clock distribution section. This input can receive up to 2.4 GHz. The pins are internally self-biased, and the input signal should be ac-coupled via capacitors.

CLOCK INPUT

STAGE

07972-032

The CLK/

VS

LK

2.5kΩ 2.5kΩ

5kΩ

Figure 40. CLK Equivalent Input Circuit

CLK

input can be used either as a distribution only input (with the PLL off ), or as a feedback input for an external VCO/VCXO using the PLL. The CLK/

CLK

input can be used

for frequencies up to 2.4 GHz.

Holdover

The AD9516 PLL has a holdover function. Holdover is implemented by putting the charge pump into a high impedance state. This is useful when the PLL reference clock is lost. Holdover mode allows the VCO to maintain a relatively constant frequency even though there is no reference clock. Without this function, the charge pump is placed into a constant pump-up or pumpdown state, resulting in a large VCO frequency shift. Because the charge pump is placed in a high impedance state, any leakage that occurs at the charge pump output or the VCO tuning node causes a drift of the VCO frequency. This can be mitigated by using a loop filter that contains a large capacitive component because this drift is limited by the current leakage induced slew rate (I

/C) of the VCO control voltage. For most applications,

LEAK

the frequency is sufficient for 3 sec to 5 sec.

SYNC

Both a manual holdover mode, using the

pin, and an automatic holdover mode are provided. To use either function, the holdover function must be enabled (Register 0x01D[0] and Register 0x01D[2]).

Manual Holdover Mode

A manual holdover mode can be enabled that allows the user to place the charge pump into a high impedance state when the SYNC

pin is asserted low. This operation is edge sensitive, not level sensitive. The charge pump enters a high impedance state immediately. To take the charge pump out of a high impedance state, take the

SYNC

pin high. The charge pump then leaves the high impedance state synchronously with the next PFD rising edge from the reference clock. This prevents extraneous charge pump events from occurring during the time between

SYNC

going high and the next PFD event. This also means that the charge pump stays in a high impedance state as long as there is no reference clock present.

The B counter (in the N divider) is reset synchronously with the charge pump leaving the high impedance state on the reference path PFD event. This helps align the edges out of the R and N dividers for faster settling of the PLL. Because the prescaler is not reset, this feature works best when the B and R numbers are close because this results in a smaller phase difference for the loop to settle out.

When using this mode, set the channel dividers to ignore the SYNC

pin (at least after an initial not set to ignore the each time

SYNC

is taken low to put the part into holdover.

SYNC

event). If the dividers are

pin, the distribution outputs turn off

Rev. A | Page 32 of 76

AD9516-5

Automatic/Internal Holdover Mode

When enabled, this function automatically puts the charge pump into a high impedance state when the loop loses lock. The assumption is that the only reason that the loop loses lock is due to the PLL losing the reference clock; therefore, the holdover function puts the charge pump into a high impedance state to maintain the VCO frequency as close as possible to the original frequency before the reference clock disappears.

See Figure 41 for a flowchart of the internal/automatic holdover function operation.

The holdover function senses the logic level of the LD pin as a condition to enter holdover. The signal at LD can be from the DLD, ALD, or current source LD (CSDLD) mode. It is possible to disable the LD comparator (Register 0x01D[3]), which causes the holdover function to always sense LD as high. If DLD is used, it is possible for the DLD signal to chatter somewhat while the PLL is reacquiring lock. The holdover function may retrigger, thereby preventing the holdover mode from ever terminating. Use of the current source lock detect mode is recommended to avoid this situation (see the Current Source Digital Lock Detect section).

When in holdover mode, the charge pump stays in a high impedance state as long as there is no reference clock present.

As in the external holdover mode, the B counter (in the N divider) is reset synchronously with the charge pump leaving the high impedance state on the reference path PFD event. This helps to align the edges out of the R and N dividers for faster settling of the PLL and reduce frequency errors during settling. Because the prescaler is not reset, this feature works best when the B and R numbers are close because this results in a smaller phase difference for the loop to settle out.

After leaving holdover, the loop then reacquires lock, and the LD pin must charge (if Register 0x01D[3] = 1) before it can re-enter holdover (CP high impedance).

The holdover function always responds to the state of the currently selected reference (Register 0x01C). If the loop loses lock during a reference switchover (see the Reference Switchover section), holdover is triggered briefly until the next reference clock edge at the PFD.

PLL ENABLED

LOOP OUT OF LOCK. DIGITAL LOCK

NO

DETECT SIGNAL GOES LOW WHEN THE LOOP LEAVES LOCK AS DETERMINED

DLD == LOW

YES

WAS

LD PIN == HIGH

WHEN DLD WENT

LOW?

YES

HIGH IMPEDANCE

CHARGE PUMP

YES

REFERENCE

EDGE AT PFD?

YES

RELEASE

CHARGE PUMP

HIGH IMPEDANCE

YES

DLD == HIG H

BY THE PHASE DIFFERENCE AT THE INPUT OF THE PFD.

NO

ANALOG L OCK DETECT PIN INDI CATES LOCK WAS P REVIOUSL Y ACHIEVED. REGISTER 0x1D[3] = 1: USE LD PIN VOLTAGE WITH HOLDOVER. REGISTER 0x1D[3] = 0: IGNORE LD PIN VOLTAG E,TREAT LD PIN AS ALWAYS HI GH.

CHARGE PUMP I S MADE HIGH IMP EDANCE. PLL COUNT ERS CONTI NUE OPERATI NG NORMALL Y.

NO

CHARGE PUMP REMAINS HIGH IMPEDANCE UNTIL THE REFERENCE HAS RETURNED.

YES

TAKE CHARGE PUM P OUT OF HIGH IMP EDANCE. PLL CAN NOW RESETTLE.

NO

WAIT FOR DLD TO GO HIGH. THIS TAKES 5 TO 255 CYCLES (PROGRAMMI NG OF THE DLD DEL AY COUNTER) WITH T HE REFERENCE AND F EEDBACK CLOCKS INSIDE THE LOCK WINDOW AT THE PFD. THIS ENSURES THAT THE HOLDOVER FUNCTION WAITS FOR THE PLL TO SET TLE AND LOCK BEFORE THE HOLDOVER FUNCTIO N CAN BE RETRIG GERED.

Figure 41. Flowchart of Automatic/Internal Holdover Mode

07972-069

Rev. A | Page 33 of 76

AD9516-5

V

The following registers affect the internal/automatic holdover function:

• Register 0x018[6:5], lock detect counter. These bits change

how many PFD cycles with edges inside the lock detect window are required for the DLD indicator to indicate lock. This impacts the time required before the LD pin can begin to charge, as well as the delay from the end of a holdover event until the holdover function can be reengaged.

• Register 0x018[3], disable digital lock detect. This bit must

be set to 0b to enable the DLD circuit. Internal/automatic holdover does not operate correctly without the DLD function enabled.

• Register 0x01A[5:0], lock detect pin output select. Set this

to 000100b to put it in the current source lock detect mode if using the LD pin comparator. Load the LD pin with a capacitor of an appropriate value.

• Register 0x01D[3], LD pin comparator enable. 1b = enable;

0b = disable. When disabled, the holdover function always senses the LD pin as high.

• Register 0x01D[1], external holdover control.

• Register 0x01D[0] and Register 0x01D[2], holdover enable.

If holdover is disabled, both external and automatic/internal holdover are disabled.

For example, to use automatic holdover with the following:

• Digital lock detect: five PFD cycles, high range window

• Automatic holdover using the LD pin comparator

Set the following registers (in addition to the normal PLL registers):

• Register 0x018[6:5] = 00b; lock detect counter = five cycles.

• Register 0x018[4] = 0b; lock detect window = high range.

• Register 0x018[3] = 0b; DLD normal operation.

• Register 0x01A[5:0] = 000100b; current source lock detect

mode.

• Register 0x01B[7:0] = 0xF7; set REFMON pin to status of

REF1 (active low).

• Register 0x01C[2:1] = 11b; enable REF1 and REF2 input

buffers.

• Register 0x01D[3] = 1b; enable LD pin comparator.

• Register 0x01D[2] = 1b; enable holdover function.

• Register 0x01D[1] = 0b; use internal/automatic holdover

mode.

• Register 0x01D[0] = 1b; enable holdover function

(complete VCO calibration before enabling this bit).

• Register 0x232 = 0x01; update all registers.

And, finally,

• Connect REFMON pin to REFSEL pin.

Frequency Status Monitors

The AD9516 contains three frequency status monitors that are used to indicate if the PLL reference (or references, in the case of single-ended mode) and the VCO have fallen below a threshold frequency. Figure 42 is a diagram that shows their location in the PLL.

The PLL reference frequency monitors have two threshold frequencies: normal and extended (see Tabl e 12 ). The reference frequency monitor thresholds are selected in Register 0x01B[7:5]. The reference frequency monitor status can be found in Register 0x01F[3:1].

REFIN ( REF1)

REFIN ( REF2)

CLK

REF1

REF2

REF_SEL CPRSETVCP

REFERENCE

SWITCHOVER

STATUS

S GND RSET

DISTRIBUTI ON

REFERENCE

R

DIVIDER

N DIVIDE R

P, P + 1

PRESCALER

DIVIDE BY

2, 3, 4, 5, OR 6

01

A/B

COUNTERS

PROGRAMMABLE

CLK FREQUENCY

STATUS

0

1

REFMO N

R DELAY

N DELAY

LOCK

DETECT

PHASE

FREQUENCY

DETECT OR

PLL

REFERENCE

Figure 42. Reference and CLK Status Monitors

Rev. A | Page 34 of 76

CHARGE

PUMP

HOLD

LD

CP

STATUS

07972-070

AD9516-5

CLOCK DISTRIBUTION

A clock channel consists of a pair (or double pair, in the case of CMOS) of outputs that share a common divider. A clock output consists of the drivers that connect to the output pins. The clock outputs have either LVPECL or LVDS/CMOS signal levels at the pins.

The AD9516 has five clock channels: three channels are LVPECL (six outputs); two channels are LVDS/CMOS (up to four LVDS outputs, or up to eight CMOS outputs).

Each channel has its own programmable divider that divides the clock frequency that is applied to its input. The LVPECL channel dividers can divide by any integer from 2 to 32, or the divider can be bypassed to achieve a divide-by-1. Each LVDS/CMOS channel divider contains two of these divider blocks in a cascaded configuration. The total division of the channel is the product of the divide value of the cascaded dividers. This allows divide values of (1 to 32) × (1 to 32), or up to 1024 (note that this is not all values from 1 to 1024 but only the set of numbers that are the product of the two dividers).

The VCO divider can be set to divide by 2, 3, 4, 5, or 6 and must be used if the external clock signal connected to the CLK input is greater than 1600 MHz.

The channel dividers allow for a selection of various duty cycles, depending on the currently set division. That is, for any specific division, D, the output of the divider can be set to high for N + 1 input clock cycles and low for M + 1 input clock cycles (where D = N + M + 2). For example, a divide-by-5 can be high for one divider input cycle and low for four cycles, or a divide-by-5 can be high for three divider input cycles and low for two cycles. Other combinations are also possible.

The channel dividers include a duty-cycle correction function that can be disabled. In contrast to the selectable duty cycle just described, this function can correct a non-50% duty cycle caused by an odd division. However, this requires that the division be set by M = N + 1.

In addition, the channel dividers allow a coarse phase offset or delay to be set. Depending on the division selected, the output can be delayed by up to 31 input clock cycles. The divider outputs can also be set to start high or start low.

Operating Modes

There are two clock distribution operating modes. These operating modes are shown in Table 25 .

It is not necessary to use the VCO divider if the CLK frequency is less than the maximum channel divider input frequency (1600 MHz); otherwise, the VCO divider must be used to reduce the frequency going to the channel dividers.

Table 25. Clock Distribution Operating Modes

Mode 0x1E1[0] VCO Divider

2 0 Used 1 1 Not used

CLK Direct to LVPECL Outputs

It is possible to connect the CLK directly to the LVPECL outputs, OUT0 to OUT5. However, the LVPECL outputs may not be able to provide full a voltage swing at the highest frequencies.

To connect the LVPECL outputs directly to the CLK input, the VCO divider must be selected as the source to the distribution section even if no channel uses it.

Table 26. Settings for Routing VCO Divider Input Directly to LVPECL Outputs

Register Setting Selection

0x1E1[0] = 0b VCO divider selected 0x192[1] = 1b Direct to OUT0, OUT1 outputs 0x195[1] = 1b Direct to OUT2, OUT3 outputs 0x198[1] = 1b Direct to OUT4, OUT5 outputs

Clock Frequency Division

The total frequency division is a combination of the VCO divider (when used) and the channel divider. When the VCO divider is used, the total division from the VCO or CLK to the output is the product of the VCO divider (2, 3, 4, 5, and 6) and the division of the channel divider. Tab l e 2 7 and Ta b le 2 8 indicate how the frequency division for a channel is set. For the LVPECL outputs, there is only one divider per channel. For the LVDS/ CMOS outputs, there are two dividers (X.1, X.2) cascaded per channel.

Table 27. Frequency Division for Divider 0 to Divider 2

VCO Divider Setting

2 to 6 Don’t care Enable 1 2 to 6 Bypass Disable (2 to 6) × (1) 2 to 6 2 to 32 Disable (2 to 6) × (2 to 32) VCO Divider

Bypassed

VCO Divider

Bypassed

Channel Divider Setting

Bypass No 1

2 to 32 No 2 to 32

CLK Direct to Out put Setting

Frequency Division

Table 28. Frequency Division for Divider 3 and Divider 4

VCO Divider Setting

2 to 6 Bypass Bypass (2 to 6) × (1) × (1) 2 to 6 2 to 32 Bypass (2 to 6) × (2 to 32) × (1) 2 to 6 2 to 32 2 to 32

Bypass 1 1 1 Bypass 2 to 32 1 (2 to 32) × (1) Bypass 2 to 32 2 to 32 2 to 32 × (2 to 32)

Channel Divider Setting

X.1 X.2

Resulting Frequency Division

(2 to 6) × (2 to 32) × (2 to 32)

The channel dividers feeding the LVPECL output drivers contain one 2-to-32 frequency divider. This divider provides for division by 2 to 32. Division by 1 is accomplished by bypassing the divider. The dividers also provide for a programmable duty cycle, with optional duty-cycle correction when the divide ratio is odd.

Rev. A | Page 35 of 76

AD9516-5

A phase offset or delay in increments of the input clock cycle is selectable. The channel dividers operate with a signal at their inputs up to 1600 MHz. The features and settings of the dividers are selected by programming the appropriate setup and control registers (see Ta b le 4 7 through Tabl e 5 7 ).

VCO Divider

The VCO divider provides frequency division between the external CLK input and the clock distribution channel dividers. The VCO divider can be set to divide by 2, 3, 4, 5, or 6 (see Tabl e 55 , Register 0x1E0[2:0]).

Channel Dividers—LVPECL Outputs

Each pair of LVPECL outputs is driven by a channel divider. There are three channel dividers (0, 1, and 2) driving six LVPECL outputs (OUT0 to OUT5). Tab le 2 9 lists the register locations used for setting the division and other functions of these dividers. The division is set by the values of M and N. The divider can be bypassed (equivalent to divide-by-1, divider circuit is powered down) by setting the bypass bit. The duty-cycle correction can be enabled or disabled according to the setting of the DCCOFF bits.

Table 29. Setting D

Low Cycles M High Cycles

Divider

0 0x190[7:4] 0x190[3:0] 0x191[7] 0x192[0] 1 0x193[7:4] 0x193[3:0] 0x194[7] 0x195[0] 2 0x196[7:4] 0x196[3:0] 0x197[7] 0x198[0]

1

Note that the value stored in the register = # of cycles minus 1. For example,

0x190[7:4] = 0001b equals two low cycles (M = 2) for Divider 0.

for Divider 0, Divider 1, and Divider 21

X

N Bypass DCCOFF

Channel Frequency Division (0, 1, and 2)

For each channel (where the channel number is x: 0, 1, or 2), the frequency division, D

, is set by the values of M and N

X

(four bits each, representing Decimal 0 to Decimal 15), where

Number of Low Cycles = M + 1

Number of High Cycles = N + 1

The cycles are cycles of the clock signal currently routed to the input of the channel dividers (VCO divider out or CLK).

When a divider is bypassed, D

Otherwise, D

= (N + 1) + (M + 1) = N + M + 2. This allows

X

= 1.

X

each channel divider to divide by any integer from 2 to 32.

Duty Cycle and Duty-Cycle Correction (0, 1, and 2)

The duty cycle of the clock signal at the output of a channel is a result of some or all of the following conditions:

• What are the M and N values for the channel?

• Is the DCC enabled?

• Is the VCO divider used?

• What is the CLK input duty cycle?

The DCC function is enabled, by default, for each channel divider. However, the DCC function can be disabled individually for each channel divider by setting the DCCOFF bit for that channel.

Certain M and N values for a channel divider result in a non-50% duty cycle. A non-50% duty cycle can also result with an even division, if M ≠ N. The duty-cycle correction function automatically corrects non-50% duty cycles at the channel divider output to 50% duty cycle. Duty-cycle correction requires the following channel divider conditions:

• An even division must be set as M = N

• An odd division must be set as M = N + 1

When not bypassed or corrected by the DCC function, the duty cycle of each channel divider output is the numerical value of (N + 1)/(N + M + 2), expressed as a percentage (%).

Tabl e 3 0 to Ta bl e 32 list the duty cycles at the output of the channel dividers for various configurations.

Table 30. Duty Cycle with VCO Divider, Input Duty Cycle Is 50%

VCO Divider

Even

Odd = 3

Odd = 5

Even, Odd

DX Output Duty Cycle

N + M + 2 DCCOFF = 1 DCCOFF = 0

1 (divider bypassed)

Even

Odd

50% 50%

33.3% 50%

40% 50%

(N + 1)/ (N + M + 2)

50%, requires M = N

50%, requires M = N + 1

Table 31. Duty Cycle with VCO Divider, Input Duty Cycle Is X%

VCO Divider

Even

Odd = 3

Odd = 5

Even Even

Odd

Odd = 3 Even

Odd = 3 Odd

Odd = 5 Even

Odd = 5 Odd

DX Output Duty Cycle

N + M + 2 DCCOFF = 1 DCCOFF = 0

1 (divider bypassed)

50% 50%

33.3% (1 + X%)/3

40% (2 + X%)/5

(N + 1)/ (N + M + 2)

50%, requires M = N

50%, requires M = N + 1

50%, requires M = N

(3N + 4 + X%)/(6N + 9), requires M = N + 1

50%, requires M = N

(5N + 7 + X%)/(10N + 15), requires M = N + 1

Rev. A | Page 36 of 76

AD9516-5

Table 32. Channel Divider Output Duty Cycle When the VCO Divider Is Not Used

Input Clock Duty Cycle

Any

DX Output Duty Cycle

N + M + 2 DCCOFF = 1 DCCOFF = 0

Channel divider

1 (divider bypassed)

Same as input duty cycle

bypassed

Any Even

(N + 1)/

50%, requires M = N

(M + N + 2)

50% Odd

X% Odd

(N + 1)/ (M + N + 2)

50%, requires M = N + 1

(N + 1 + X%)/(2 × N + 3), requires M = N + 1

If the CLK input is routed directly to the output, the duty cycle of the output is the same as the CLK input.

Phase Offset or Coarse Time Delay (0, 1, and 2)

Each channel divider allows for a phase offset, or a coarse time delay, to be programmed by setting register bits (see Ta b le 3 3). These settings determine the number of cycles (successive rising edges) of the channel divider input frequency by which to offset, or delay, the rising edge of the output of the divider. This delay is with respect to a nondelayed output (that is, with a phase offset of zero). The amount of the delay is set by five bits loaded into the phase offset (PO) register, plus the start high (SH) bit for each channel divider. When the start high bit is set, the delay is also affected by the number of low cycles (M) that are programmed for the divider.

The sync function must be used to make phase offsets effective (see the Synchronizing the Outputs—SYNC Function section).

Table 33. Setting Phase Offset and Division for Divider 0, Divider 1, and Divider 2

Start

Divider

High (SH)

1

Phase Offset (PO)

Low Cycles (M)

High Cycles (N)

0 0x191[4] 0x191[3:0] 0x190[7:4] 0x190[3:0] 1 0x194[4] 0x194[3:0] 0x193[7:4] 0x193[3:0] 2 0x197[4] 0x197[3:0] 0x196[7:4] 0x196[3:0]

1

Note that the value stored in the register = # of cycles minus 1. For example,

Register 0x190[7:4] = 0001b equals two low cycles (M = 2) for Divider 0.

Let

= delay (in seconds).

Δ

t

Δ

= delay (in cycles of clock signal at input to DX).

c

= period of the clock signal at the input of the divider, DX (in

T

X

seconds). Φ = 16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]

The channel divide-by is set as N = high cycles and M = low cycles.

Rev. A | Page 37 of 76

Case 1

For Φ ≤ 15: Δ

= Φ × TX

t

Δ

= Δt/TX = Φ

c

Case 2

For Φ ≥ 16: Δ

= (Φ − 16 + M + 1) × T

t

X

Δc = Δt/TX

By giving each divider a different phase offset, output-to-output delays can be set in increments of the channel divider input clock cycle. Figure 43 shows the results of setting such a coarse offset between outputs.

CHANNEL

DIVIDER I NPUT

DIVIDER 0

DIVIDER 1

DIVIDER 2

0123456789101112131415

Tx

SH = 0 PO = 0

SH = 0 PO = 1

SH = 0 PO = 2

Figure 43. Effect of Coarse Phase Offset (or Delay)

C

A

H

N

1 × Tx

2 × Tx

E

L

D I

D

V

T

P

T

U

S

U

E

D

R

O

I

V

I

=

5

0

4

,

=

%

T

U

D

Y

Channel Dividers—LVDS/CMOS Outputs

Channel Divider 3 and Channel Divider 4 each drive a pair of LVDS out p u t s , g iving four LVDS output s (OUT6 to OUT9). Alternatively, each of these LVDS differential outputs can be configured individually as a pair (A and B) of CMOS singleended outputs, providing for up to eight CMOS outputs. By default, the B output of each pair is off but can be turned on as desired.

Channel Divider 3 and Channel Divider 4 each consist of two cascaded, 2 to 32, frequency dividers. The channel frequency division is D

X.1

× D

, or up to 1024. Divide-by-1 is achieved by

X.2

bypassing one or both of these dividers. Both of the dividers also have DCC enabled by default, but this function can be disabled, if desired, by setting the DCCOFF bit of the channel. A coarse phase offset or delay is also programmable (see the Phase Offset or Coarse Time Delay (Divider 3 and Divider 4) section). The channel dividers operate up to 1600 MHz. The features and settings of the dividers are selected by programming the appropriate setup and control registers (see Tabl e 47 and Tabl e 4 8 through Tab l e 5 7 ).

Table 34. Setting Division (D

) for Divider 3 and Divider 41

X

Divider M N Bypass DCCOFF

3 3.1 0x199[7:4] 0x199[3:0] 0x19C[4] 0x19D[0]

3.2 0x19B[7:4] 0x19B[3:0] 0x19C[5] 0x19D[0] 4 4.1 0x19E[7:4] 0x19E[3:0] 0x1A1[4] 0x1A2[0]

4.2 0x1A0[7:4] 0x1A0[3:0] 0x1A1[5] 0x1A2[0]

1

Note that the value stored in the register = # of cycles minus 1. For example,

Register 0x199[7:4] = 0001b equals two low cycles (M = 2) for Divider 3.1.

07972-071

AD9516-5

Channel Frequency Division (Divider 3 and Divider 4)

The division for each channel divider is set by the bits in the registers for the individual dividers (X.Y = 3.1, 3.2, 4.1, and 4.2).

Number of Low Cycles = M

Number of High Cycles = N

When both X.1 and X.2 are bypassed, D

When only X.2 is bypassed, D

When both X.1 and X.2 are not bypassed, D (N

+ M

X.2

+ 2).

X.2

X.Y

= (N

X

+ 1

X.1

= 1 × 1 = 1.

X

+ M

+ 2) × 1.

X.1

= (N

X

X.1

+ M

+ 2) ×

X.1

By cascading the dividers, channel division up to 1024 can be obtained. However, not all integer value divisions from 1 to 1024 are obtainable; only the values that are the product of the separate divisions of the two dividers (D

X.1

× D

X.2

) can be realized.

If only one divider is needed when using Divider 3 and Divider 4, use the first one (X.1) and bypass the second one (X.2). Do not bypass X.1 and use X.2.

Duty Cycle and Duty-Cycle Correction (Divider 3 and Divider 4)

The same duty cycle and DCC considerations apply to Divider 3 and Divider 4 as to Divider 0, Divider 1, and Divider 2 (see the Duty Cycle and Duty-Cycle Correction (0, 1, and 2) section); however, with these channel dividers, the number of possible configurations is more complex.

Duty-cycle correction on Divider 3 and Divider 4 requires the following channel divider conditions:

• An even D

must be set as M

X.Y

= N

(low cycles = high

X.Y

cycles).

• An odd D

must be set as M

X.Y

= N

+ 1 (number of low

X.Y

cycles must be one greater than the number of high cycles).

• If only one divider is bypassed, it must be the second

divider, X.2.

• If only one divider has an even divide-by, it must be the

second divider, X.2.

The possibilities for the duty cycle of the output clock from Divider 3 and Divider 4 are shown in Tab le 3 5 through Tabl e 39 .

Table 36. Divider 3 and Divider 4 Duty Cycle; VCO Divider Not Used; Duty Cycle Correction Off (DCCOFF = 1)

D

X.1

Input

X.2

Clock

+ 2

Output Duty Cycle

Duty Cycle

+ M

N

X.1

+ 2 N

X.1

X.2

+ M

X.2

50% Bypassed Bypassed 50% X% Bypassed Bypassed X% 50% Even, odd Bypassed

X% Even, odd Bypassed

50% Even, odd Even, odd

X% Even, odd Even, odd

(N (N

+ 1)/

X.1

+ M

X.1

+ 1)/

X.1

+ M

X.1

+ 1)/

X.2

+ M

X.2

+ 1)/

X.2

+ M

X.2

X.1

X.2

+ 2)

Table 37. Divider 3 and Divider 4 Duty Cycle; VCO Divider Used; Duty Cycle Correction On (DCCOFF = 0); VCO Divider Input Duty Cycle = 50%

VCO Divider

D

X.1

N

+ M

X.1

+ 2 N

X.1

X.2

+ M

X.2

+ 2

Output Duty Cycle

D

Even Bypassed Bypassed 50% Odd Bypassed Bypassed 50% Even Even (N Odd Even (N Even Odd (M Odd Odd (M Even Even (N

Odd Even (N

Even Odd (M

Odd Odd (M

Even Odd (M

Odd Odd (M

= M

X.1

) Bypassed 50%

X.1

= M

) Bypassed 50%

X.1

= N

+ 1) Bypassed 50%

X.1

= N

+ 1) Bypassed 50%

X.1

= M

)

Even

= M

= N

X.1

)

X.1

+ 1)

(N

X.2

Even (N

X.2

Even (N

X.2

Even (N

X.2

Odd (M

X.2

Odd (M

X.2

= M

= N

X.2

50%

)

50%

)

50%

)

50%

)

50%

+ 1)

50%

+ 1)

Table 35. Divider 3 and Divider 4 Duty Cycle; VCO Divider Used; Duty Cycle Correction Off (DCCOFF = 1)

VCO Divider

D

X.1

N

+ M

X.1

+ 2 N

X.1

X.2

+ M

X.2

Output Duty Cycle

+ 2

X.2

D

Even Bypassed Bypassed 50% Odd = 3 Bypassed Bypassed 33.3% Odd = 5 Bypassed Bypassed 40% Even Even, odd Bypassed

Odd Even, odd Bypassed

Even Even, odd Even, odd

Odd Even, odd Even, odd

(N (N

X.1

X.2

+ 1)/ + M

+ 2)

X.1

+ 2)

X.1

+ 2)

X.2

+ 2)

X.2

Rev. A | Page 38 of 76

AD9516-5

Table 38. Divider 3 and Divider 4 Duty Cycle; VCO Divider Used; Duty Cycle Correction On (DCCOFF = 0); VCO Divider Input Duty Cycle = X%

D

VCO Divider

D

X.1

N

+ M

+ 2

X.1

2

X.2

+ M

X.2

Output

+

X.2

Duty Cycle

Even Bypassed Bypassed 50% Odd = 3 Bypassed Bypassed (1 + X%)/3 Odd = 5 Bypassed Bypassed (2 + X%)/5 Even

Odd

Even

Odd = 3

Odd = 5

Even

Odd

Even

Odd

Even

Odd = 3

Odd = 5

Even (N

X.1

Even (N

X.1

Odd (M

X.1

Odd (M

X.1

Odd (M

X.1

Even (N

X.1

Even (N

X.1

Odd (M

X.1

Odd (M

X.1

Odd (M

X.1

Odd (M

X.1

Odd (M

X.1

= M

= N

= M

= N

X.1

+ 1)

Bypassed 50%

)

Bypassed 50%

)

Bypassed 50%

Bypassed

Even

)

(N

= M

)

X.2

Even

)

(N

= M

)

X.2

Even (N

= M

)

X.2

Even (N

= M

)

X.2

Odd (M

= N

+ 1)

X.2

Odd (M

= N

+ 1)

X.2

Odd (M

= N

+ 1)

X.2

+ 4 + X%)/

(3N

X.1

+ 9)

(6N

X.1

+ 7 + X%)/

(5N

X.1

(10N

X.1

50%

(6N

X.1NX.2

+ 13 + X%)/

9N

X.2

(3(2N

X.1

+ 3))

(2N

X.2

(10N

X.1NX.2

15N

X.2

(5(2 N (2 N

X.2

+ 15)

+ 9N

+

X.1

+ 3)

+ 15N

+ 22 + X%)/

+ 3)

X.1

+ 3))

Table 39. Divider 3 and Divider 4 Duty Cycle; VCO Divider Not Used; Duty Cycle Correction On (DCCOFF = 0)

Input Clock Duty Cycle

D

X.1

X.2

Output

+ M

N

X.1

+ 2 N

X.1

X.2

+ M

X.2

+ 2

Duty Cycle

50% Bypassed Bypassed 50% 50%

Even (N

X.1

= M

X.1

Bypassed 50%

) X% Bypassed Bypassed X% (high) X%

50%

X%

50%

X%

50%

X%

50%

X%

Even (N

X.1

Odd (M

X.1

Odd (M

X.1

Odd (M

X.1

Even (N

X.1

Even (N

X.1

Odd (M

X.1

Odd (M

X.1

Odd (M

X.1

Odd (M

X.1

= M

= N

= M

= N

X.1

Bypassed 50%

)

Bypassed 50%

+ 1)

Bypassed

+ 1)

Bypassed

+ 1)

Even

)

(N

= M

X.2

)

X.2

Even

)

(N

= M

X.2

)

X.2

Even

+ 1)

(N

= M

X.2

)

X.2

Even

+ 1)

(N

= M

X.2

)

X.2

Odd

+ 1)

(M

= N

+ 1)

X.2

Odd

+ 1)

(M

= N

+ 1)

X.2

+ 1 + X%)/

(N

X.1

(2N

X.1

+ 1 + X%)/

(N

X.1

(2N

X.1

50%

(2N

X.1NX.2

+ 4 + X%)/

3N

X.2

((2N

X.1

+ 3)

+ 3N

+ 3)(2N

X.1

X.2

+

+ 3))

Phase Offset or Coarse Time Delay (Divider 3 and Divider 4)

+

X.1

Divider 3 and Divider 4 can be set to have a phase offset or delay. The phase offset is set by a combination of the bits in the phase offset and start high registers (see Tab l e 4 0 ).

Table 40. Setting Phase Offset and Division for Divider 3 and

1

Divider 4

Divider

Start High (SH)

Phase Offset (PO)

Low Cycles M

High Cycles N

3 3.1 0x19C[0] 0x19A[3:0] 0x199[7:4] 0x199[3:0]

3.2 0x19C[1] 0x19A[7:4] 0x19B[7:4] 0x19B[3:0] 4 4.1 0x1A1[0] 0x19F[3:0] 0x19E[7:4] 0x19E[3:0]

4.2 0x1A1[1] 0x19F[7:4] 0x1A0[7:4] 0x1A0[3:0]

1

Note that the value stored in the register is equal to the number of cycles

minus 1. For example, Register 0x199[7:4] = 0001b equals two low cycles (M = 2) for Divider 3.1.

Rev. A | Page 39 of 76

AD9516-5

Let

= delay (in seconds).

Δ

t

Φ

= 16 × SH[0] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] +

x.y

1 × PO[0]. T

= period of the clock signal at the input to D

X.1

T

= period of the clock signal at the input to D

X.2

(in seconds).

X.1

(in seconds).

X.2

Case 1

When Φ Δ

= Φ

t

≤ 15 and Φ

x.1

× T

x.1

X.1

+ Φ

X.2

x.2

× T

≤ 15:

x.2

Case 2

When Φ Δ

= Φ

t

X.1

≤ 15 and Φ

x.1

× T

+ (Φ

X.1

≥ 16:

x.2

– 16 + M

X.2

+ 1) × T

X.2

Case 3

When Φ Δ

= (Φ

t

≥ 16 and Φ

X.1

− 16 + M

X.1

X.2

+ 1) × T

X.1

≤ 15:

X.1

+ Φ

X.2

× T

X.2

Case 4

When Φ Δ

=

t

(Φ

X.1

− 16 + M

X.1

≥ 16 and Φ

+ 1) × T

X.1

≥ 16:

X.2

X.1

+ (Φ

− 16 + M

X.2

+ 1) × T

X.2

Fine Delay Adjust (Divider 3 and Divider 4)

Each AD9516 LVDS/CMOS output (OUT6 to OUT9) includes an analog delay element that can be programmed to give variable time delays (Δ

VCO

CLK

DIVIDER

) in the clock signal at that output.

t

BYPASS

∆t

FINE DELAY

DIVIDER

X.1

DIVIDER

X.2

Figure 44. Fine Delay (OUT6 to OUT9)

ADJUST

BYPASS

∆t

FINE DELAY

ADJUST

CMOS

LVDS

CMOS

LVDS

CMOS

OUTM

OUTPUT DRIVERS

OUTN

07972-072

The amount of delay applied to the clock signal is determined by programming four registers per output (see Table 41).

Table 41. Setting Analog Fine Delays

OUTPUT (LVDS/CMOS)

Ramp Capacitors

Ramp Curre nt

Delay Fract ion

Delay Bypass

OUT6 0x0A1[5:3] 0x0A1[2:0] 0x0A2[5:0] 0x0A0[0] OUT7 0x0A4[5:3] 0x0A4[2:0] 0x0A5[5:0] 0x0A3[0] OUT8 0x0A7[5:3] 0x0A7[2:0] 0x0A8[5:0] 0x0A6[0] OUT9 0x0AA[5:3] 0x0AA[2:0] 0x0AB[5:0] 0x0A9[0]

Calculating the Fine Delay

The following values and equations are used to calculate the delay of the delay block.

I

(μA) = 200 × (Ramp Current + 1)

RAMP

Number of Capacitors = Number of Bits =

0 in Ramp Capacitors + 1

Example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3; 001 = 2 + 1 = 3; 111 = 0 + 1 = 1.

Delay Range (ns) = 200 × ((No. of Caps + 3)/(I

4



IOffset

RAMP



1016000.34ns

 



 

)) × 1.3286

RAMP

I

CapsofNo.

RAMP



1

Delay Full Scale (ns) = Delay Range + Offset

Fine Delay (ns) = Delay Range × Delay Fraction × (1/63) + Offset

Note that only delay fraction values up to 47 decimal (101111b; 0x02F) are supported.

In no case can the fine delay exceed one-half of the output clock period. If a delay longer than half of the clock period is attempted, the output stops clocking.

The delay function adds some jitter that is greater than that specified for the nondelayed output. This means that the delay function should be used primarily for clocking digital chips, such as FPGA, ASIC, DUC, and DDC. An output with this delay enabled may not be suitable for clocking data converters. The jitter is higher for long full scales because the delay block uses a ramp and trip points to create the variable delay. A slower ramp time produces more time jitter.

Synchronizing the Outputs—SYNC Function

The AD9516 clock outputs can be synchronized to each other. Outputs can be individually excluded from synchronization. Synchronization consists of setting the nonexcluded outputs to a preset set of static conditions and, subsequently, releasing these outputs to continue clocking at the same instant with the preset conditions applied. This allows for the alignment of the edges of two or more outputs or for the spacing of edges according to the coarse phase offset settings for two or more outputs.

Synchronization of the outputs is executed in several ways:

 By forcing the

SYNC

pin and then releasing it (manual sync)

 By setting and then resetting any one of the following three

bits: the soft SYNC bit (Register 0x230[0]), the soft reset bit (Register 0x000[2] [mirrored]), or the power-down distribution reference bit (Register 0x230[1])

 By executing synchronization of the outputs as part of the

chip power-up sequence

 By forcing the  By forcing the

RESET

pin low, then releasing it (chip reset)

PD

pin low, then releasing it (chip power-down)

 

6



 

Rev. A | Page 40 of 76

AD9516-5

S

R

The most common way to execute the SYNC function is to use

SYNC

the This requires a low going signal on the

pin to do a manual synchronization of the outputs.

SYNC

pin, which is held low and then released when synchronization is desired. The timing of the SYNC operation is shown in (using VCO divider) and (VCO divider not used). There is an uncertainty

Figure 46

Figure 45

of up to one cycle of the clock at the input to the channel divider due to the asynchronous nature of the SYNC signal with respect to the clock edges inside the . The delay from the

AD9516

SYNC

rising edge to the beginning of synchronized output clocking is

CHANNEL DIVIDE

OUTPUT CLOCKING

CHANNEL DIVIDER O UTPUT STAT IC

between 14 and 15 cycles of clock at the channel divider input, plus either one cycle of the VCO divider input (see ), or one cycle of the CLK input (see ), depending on

Figure 46

Figure 45

whether the VCO divider is used. Cycles are counted from the rising edge of the signal.

Another common way to execute the SYNC function is by setting and resetting the soft SYNC bit at Register 0x230[0] (see Ta b l e 47 through Tabl e 57 for details). Both the setting and resetting of the soft SYNC bit require an update all registers operation (Register 0x232[0] = 1) to take effect.

CHANNEL DIVIDE

OUTPUT CLOCKING

INPUT TO VCO DIVIDER

INPUT TO CHANNEL DIVIDER

YNC PIN

OUTPUT OF

CHANNEL DIVIDER

CHANNEL DIVIDE

OUTPUT CLOCKING

INPUT TO CLK

INPUT TO CHANNEL DIVIDE

123 456 78910

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT

Figure 45. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input

CHANNEL DIVIDER O UTPUT STAT IC

12345678910

11

1

11

12

13 14

CHANNEL DIVIDE

OUTPUT CLO CKING

1

07972-073

SYNC PIN

OUTPUT OF

CHANNEL DIVIDER

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK I NPUT

7972-074

Figure 46. SYNC Timing When VCO Divider Is Not Used—CLK Input Only

Rev. A | Page 41 of 76

AD9516-5

3

A

3

A

V

A sync operation brings all outputs that have not been excluded (by the nosync bit) to a preset condition before allowing the outputs to begin clocking in synchronicity. The preset condition takes into account the settings in each of the channel’s start high bit and its phase offset. These settings govern both the static state of each output when the sync operation is happening and the state and relative phase of the outputs when they begin clocking again upon completion of the sync operation. Between outputs and after synchronization, this allows for the setting of phase offsets.

The AD9516 outputs are in pairs, sharing a channel divider per pair (two pairs of pairs, four outputs, in the case of CMOS). The synchronization conditions apply to both outputs of a pair.

Each channel (a divider and its outputs) can be excluded from any sync operation by setting the nosync bit of the channel. Channels that are set to ignore SYNC (excluded channels) do not set their outputs static during a sync operation, and their outputs are not synchronized with those of the nonexcluded channels.

Clock Outputs

The AD9516 offers three output level choices: LVPECL, LVDS, and CMOS. OUT0 to OUT5 are LVPECL differential outputs; and OUT6 to OUT9 are LVDS/CMOS outputs. These outputs can be configured as either LVDS differential or as pairs of single-ended CMOS outputs.

LVPECL Outputs—OUT0 to OUT5

The LVPECL differential voltage (VOD) is selectable from 400 mV to 960 mV (see Register 0x0F0[3:2] to Register 0x0F5[3:2]). The LVPECL outputs have dedicated pins for power supply (VS_LVPECL), allowing a separate power supply to be used. V

can range from 2.5 V to 3.3 V.

S_LVPECL

3.3V

GND

Figure 47. LVPECL Output, Simplified Equivalent Circuit

OUT

07972-033

The LVPECL output polarity can be set as noninverting or inverting, which allows for the adjustment of the relative polarity of outputs within an application without requiring a board layout change. Each LVPECL output can be powered down or powered up as needed. Because of the architecture of the LVPECL output stages, there is the possibility of electrical overstress and breakdown under certain power-down conditions.

For this reason, the LVPECL outputs have several power-down modes. This includes a safe power-down mode that continues to protect the output devices while powered down, although it consumes somewhat more power than a total power-down. If the LVPECL output pins are terminated, it is best to select the safe power-down mode. If the pins are not connected (unused), it is acceptable to use the total power-down mode.

LVDS/CMOS Outputs—OUT6 to OUT9

OUT6 to OUT9 can be configured as either an LVDS differential output or as a pair of CMOS single-ended outputs. The LVDS outputs allow for selectable output current from ~1.75 mA to ~7 mA.

.5m

OUT

.5m

Figure 48. LVDS Output, Simplified Equivalent Circuit with

3.5 mA Typical Current Source

07972-034

The LVDS output polarity can be set as noninverting or inverting, which allows for the adjustment of the relative polarity of outputs within an application without requiring a board layout change. Each LVDS output can be powered down, if not needed, to save power.

OUT6 to OUT9 can also be CMOS outputs. Each LVDS output can be configured to be two CMOS outputs. This provides for up to eight CMOS outputs: OUT6A, OUT6B, OUT7A, OUT7B, OUT8A, OUT8B, OUT9A, and OUT9B. When an output is configured as CMOS, the CMOS Output A is automatically turned on. The CMOS Output B can be turned on or off independently. The relative polarity of the CMOS outputs can also be selected for any combination of inverting and noninverting. See Ta bl e 52 : Register 0x140[7:5], Register 0x141[7:5], Register 0x142[7:5], and Register 0x143[7:5].

Each LVDS/CMOS output can be powered down, as needed, to save power. The CMOS output power-down is controlled by the same bit that controls the LVDS power-down for that output. This power-down control affects both CMOS Output A and CMOS Output B. However, when CMOS Output A is powered up, CMOS Output B output can be powered on or off separately.

S

OUT1/ OUT1

07972-035

Figure 49. CMOS Equivalent Output Circuit

Rev. A | Page 42 of 76

AD9516-5

PD

RESET MODES

The AD9516 has several ways to force the chip into a reset condition that restores all registers to their default values and makes these settings active.

Power-On Reset—Start-Up Conditions When VS Is Applied

A power-on reset (POR) is issued when the VS power supply is turned on. The POR pulse duration is <100 ms and initializes the chip to the power-on conditions that are determined by the default register settings. These are indicated in the Default Value (Hex) column of Tab le 4 7. At power-on, the AD9516 also executes a SYNC operation, which brings the outputs into phase alignment according to the default settings. It is recommended that the user not toggle SCLK during the reset pulse.

Asynchronous Reset via the

An asynchronous hard reset is executed by momentarily pulling RESET

low. A reset restores the chip registers to the default settings. It is recommended that the user not toggle SCLK for 20 ns after RESET

goes high.

RESET

Soft Reset via Register 0x000[2]

A soft reset is executed by writing Register 0x000[2] and Register 0x000[5] = 1b. This bit is not self-clearing; therefore, it must be cleared by writing Register 0x000[2] and Register 0x000[2] = 0b to reset it and complete the soft reset operation. A soft reset restores the default values to the internal registers. The soft reset bit does not require an update registers command (Register 0x232 = 0x01) to be issued.

POWER-DOWN MODES

Chip Power-Down via PD

The AD9516 can be put into a power-down condition by pulling

PD

pin low. Power-down turns off most of the functions and

the currents inside the . The chip remains in this power-down state until wakes up, it returns to the settings programmed into its registers prior to the power-down, unless the registers are changed by new programming while the

PD

power-down shuts down the currents on the chip, except

The the bias current that is necessary to maintain the LVPECL outputs in a safe shutdown mode. This is needed to protect the LVPECL output circuitry from damage that can be caused by certain termination and load configurations when tristated. Because this is not a complete power-down, it can be called sleep mode.

AD9516

PD

is brought back to logic high. When the

PD

pin is held low.

AD9516

Rev. A | Page 43 of 76

When the AD9516 is in a following state:

The PLL is off (asynchronous power-down).

•

The CLK input buffer is off.

•

All dividers are off.

•

All LVDS/CMOS outputs are off.

•

All LVPECL outputs are in safe off mode.

•

The serial port is active and responds to commands.

If the AD9516 clock outputs must be synchronized to each other, a SYNC is required upon exiting power-down (see the Synchronizing the Outputs—SYNC Function section).

PLL Power-Down

The PLL section of the AD9516 can be selectively powered down. There are three PLL operating modes that are set by Register 0x010[1:0], as shown in Table 4 9.

In asynchronous power-down mode, the device powers down as soon as the registers are updated.

In synchronous power-down mode, the PLL power-down is gated by the charge pump to prevent unwanted frequency jumps. The device goes into power-down on the occurrence of the next charge pump event after the registers are updated.

Distribution Power-Down

The distribution section can be powered down by writing to Register 0x230[1] = 1b. This turns off the bias to the distribution section. If the LVPECL power-down mode is normal operation (00b), it is possible for a low impedance load on that LVPECL output to draw significant current during this power-down. If the LVPECL power-down mode is set to 11b, the LVPECL output is not protected from reverse bias and can be damaged under certain termination conditions.

Individual Clock Output Power-Down

Any of the clock distribution outputs can be powered down individually by writing to the appropriate registers. The register map details the individual power-down settings for each output. The LVDS/CMOS outputs can be powered down, regardless of their output load configuration.

The LVPECL outputs have multiple power-down modes (see Tabl e 53 ) that give some flexibility in dealing with the various output termination conditions. When the mode is set to 10b, the LVPECL output is protected from reverse bias to 2 VBE + 1 V. If the mode is set to 11b, the LVPECL output is not protected from reverse bias and can be damaged under certain termination conditions. This setting also affects the operation when the distribution block is powered down with 0x230[1] = 1b (see the Distribution Power-Down section).

Individual Circuit Block Power-Down

Other AD9516 circuit blocks (such as CLK, REF1, and REF2) can be powered down individually. This gives flexibility in configuring the part for power savings whenever certain chip functions are not needed.

power-down, the chip is in the

AD9516-5

SERIAL CONTROL PORT

The AD9516 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The

AD9516 serial control port is compatible with most synchronous

transfer formats, including both the Motorola SPI® and Intel® SSR® protocols. The serial control port allows read/write access to all registers that configure the AD9516. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The AD9516 serial control port can be configured for a single bidirectional I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO/SDO). By default, the AD9516 is in bidirectional mode, long instruction (long instruction is the only instruction mode supported).

SERIAL CONTROL PORT PIN DESCRIPTIONS

SCLK (serial clock) is the serial shift clock. This pin is an input. SCLK is used to synchronize serial control port reads and writes. Write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. This pin is internally pulled down by a 30 kΩ resistor to ground.

SDIO (serial data input/output) is a dual-purpose pin that acts as either an input only (unidirectional mode) or as both an input/ output (bidirectional mode). The AD9516 defaults to the bidirectional I/O mode (Register 0x000[0] = 0b).

SDO (serial data output) is used only in the unidirectional I/O mode (Register 0x000[0] = 1b) as a separate output pin for reading back data.

CS

(chip select bar) is an active low control that gates the read

and write cycles. When

CS

is high, SDO and SDIO are in a high impedance state. This pin is internally pulled up by a 30 kΩ resistor to VS.

16

SCLK

SDO

SDIO

Figure 50. Serial Control Port

CS

AD9516-5

17

SERIAL

21

CONTRO L

22

PORT

07972-036

GENERAL OPERATION OF SERIAL CONTROL PORT

A write or a read operation to the AD9516 is initiated by pulling

low.

CS

stall high is supported in modes where three or fewer bytes

CS of data (plus instruction data) are transferred (see ).

In these modes,

can temporarily return high on any byte

CS boundary, allowing time for the system controller to process the next byte.

can go high on byte boundaries only and during

CS

either part (instruction or data) of the transfer.

Table 4 2

During this period, the serial control port state machine enters a wait state until all data is sent. If the system controller decides to abort the transfer before all of the data is sent, the state machine must be reset, either by completing the remaining transfers or by returning the

(but less than eight SCLK cycles). Raising the

low for at least one complete SCLK cycle

CS

on a nonbyte

CS

boundary terminates the serial transfer and flushes the buffer.

In streaming mode (see Ta b l e 4 2 ), any number of data bytes can be transferred in a continuous stream. The register address is automatically incremented or decremented (see the MSB/LSB First Transfers section).

must be raised at the end of the last

CS

byte to be transferred, thereby ending the stream mode.

Communication Cycle—Instruction Plus Data

There are two parts to a communication cycle with the AD9516. The first part writes a 16-bit instruction word into the AD9516, coincident with the first 16 SCLK rising edges. The instruction word provides the AD9516 serial control port with information regarding the data transfer, which is the second part of the communication cycle. The instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer.

Write

If the instruction word is for a write operation, the second part is the transfer of data into the serial control port buffer of the

AD9516. Data bits are registered on the rising edge of SCLK.

The length of the transfer (1, 2, or 3 bytes or streaming mode) is indicated by two bits ([W1:W0]) in the instruction byte. When the transfer is 1, 2, or 3 bytes, but not streaming,

CS

can

be raised after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle). When the bus is stalled, the serial transfer resumes when

is lowered. Raising CS on

CS

a nonbyte boundary resets the serial control port. During a write, streaming mode does not skip over reserved or unused registers; therefore, the user must know the correct bit pattern to write to the reserved registers to preserve proper operation of the part. Refer to the register map (see ) to determine if the default

Tabl e 47 value for reserved registers is nonzero. It does not matter what data is written to blank or unused registers.

Because data is written into a serial control port buffer area, and not directly into the actual control registers of the AD9516, an additional operation is needed to transfer the serial control port buffer contents to the actual control registers of the AD9516, thereby causing them to become active. The update registers operation consists of setting Register 0x232[0] = 1b (this bit is selfclearing). Any number of bytes of data can be changed before executing an update registers. The update registers operation simultaneously actuates all register changes that have been written to the buffer since any previous update.

Rev. A | Page 44 of 76

AD9516-5

Read

If the instruction word is for a read operation, the next N × 8 SCLK cycles clock out the data from the address specified in the instruction word, where N is 1 to 3, as determined by [W1:W0]. If N = 4, the read operation is in streaming mode, continuing until

is raised. Streaming mode does not skip over reserved

CS

or blank registers. The readback data is valid on the falling edge of SCLK.

The default mode of the AD9516 serial control port is the bidirectional mode. In bidirectional mode, both the sent data and the readback data appear on the SDIO pin. It is also possible to set the AD9516 to unidirectional mode via the SDO active bit (Register 0x000[0] = 1b). In unidirectional mode, the readback data appears on the SDO pin.

A readback request reads the data that is in the serial control port buffer area, or the data that is in the active registers (see Figure 51). Readback of the buffer or active registers is controlled by Register 0x004[0].

The AD9516 supports only the long instruction mode; therefore, Register 0x000[4:3] must be set to 11b. (This register uses mirrored bits). Long instruction mode is the default at powerup or reset.

The AD9516 uses Register Address 0x000 to Register Address 0x232.

SCLK

SDIO

SDO

CS

SERIAL CONTROL PORT

WRITE RE GISTE R 0x232 = 0x01 TO UDATE REG ISTERS

Figure 51. Relationship Between Serial Control Port Buffer Registers and

Active Registers of the AD9516

UPDATE

REGISTERS

BUFFER REGI STERS

ACTIVE REGI STERS

07972-037

INSTRUCTION WORD (16 BITS)

The MSB of the instruction word is R/W, which indicates whether the instruction is a read or a write. The next two bits, [W1:W0], indicate the length of the transfer in bytes. The final 13 bits are the address ([A12:A0]) at which to begin the read or write operation.

For a write, the instruction word is followed by the number of bytes of data indicated by Bits[W1:W0], see Tab l e 4 2 .

Table 42. Byte Transfer Count

W1 W0 Bytes to Transfer

0 0 1 0 1 2 1 0 3 1 1 Streaming mode

The 13 bits found in Bits[A12:A0] select the address within the register map that is written to or read from during the data transfer portion of the communications cycle. Only Bits[A9:A0] are needed to cover the range of the 0x232 registers used by the

AD9516. Bits[A12:A10] must always be set to 0b. For multibyte

transfers, this address is the starting byte address. In MSB first mode, subsequent bytes decrement the address.

MSB/LSB FIRST TRANSFERS

The AD9516 instruction word and byte data can be MSB first or LSB first. Any data written to Register 0x000 must be mirrored; the upper four bits (Bits[7:4]) must mirror the lower four bits (Bits[3:0]). This makes it irrelevant whether LSB first or MSB first is in effect. As an example of this mirroring, see the default setting for this register: 0x000, which mirrors Bit 4 and Bit 3. This sets the long instruction mode (which is the default and the only mode that is supported).

The default for the AD9516 is MSB first.

When LSB first is set by Register 0x000[1] and Register 0x000[6], it takes effect immediately, because it affects only the operation of the serial control port and does not require that an update be executed.

When MSB first mode is active, the instruction and data bytes must be written from MSB to LSB. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes must follow, in order, from high address to low address. In MSB first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle.

When LSB first is active, the instruction and data bytes must be written from LSB to MSB. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The internal byte address generator of the serial control port increments for each byte of the multibyte transfer cycle.

The AD9516 serial control port register address decrements from the register address just written toward 0x000 for multibyte I/O operations if the MSB first mode is active (default). If the LSB first mode is active, the register address of the serial control port increments from the address just written toward Register 0x232 for multibyte I/O operations.

Streaming mode always terminates when it hits Address 0x232. Note that unused addresses are not skipped during multibyte I/O operations.

Table 43. Streaming Mode (No Addresses Are Skipped)

Write Mode Address Direction Stop Sequence

LSB first Increment 0x230, 0x231, 0x232, stop MSB first Decrement 0x001, 0x000, 0x232, stop

Rev. A | Page 45 of 76

AD9516-5

Table 44. Serial Control Port, 16-Bit Instruction Word, MSB First

MSB LSB

I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

R/W

CS

SCLK

DON'T CARE

W1 W0 A12 = 0 A11 = 0 A10 = 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

DON'T CARE

SDIO A12W0W1R/W A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

16-BIT INST RUCTION HEADE R REGISTE R (N) DATA RE GISTE R (N – 1) DATA

Figure 52. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data

CS

SCLK

DON'T CARE

SDIO

SDO

DON'T CARE

A12W0W1R/ W A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

REGISTER (N) DATA16-BIT INST RUCTION HEADER REGI STER (N – 1) DATA REGISTER (N – 2) DATA RE GISTE R (N – 3) DATA

Figure 53. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data

t

CS

SCLK

SDIO

DON'T CARE

t

DS

t

S

R/W

t

DH

W1W0A12A11A10A9A8A7A6A5D4D3D2D1D0

t

LOW

HIGH

t

SCLK

t

C

DON'T CARE

Figure 54. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements

CS

DON'T CARE

7972-040

7972-038

07972-039

SCLK

SDIO

CS

DON'T CARE

SCLK

t

DV

SDIO

SDO

DATA BIT N – 1DATA BIT N

07972-041

Figure 55. Timing Diagram for Serial Control Port Register Read

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 D1D0R/WW1W0 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

16-BIT INST RUCTION HEADE R REGISTE R (N) DATA REG ISTER ( N + 1) DATA

Figure 56. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data

Rev. A | Page 46 of 76

DON'T CARE

7972-042

AD9516-5

CS

SCLK

t

S

t

SCLK

t

HIGH

t

DS

t

DH

t

LOW

t

C

SDIO

BIT N BI T N + 1

Figure 57. Serial Control Port Timing—Write

Table 45. Serial Control Port Timing

Parameter Description

tDS Setup time between data and the rising edge of SCLK tDH Hold time between data and the rising edge of SCLK t

Period of the clock

CLK

tS tC t

Minimum period that SCLK should be in a logic high state

HIGH

t

Minimum period that SCLK should be in a logic low state

LOW

t

SCLK to valid SDIO and SDO (see Figure 55)

DV

Setup time between the CS falling edge and the SCLK rising edge (start of communication cycle) Setup time between the SCLK rising edge and the CS

rising edge (end of communication cycle)

07972-043

Rev. A | Page 47 of 76

AD9516-5

THERMAL PERFORMANCE

Table 46. Thermal Parameters for 64-Lead LFCSP

Symbol Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board Value (°C/W)

θJA Junction-to-ambient thermal resistance, natural convection per JEDEC JESD51-2 (still air) 22.0 θ

Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) 19.2

JMA

θ

Junction-to-ambient thermal resistance, 2.0 m/sec airflow per JEDEC JESD51-6 (moving air) 17.2

JMA

ΨJB

Junction-to-board characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air)

and JEDEC JESD51-8 θJC Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1 1.3 ΨJT Junction-to-top-of-package characterization parameter, natural convection per JEDEC JESD51-2 (still air) 0.1

The AD9516 is specified for a case temperature (T that T

is not exceeded, an airflow source can be used.

CASE

). To ensure

CASE

Use the following equation to determine the junction temperature on the application PCB:

T

= T

+ (ΨJT × PD)

J

CASE

where:

is the junction temperature (°C).

T

J

is the case temperature (°C) measured by the user at the

T

CASE

top center of the package.

is the value from Tabl e 46 .

Ψ

JT

Val u es o f θ design considerations. θ approximation of T

where T

Val u es o f θ

are provided for package comparison and PCB

JA

can be used for a first-order

JA

by the following equation:

J

T

= TA + (θJA × PD)

J

is the ambient temperature (°C).

A

are provided for package comparison and PCB

JC

design considerations when an external heat sink is required.

Val u es o f Ψ

are provided for package comparison and PCB

JB

design considerations.

PD is the power dissipation of the device (see Table 13.)

11.6

Rev. A | Page 48 of 76

AD9516-5

REGISTER MAPS

REGISTER MAP OVERVIEW

Register addresses that are not listed in Tab l e 4 7 (as well as ones marked unused) are not used and writing to those registers has no effect. The user should write the default value only to the register addresses marked reserved.

Table 47. Register Map Overview

Ref. Addr. (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

Serial Port Configuration

0x000 Serial port

configuration

0x001 Blank 0x002 Reserved 0x003 Part ID Part ID (read only) 0x01 0x004 Readback

control

PLL

0x010 PFD and

charge pump 0x011 R Counter 14-bit R divider, Bits[7:0] (LSB) 0x01 0x012 Blank 14-bit R divider, Bits[13:8] (MSB) 0x00 0x013 A counter Blank 6-bit A counter 0x00 0x014 B counter 13-bit B counter, Bits[7:0] (LSB) 0x03 0x015 Blank 13-bit B counter, Bits[12:8] (MSB) 0x00 0x016 PLL Control 1 Set CP pin

0x017 PLL Control 2 STATUS pin control Antibacklash pulse width 0x00 0x018 PLL Control 3 Reserved Lock detect counter Digital

0x019 PLL Control 4 R, A, B counters

0x01A PLL Control 5 Reserved Reference

0x01B PLL Control 6 CLK

0x01C PLL Control 7 Disable

0x01D PLL Control 8 Reserved PLL status

0x01E PLL Control 9 Reserved 0x00 0x01F PLL readback

(read-only)

0x020 to 0x04F

SDO active LSB first Soft reset Long

PFD polarity

Reset R

/2

to V

CP

SYNC

frequency monitor

switchover deglitch

counter

pin reset

frequency monitor threshold

REF2 ( frequency monitor

Select REF2

Reserved Holdover

REFIN

Charge pump current Charge pump mode PLL power-down 0x7D

Reset A and B counters

REF1 (REFIN) frequency

)

monitor

Use REF_SEL pin

active

instruction

Reset all counters

lock detect window

R path delay N path delay 0x00

register disable

REF2 selected

Long instruction

Blank Read back

B counter bypass

Disable digital lock detect

LD pin control 0x00

Reserved REF2

LD pin comparator enable

CLK frequency > threshold

Blank

Soft reset LSB first SDO active 0x18

active registers

Prescaler P 0x06

Reserved 0x06

REFMON pin control 0x00

power-on

Holdover enable

REF2 frequency > threshold

REF1 power-on

External holdover control

REF1 frequency > threshold

Differential reference

Holdover enable

Digital lock detect

Default Value (Hex)

0x00

N/A

Rev. A | Page 49 of 76

AD9516-5

Ref. Addr. (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

Fine Delay Adjust—OUT6 to OUT9

0x0A0 OUT6 delay

0x0A1 OUT6 delay

0x0A2 OUT6 delay

0x0A3 OUT7 delay

0x0A4 OUT7 delay

0x0A5 OUT7 delay

0x0A6 OUT8 delay

0x0A7 OUT8 delay

0x0A8 OUT8 delay

0x0A9 OUT9 delay

0x0AA OUT9 delay

0x0AB OUT9 delay

0x0AC to 0x0EF

LVPECL Outputs

0x0F0 OUT0 Blank OUT0

0x0F1 OUT1 Blank OUT1

0x0F2 OUT2 Blank OUT2

0x0F3 OUT3 Blank OUT3

0x0F4 OUT4 Blank OUT4

0x0F5 OUT5 Blank OUT5

0x0F6 to 0x13F

LVDS/CMOS Outputs

0x140 OUT6 OUT6 CMOS

0x141 OUT7 OUT7 CMOS

0x142 OUT8 OUT8 CMOS

0x143 OUT9 OUT9 CMOS

0x144 to 0x18F

bypass

Blank OUT6 ramp capacitors OUT6 ramp current 0x00

full-scale

Blank OUT6 delay fraction 0x00

fraction

bypass

Blank OUT7 ramp capacitors OUT7 ramp current 0x00

full-scale

Blank OUT7 delay fraction 0x00

fraction

bypass

Blank OUT8 ramp capacitors OUT8 ramp current 0x00

full-scale

Blank OUT8 delay fraction 0x00

fraction

bypass

Blank OUT9 ramp capacitors OUT9 ramp current 0x00

full-scale

Blank OUT9 delay fraction 0x00

fraction

output polarity

Blank OUT6 delay

Blank OUT7 delay

Blank OUT8 delay

Blank OUT9 delay

Blank

invert

OUT6 CMOS B

OUT7 CMOS B

OUT8 CMOS B

OUT9 CMOS B

Blank

OUT0 LVPECL

differential voltage

OUT1 LVPECL

differential voltage

OUT2 LVPECL

differential voltage

OUT3 LVPECL

differential voltage

OUT4 LVPECL

differential voltage

OUT5 LVPECL

differential voltage

OUT6 select LVDS/CMOS

OUT7 select LVDS/CMOS

OUT8 select LVDS/CMOS

OUT9 select LVDS/CMOS

OUT6 LVDS

output current

OUT7 LVDS

output current

OUT8 LVDS

output current

OUT9 LVDS

output current

OUT0 power-down 0x08

OUT1 power-down 0x0A

OUT2 power-down 0x08

OUT3 power-down 0x0A

OUT4 power-down 0x08

OUT5 power-down 0x0A

bypass

OUT6 power-down

OUT7 power-down

OUT8 power-down

OUT9 power-down

Default Value (Hex)

0x01

0x42

0x43

0x42

0x43

Rev. A | Page 50 of 76

AD9516-5

Ref. Addr.

(Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

LVPECL Channel Dividers

0x190 Divider 0 0x191 Divider 0

0x192 Blank Divider 0

0x193 Divider 1 0x194 Divider 1

0x195 Blank Divider 1

0x196 Divider 2 0x197 Divider 2

0x198 Blank Divider 2

LVDS/CMOS Channel Dividers

0x199 Divider 3

0x19A Phase Offset Divider 3.2 Phase Offset Divider 3.1 0x00 0x19B Low Cycles Divider 3.2 High Cycles Divider 3.2 0x11 0x19C Reserved Bypass

0x19D Blank Divider 3

0x19E Divider 4 0x19F Phase Offset Divider 4.2 Phase Offset Divider 4.1 0x00 0x1A0 Low Cycles Divider 4.2 High Cycles Divider 4.2 0x11 0x1A1 Reserved Bypass

0x1A2 Blank Divider 4

0x1A3 Reserved (read-only) 0x1A4

to 0x1DF

VCO Divider and CLK Input

0x1E0 VCO divider Blank VCO divider 0x02 0x1E1 Input CLKs Reserved Power-

0x1E2 to 0x22A

System

0x230 Power-down

0x231 Blank 0x00

Update All Registers

0x232 Update all

(PECL)

bypass

(PECL)

bypass

(PECL)

bypass

(LVDS/CMOS)

and SYNC

registers

Divider 0 low cycles Divider 0 high cycles 0x00

Divider 0 nosync

Divider 1 low cycles Divider 1 high cycles 0xBB

Divider 1 nosync

Divider 2 low cycles Divider 2 high cycles 0x00

Divider 2 nosync

Low Cycles Divider 3.1 High Cycles Divider 3.1 0x22

Low Cycles Divider 4.1 High Cycles Divider 4.1 0x22

Divider 0 force high

Divider 1 force high

Divider 2 force high

Divider 3.2

Divider 4.2

Reserved Power-

Divider 0 start high

Divider 1 start high

Divider 2 start high

Bypass Divider 3.1

Bypass Divider 4.1

down clock input section

Blank Update all

Divider 3 nosync

Divider 4 nosync

Blank

Divider 0 phase offset 0x80

direct to output

Divider 1 phase offset 0x00

direct to output

Divider 2 phase offset 0x00

direct to output

Divider 3 force high

Divider 4 force high

Reserved Bypass

down SYNC

Start High Divider 3.2

Start High Divider 4.2

Powerdown distribution reference

Divider 0 DCCOFF

Divider 1 DCCOFF

Divider 2 DCCOFF

Start High Divider 3.1

DCCOFF

Start High Divider 4.1

DCCOFF

VCO divider

Soft SYNC 0x00

registers (self-clearing)

Default Value (Hex)

0x00

Rev. A | Page 51 of 76

AD9516-5

REGISTER MAP DESCRIPTIONS

Tabl e 48 through Ta b le 5 7 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal address. A range of bits (for example, from Bit 5 through Bit 2) is indicated using a colon and brackets, as follows: [5:2].

Table 48. Serial Port Configuration

Reg. Addr. (Hex)

0x000 [7:4] Mirrored, Bits[3:0]

Bit 7 = Bit 0. Bit 6 = Bit 1. Bit 5 = Bit 2. Bit 4 = Bit 3. 3 Long instruction

0: 8-bit instruction (short). 1: 16-bit instruction (long) (default). 2 Soft reset Soft reset.

1 LSB first MSB or LSB data orientation. 0: data-oriented MSB first; addressing decrements (default). 1: data-oriented LSB first; addressing increments. 0 SDO active Selects unidirectional or bidirectional data transfer mode. 0: SDIO pin used for write and read; SDO set to high impedance; bidirectional mode (default). 1: SDO used for read, SDIO used for write; unidirectional mode. 0x003 [7:0] Part ID (read only) Uniquely identifies the dash version (-0 through -5) of the AD9516. AD9516-0: 0x01. AD9516-1: 0x41. AD9516-2: 0x81. AD9516-3: 0x43. AD9516-4: 0xC3. AD9516-5: 0xC1. 0x004 0 Read back active registers Selects register bank used for a readback. 0: reads back buffer registers (default). 1: reads back active registers.

Bits Name Description

Bits[7:4] should always mirror Bits[3:0], so that it does not matter whether the part is in MSB or LSB first mode (see Bit 1, Register 0x000). The user should set the bits as follows:

Short/long instruction mode. This part uses long instruction mode only, so this bit should always be set to 1b.

1: soft reset; restores default values to internal registers. Not self-clearing. Must be cleared to 0b to complete reset operation.

Rev. A | Page 52 of 76

AD9516-5

Table 49. PLL

Reg. Addr. (Hex) Bits Name Description

0x010 7 PFD polarity Sets the PFD polarity. 0: positive; higher control voltage produces higher frequency (default). 1: negative; higher control voltage produces lower frequency. [6:4] CP current Charge pump current (with CPRSET = 5.1 kΩ).

0 0 0 0.6 0 0 1 1.2 0 1 0 1.8 0 1 1 2.4 1 0 0 3.0 1 0 1 3.6 1 1 0 4.2 1 1 1 4.8 (default) [3:2] CP mode Charge pump operating mode.

0 0 High impedance state 0 1 Force source current (pump up) 1 0 Force sink current (pump down) 1 1 Normal operation (default) [1:0] PLL power-down PLL operating mode.

0 0 Normal operation 0 1 Asynchronous power-down (default) 1 0 Normal operation 1 1 Synchronous power-down 0x011 [7:0] 14-bit R divider,

0x012 [5:0] 14-bit R divider,

0x013 [5:0] 6-bit A counter A counter (part of N divider) (default = 0x00). 0x014 [7:0] 13-bit B counter,

0x015 [4:0] 13-bit B counter,

0x016 7 Set CP pin 0: CP normal operation (default). 1: CP pin set to VCP/2. 6 Reset R counter Resets R counter (R divider). This bit is not self-clearing. 0: normal (default). 1: holds the R counter in reset. 5 Reset A and B 0: normal (default). This bit is not self-clearing. 1: holds the A and B counters in reset. 4 Reset all counters Resets R, A, and B counters. This bit is not self-clearing. 0: normal (default). 1: holds the R, A, and B counters in reset. 3 B counter bypass B counter bypass. This is valid only when operating the prescaler in FD mode. 0: normal (default). 1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.

Bits[7:0] (LSB)

Bits[13:8] (MSB)

Bits[7:0] (LSB)

Bits[12:8] (MSB)

to V

/2

CP

counters

6 5 4 ICP (mA)

3 2 Charge Pump Mode

1 0 Mode

R divider LSBs—lower eight bits (default = 0x01).

R divider MSBs—upper six bits (default = 0x00).

B counter (part of N divider)—lower eight bits (default = 0x03).

B counter (part of N divider)—upper five bits (default = 0x00).

Sets the CP pin to one-half of the V

Resets A and B counters (part of N divider).

supply voltage.

CP

Rev. A | Page 53 of 76

AD9516-5

Reg. Addr. (Hex)

[2:0] Prescaler P Prescaler. DM = dual modulus, and FD = fixed divide.

0 0 0 FD Divide-by-1 0 0 1 FD Divide-by-2 0 1 0 DM Divide-by-2 (2/3 mode) 0 1 1 DM Divide-by-4 (4/5 mode) 1 0 0 DM Divide-by-8 (8/9 mode) 1 0 1 DM Divide-by-16 (16/17 mode) 1 1 0 DM Divide-by-32 (22/23 mode) (default) 1 1 1 FD Divide-by-3 0x017 [7:2] Selects the STATUS pin signal.

0 0 0 0 0 0 LVL Ground (dc) (default) 0 0 0 0 0 1 DYN N divider output (after the delay) 0 0 0 0 1 0 DYN R divider output (after the delay) 0 0 0 0 1 1 DYN A divider output 0 0 0 1 0 0 DYN Prescaler output 0 0 0 1 0 1 DYN PFD up pulse 0 0 0 1 1 0 DYN PFD down pulse 0 X X X X X LVL Ground (dc); for all other cases of 0x0XXXX not specified The selections that follow are the same as for REFMON: 1 0 0 0 0 0 LVL Ground (dc) 1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode) 1 0 0 0 1 0 DYN REF2 clock (not available in differential mode) 1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode) 1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode) 1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high 1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high 1 0 0 1 1 1 LVL Status of REF1 frequency (active high) 1 0 1 0 0 0 LVL Status of REF2 frequency (active high) 1 0 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency) 1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of CLK) 1 0 1 0 1 1 LVL Status of CLK frequency (active high) 1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2) 1 0 1 1 0 1 LVL Digital lock detect (DLD); active high 1 0 1 1 1 0 LVL Holdover active (active high) 1 0 1 1 1 1 LVL LD pin comparator output (active high) 1 1 0 0 0 0 LVL VS (PLL supply) 1 1 0 0 0 1 DYN REF1 clock

1 1 0 0 1 0 DYN REF2 clock

1 1 0 0 1 1 DYN Selected reference to PLL

1 1 0 1 0 0 DYN Unselected reference to PLL

1 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low 1 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low 1 1 0 1 1 1 LVL Status of REF1 frequency (active low) 1 1 1 0 0 0 LVL Status of REF2 frequency (active low) 1 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency)

1 1 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of CLK)

1 1 1 0 1 1 LVL Status of CLK Frequency (active low) 1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1) 1 1 1 1 0 1 LVL Digital lock detect (DLD) (active low) 1 1 1 1 1 0 LVL Holdover active (active low) 1 1 1 1 1 1 LVL LD pin comparator output (active low)

Bits Name Description

2 1 0 Mode Prescaler

STATUS pin control

7 6 5 4 3 2

Level or Dynamic Signal

Signal at STATUS Pin

(differential reference when in differential mode)

(not available in differential mode)

(differential reference when in differential mode)

(not available when in differential mode)

Rev. A | Page 54 of 76

AD9516-5

Reg. Addr. (Hex)

[1:0] 0 0 2.9 (default) 0 1 1.3 1 0 6.0

0x018 [6:5] Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked

0 0 5 (default) 0 1 16 1 0 64

4 If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital

0: high range (default).

3 Digital lock detect operation. 0: normal lock detect operation (default).

0x019 [7:6] 0 0

0 1 Asynchronous reset 1 0 Synchronous reset

[5:3] R path delay R path delay (default = 0x0); see Table 2. [2:0] N path delay N path delay (default = 0x0); see Table 2.

Bits Name Description

Antibacklash pulse width

Lock detect counter

Digital lock detect window

Disable digital lock detect

R, A, B counters SYNC

pin reset

1 0 Antibacklash Pulse Width (ns)

1 1 2.9

condition.

6 5 PFD Cycles to Determine Lock

1 1 255

lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.

1: low range.

1: disables lock detect.

7 6 Action

Does nothing on

1 1

Does nothing on

SYNC

(default)

Rev. A | Page 55 of 76

AD9516-5

Reg. Addr. (Hex) Bits Name Description

0x01A 6 Reference

0: frequency valid if frequency is above the higher frequency threshold (default). 1: frequency valid if frequency is above the lower frequency threshold. [5:0] LD pin control Selects the LD pin signal.

0 0 0 0 0 0 LVL Digital lock detect (high = lock, low = unlock) (default) 0 0 0 0 0 1 DYN P-channel, open-drain lock detect (analog lock detect) 0 0 0 0 1 0 DYN N-channel, open-drain lock detect (analog lock detect) 0 0 0 0 1 1 HIZ High-Z LD pin 0 0 0 1 0 0 CUR Current source lock detect (110 μA when DLD is true) 0 X X X X X LVL Ground (dc); for all other cases of 0x0XXXX not specified The selections that follow are the same as for REFMON: 1 0 0 0 0 0 LVL Ground (dc) 1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode) 1 0 0 0 1 0 DYN REF2 clock (not available in differential mode) 1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode) 1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode) 1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high 1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high 1 0 0 1 1 1 LVL Status of REF1 frequency (active high) 1 0 1 0 0 0 LVL Status of REF2 frequency (active high) 1 0 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency) 1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of CLK) 1 0 1 0 1 1 LVL Status of CLK frequency (active high) 1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2) 1 0 1 1 0 1 LVL Digital lock detect (DLD); active high 1 0 1 1 1 0 LVL Holdover active (active high) 1 0 1 1 1 1 LVL Not available; do not use 1 1 0 0 0 0 LVL VS (PLL supply) 1 1 0 0 0 1 DYN REF1 clock

1 1 0 0 1 0 DYN REF2 clock

1 1 0 0 1 1 DYN Selected reference to PLL

1 1 0 1 0 0 DYN Unselected reference to PLL

1 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low 1 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low 1 1 0 1 1 1 LVL Status of REF1 frequency (active low) 1 1 1 0 0 0 LVL Status of REF2 frequency (active low) 1 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency)

1 1 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of CLK)

1 1 1 0 1 1 LVL Status of CLK frequency (active low) 1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1) 1 1 1 1 0 1 LVL Digital lock detect (DLD); active low 1 1 1 1 1 0 LVL Holdover active (active low) 1 1 1 1 1 1 LVL Not available; do not use 0x01B 7 CLK frequency 0: disables CLK frequency monitor (default). 1: enables CLK frequency monitor. 6 0: disables REF2 frequency monitor (default). 1: enables REF2 frequency monitor. 5 REF1 (REFIN)

0: disables REF1 (REFIN) frequency monitor (default). 1: enables REF1 (REFIN) frequency monitor.

frequency monitor threshold

monitor

REFIN

REF2 ( frequency monitor

frequency monitor

Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the CLK frequency monitor’s detection threshold (see Table 12: REF1, REF2, and CLK frequency status monitor parameter).

Level or

5 4 3 2 1 0

Enables or disables CLK frequency monitor.

Enables or disables REF2 frequency monitor.

)

REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs (as selected by differential reference mode).

Dynamic Signal Signal at LD Pin

(differential reference when in differential mode)

(not available in differential mode)

(differential reference when in differential mode)

(not available when in differential mode)

Rev. A | Page 56 of 76

AD9516-5

Reg. Addr. (Hex)

[4:0] Selects the signal that is connected to the REFMON pin.

0 0 0 0 0 LVL Ground (dc) (default) 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode) 0 0 0 1 0 DYN REF2 clock (not available in differential mode) 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode) 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode) 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high 0 0 1 1 1 LVL Status of REF1 frequency (active high) 0 1 0 0 0 LVL Status of REF2 frequency (active high) 0 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency) 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of CLK) 0 1 0 1 1 LVL Status of CLK frequency (active high) 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2) 0 1 1 0 1 LVL Digital lock detect (DLD); active low 0 1 1 1 0 LVL Holdover active (active high) 0 1 1 1 1 LVL LD pin comparator output (active high) 1 0 0 0 0 LVL VS (PLL supply) 1 0 0 0 1 DYN REF1 clock

1 0 0 1 0 DYN REF2 clock

1 0 0 1 1 DYN Selected reference to PLL

1 0 1 0 0 DYN Unselected reference to PLL

1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low 1 0 1 1 1 LVL Status of REF1 frequency (active low) 1 1 0 0 0 LVL Status of REF2 frequency (active low) 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency)

1 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of CLK)

1 1 0 1 1 LVL Status of CLK frequency (active low) 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1) 1 1 1 0 1 LVL Digital lock detect (DLD); active low 1 1 1 1 0 LVL Holdover active (active low) 1 1 1 1 1 LVL LD pin comparator output (active low) 0x01C 7 Disables or enables the switchover deglitch circuit. 0: enables switchover deglitch circuit (default).

6 Select REF2 If Register 0x01C[5] = 0, selects reference for PLL. 0: select REF1 (default). 1: select REF2. 5 Use REF_SEL pin If Register 0x01C[4] = 0 (manual), sets method of PLL reference selection. 0: uses Register 0x01C[6] (default). 1: uses REF_SEL pin. 4 Reserved 0: default. 3 Reserved 0: default. 2 This bit turns the REF2 power on. 0: REF2 power off (default).

1 This bit turns the REF1 power on. 0: REF1 power off (default).

0 Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the automatic

0: single-ended reference mode (default).

Bits Name Description

REFMON pin control

4 3 2 1 0

Disable switchover deglitch

REF2 power-on

REF1 power-on

Differential reference

1: disables switchover deglitch circuit.

1: REF2 power on.

1: REF1 power on.

reference switchover or REF1 and REF2 to work.

1: differential reference mode.

Level or Dynamic Signal

Signal at REFMON Pin

Rev. A | Page 57 of 76

(differential reference when in differential mode)

(not available in differential mode)

(differential reference when in differential mode)

(not available when in differential mode)

AD9516-5

Reg. Addr. (Hex)

0x01D 4 Disables the PLL status register readback. 0: PLL status register enable (default).

3 Enables the LD pin voltage comparator. This function is used with the LD pin current source lock detect mode. When in

0: disables LD pin comparator; internal/automatic holdover controller treats this pin as true/high (default).

2 Along with Register 0x01D[0], enables the holdover function. 0: holdover disabled (default).

1

0: automatic holdover mode—holdover controlled by automatic holdover circuit (default).

0 Along with Register 0x01D[2], enables the holdover function. 0: holdover disabled (default).

0x01F 5 Holdover active

4 Read-only register. Indicates which PLL reference is selected as the input to the PLL. 0: REF1 selected (or differential reference if in differential mode).

3 Read-only register. Indicates if the CLK frequency is greater than the threshold (see Table 12: REF1, REF2, and CLK

0: CLK frequency is less than the threshold.

Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by

0: REF2 frequency is less than threshold frequency.

1 Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by

0: REF1 frequency is less than threshold frequency.

0 Read-only register. Digital lock detect. 0: PLL is not locked.

Bits Name Description

PLL status register disable

1: PLL status register disable.

LD pin comparator enable

Holdover enable

External holdover control

Holdover enable

REF2 selected

CLK frequency > threshold

2 REF2

frequency > threshold

REF1 frequency > threshold

Digital lock detect

the internal (automatic) holdover mode, this function enables the use of the voltage on the LD pin to determine if the PLL was previously in a locked state (see Figure 41). Otherwise, this function can be used with the REFMON and STATUS pins to monitor the voltage on the LD pin.

1: enables LD pin comparator.

1: holdover enabled. Enables the external hold control through the

1: external holdover mode—holdover controlled by

1: holdover enabled. Read-only register. Indicates if the part is in the holdover state (see Figure 41). This is not the same as holdover enabled. 0: not in holdover. 1: holdover state active.

1: REF2 selected.

frequency status monitor).

1: CLK frequency is greater than the threshold.

Register 0x01A[6].

1: REF2 frequency is greater than threshold frequency.

Register 0x01A[6].

1: REF1 frequency is greater than threshold frequency.

1: PLL is locked.

SYNC

pin. (This disables the internal holdover mode.)

SYNC

pin.

Rev. A | Page 58 of 76

AD9516-5

Table 50. Fine Delay Adjust—OUT6 to OUT9

Reg. Addr. (Hex)

0x0A0 0 Bypasses or uses the delay function. 0: uses the delay function.

0x0A1 [5:3]

0 0 0 4 (default) 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 [2:0]

0 0 0 200 (default) 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 0x0A2 [5:0]

0x0A3 0 Bypasses or uses the delay function. 0: uses the delay function.

0x0A4 [5:3]

0 0 0 4 (default) 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1

B

its Name Description

OUT6 delay bypass

1: bypasses the delay function (default).

OUT6 ramp capacitors

OUT6 ramp current

OUT6 delay fraction

OUT7 delay bypass

OUT7 ramp capacitors

Selects the number of ramp capacitors used by the delay function. The combination of the number of capacitors and the ramp current sets the full-scale delay.

5 4 3 Number of Capacitors

Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the full-scale delay.

2 1 0 Current (μA)

Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000b gives zero delay. Only delay values of up to 47 decimals (101111b; 0x02F) are supported (default: 0x00).

1: bypasses the delay function (default). Selects the number of ramp capacitors used by the delay function. The combination of the number of the

capacitors and the ramp current sets the full-scale delay.

5 4 3 Number of Capacitors

Rev. A | Page 59 of 76

AD9516-5

Reg. Addr. (Hex) Bits Name Description

0x0A4 [2:0]

0 0 0 200 (default) 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 0x0A5 [5:0]

0x0A6 0 Bypasses or uses the delay function. 0: uses the delay function.

0x0A7 [5:3]

0 0 0 4 (default) 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 [2:0]

0 0 0 200 (default) 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 0x0A8 [5:0]

0x0A9 [0] Bypasses or uses the delay function. 0: uses the delay function.

OUT7 ramp current

OUT7 delay fraction

OUT8 delay bypass

OUT8 ramp capacitors

OUT8 ramp current

OUT8 delay fraction

OUT9 delay bypass

Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the full-scale delay.

2 1 0 Current (μA)

Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000b gives zero delay. Only delay values of up to 47 decimals (101111b; 0x02F) are supported (default: 0x00).

1: bypasses the delay function (default). Selects the number of ramp capacitors used by the delay function. The combination of the number of

capacitors and the ramp current sets the full-scale delay.

5 4 3 Number of Capacitors

Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the full-scale delay.

2 1 0 Current (μA)

Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000b gives zero delay. Only delay values of up to 47 decimals (101111b; 0x02F) are supported (default: 0x00).

1: bypasses the delay function (default).

Rev. A | Page 60 of 76

AD9516-5

Reg. Addr. (Hex) Bits Name Description

0x0AA [5:3]

0 0 0 4 (default) 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 [2:0]

0 0 0 200 (default) 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 0x0AB [5:0]

OUT9 ramp capacitors

OUT9 ramp current

OUT9 delay fraction

Selects the number of ramp capacitors used by the delay function. The combination of the number of capacitors and the ramp current sets the full-scale delay.

5 4 3 Number of Capacitors

Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the full-scale delay.

2 1 0 Current Value (μA)

Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000b gives zero delay. Only delay values of up to 47 decimals (101111b; 0x02F) are supported (default: 0x00).

Table 51. LVPECL Outputs

Reg. Addr. (Hex) Bits Name Description

0x0F0 4 OUT0 invert Sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] Sets the LVPECL output differential voltage (VOD).

0 0 400 0 1 600 1 0 780 (default)

[1:0] LVPECL power-down modes.

0 0 Normal operation (default) On 0 1 Partial power-down, reference on; use only if there are no external load resistors Off 1 0 Partial power-down, reference on; safe LVPECL power-down Off

OUT0 LVPECL differential voltage

OUT0 power-down

3 2 VOD (mV)

1 1 960

1 0 Mode Output

1 1 Total power-down, reference off; use only if there are no external load resistors Off

Rev. A | Page 61 of 76

AD9516-5

Reg. Addr. (Hex) Bits Name Description

0x0F1 4 Sets the output polarity. 0: noninverting (default).

[3:2] Sets the LVPECL output differential voltage (VOD). 3 2 VOD (mV) 0 0 400 0 1 600 1 0 780 (default)

[1:0] LVPECL power-down modes. 1 0 Mode Output 0 0 Normal operation On 0 1 Partial power-down, reference on; use only if there are no external load resistors Off 1 0 Partial power-down, reference on; safe LVPECL power-down (default) Off

0x0F2 4 Sets the output polarity. 0: noninverting (default).

[3:2] Sets the LVPECL output differential voltage (VOD). 3 2 VOD (mV) 0 0 400 0 1 600 1 0 780 (default)

[1:0] LVPECL power-down modes. 1 0 Mode Output 0 0 Normal operation (default) On 0 1 Partial power-down, reference on; use only if there are no external load resistors Off 1 0 Partial power-down, reference on, safe LVPECL power-down Off

0x0F3 4 Sets the output polarity. 0: noninverting (default).

[3:2] Sets the LVPECL output differential voltage (VOD). 3 2 VOD (mV) 0 0 400 0 1 600 1 0 780 (default)

[1:0] LVPECL power-down modes.

0 0 Normal operation On 0 1 Partial power-down, reference on; use only if there are no external load resistors Off 1 0 Partial power-down, reference on, safe LVPECL power-down (default) Off 1 1 Total power-down, reference off; use only if there are no external load resistors Off

OUT1 invert

OUT1 LVPECL differential voltage

OUT1 power-down

OUT2 invert

OUT2 LVPECL differential voltage

OUT2 power-down

OUT3 invert

OUT3 LVPECL differential voltage

OUT3 power-down

1: inverting.

1 1 960

1 1 Total power-down, reference off; use only if there are no external load resistors Off

1: inverting.

1 1 960

1 1 Total power-down, reference off; use only if there are no external load resistors Off

1: inverting.

1 1 960

1 0 Mode Output

Rev. A | Page 62 of 76

AD9516-5

Reg. Addr. (Hex) Bits Name Description

0x0F4 4 Sets the output polarity. 0: noninverting (default).

[3:2] Sets the LVPECL output differential voltage (VOD). 3 2 VOD (mV) 0 0 400 0 1 600 1 0 780 (default)

[1:0] LVPECL power-down modes. 1 0 Mode Output 0 0 Normal operation On 0 1 Partial power-down, reference on; use only if there are no external load resistors Off 1 0 Partial power-down, reference on, safe LVPECL power-down Off

0x0F5 4 Sets the output polarity. 0: noninverting (default).

[3:2] Sets the LVPECL output differential voltage (VOD). 3 2 VOD (mV) 0 0 400 0 1 600 1 0 780 (default)

[1:0]

OUT4 invert

OUT4 LVPECL differential voltage

OUT4 power-down

OUT5 invert

OUT5 LVPECL differential voltage

OUT5 power-down

1: inverting.

1 1 960

1 1 Total power-down, reference off; use only if there are no external load resistors Off

1: inverting.

1 1 960 LVPECL power-down modes.

1 0 Mode Output

0 0 Normal operation On 0 1 Partial power-down, reference on; use only if there are no external load resistors Off 1 0 Partial power-down, reference on, safe LVPECL power-down (default) Off 1 1 Total power-down, reference off; use only if there are no external load resistors Off

Rev. A | Page 63 of 76

AD9516-5

Table 52. LVDS/CMOS Outputs

Reg. Addr. (Hex)

0x140 [7:5] OUT6 output polarity

0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting (default) 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 0 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 4 OUT6 CMOS B In CMOS mode, turns on/off the CMOS B output. This has no effect in LVDS mode. 0: turns off the CMOS B output (default). 1: turns on the CMOS B output. 3 OUT6 select LVDS/CMOS Selects LVDS or CMOS logic levels. 0: LVDS (default). 1: CMOS. [2:1] OUT6 LVDS output current Sets output current level in LVDS mode. This has no effect in CMOS mode.

0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7 50 0 OUT6 power-down Power-down output (LVDS/CMOS). 0: powers on (default). 1: powers off. 0x141 [7:5] OUT7 output polarity

0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting (default) 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 0 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 4 OUT7 CMOS B In CMOS mode, turns on/off the CMOS B output. This has no effect in LVDS mode. 0: turns off the CMOS B output (default). 1: turns on the CMOS B output. 3 OUT7 select LVDS/CMOS Selects LVDS or CMOS logic levels. 0: LVDS (default). 1: CMOS. [2:1] OUT7 LVDS output current Sets output current level in LVDS mode. This has no effect in CMOS mode.

0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7 50

Bits Name Description

In CMOS mode, Bits[7:5] select the output polarity of each CMOS output. In LVDS mode, only Bit 5 determines LVDS polarity.

7 6 5 OUT6A (CMOS) OUT6B (CMOS) OUT6 (LVDS)

2 1 Current (mA) Recommended Termination (Ω)

In CMOS mode, Bits[7:5] select the output polarity of each CMOS output. In LVDS mode, only Bit 5 determines LVDS polarity.

7 6 5 OUT7A (CMOS) OUT7B (CMOS) OUT7 (LVDS)

2 1 Current (mA) Recommended Termination (Ω)

Rev. A | Page 64 of 76

AD9516-5

Reg. Addr. (Hex) Bits Name Description

0 OUT7 power-down Power-down output (LVDS/CMOS). 0: powers on. 1: powers off (default). 0x142 [7:5] OUT8 output polarity

0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting (default) 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 0 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 4 OUT8 CMOS B In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode. 0: turns off the CMOS B output (default). 1: turns on the CMOS B output. 3 OUT8 select LVDS/CMOS Selects LVDS or CMOS logic levels. 0: LVDS (default). 1: CMOS. [2:1] OUT8 LVDS output current Sets output current level in LVDS mode. This has no effect in CMOS mode.

0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7 50 0 OUT8 power-down Power-down output (LVDS/CMOS). 0: powers on (default). 1: powers off. 0x143 [7:5] OUT9 output polarity

0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting (default) 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 0 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 4 OUT9 CMOS B In CMOS mode, turns on/off the CMOS B output. This has no effect in LVDS mode. 0: turns off the CMOS B output (default). 1: turns on the CMOS B output. 3 OUT9 select LVDS/CMOS Selects LVDS or CMOS logic levels. 0: LVDS (default). 1: CMOS.

In CMOS mode, Bits[7:5] select the output polarity of each CMOS output. In LVDS mode, only Bit 5 determines LVDS polarity.

7 6 5 OUT8A (CMOS) OUT8B (CMOS) OUT8 (LVDS)

2 1 Current (mA) Recommended Termination (Ω)

In CMOS mode, Bits[7:5] select the output polarity of each CMOS output. In LVDS mode, only Bit 5 determines LVDS polarity.

7 6 5 OUT9A (CMOS) OUT9B (CMOS) OUT9 (LVDS)

Rev. A | Page 65 of 76

AD9516-5

Reg. Addr. (Hex) Bits Name Description

[2:1] OUT9 LVDS output current Sets output current level in LVDS mode. This has no effect in CMOS mode.

0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7 50 [0] OUT9 power-down Power-down output (LVDS/CMOS). 0: powers on. 1: powers off (default).

Table 53. LVPECL Channel Dividers

Reg. Addr. (Hex) Bits Name Description

0x190 [7:4] Divider 0 low cycles

[3:0] Divider 0 high cycles

0x191 7 Divider 0 bypass Bypasses and powers down the divider; routes input to the divider output. 0: uses the divider. 1: bypasses the divider (default). 6 Divider 0 nosync No sync. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. 5 Divider 0 force high

0: normal operation (default). 1: divider output forced to the setting of the Divider 0 start high bit. 4 Divider 0 start high Selects clock output to start high or start low. 0: starts low (default). 1: starts high. [3:0] Divider 0 phase offset Phase offset (default: 0x0). 0x192 1 Divider 0 direct to output Connects OUT0 and OUT1 to Divider 0 or directly to CLK input. 0: OUT0 and OUT1 are connected to Divider 0 (default).

0 Divider 0 DCCOFF Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. 0x193 [7:4] Divider 1 low cycles

[3:0] Divider 1 high cycles

0x194 7 Divider 1 bypass Bypasses and powers down the divider; routes input to divider output. 0: uses divider (default). 1: bypasses divider. 6 Divider 1 nosync No sync. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal.

2 1 Current (mA) Recommended Termination (Ω)

Number of clock cycles (minus 1) of the Divider 0 input during which the Divider 0 output stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).

Number of clock cycles (minus 1) of the Divider 0 input during which the Divider 0 output stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).

Forces divider output to high. This operation requires that the Divider 0 nosync bit (Bit 6) also be set. This bit has no effect if the Divider 0 bypass bit (Bit 7) is set.

1: If Register 0x1E1[0] = 0b, the CLK is routed directly to OUT0 and OUT1. If Register 0x1E1[0] = 1b, there is no effect.

Number of clock cycles (minus 1) of the Divider 1 input during which the Divider 1 output stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0xB).

Number of clock cycles (minus 1) of the Divider 1 input during which the Divider 1 output stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0xB).

Rev. A | Page 66 of 76

AD9516-5

Reg. Addr. (Hex) Bits Name Description

5 Divider 1 force high

0: normal operation (default). 1: divider output forced to the setting of the Divider 1 start high bit. 4 Divider 1 start high Selects clock output to start high or start low. 0: starts low (default). 1: starts high. [3:0] Divider 1 phase offset Phase offset (default: 0x0). 0x195 1 Divider 1 direct to output Connects OUT2 and OUT3 to Divider 1 or directly to CLK input. 0: OUT2 and OUT3 are connected to Divider 1 (default).

0 Divider 1 DCCOFF Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. 0x196 [7:4] Divider 2 low cycles

[3:0] Divider 2 high cycles

0x197 7 Divider 2 bypass Bypasses and powers down the divider; route input to divider output. 0: uses divider (default). 1: bypasses divider. 6 Divider 2 nosync No sync. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. 5 Divider 2 force high

0: normal operation (default). 1: divider output forced to the setting of the Divider 2 start high bit. 4 Divider 2 start high Selects clock output to start high or start low. 0: starts low (default). 1: starts high. [3:0] Divider 2 phase offset Phase offset (default: 0x0). 0x198 1 Divider 2 direct to output Connects OUT4 and OUT5 to Divider 2 or directly to CLK input. 0: OUT4 and OUT5 are connected to Divider 2 (default).

0 Divider 2 DCCOFF Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction.

Forces divider output to high. This operation requires that the Divider 1 nosync bit (Bit 6) also be set. This bit has no effect if the Divider 1 bypass bit (Bit 7) is set.

1: If Register 0x1E1[0] = 0b, the CLK is routed directly to OUT2 and OUT3. If Register 0x1E1[0] = 1b, this has no effect.

Number of clock cycles (minus 1) of the Divider 2 input during which the Divider 2 output stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).

Number of clock cycles (minus 1) of the Divider 2 input during which the Divider 2 output stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).

Forces divider output to high. This operation requires that the Divider 2 nosync bit (Bit 6) also be set. This bit has no effect if the Divider 2 bypass bit (Bit 7) is set.

1: if 0x1E1[0] = 0b, the CLK is routed directly to OUT4 and OUT5. If 0x1E1[0] = 1b, there is no effect.

Rev. A | Page 67 of 76

AD9516-5

Table 54. LVDS/CMOS Channel Dividers

Reg. Addr. (Hex) Bits Name Description

0x199 [7:4] Low Cycles Divider 3.1

[3:0] High Cycles Divider 3.1

0x19A [7:4] Phase Offset Divider 3.2 Refers to LVDS/CMOS channel divider function description (default: 0x0). [3:0] Phase Offset Divider 3.1 Refers to LVDS/CMOS channel divider function description (default: 0x0). 0x19B [7:4] Low Cycles Divider 3.2

[3:0] High Cycles Divider 3.2

0x19C 5 Bypass Divider 3.2 Bypasses (and powers down) 3.2 divider logic, routes clock to 3.2 output. 0: does not bypass (default). 1: bypasses. 4 Bypass Divider 3.1 Bypasses (and powers down) 3.1 divider logic, routes clock to 3.1 output. 0: does not bypass (default). 1: bypasses. 3 Divider 3 nosync No sync. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. 2 Divider 3 force high Forces Divider 3 output high. Requires that the Divider 3 nosync bit (Bit 3) also be set. 0: forces low (default). 1: forces high. 1 Start High Divider 3.2 Divider 3.2 starts high/low. 0: starts low (default). 1: starts high. 0 Start High Divider 3.1 Divider 3.1 starts high/low. 0: starts low (default). 1: starts high. 0x19D 0 Divider 3 DCCOFF Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. 0x19E [7:4] Low Cycles Divider 4.1

[3:0] High Cycles Divider 4.1

0x19F [7:4] Phase Offset Divider 4.2 Refers to LVDSCMOS channel divider function description (default: 0x0). [3:0] Phase Offset Divider 4.1 Refers to LVDSCMOS channel divider function description (default: 0x0). 0x1A0 [7:4] Low Cycles Divider 4.2

[3:0] High Cycles Divider 4.2

0x1A1 5 Bypass Divider 4.2

4 Bypass Divider 4.1 Bypasses (and powers down) 4.1 divider logic, routes clock to 4.1 output. 0: does not bypass (default). 1: bypasses. 3 Divider 4 nosync No sync. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal.

Number of clock cycles (minus 1) of the Divider 3.1 input during which the Divider 3.1 output stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).

Number of clock cycles (minus 1) of the Divider 3.1 input during which the Divider 3.1 output stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).

Number of clock cycles (minus 1) of the Divider 3.2 input during which the Divider 3.2 output stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).

Number of clock cycles (minus 1) of the Divider 3.2 input during which the Divider 3.2 output stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).

Number of clock cycles (minus 1) of the Divider 4.1 input during which the Divider 4.1 output stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).

Number of clock cycles (minus 1) of the Divider 4.1 input during which the Divider 4.1 output stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).

Number of clock cycles (minus 1) of the Divider 4.2 input during which the Divider 4.2 output stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).

Number of clock cycles (minus 1) of the Divider 4.2 input during which the Divider 4.2 output stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).

Bypasses (and powers down) 4.2 divider logic, routes clock to 4.2 output. 0: does not bypass (default). 1: bypasses.

Rev. A | Page 68 of 76

AD9516-5

Reg. Addr. (Hex) Bits Name Description

2 Divider 4 force high Forces Divider 4 output high. Requires that the Divider 4 nosync bit (Bit 3) also be set. 0: forces low (default). 1: forces high. 1 Start High Divider 4.2 Divider 4.2 starts high/low. 0: starts low (default). 1: starts high. 0 Start High Divider 4.1 Divider 4.1 starts high/low. 0: starts low (default). 1: starts high. 0x1A2 0 Divider 4 DCCOFF Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction.

Table 55. VCO Divider and CLK Input

Reg. Addr. (Hex) Bits Name Description

0x1E0 [2:0] VCO divider 0 0 0 2 0 0 1 3 0 1 0 4 (default) 0 1 1 5 1 0 0 6 1 0 1 Output static 1 1 0 Output static 1 1 1 Output static 0x1E1 4 0: normal operation (default). 1: powers down. 0 Bypass VCO divider Bypasses or uses the VCO divider. 0: uses VCO divider (default). 1: bypasses VCO divider.

Power-down clock input section

2 1 0 Divide

Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).

Table 56. System

Reg. Addr. (Hex)

230 2 Power-down SYNC Powers down the sync function. 0: normal operation of the sync function (default). 1: powers down the SYNC circuitry. 1 0: normal operation of the reference for the distribution section (default). 1: powers down the reference for the distribution section. 0 Soft SYNC

Bits Name Description

Power-down distribution reference

Powers down the reference for distribution section.

The soft SYNC bit works the same as the SYNC reversed; that is, a high level forces selected channels into a predetermined static state, and a 1to-0 transition triggers a SYNC.

0: same as SYNC 1: same as SYNC

Rev. A | Page 69 of 76

pin, except that the polarity of the bit is

high (default). low.

AD9516-5

Table 57. Update All Registers

Reg. Addr. (Hex) Bits Name Description

0x232 0 Update all registers

1: updates all active registers to the contents of the buffer registers (self-clearing).

This bit must be set to 1 to transfer the contents of the buffer registers into the active registers, which happens on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0.

Rev. A | Page 70 of 76

AD9516-5

APPLICATIONS INFORMATION

FREQUENCY PLANNING USING THE AD9516

The AD9516 is a highly flexible PLL. When choosing the PLL settings and version of the AD9516, keep in mind the following guidelines.

The AD9516 has the following four frequency dividers: the reference (or R) divider, the feedback (or N) divider, the VCO divider, and the channel divider. When trying to achieve a particularly difficult frequency divide ratio requiring a large amount of frequency division, some of the frequency division can be done by either the VCO divider or the channel divider, thus allowing a higher phase detector frequency and more flexibility in choosing the loop bandwidth.

Within the AD9516 family, lower VCO frequencies generally result in slightly lower jitter. The difference in integrated jitter (from 12 kHz to 20 MHz offset) for the same output frequency is usually less than 150 fs over the entire VCO frequency range (1.45 GHz to 2.95 GHz) of the AD9516 family. If the desired frequency plan can be achieved with a version of the AD9516 that has a lower VCO frequency, choosing the lower frequency part results in the lowest phase noise and the lowest jitter. However, choosing a higher VCO frequency may result in more flexibility in frequency planning.

Choosing a nominal charge pump current in the middle of the allowable range as a starting point allows the designer to increase or decrease the charge pump current and, thus, allows the designer to fine-tune the PLL loop bandwidth in either direction.

ADIsimCLK is a powerful PLL modeling tool that can be downloaded from www.analog.com. It is a very accurate tool for determining the optimal loop filter for a given application.

USING THE AD9516 OUTPUTS FOR ADC CLOCK APPLICATIONS

Any high speed ADC is extremely sensitive to the quality of its sampling clock. An ADC can be thought of as a sampling mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the analog-to-digital output. Clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at ≥14-bit resolution being the most stringent. The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock.

Considering an ideal ADC of infinite resolution, where the step size and quantization error can be ignored, the available SNR can be expressed approximately by

SNR

⎛ ⎜

log20(dB)

×=

⎜

π

2

⎝

⎞

1

⎟ ⎟

tf

××

JA

⎠

where:

is the highest analog frequency being digitized.

f

A

is the rms jitter on the sampling clock.

t

J

Figure 58 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (ENOB).

110

f

A

(MHz)

SNR = 20log

t

J

=

1

0

2

0

f

S

4

0

f

S

1

p

s

2

p

s

1

0

p

s

0

100

90

80

70

SNR (dB)

60

50

40

30

10 1k100

Figure 58. SNR and ENOB vs. Analog Input Frequency

2πf

f

S

18

1

AtJ

16

14

12

ENOB

10

8

6

See the AN-756 Application Note, Sampled Systems and the Effects of Clock Phase Noise and Jitter; and the AN-501 Application Note, Aperture Uncertainty and ADC System Performance, at

www.analog.com.

Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB. (Distributing a single-ended clock on a noisy PCB may result in coupled noise on the sample clock. Differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment.) The AD9516 features both LVPECL and LVDS outputs that provide differential clock outputs, which enable clock solutions that maximize converter SNR performance. The input requirements of the ADC (differential or single-ended, logic level, and termination) should be considered when selecting the best clocking/converter solution.

07972-044

Rev. A | Page 71 of 76

AD9516-5

V

LVPECL CLOCK DISTRIBUTION

The LVPECL outputs of the AD9516 provide the lowest jitter clock signals that are available from the AD9516. The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 47 shows the LVPECL output stage.

In most applications, an LVPECL far-end Thevenin termination (see Figure 59) or Y-termination (see Figure 60) is recommended. In each case, the V

. If it does not match, ac coupling is recommended (see

V

S_LVPECL

Figure 61).

The resistor network is designed to match the transmission line impedance (50 Ω) and the switching threshold (V

V

S_LVPECL

LVPECL

Figure 59. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination

S_LVPECL

LVPECL

Figure 60. DC-Coupled 3.3 V LVPECL Y-Termination

S_LVPECL

LVP EC L

200Ω 200Ω

Figure 61. AC-Coupled LVPECL with Parallel Transmission Line

of the receiving buffer should match the

S

− 1.3 V).

S

S_DRV

V

S

50Ω

127Ω127Ω

83Ω

50Ω

100Ω

LVP ECL

= 3.3V

S

LVPECL

S

LVP EC L

50Ω

SINGLE -ENDED

(NOT COUPLED)

50Ω

Z0 = 50Ω

0.1nF

100Ω DIFFERENTIAL

0.1nF

(COUPLED)

TRANSMISSION LINE

07972-045

7972-147

7972-046

LVPECL Y-termination is an elegant termination scheme that uses the fewest components and offers both odd- and even-mode impedance matching. Even-mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. Its main drawback is that it offers limited flexibility for varying the drive strength of the emitter-follower LVPECL driver. This can be an important consideration when driving long trace lengths but is usually not an issue. In the case shown in Figure 60, where V

= 2.5 V, the 50 Ω termination

S_LVPECL

resistor connected to ground should be changed to 19 Ω.

Thevenin-equivalent termination uses a resistor network to provide 50 Ω termination to a dc voltage that is below V driver. In this case, V

on the AD9516 should equal VS of

S_LVPECL

of the LVPECL

OL

the receiving buffer. Although the resistor combination shown in Figure 60 results in a dc bias point of V common-mode voltage is V

− 1.3 V because additional

S_LVPECL

− 2 V, the actual

S_LVPECL

current flows from the AD9516 LVPECL driver through the pulldown resistor.

The circuit is identical when V

= 2.5 V, except that the

S_LVPECL

pull-down resistor is 62.5 Ω and the pull-up resistor is 250 Ω.

LVDS CLOCK DISTRIBUTION

The AD9516 provides four clock outputs (OUT6 to OUT9) that are selectable as either CMOS or LVDS level outputs. LVDS is a differential output option that uses a current mode output stage. The nominal current is 3.5 mA, which yields a 350 mV output swing across a 100 Ω resistor. An output current of 7 mA is also available in cases where a larger output swing is required. The LVDS output meets or exceeds all ANSI/TIA/EIA-644 specifications.

A recommended termination circuit for the LVDS outputs is shown in Figure 62.

S

LVDS

DIFFERENTIAL (COUPLED)

100Ω

Figure 62. LVDS Output Termination

See the AN-586 Application Note, LVDS Data Outputs for HighSpeed Analog-to-Digital Converters for more information on LVDS.

S

LVDS

07972-047

Rev. A | Page 72 of 76

AD9516-5

Ω

V

CMOS CLOCK DISTRIBUTION

The AD9516 provides four clock outputs (OUT6 to OUT9) that are selectable as either CMOS or LVDS level outputs. When selected as CMOS, each output becomes a pair of CMOS outputs, each of which can be individually turned on or off and set as noninverting or inverting. These outputs are 3.3 V CMOS compatible.

Whenever single-ended CMOS clocking is used, some general guidelines should be followed.

Point-to-point nets should be designed such that a driver has only one receiver on the net, if possible. This allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the net. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. The value of the resistor is dependent on the board design and timing requirements (typically 10 Ω to 100 Ω is used). CMOS outputs are also limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 3 inches are recommended to preserve signal rise/fall times and preserve signal integrity.

60.4

(1.0 INCH)

10Ω

CMOS CMOS

Figure 63. Series Termination of CMOS Output

MICROSTRIP

07972-076

Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9516 do not supply enough current to provide a full voltage swing with a low impedance resistive, farend termination, as shown in Figure 64. The far-end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets.

S

10Ω

CMOS CMOS

Figure 64. CMOS Output with Far-End Termination

50Ω

100Ω

7972-077

Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9516 offers both LVPECL and LVDS outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters.

Rev. A | Page 73 of 76

AD9516-5

OUTLINE DIMENSIONS

49

48

0.60 MAX

EXPOSED PAD

(BOTTOM VIEW)

PIN 1

64

INDICATOR

1

6.35

6.20 SQ

6.05

PIN 1

INDICATOR

9.00

BSC SQ

TOP VIE W

8.75

BSC SQ

0.60

MAX

0.50

BSC

1.00

0.85

0.80

SEATING

PLANE

12° MAX

0.50

0.40

0.30

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

0.05 MAX

0.02 NOM

0.20 REF

33

32

7.50 REF

16

17

FOR PROPER CO NNECTION O F THE EXPOSED PAD, REFER TO THE PIN CONF IGURATIO N AND FUNCTION DESCRI PTIONS SECTION OF THIS DATA SHEET.

0.25 MIN

091707-C

Figure 65. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD9516-5BCPZ −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 AD9516-5BCPZ-REEL7 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 AD9516-5/PCBZ Evaluation Board

1

Z = RoHS Compliant Part.

Rev. A | Page 74 of 76

AD9516-5

NOTES

Rev. A | Page 75 of 76

AD9516-5

NOTES

Rev. A | Page 76 of 76

ANALOG DEVICES AD9516-5 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

POWER SUPPLY REQUIREMENTS

PLL CHARACTERISTICS

CLOCK INPUTS

CLOCK OUTPUTS

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)

DELAY BLOCK ADDITIVE TIME JITTER

SERIAL CONTROL PORT

LD, STATUS, AND REFMON PINS

POWER DISSIPATION

TIMING CHARACTERISTICS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

DETAILED BLOCK DIAGRAM

THEORY OF OPERATION

OPERATIONAL CONFIGURATIONS

Mode 1—Clock Distribution or External VCO < 1600 MHz

Mode 2 (High Frequency Clock Distribution)—CLK or External VCO > 1600 MHz

Phase-Locked Loop (PLL)

Configuration of the PLL

Phase Frequency Detector (PFD)

Charge Pump (CP)

PLL External Loop Filter

PLL Reference Inputs

Reference Switchover

Reference Divider R

VCXO/VCO Feedback Divider N—P, A, B

Prescaler

A and B Counters

R and N Divider Delays

LOCK DETECT

Digital Lock Detect (DLD)

Analog Lock Detect (ALD)

Current Source Digital Lock Detect (CSDLD)

Holdover

Manual Holdover Mode

Automatic/Internal Holdover Mode

Frequency Status Monitors

CLOCK DISTRIBUTION

Operating Modes

Clock Frequency Division

VCO Divider

Channel Dividers—LVPECL Outputs

Channel Frequency Division (0, 1, and 2)

Duty Cycle and Duty-Cycle Correction (0, 1, and 2)

Phase Offset or Coarse Time Delay (0, 1, and 2)

Channel Dividers—LVDS/CMOS Outputs

Channel Frequency Division (Divider 3 and Divider 4)

Duty Cycle and Duty-Cycle Correction (Divider 3 and Divider 4)

Phase Offset or Coarse Time Delay (Divider 3 and Divider 4)

Fine Delay Adjust (Divider 3 and Divider 4)

Calculating the Fine Delay

Synchronizing the Outputs—SYNC Function

Clock Outputs

LVPECL Outputs—OUT0 to OUT5

LVDS/CMOS Outputs—OUT6 to OUT9

RESET MODES

Power-On Reset—Start-Up Conditions When VS Is Applied

Soft Reset via Register 0x000[2]

POWER-DOWN MODES

PLL Power-Down

Distribution Power-Down