ANALOG DEVICES AD9516-5 Service Manual

14-Output Clock Generator

FEATURES

Low phase noise, phase-locked loop (PLL)

External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic revertive and manual reference

switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable

Six 1.6 GHz LVPECL outputs, arranged in 3 groups

Each group shares a 1-to-32 divider with coarse phase delay Additive output jitter: 225 fs rms Channel-to-channel skew paired outputs of <10 ps

Four 800 MHz LVDS outputs, arranged in 2 groups

Each group has 2 cascaded 1-to-32 dividers with coarse

phase delay Additive output jitter: 275 fs rms Fine delay adjust (Δt) on each LVDS output Each LVDS output can be reconfigured as two 250 MHz

CMOS outputs

Automatic synchronization of all outputs on power-up Manual output synchronization available Available in 64-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET,

Synchronous Ethernet, OTU2/3/4

Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation

GENERAL DESCRIPTION

The AD9516-51 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO/VCXO of up to 2.4 GHz.

The AD9516-5 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.

AD9516-5

FUNCTIONAL BLOCK DIAGRAM

CP

REF1

REFIN

CLK

REF2

DIV/Φ DIV/Φ

SERIAL CONTRO L PORT

AND

DIGITAL LOGIC

SWITCHOVER

AND MONITOR

DIVIDER

AND MUXes

DIV/Φ

Figure 1.

PLL

∆t

The AD9516-5 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.

Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.

The AD9516-5 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (V LVPECL power supply can be from 2.375 V to 3.6 V (nominal).

The AD9516-5 is specified for operation over the industrial range of −40°C to +85°C.

For applications requiring an integrated EEPROM, or needing additional outputs, the AD9520-5 and AD9522-5 are available.

1

AD9516 is used throughout the data sheet to refer to all members of the AD9516

family. However, when AD9516-5 is used, it refers to that specific member of the

AD9516 family.

STATUS

MONITOR

LVPECL

LVDS/CMOS

AD9516-5

) to 5.5 V. A separate

CP

OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9

07972-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9516-5

REVISION HISTORY

8/11—Rev. 0 to Rev. A

Changes to Features, Applications, and General Description ..... 1

Changes to CPRSET Pin Resistor Parameter, Table 1 .................. 4

Change to P = 2 DM (2/3) Parameter, Table 2 .............................. 5

Changes Test Conditions/Comments, Table 4 .............................. 6

Moved Table 5 to End of Specifications and Renumbered

Sequentially ...................................................................................... 13

Change to Shortest Delay Range Parameter,

Test Conditions/Comments, Table 14 .......................................... 13

Moved Timing Diagrams ............................................................... 14

Change to Endnote, Table 16 ......................................................... 15

Change to Caption, Figure 8 .......................................................... 18

Change to Captions, Figure 20 and Figure 21 ............................. 20

Moved Figure 23 and Figure 24 ..................................................... 21

Added Figure 31; Renumbered Sequentially ............................... 22

Change to Mode 1—Clock Distribution or External VCO <

1600 MHz Section .......................................................................... 25

Changes to Mode 2 (High Frequency Clock Distribution)—

CLK or External VCO > 1600 MHz; Change to Table 22 .......... 26

Change to Charge Pump (CP) Section ......................................... 28

Changes to PLL Reference Inputs and Reference Switchover

Sections ............................................................................................. 29

Changes to Prescaler Section and Table 24 .................................. 30

Changes to A and B Counters, Digital Lock Detect (DLD),

and Current Source Digital Lock Detect (CSDLD) Sections .... 31

Change to Holdover Section .......................................................... 32

Changes to Automatic/Internal Holdover Mode ........................ 34

Changes to Clock Distribution Section ........................................ 35

Changes to Channel Dividers—LVDS/CMOS Outputs

Section .............................................................................................. 37

Change to the Instruction Word (16 Bits) Section ..................... 45

Change to Figure 53 ........................................................................ 46

Changes to θ Changes to Register Address 0x003 and

Register Address 0x01C, Table 47 ................................................. 49

Changes to Register Address 0x003, Table 48 ............................. 52

Changes to Register Address 0x016, Bits[2:0], Table 49 ............ 54

Changes to Register Address 0x01C, Bits[4:3], Table 49 ........... 57

Changes to Register Address 0x191, Register Address 0x194,

and Register Address 0x197, Bit 5, Table 53 ................................ 66

Added Frequency Planning Using the AD9516 Section ............ 71

Changes to LVPECL Clock Distribution and LVDS Clock Distribution Sections; Changes to Figure 59, Figure 60, and

Figure 61 ........................................................................................... 72

1/09—Revision 0: Initial Version

and ΨJT Parameters, Table 46 ............................... 48

JA

Rev. A | Page 3 of 76

AD9516-5

SPECIFICATIONS

Typical is g i v e n for VS = V Minimum and maximum values are given over full V

POWER SUPPLY REQUIREMENTS

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

VS 3.135 3.3 3.465 V 3.3 V ± 5% V

2.375 VS V Nominally 2.5 V to 3.3 V ± 5%

S_LVPECL

VCP V RSET Pin Resistor 4.12 kΩ Sets internal biasing currents; connect to ground CPRSET Pin Resistor 2.7 5.1 10 kΩ

PLL CHARACTERISTICS

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE INPUTS

Differential Mode (REFIN, REFIN)

Input Frequency 0 250 MHz

Input Sensitivity 250 mV p-p

Self-Bias Voltage, REFIN 1.35 1.60 1.75 V Self-bias voltage of REFIN1 Self-Bias Voltage, REFIN Input Resistance, REFIN 4.0 4.8 5.9 kΩ Self-biased1 Input Resistance, REFIN

Dual Single-Ended Mode (REF1, REF2) Two single-ended CMOS-compatible inputs

Input Frequency (AC-Coupled) 20 250 MHz Slew rate > 50 V/μs Input Frequency (DC-Coupled) 0 250 MHz Slew rate > 50 V/μs; CMOS levels Input Sensitivity (AC-Coupled) 0.8 V p-p Should not exceed VS p-p Input Logic High 2.0 V Input Logic Low 0.8 V Input Current −100 +100 μA

Input Capacitance 2 pF

PHASE/FREQUENCY DETECTOR (PFD)

PFD Input Frequency 100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns 45 MHz Antibacklash pulse width = 6.0 ns Antibacklash Pulse Width 1.3 ns Register 0x017[1:0] = 01b

2.9 ns Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b

6.0 ns Register 0x017[1:0] = 10b

CHARGE PUMP (CP)

ICP Sink/Source Programmable

High Value 4.8 mA With CP Low Value 0.60 mA Absolute Accuracy 2.5 % CPV = VCP/2

CPRSET Range 2.7/10 kΩ ICP High Impedance Mode Leakage 1 nA Sink-and-Source Current Matching 2 % 0.5 < CPV < VCP − 0.5 V ICP vs. CPV 1.5 % 0.5 < CPV < VCP − 0.5 V ICP vs. Temperature 2 % VCP = VCP/2 V

= 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; R

S_LVPECL

and TA (−40°C to +85°C) variation.

S

5.25 V Nominally 3.3 V to 5.0 V ± 5%

S

1.30 1.50 1.60 V

4.4 5.3 6.4 kΩ Self-biased

Rev. A | Page 4 of 76

= 4.12 kΩ; CP

SET

= 5.1 kΩ, unless otherwise noted.

RSET

Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA); actual current can be calculated by: CP_lsb = 3.06/CPRSET; connect to ground

Differential mode (can accommodate single-ended input by ac grounding undriven input)

Frequencies below about 1 MHz should be dc-coupled; be careful to match V

(self-bias voltage)

CM

PLL figure of merit (FOM) increases with increasing slew rate; see Figure 13

Self-bias voltage of REFIN1

1

Each pin, REFIN/REFIN

= 5.1 kΩ

RSET

(REF1/REF2)

AD9516-5

Parameter Min Typ Max Unit Test Conditions/Comments

PRESCALER (PART OF N DIVIDER) See the VCXO/VCO Feedback Divider N—P, A, B section

Prescaler Input Frequency

P = 1 FD 300 MHz P = 2 FD 600 MHz P = 3 FD 900 MHz P = 2 DM (2/3) 200 MHz P = 4 DM (4/5) 1000 MHz P = 8 DM (8/9) 2400 MHz P = 16 DM (16/17) 3000 MHz P = 32 DM (32/33) 3000 MHz

Prescaler Output Frequency 300 MHz

PLL DIVIDER DELAYS Register 0x019: R, Bits[5:3]; N, Bits[2:0]; see Table 49

000 Off ps 001 330 ps 010 440 ps 011 550 ps 100 660 ps 101 770 ps 110 880 ps 111 990 ps

NOISE CHARACTERISTICS

In-Band Phase Noise of the Charge Pump/Phase Frequency Detector (In-Band Is Within the LBW of the PLL)

At 500 kHz PFD Frequency −165 dBc/Hz At 1 MHz PFD Frequency −162 dBc/Hz At 10 MHz PFD Frequency −151 dBc/Hz At 50 MHz PFD Frequency −143 dBc/Hz

PLL Figure of Merit (FOM) −220 dBc/Hz

PLL DIGITAL LOCK DETECT WINDOW2

Required to Lock (Coincidence of Edges) Selected by Register 0x017[1:0] and Register 0x018[4]

Low Range (ABP 1.3 ns, 2.9 ns) 3.5 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b High Range (ABP 6.0 ns) 3.5 ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b

To Unlock After Lock (Hysteresis)2

Low Range (ABP 1.3 ns, 2.9 ns) 7 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b High Range (ABP 1.3 ns, 2.9 ns) 15 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b High Range (ABP 6.0 ns) 11 ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b

1

The REFIN and

2

For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

REFIN

self-bias points are offset slightly to avoid chatter on an open input condition.

A, B counter input frequency (prescaler input frequency divided by P)

The PLL in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the value of the N divider)

Reference slew rate > 0.25 V/ns; FOM + 10 log(f

PFD

) is an approximation of the PFD/CP in-band phase noise (in the flat region) inside the PLL loop bandwidth; when running closed-loop, the phase noise, as observed at the VCO output, is increased by 20 log(N)

Signal available at the LD, STATUS, and REFMON pins when selected by appropriate register settings

Rev. A | Page 5 of 76

AD9516-5

CLOCK INPUTS

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

CLOCK INPUTS (CLK,

CLK

) Input Frequency 01 2.4 GHz High frequency distribution (VCO divider enabled) 0

Input Sensitivity, Differential 150 mV p-p Measured at 2.4 GHz; jitter performance is

Input Level, Differential 2 V p-p Larger voltage swings may turn on the

Input Common-Mode Voltage, VCM 1.3 1.57 1.8 V Self-biased; enables ac coupling Input Common-Mode Range, V Input Sensitivity, Single-Ended 150 mV p-p Input Resistance 3.9 4.7 5.7 kΩ Self-biased Input Capacitance 2 pF

1

Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.

CLOCK OUTPUTS

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL CLOCK OUTPUTS Termination = 50 Ω to V

OUT0, OUT1, OUT2, OUT3, OUT4,

OUT5 Output Frequency, Maximum 2400 MHz Using direct to output; see Figure 20 for peak-to-

Output High Voltage (VOH) V

Output Low Voltage (VOL) V

Output Differential Voltage (VOD) 550 790 980 mV VOH − VOL for each leg of a differential pair for

LVDS CLOCK OUTPUTS Differential termination 100 Ω at 3.5 mA

OUT6, OUT7, OUT8, OUT9

Output Frequency, Maximum 800 MHz The AD9516 outputs can toggle at higher

Differential Output Voltage (VOD) 247 360 454 mV VOH − VOL measurement across a differential pair

Delta VOD 25 mV This is the absolute value of the difference between

Output Offset Voltage (VOS) 1.125 1.24 1.375 V (VOH + VOL)/2 across a differential pair at the

Delta VOS 25 mV This is the absolute value of the difference between

Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND

CMOS CLOCK OUTPUTS

OUT6A, OUT6B, OUT7A, OUT7B,

OUT8A, OUT8B, OUT9A, OUT9B Output Frequency 250 MHz See Figure 22 Output Voltage High (VOH) V Output Voltage Low (VOL) 0.1 V At 1 mA load

Differential input

1

1.6 GHz Distribution only (VCO divider bypassed; this is the frequency range supported by the channel divider)

improved with slew rates > 1 V/ns

protection diodes and may degrade jitter performance

1.3 1.8 V With 200 mV p-p signal applied; dc-coupled

CMR

CLK ac-coupled;

Differential (OUT,

CLK

ac-bypassed to RF ground

− 2 V

S_LVPECL

OUT

)

peak differential amplitude

S_LVPECL

− 1.12 V

S_LVPECL

− 0.98 V

− 0.84 V Measured at dc using the default amplitude setting;

S_LVPECL

see Figure 20 for amplitude vs. frequency

S_LVPECL

− 2.03 V

S_LVPECL

− 1.77 V

− 1.49 V Measured at dc using the default amplitude setting;

S_LVPECL

see Figure 20 for amplitude vs. frequency

default amplitude setting with driver not toggling; see Figure 20 for variation over frequency

Differential (OUT,

OUT

)

frequencies, but the output amplitude may not meet the V

specification; see Figure 21

OD

at the default amplitude setting with output driver not toggling; see Figure 21 for variation over frequency

when the normal output is high vs. when the

V

OD

complementary output is high

default amplitude setting with output driver not toggling

when the normal output is high vs. when the

V

OS

complementary output is high

Single-ended; termination = 10 pF

− 0.1 V At 1 mA load

S_LVPECL

Rev. A | Page 6 of 76

AD9516-5

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

CLK-TO-LVPECL ADDITIVE PHASE NOISE Distribution section only; does not include PLL input

CLK = 1 GHz, Output = 1 GHz slew rate > 1 V/ns

Divider = 1

At 10 Hz Offset −109 dBc/Hz At 100 Hz Offset −118 dBc/Hz At 1 kHz Offset −130 dBc/Hz At 10 kHz Offset −139 dBc/Hz At 100 kHz Offset −144 dBc/Hz At 1 MHz Offset −146 dBc/Hz At 10 MHz Offset −147 dBc/Hz At 100 MHz Offset −149 dBc/Hz

CLK = 1 GHz, Output = 200 MHz Input slew rate > 1 V/ns

Divider = 5

At 10 Hz Offset −120 dBc/Hz At 100 Hz Offset −126 dBc/Hz At 1 kHz Offset −139 dBc/Hz At 10 kHz Offset −150 dBc/Hz At 100 kHz Offset −155 dBc/Hz At 1 MHz Offset −157 dBc/Hz >10 MHz Offset −157 dBc/Hz

CLK-TO-LVDS ADDITIVE PHASE NOISE Distribution section only; does not include input slew

CLK = 1.6 GHz, Output = 800 MHz rate > 1 V/ns

Divider = 2

At 10 Hz Offset −103 dBc/Hz At 100 Hz Offset −110 dBc/Hz At 1 kHz Offset −120 dBc/Hz At 10 kHz Offset −127 dBc/Hz At 100 kHz Offset −133 dBc/Hz At 1 MHz Offset −138 dBc/Hz At 10 MHz Offset −147 dBc/Hz At 100 MHz Offset −149 dBc/Hz

CLK = 1.6 GHz, Output = 400 MHz Input slew rate > 1 V/ns

Divider = 4

At 10 Hz Offset −114 dBc/Hz At 100 Hz Offset −122 dBc/Hz At 1 kHz Offset −132 dBc/Hz At 10 kHz Offset −140 dBc/Hz At 100 kHz Offset −146 dBc/Hz At 1 MHz Offset −150 dBc/Hz >10 MHz Offset −155 dBc/Hz

CLK-TO-CMOS ADDITIVE PHASE NOISE Distribution section only; does not include PLL input

CLK = 1 GHz, Output = 250 MHz slew rate > 1 V/ns

Divider = 4

At 10 Hz Offset −110 dBc/Hz At 100 Hz Offset −120 dBc/Hz At 1 kHz Offset −127 dBc/Hz At 10 kHz Offset −136 dBc/Hz At 100 kHz Offset −144 dBc/Hz At 1 MHz Offset −147 dBc/Hz >10 MHz Offset −154 dBc/Hz

Rev. A | Page 7 of 76

AD9516-5

Parameter Min Typ Max Unit Test Conditions/Comments

CLK = 1 GHz, Output = 50 MHz Input slew rate > 1 V/ns

Divider = 20

At 10 Hz Offset −124 dBc/Hz At 100 Hz Offset −134 dBc/Hz At 1 kHz Offset −142 dBc/Hz At 10 kHz Offset −151 dBc/Hz At 100 kHz Offset −157 dBc/Hz At 1 MHz Offset −160 dBc/Hz >10 MHz Offset −163 dBc/Hz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

LVPECL = 245.76 MHz; PLL LBW = 125 Hz 54 fs rms Integration bandwidth = 200 kHz to 5 MHz 77 fs rms Integration bandwidth = 200 kHz to 10 MHz 109 fs rms Integration bandwidth = 12 kHz to 20 MHz LVPECL = 122.88 MHz; PLL LBW = 125 Hz 79 fs rms Integration bandwidth = 200 kHz to 5 MHz 114 fs rms Integration bandwidth = 200 kHz to 10 MHz 163 fs rms Integration bandwidth = 12 kHz to 20 MHz LVPECL = 61.44 MHz; PLL LBW = 125 Hz 124 fs rms Integration bandwidth = 200 kHz to 5 MHz 176 fs rms Integration bandwidth = 200 kHz to 10 MHz 259 fs rms Integration bandwidth = 12 kHz to 20 MHz

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

Application example based on a typical setup using an external 245.76 MHz VCXO (Toyocom TCO-2112); reference = 15.36 MHz; R = 1

Table 7.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

CLK = 622.08 MHz; LVPECL = 622.08 MHz;

Divider = 1

CLK = 622.08 MHz; LVPECL = 155.52 MHz;

Divider = 4

CLK = 1.6 GHz; LVPECL = 100 MHz;

Divider = 16

CLK = 500 MHz; LVPECL = 100 MHz;

Divider = 5

LVDS OUTPUT ADDITIVE TIME JITTER

CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2

(VCO Divider Not Used) CLK = 1 GHz; LVDS = 200 MHz; Divider = 5 113 fs rms Bandwidth = 12 kHz to 20 MHz CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16 280 fs rms

CMOS OUTPUT ADDITIVE TIME JITTER

CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16 365 fs rms

40 fs rms Bandwidth = 12 kHz to 20 MHz

80 fs rms Bandwidth = 12 kHz to 20 MHz

215 fs rms

245 fs rms Calculated from SNR of ADC method; DCC on

85 fs rms Bandwidth = 12 kHz to 20 MHz

Distribution section only; does not include PLL; uses rising edge of clock signal

Calculated from SNR of ADC method; DCC not used for even divides

Distribution section only; does not include PLL; uses rising edge of clock signal

Calculated from SNR of ADC method; DCC not used for even divides

Distribution section only; does not include PLL; uses rising edge of clock signal

Calculated from SNR of ADC method; DCC not used for even divides

Rev. A | Page 8 of 76

AD9516-5

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)

Table 8.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

CLK = 2.4 GHz; VCO Div = 2; LVPECL = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

LVDS OUTPUT ADDITIVE TIME JITTER

CLK = 2.4 GHz; VCO Div = 2; LVDS = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

CMOS OUTPUT ADDITIVE TIME JITTER

CLK = 2.4 GHz; VCO Div = 2; CMOS = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

210 fs rms Calculated from SNR of ADC method

285 fs rms Calculated from SNR of ADC method

350 fs rms Calculated from SNR of ADC method

DELAY BLOCK ADDITIVE TIME JITTER

Table 9.

Parameter Min Typ Max Unit Test Conditions/Comments

DELAY BLOCK ADDITIVE TIME JITTER1 Incremental additive jitter

100 MHz Output

Delay (1600 μA, 0x1C) Fine Adjust 000000b 0.54 ps rms Delay (1600 μA, 0x1C) Fine Adjust 101111b 0.60 ps rms Delay (800 μA, 0x1C) Fine Adjust 000000b 0.65 ps rms Delay (800 μA, 0x1C) Fine Adjust 101111b 0.85 ps rms Delay (800 μA, 0x4C) Fine Adjust 000000b 0.79 ps rms Delay (800 μA, 0x4C) Fine Adjust 101111b 1.2 ps rms Delay (400 μA, 0x4C) Fine Adjust 000000b 1.2 ps rms Delay (400 μA, 0x4C) Fine Adjust 101111b 2.0 ps rms Delay (200 μA, 0x1C) Fine Adjust 000000b 1.3 ps rms Delay (200 μA, 0x1C) Fine Adjust 101111b 2.5 ps rms Delay (200 μA, 0x4C) Fine Adjust 000000b 1.9 ps rms Delay (200 μA, 0x4C) Fine Adjust 101111b 3.8 ps rms

1

This value is incremental; that is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter

should be added to this value using the root sum of the squares (RSS) method.

Distribution section only; does not include PLL; uses rising edge of clock signal

Rev. A | Page 9 of 76

AD9516-5

SERIAL CONTROL PORT

Table 10.

Parameter Min Typ Max Unit Test Conditions/Comments

CS (INPUT)

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 3 μA Input Logic 0 Current 110 μA Input Capacitance 2 pF

SCLK (INPUT) SCLK has an internal 30 kΩ pull-down resistor

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 110 μA Input Logic 0 Current 1 μA Input Capacitance 2 pF

SDIO (WHEN INPUT)

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 10 nA Input Logic 0 Current 20 nA Input Capacitance 2 pF

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V

TIMING

Clock Rate (SCLK, 1/t Pulse Width High, t Pulse Width Low, t

) 25 MHz

SCLK

16 ns

HIGH

16 ns

LOW

SDIO to SCLK Setup, tDS 2 ns SCLK to SDIO Hold, tDH 1.1 ns SCLK to Valid SDIO and SDO, tDV 8 ns CS to SCLK Setup and Hold, tS, tH

CS Minimum Pulse Width High, t

2 ns 3 ns

PWH

CS has an internal 30 kΩ pull-up resistor

PD, RESET, AND SYNC PINS

Table 11.

Parameter Min Typ Max Unit Test Conditions/Comments

INPUT CHARACTERISTICS Each of these pins has an internal 30 kΩ pull-up resistor

Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 110 μA Logic 0 Current 1 μA Capacitance 2 pF

RESET TIMING

Pulse Width Low 50 ns

SYNC TIMING

Pulse Width Low 1.5

High speed

High speed clock is CLK input signal

clock cycles

Rev. A | Page 10 of 76

AD9516-5

LD, STATUS, AND REFMON PINS

Table 12.

Parameter Min Typ Max Unit Test Conditions/Comments

OUTPUT CHARACTERISTICS

Output Voltage High, VOH 2.7 V Output Voltage Low, VOL 0.4 V

MAXIMUM TOGGLE RATE 100 MHz

ANALOG LOCK DETECT

Capacitance 3 pF

REF1, REF2, AND CLK FREQUENCY STATUS

MONITOR Normal Range 1.02 MHz

Extended Range 8 kHz

LD PIN COMPARATOR

Trip Point 1.6 V Hysteresis 260 mV

When selected as a digital output (CMOS); there are other modes in which these pins are not CMOS digital outputs; see Table 49: Register 0x017, Register 0x01A, and Register 0x01B

Applies when mux is set to any divider or counter output or PFD up/down pulse; also applies in analog lock detect mode; usually debug mode only; beware that spurs may couple to output when any of these pins are toggling

On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor

Frequency above which the monitor always indicates the presence of the reference

POWER DISSIPATION

Table 13.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER DISSIPATION, CHIP

Power-On Default 1.0 1.2 W

Full Operation; CMOS Outputs at 225 MHz 1.5 2.1 W

Full Operation; LVDS Outputs at 225 MHz 1.5 2.1 W

PD Power-Down

PD Power-Down, Maximum Sleep

VCP Supply 4 4.8 mW

AD9516 Core 220 mW

75 185 mW

31 mW

The values in this table include all power supplies, unless otherwise noted; the power deltas for individual drivers are at dc; see Figure 7, Figure 8, and Figure 9 for power dissipation vs. output frequency

No clock; no programming; default register values; does not include power dissipated in external resistors; this configuration has the following blocks already powered up: VCO divider, six channel dividers, three LVPECL drivers, and two LVDS drivers

= 2.25 GHz; VCO divider = 2; all channel dividers on; six

f

CLK

LVPECL outputs at 562.5 MHz; eight CMOS outputs (10 pF load) at 225 MHz; all four fine delay blocks on, maximum current; does not include power dissipated in external resistors

= 2.25 GHz; VCO divider = 2; all channel dividers on; six

f

CLK

LVPECL outputs at 562.5 MHz; four LVDS outputs at 225 MHz; all four fine delay blocks on: maximum current; does not include power dissipated in external resistors

PD pin pulled low; does not include power dissipated in terminations

PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b; SYNC power-down, Register 0x230[2] = 1b; REF for distribution power-down, Register 0x230[1] = 1b

PLL operating; typical closed-loop configuration (this number is included in all other power measurements)

AD9516 core only, all drivers off, PLL off, VCO divider off, and

delay blocks off; the power consumption of the configuration of the user can be derived from this number and the power deltas that follow

Rev. A | Page 11 of 76

AD9516-5

Parameter Min Typ Max Unit Test Conditions/Comments

POWER DELTAS, INDIVIDUAL FUNCTIONS Power delta when a function is enabled/disabled

VCO Divider 30 mW VCO divider bypassed REFIN (Differential) 20 mW All references off to differential reference enabled REF1, REF2 (Single-Ended) 4 mW

PLL 75 mW PLL off to PLL on, normal operation; no reference enabled Channel Divider 30 mW Divider bypassed to divide-by-2 to divide-by-32 LVPECL Channel (Divider Plus Output Driver) 120 mW

LVPECL Driver 90 mW

LVDS Channel (Divider Plus Output Driver) 140 mW

LVDS Driver 50 mW

CMOS Channel (Divider Plus Output Driver) 100 mW

CMOS Driver (Second in Pair) 0 mW

CMOS Driver (First in Second Pair) 30 mW

Fine Delay Block 50 mW

All references off to REF1 or REF2 enabled; differential reference not enabled

No LVPECL output on to one LVPECL output on (that is, enabling OUT0 with OUT1 off; Divider 0 enabled), independent of frequency

Second LVPECL output turned on, same channel (that is, enabling OUT0 with OUT1 already on)

No LVDS output on to one LVDS output on (that is, enabling OUT8 with OUT9 off with Divider 4.1 enabled and Divider 4.2 bypassed); see Figure 8 for dependence on output frequency

Second LVDS output turned on, same channel (that is, enabling OUT8 with OUT9 already on)

Static; no CMOS output on to one CMOS output on (that is, enabling OUT8A starting with OUT8 and OUT9 off); see Figure 9 for variation over output frequency

Static; second CMOS output, same pair, turned on (that is, enabling OUT8A with OUT8B already on)

Static; first output, second pair, turned on (that is, enabling OUT9A with OUT9B off and OUT8A and OUT8B already on)

Delay block off to delay block enabled; maximum current setting

Rev. A | Page 12 of 76

AD9516-5

TIMING CHARACTERISTICS

Table 14.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL Termination = 50 Ω to V

(810 mV) Output Rise Time, tRP 70 180 ps 20% to 80%, measured differentially Output Fall Time, tFP 70 180 ps 80% to 20%, measured differentially

PROPAGATION DELAY, t

, CLK-TO-LVPECL OUTPUT

PECL

High Frequency Clock Distribution Configuration 835 995 1180 ps See Figure 34 Clock Distribution Configuration 773 933 1090 ps See Figure 33 Variation with Temperature 0.8 ps/°C

OUTPUT SKEW, LVPECL OUTPUTS1

LVPECL Outputs That Share the Same Divider 5 15 ps LVPECL Outputs on Different Dividers 13 40 ps All LVPECL Outputs Across Multiple Parts 220 ps

LVDS Termination = 100 Ω differential; 3.5 mA setting

Output Rise Time, tRL 170 350 ps 20% to 80%, measured differentially2 Output Fall Time, tFL 160 350 ps 20% to 80%, measured differentially2

PROPAGATION DELAY, t

, CLK-TO-LVDS OUTPUT Delay off on all outputs

LVDS

OUT6, OUT7, OUT8, OUT9

For All Divide Values 1.4 1.8 2.1 ns Variation with Temperature 1.25 ps/°C

OUTPUT SKEW, LVDS OUTPUTS1 Delay off on all outputs

LVDS Outputs That Share the Same Divider 6 62 ps LVDS Outputs on Different Dividers 25 150 ps All LVDS Outputs Across Multiple Parts 430 ps

CMOS Termination = open

Output Rise Time, tRC 495 1000 ps 20% to 80%; C Output Fall Time, tFC 475 985 ps 80% to 20%; C

PROPAGATION DELAY, t

, CLK-TO-CMOS OUTPUT Fine delay off

CMOS

LOAD

= 10 pF = 10 pF

For All Divide Values 1.6 2.1 2.6 ns Variation with Temperature 2.6 ps/°C

OUTPUT SKEW, CMOS OUTPUTS1 Fine delay off

CMOS Outputs That Share the Same Divider 4 66 ps All CMOS Outputs on Different Dividers 28 180 ps All CMOS Outputs Across Multiple Parts 675 ps

DELAY ADJUST3 LVDS and CMOS

Shortest Delay Range4 Register 0x0A1 (0x0A4, 0x0A7, 0x0AA), Bits[5:0] = 101111b

Zero Scale 50 315 680 ps Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b Full Scale 540 880 1180 ps Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b

Longest Delay Range4 Register 0x0A1 (0x0A4, 0x0A7, 0x0AA) Bits[5:0] = 000000b

Zero Scale 200 570 950 ps Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b Quarter Scale 1.72 2.31 2.89 ns Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 001100b Full Scale 5.7 8.0 10.1 ns Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b

Delay Variation with Temperature

Short Delay Range5

Zero Scale 0.23 ps/°C Full Scale −0.02 ps/°C

Long Delay Range5

Zero Scale 0.3 ps/°C Full Scale 0.24 ps/°C

1

This is the difference between any two similar delay paths while operating at the same voltage and temperature.

2

Corresponding CMOS drivers set to OUTxA for noninverting and OUTxB for inverting; x = 6, 7, 8, or 9.

3

The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output.

4

Incremental delay; does not include propagation delay.

5

All delays between zero scale and full scale can be estimated by linear interpolation.

Rev. A | Page 13 of 76

− 2 V; default amplitude setting

S_LVPECL

AD9516-5

K

Timing Diagrams

t

CLK

CL

t

LVDS

t

CMOS

Figure 2. CLK/

DIFFERENTIAL

80%

20%

Figure 3. LVPECL Timing, Differential

PECL

CLK

to Clock Output Timing, Divider = 1

LVPECL

t

RP

07972-060

t

FP

07972-061

DIFFERENTIAL

80%

LVDS

20%

t

RL

t

FL

Figure 4. LVDS Timing, Differential

SINGLE-ENDED

80%

CMOS

10pF LOAD

20%

t

RC

t

FC

Figure 5. CMOS Timing, Single-Ended, 10 pF Load

07972-062

07972-063

Rev. A | Page 14 of 76

AD9516-5

ABSOLUTE MAXIMUM RATINGS

Table 15.

Parameter Rating

VS, VS_LVPECL to GND −0.3 V to +3.6 V VCP to GND −0.3 V to +5.8 V REFIN, REFIN to GND REFIN to REFIN

−0.3 V to VS + 0.3 V

−3.3 V to +3.3 V

RSET to GND −0.3 V to VS + 0.3 V CPRSET to GND −0.3 V to VS + 0.3 V CLK, CLK to GND

CLK to CLK SCLK, SDIO, SDO, CS to GND OUT0, OUT0, OUT1, OUT1, OUT2, OUT2,

OUT3, OUT3 OUT6, OUT6 OUT9, OUT9

SYNC

to GND

, OUT4, OUT4, OUT5, OUT5, , OUT7, OUT7, OUT8, OUT8, to GND

−0.3 V to VS + 0.3 V

−1.2 V to +1.2 V

−0.3 V to VS + 0.3 V

REFMON, STATUS, LD to GND −0.3 V to VS + 0.3 V Temperature

Junction Temperature1 150°C Storage Temperature Range −65°C to +150°C Lead Temperature (10 sec) 300°C

1

See Table 16 for θJA.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

Table 16.

Package Type1 θ

64-Lead LFCSP (CP-64-4) 22 °C/W

1

Thermal impedance measurements were taken on a 4-layer board in still air

in accordance with EIA/JESD51-2.

Unit

JA

ESD CAUTION

Rev. A | Page 15 of 76

AD9516-5

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REFIN (REF 1)

REFIN (REF 2)

CPRSETVSVS

GND

RSETVSOUT0

OUT0

VS_LVPECL

OUT1

OUT1VSVS

646362616059585756555453525150

VS

49

1

VS

REFMON

LD

VCP

CP

STATUS

REF_SEL

SYNC

NC

10

NC

11

VS

12

VS

13

CLK

14

CLK

15

NC

16

SCLK

NOTES

1. NC = NO CONNE CT. DO NO T CONNECT TO THI S PIN.

2. EXPOSED DIE PAD MUST BE CONNECTED TO GND.

PIN 1 INDICATOR

2 3 4 5 6 7 8 9

171819202122232425262728293031

CS

NCNCNC

AD9516-5

TOP VIEW

(Not to Scale)

SDO

SDIO

RESET

Figure 6. Pin Configuration

Table 17. Pin Function Descriptions

Input/

Pin No.

1, 11, 12, 30,

Output Pin Type Mnemonic Description

I Power VS 3.3 V Power Pins. 31, 32, 38, 49, 50, 51, 57, 60, 61

2 O 3.3 V CMOS REFMON

Reference Monitor (Output). This pin has multiple selectable outputs; see Tab le 49, Register 0x01B.

3 O 3.3 V CMOS LD

Lock Detect (Output). This pin has multiple selectable outputs; see Table 4 9,

Register 0x01A. 4 I Power VCP 5 O Loop filter CP

Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.25 V.

Charge Pump (Output). This pin connects to an external loop filter. This pin can

be left unconnected if the PLL is not used. 6 O 3.3 V CMOS STATUS

Status (Output). This pin has multiple selectable outputs; see Table 49,

Register 0x017. 7 I 3.3 V CMOS REF_SEL

Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ

pull-down resistor. 8 I 3.3 V CMOS

SYNC

Manual Synchronizations and Manual Holdover. This pin initiates a manual

synchronization and is also used for manual holdover. Active low. This pin has

an internal 30 kΩ pull-up resistor. 9, 10, 15, 18,

N/A NC NC

No Connection. These pins can be left floating. 19, 20

13 I

Differential

CLK

Along with CLK

clock input

14 I

Differential clock input

Along with CLK, this is the differential input for the clock distribution section.

CLK

If a single-ended input is connected to the CLK pin, connect a 0.1 μF bypass

capacitor from CLK

LVPECL LVPECL

PD

OUT4

OUT5

VS_LVPECL

OUT6 (OUT6A)

48

OUT6 (OUT6B)

47

OUT7 (OUT7A)

46

OUT7 (OUT7B)

45

OUT5

LVDS/CMOS

w/FINE DELAY ADJUST

LVDS/CMOS

w/FI NE DELAY ADJUST

32

VSVSVS

LVPECL LVPECL

GND

44

OUT2

43

OUT2

42

VS_LVPECL

41

OUT3

40

OUT3

39

VS

38

GND

37

OUT9 (OUT9B)

36

OUT9 (OUT9A)

35

OUT8 (OUT8B)

34

OUT8 (OUT8A)

33

07972-003

, this is the differential input for the clock distribution section.

to ground.

Rev. A | Page 16 of 76

AD9516-5

Input/

Pin No.

16 I 3.3 V CMOS SCLK Serial Control Port Data Clock Signal. 17 I 3.3 V CMOS

21 O 3.3 V CMOS SDO Serial Control Port Unidirectional Serial Data Output. 22 I/O 3.3 V CMOS SDIO Serial Control Port Bidirectional Serial Data Input/Output. 23 I 3.3 V CMOS

24 I 3.3 V CMOS 25 O LVPECL OUT4 LVPECL Output; One Side of a Differential LVPECL Output.

26 O LVPECL 27, 41, 54 I Power VS_LVPECL Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins. 28 O LVPECL OUT5 LVPECL Output; One Side of a Differential LVPECL Output. 29 O LVPECL 33 O LVDS or CMOS OUT8 (OUT8A)

34 O LVDS or CMOS

35 O LVDS or CMOS OUT9 (OUT9A)

36 O LVDS or CMOS

37, 44, 59, EPAD

39 O LVPECL 40 O LVPECL OUT3 LVPECL Output; One Side of a Differential LVPECL Output.

42 O LVPECL 43 O LVPECL OUT2 LVPECL Output; One Side of a Differential LVPECL Output. 45 O LVDS or CMOS

46 O LVDS or CMOS OUT7 (OUT7A)

47 O LVDS or CMOS

48 O LVDS or CMOS OUT6 (OUT6A)

52 O LVPECL 53 O LVPECL OUT1 LVPECL Output; One Side of a Differential LVPECL Output.

55 O LVPECL 56 O LVPECL OUT0 LVPECL Output; One Side of a Differential LVPECL Output. 58 O

62 O

63 I

64 I

Output Pin Type Mnemonic Description

Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up

CS

resistor.

RESET PD

OUT4

OUT5

(OUT8B) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

OUT8

(OUT9B) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

OUT9

I GND GND

OUT3

OUT2

(OUT7B) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

OUT7

(OUT6B) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

OUT6

OUT1

OUT0

Current set resistor

Reference input

RSET A resistor connected to this pin sets internal bias currents. Nominal value = 4.12 kΩ.

CPRSET

(REF2) Along with REFIN, this pin is the differential input for the PLL reference.

REFIN

REFIN (REF1)

Chip Reset; Active Low. This pin has an internal 30 kΩ pull-up resistor. Chip Power-Down; Active Low. This pin has an internal 30 kΩ pull-up resistor.

LVPECL Output; One Side of a Differential LVPECL Output.

LVPECL Output; One Side of a Differential LVPECL Output. LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

CMOS Output.

CMOS Output. LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

CMOS Output.

CMOS Output. Ground Pins, Including External Paddle (EPAD). The external die paddle on the

bottom of the package must be connected to ground for proper operation. LVPECL Output; One Side of a Differential LVPECL Output.

LVPECL Output; One Side of a Differential LVPECL Output.

CMOS Output. LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

CMOS Output.

CMOS Output. LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

CMOS Output. LVPECL Output; One Side of a Differential LVPECL Output.

LVPECL Output; One Side of a Differential LVPECL Output.

A resistor connected to this pin sets the CP current range. Nominal value = 5.1 kΩ. This resistor can be omitted if the PLL is not used.

Alternatively, this pin is a single-ended input for REF2. This pin can be left unconnected when the PLL is not used.

Along with REFIN Alternatively, this pin is a single-ended input for REF1. This pin can be left

unconnected when the PLL is not used.

, this pin is the differential input for the PLL reference.

Rev. A | Page 17 of 76

AD9516-5

–

TYPICAL PERFORMANCE CHARACTERISTICS

300

280

260

240

220

200

180

CURRENT (mA)

160

140

120

100

0 500 1000 1500 2000 2500 3000

3 CHANNELS—6 LVPE CL

3 CHANNELS—3 LVPE CL

2 CHANNELS—2 LVPE CL

1 CHANNEL—1 LVPECL

FREQUENCY (MHz)

Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs

07972-007

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

CURRENT FROM CP P IN (mA)

1.0

0.5

PUMP DOWN PUMP UP

0

0 0.5 1.0 1.5 2.0 2.5 3.0

VOLTAGE ON CP PIN (V)

Figure 10. Charge Pump Characteristics at VCP = 3.3 V

07972-011

180

2 CHANNELS—4 LVDS

160

140

120

CURRENT (mA)

100

80

0 200 400 600 800

2 CHANNELS—2 LVDS

1 CHANNEL—1 LVDS

FREQUENCY (MHz )

Figure 8. Current vs. Frequency—LVDS Outputs

(Includes Clock Distribution Current Draw)

240

220

200

180

160

140

CURRENT (mA)

120

100

1 CHANNEL—2 CMOS

80

0220015010050

2 CHANNELS—8 CMOS

2 CHANNELS—2 CMOS

1 CHANNEL—1 CMOS

FREQUENCY (MHz )

Figure 9. Current vs. Frequency—CMOS Outputs with 10 pF Load

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

CURRENT FROM CP P IN (mA)

1.0

0.5

0

07972-008

PUMP DOWN PUMP UP

0 0.5 1.0 1.5 2.0 3.0 4.02.5 3.5 5.04.5

VOLTAGE ON CP PIN (V)

Figure 11. Charge Pump Characteristics at V

140

–145

–150

–155

(dBc/Hz)

–160

–165

PFD PHASE NOI SE REFERRED TO PFD INPUT

50

07972-009

–170

0.1 1 10010

PFD FREQUENCY (MHz)

Figure 12. PFD Phase Noise Referred to PFD Input vs. PFD Frequency

= 5.0 V

CP

07972-012

07972-013

Rev. A | Page 18 of 76

AD9516-5

–

210

–212

–214

–216

–218

0.4

0.2

0

–220

PLL FIGURE OF MERIT (dBc/ Hz)

–222

–224

022.01.51.00.5

SLEW RATE (V/n s)

Figure 13. PLL Figure of Merit vs. Slew Rate at REFIN/

1.0

0.6

0.2

–0.2

DIFFERENTIAL OUTPUT (V)

–0.6

–1.0

022015105

TIME (ns)

Figure 14. LVPECL Output (Differential) at 100 MHz

–0.2

DIFFERENTIAL OUTPUT (V)

–0.4

.5

07972-136

REFIN

5

07972-014

022015105

Figure 16. LVDS Output (Differential) at 100 MHz

0.4

0.2

0

–0.2

DIFFERENTIAL OUTPUT (V)

–0.4

021

Figure 17. LVDS Output (Differential) at 800 MHz

TIME (ns)

5

07972-016

07972-017

1.0

0.6

0.2

–0.2

DIFFERENTIAL OUTPUT (V)

–0.6

–1.0

021

TIME (ns)

Figure 15. LVPECL Output (Differential) at 1600 MHz

07972-015

Rev. A | Page 19 of 76

2.8

1.8

0.8

DIFFERENTIAL OUTPUT (V)

–0.2

0860 1004020

Figure 18. CMOS Output at 25 MHz

TIME (ns)

0

07972-018

AD9516-5

OUTPUT (V)

DIFFERENTIAL SWING (mV p-p)

2.8

1.8

0.8

–0.2

08611042

1600

1400

1200

1000

TIME (ns)

Figure 19. CMOS Output at 250 MHz

DIFFERENTIAL SWING (mV p-p)

2

07972-019

OUTPUT SWING (V)

700

600

500

08700600500400300200100

FREQUENCY (MHz )

Figure 21. LVDS Differential Swing vs. Frequency

(Using a Differential Probe Across the Output Pair)

3

2

1

CL = 2pF

C

= 10pF

L

= 20pF

C

L

00

07972-021

800

0321

FREQUENCY (GHz)

Figure 20. LVPECL Differential Swing vs. Frequency

07972-020

0

0 600500400300200100

OUTPUT FREQUENCY (MHz)

Figure 22. CMOS Output Swing vs. Frequency and Capacitive Load

07972-133

(Using a Differential Probe Across the Output Pair)

Rev. A | Page 20 of 76

AD9516-5

–

120

110

–125

–130

–135

–140

–145

PHASE NOISE (dBc/Hz)

–150

–155

–160

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 23. Phase Noise (Additive) LVPECL at 245.76 MHz, Divide-by-1

110

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

10 100M1k 10k 100k 1M 10M100

07972-026

FREQUENCY (Hz)

07972-142

Figure 26. Phase Noise (Additive) LVDS at 200 MHz, Divide-by-1

100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–160

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 24. Phase Noise (Additive) LVPECL at 200 MHz, Divide-by-5

100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 25. Phase Noise (Additive) LVPECL at 1600 MHz, Divide-by-1

–150

10 100M10M1M100k10k1k100

07972-027

FREQUENCY (Hz)

07972-130

Figure 27. Phase Noise (Additive) LVDS at 800 MHz, Divide-by-2

120

–130

–140

–150

PHASE NOISE (dBc/Hz)

–160

–170

10 100M10M1M100k10k1k100

07972-128

FREQUENCY (Hz)

07972-131

Figure 28. Phase Noise (Additive) CMOS at 50 MHz, Divide-by-20

Rev. A | Page 21 of 76

AD9516-5

–

100

–110

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

10 100M10M1M100k10k1k100

FREQUENCY (Hz)

Figure 29. Phase Noise (Additive) CMOS at 250 MHz, Divide-by-4

07972-132

1000

100

f

OBJ

10

1

NOTE: 375UI MAX AT 10Hz OFFSET IS THE

INPUT JITTER AMPLITUDE (UI p-p)

0.1

0.01 0.1 1 10 100 1000

MAXIMUM JIT TER THAT CAN BE GENERATED BY THE TEST EQUIPMENT. FAILURE POINT IS GREATER THAN 375UI.

JITTER FRE QUENCY (kHz)

OC-48 OBJECTIVE MASK AD9516

Figure 31. GR-253 Jitter Tolerance Plot

07972-148

120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

1k 100M10M1M100k10k

FREQUENCY (Hz)

Figure 30. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)

at 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz

07972-140

Rev. A | Page 22 of 76

AD9516-5

TERMINOLOGY

Phase Jitter and Phase Noise

An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution.

This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in decibels, dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given.

It is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval.

Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways.

Time Jitter

Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings varies. In a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution.

Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the signal-to-noise ratio (SNR) and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter.

Additive Phase Noise

Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. When there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors.

Additive Time Jitter

Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.

Rev. A | Page 23 of 76

ANALOG DEVICES AD9516-5 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

POWER SUPPLY REQUIREMENTS

PLL CHARACTERISTICS

CLOCK INPUTS

CLOCK OUTPUTS

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)

DELAY BLOCK ADDITIVE TIME JITTER

SERIAL CONTROL PORT

LD, STATUS, AND REFMON PINS

POWER DISSIPATION

TIMING CHARACTERISTICS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY