Analog Devices AD9515 Service Manual

1.6 GHz Clock Distribution IC, Dividers,

FEATURES

1.6 GHz differential clock input 2 programmable dividers

Divide-by in range from1 to 32 Phase select for coarse delay adjust

1.6 GHz LVPECL clock output Additive output jitter 225 fs rms

800 MHz/250 MHz LVDS/CMOS clock output

Additive output jitter 300 fs rms/290 fs rms Time delays up to 10 ns

Device configured with 4-level logic pins Space-saving, 32-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure AT E

GENERAL DESCRIPTION

Delay Adjust, Two Outputs

FUNCTIONAL BLOCK DIAGRAM

RSET VS GND

AD9515

/1. . . /32

CLK

CLKB

SYNCB

VREF S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

/1. . . /32

SETUP LOGIC

Figure 1.

AD9515

LVPECL

OUT0

OUT0B

LVDS/CMOS

Δ

t

OUT1

OUT1B

05597-001

The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

There are two independent clock outputs. One output is LVPECL, while the other output can be set to either LVDS or CMOS levels. The LVPECL output operates to 1.6 GHz. The other output operates to 800 MHz in LVDS mode and to 250 MHz in CMOS mode.

Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to the other clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The LVDS/CMOS output features a delay element with three selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each with 16 steps of fine adjustment.

The AD9515 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ⅓ V ⅔ V

. VS (3.3 V) and GND (0 V) provide the other two logic levels.

S

. The VREF pin provides a level of

S

The AD9515 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.

The AD9515 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is −40°C to +85°C.

AD9515

REVISION HISTORY

7/05—Revision 0: Initial Version

Power and Grounding Considerations and Power Supply

Rejection...................................................................................... 26

Phase Noise and Jitter Measurement Setups........................... 27

Outline Dimensions .......................................................................28

Ordering Guide .......................................................................... 28

Rev. 0 | Page 2 of 28

AD9515

SPECIFICATIONS

Typical (typ) is given for VS = 3.3 V ± 5%, TA = 25°C, R and maximum (max) values are given over full V

S

CLOCK INPUT

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

CLOCK INPUT (CLK)

Input Frequency Input Sensitivity Input Common-Mode Voltage, V Input Common-Mode Range, V

1

CM

CMR

0 1.6 GHz 150 mV p-p

1.5 1.6 1.7 V Self-biased; enables ac coupling

1.3 1.8 V With 200 mV p-p signal applied; dc-coupled Input Sensitivity, Single-Ended 150 mV p-p CLK ac-coupled; CLKB ac-bypassed to RF ground Input Resistance 4.0 4.8 5.6 kΩ Self-biased Input Capacitance 2 pF

1

A slew rate of 1 V/ns is required to meet jitter, phase noise, and propagation delay specifications.

CLOCK OUTPUTS

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL CLOCK OUTPUT Termination = 50 Ω to VS − 2 V

(OUT0) Differential Output Frequency 0 1.6 GHz Output High Voltage (VOH) VS − 1.1 VS − 0.96 VS − 0.82 V Output Low Voltage (VOL) VS − 1.90 VS − 1.76 VS − 1.52 V Output Differential Voltage (VOD) 640 790 960 mV

LVDS CLOCK OUTPUT Termination = 100 Ω differential

(OUT1) Differential Output Frequency 0 800 MHz Differential Output Voltage (VOD) 250 350 450 mV Delta V

OD

Output Offset Voltage (VOS) 1.125 1.23 1.375 V Delta V

OS

Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND

CMOS CLOCK OUTPUT Single-ended measurements; termination open

(OUT1) Single-Ended Complementary output on (OUT1B) Output Frequency 0 250 MHz With 5 pF load Output Voltage High (VOH) VS − 0.1 V @ 1 mA load Output Voltage Low (VOL) 0.1 V @ 1 mA load

30 mV

25 mV

= 4.12 kΩ, LVPECL swing = 790 mV, unless otherwise noted. Minimum (min)

SET

and TA (−40°C to +85°C) variation.

Rev. 0 | Page 3 of 28

AD9515

TIMING CHARACTERISTICS

CLK input slew rate = 1 V/ns or greater.

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL Termination = 50 Ω to VS − 2 V

Output Rise Time, t Output Fall Time, t

PROPAGATION DELAY, t

RP

FP

, CLK-TO-LVPECL OUT

PECL

Divide = 1 355 480 635 ps Divide = 2 − 32 395 530 710 ps Variation with Temperature 0.5 ps/°C

OUTPUT SKEW, LVPECL OUTPUT

LVPECL OUT Across Multiple Parts, t

SKP_AB3

1

LVDS Termination = 100 Ω differential

Output Rise Time, t Output Fall Time, t

PROPAGATION DELAY, t

RL

FL

, CLK-TO-LVDS OUT Delay off on OUT4

LVDS

OUT3 to OUT4 Divide = 1 1.00 1.25 1.55 ns Divide = 2 − 32 1.05 1.30 1.60 ns Variation with Temperature 0.9 ps/°C

OUTPUT SKEW, LVDS OUTPUT Delay off on OUT4

LVDS OUT Across Multiple Parts, t

SKV_AB

1

CMOS B outputs are inverted; termination = open Output Rise Time, t Output Fall Time, t

PROPAGATION DELAY, t

RC

FC

, CLK-TO-CMOS OUT Delay off on OUT4

CMOS

Divide = 1 1.10 1.45 1.75 ns Divide = 2 − 32 1.15 1.50 1.80 ns Variation with Temperature 1 ps/°C

OUTPUT SKEW, CMOS OUTPUT Delay off on OUT4

CMOS OUT Across Multiple Parts, t

SKC_AB

1

LVPECL-TO-LVDS OUT Everything the same; different logic type Output Delay, t

SKP_V

LVPECL-TO-CMOS OUT Everything the same; different logic type

Output Delay, t

SKP_C

DELAY ADJUST (OUT2; LVDS AND CMOS)

S0 = 1/3

Zero Scale Delay Time

2

Zero Scale Variation with Temperature 0.20 ps/°C

Full Scale Time Delay

2

Full Scale Variation with Temperature −0.38 ps/°C

S0 = 2/3

Zero Scale Delay Time

2

Zero Scale Variation with Temperature 0.31 ps/°C

Full Scale Time Delay

2

Full Scale Variation with Temperature −1.3 ps/°C

60 100 ps 20% to 80%, measured differentially 60 100 ps 80% to 20%, measured differentially

125 ps

200 350 ps 20% to 80%, measured differentially 210 350 ps 80% to 20%, measured differentially

230 ps

650 865 ps 20% to 80%; C 650 990 ps 80% to 20%; C

LOAD

= 3 pF = 3 pF

300 ps

700 970 1150 ps LVPECL to LVDS on same part

0.88 1.14 1.43 ns LVPECL to CMOS on same part

0.34 ns

1.7 ns

0.45 ns

5.9 ns

Rev. 0 | Page 4 of 28

AD9515

Parameter Min Typ Max Unit Test Conditions/Comments

S0 = 1

Zero Scale Delay Time

Zero Scale Variation with Temperature 0.47 ps/°C

Full Scale Time Delay

Full Scale Variation with Temperature −5 ps/°C Linearity, DNL 0.2 LSB Linearity, INL 0.2 LSB

1

This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.

2

Incremental delay; does not include propagation delay.

CLOCK OUTPUT PHASE NOISE

CLK input slew rate = 1 V/ns or greater.

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

CLK-TO-LVPECL ADDITIVE PHASE NOISE

CLK = 622.08 MHz, OUT = 622.08 MHz

Divide = 1

@ 10 Hz Offset −125 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −148 dBc/Hz @ 100 kHz Offset −153 dBc/Hz >1 MHz Offset −154 dBc/Hz

CLK = 622.08 MHz, OUT = 155.52 MHz

Divide = 4

@ 10 Hz Offset −128 dBc/Hz @ 100 Hz Offset −140 dBc/Hz @ 1 kHz Offset −148 dBc/Hz @ 10 kHz Offset −155 dBc/Hz @ 100 kHz Offset −161 dBc/Hz >1 MHz Offset −161 dBc/Hz

CLK = 622.08 MHz, OUT = 38.88 MHz

Divide = 16

@ 10 Hz Offset −135 dBc/Hz @ 100 Hz Offset −145 dBc/Hz @ 1 kHz Offset −158 dBc/Hz @ 10 kHz Offset −165 dBc/Hz @ 100 kHz Offset −165 dBc/Hz >1 MHz Offset −166 dBc/Hz

CLK = 491.52 MHz, OUT = 61.44 MHz

Divide = 8

@ 10 Hz Offset −131 dBc/Hz @ 100 Hz Offset −142 dBc/Hz @ 1 kHz Offset −153 dBc/Hz @ 10 kHz Offset −160 dBc/Hz @ 100 kHz Offset −165 dBc/Hz > 1 MHz Offset −165 dBc/Hz

2

0.56 ns

11.4 ns

Rev. 0 | Page 5 of 28

AD9515

Parameter Min Typ Max Unit Test Conditions/Comments

CLK = 491.52 MHz, OUT = 245.76 MHz

Divide = 2

@ 10 Hz Offset −125 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −151 dBc/Hz @ 100 kHz Offset −157 dBc/Hz >1 MHz Offset −158 dBc/Hz

CLK = 245.76 MHz, OUT = 61.44 MHz

Divide = 4

@ 10 Hz Offset −138 dBc/Hz @ 100 Hz Offset −144 dBc/Hz @ 1 kHz Offset −154 dBc/Hz @ 10 kHz Offset −163 dBc/Hz @ 100 kHz Offset −164 dBc/Hz >1 MHz Offset −165 dBc/Hz

CLK-TO-LVDS ADDITIVE PHASE NOISE

CLK = 622.08 MHz, OUT= 622.08 MHz

Divide = 1

@ 10 Hz Offset −100 dBc/Hz @ 100 Hz Offset −110 dBc/Hz @ 1 kHz Offset −118 dBc/Hz @ 10 kHz Offset −129 dBc/Hz @ 100 kHz Offset −135 dBc/Hz @ 1 MHz Offset −140 dBc/Hz >10 MHz Offset −148 dBc/Hz

CLK = 622.08 MHz, OUT = 155.52 MHz

Divide = 4

@ 10 Hz Offset −112 dBc/Hz @ 100 Hz Offset −122 dBc/Hz @ 1 kHz Offset −132 dBc/Hz @ 10 kHz Offset −142 dBc/Hz @ 100 kHz Offset −148 dBc/Hz @ 1 MHz Offset −152 dBc/Hz >10 MHz Offset −155 dBc/Hz

CLK = 491.52 MHz, OUT = 245.76 MHz

Divide = 2

@ 10 Hz Offset −108 dBc/Hz @ 100 Hz Offset −118 dBc/Hz @ 1 kHz Offset −128 dBc/Hz @ 10 kHz Offset −138 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −148 dBc/Hz >10 MHz Offset −154 dBc/Hz

Rev. 0 | Page 6 of 28

AD9515

Parameter Min Typ Max Unit Test Conditions/Comments

CLK = 491.52 MHz, OUT = 122.88 MHz

Divide = 4

@ 10 Hz Offset −118 dBc/Hz @ 100 Hz Offset −129 dBc/Hz @ 1 kHz Offset −136 dBc/Hz @ 10 kHz Offset −147 dBc/Hz @ 100 kHz Offset −153 dBc/Hz @ 1 MHz Offset −156 dBc/Hz >10 MHz Offset −158 dBc/Hz

CLK = 245.76 MHz, OUT = 245.76 MHz

Divide = 1

@ 10 Hz Offset −108 dBc/Hz @ 100 Hz Offset −118 dBc/Hz @ 1 kHz Offset −128 dBc/Hz @ 10 kHz Offset −138 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −148 dBc/Hz >10 MHz Offset −155 dBc/Hz

CLK = 245.76 MHz, OUT = 122.88 MHz

Divide = 2

@ 10 Hz Offset −118 dBc/Hz @ 100 Hz Offset −127 dBc/Hz @ 1 kHz Offset −137 dBc/Hz @ 10 kHz Offset −147 dBc/Hz @ 100 kHz Offset −154 dBc/Hz @ 1 MHz Offset −156 dBc/Hz >10 MHz Offset −158 dBc/Hz

CLK-TO-CMOS ADDITIVE PHASE NOISE

CLK = 245.76 MHz, OUT = 245.76 MHz

Divide = 1

@ 10 Hz Offset −110 dBc/Hz @ 100 Hz Offset −121 dBc/Hz @ 1 kHz Offset −130 dBc/Hz @ 10 kHz Offset −140 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −149 dBc/Hz >10 MHz Offset −156 dBc/Hz

CLK = 245.76 MHz, OUT = 61.44 MHz

Divide = 4

@ 10 Hz Offset −125 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −143 dBc/Hz @ 10 kHz Offset −152 dBc/Hz @ 100 kHz Offset −158 dBc/Hz @ 1 MHz Offset −160 dBc/Hz >10 MHz Offset −162 dBc/Hz

Rev. 0 | Page 7 of 28

AD9515

Parameter Min Typ Max Unit Test Conditions/Comments

CLK = 78.6432 MHz, OUT = 78.6432 MHz

Divide = 1

@ 10 Hz Offset −122 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −150 dBc/Hz @ 100 kHz Offset −155 dBc/Hz @ 1 MHz Offset −158 dBc/Hz >10 MHz Offset −160 dBc/Hz

CLK = 78.6432 MHz, OUT = 39.3216 MHz

Divide = 2

@ 10 Hz Offset −128 dBc/Hz @ 100 Hz Offset −136 dBc/Hz @ 1 kHz Offset −146 dBc/Hz @ 10 kHz Offset −155 dBc/Hz @ 100 kHz Offset −161 dBc/Hz >1 MHz Offset −162 dBc/Hz

CLOCK OUTPUT ADDITIVE TIME JITTER

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

CLK = 622.08 MHz 40 fs rms BW = 12 kHz − 20 MHz (OC-12)

LVPECL (OUT0) = 622.08 MHz OUT1 off Divide = 1

CLK = 622.08 MHz 55 fs rms BW = 12 kHz − 20 MHz (OC-3)

LVPECL (OUT0) = 155.52 MHz OUT1 off Divide = 4

CLK = 400 MHz 215 fs rms Calculated from SNR of ADC method

LVPECL (OUT0) = 100 MHz OUT1 off Divide = 4

CLK = 400 MHz 215 fs rms Calculated from SNR of ADC method

LVPECL (OUT0) = 100 MHz Divide = 4 LVDS (OUT1) = 100 MHz Interferer

CLK = 400 MHz 225 fs rms Calculated from SNR of ADC method

LVPECL (OUT0) = 100 MHz Divide = 4 LVDS (OUT1) = 50 MHz Interferer

CLK = 400 MHz 230 fs rms Calculated from SNR of ADC method

LVPECL (OUT0) = 100 MHz Divide = 4 CMOS (OUT1) = 50 MHz Interferer

LVDS OUTPUT ADDITIVE TIME JITTER Delay off

CLK = 400 MHz 300 fs rms Calculated from SNR of ADC method

LVDS (OUT1) = 100 MHz OUT0 off Divide = 4

CLK = 400 MHz 350 fs rms Calculated from SNR of ADC method

LVDS (OUT1) = 100 MHz OUT0 off Divide = 4 LVPECL (OUT0)= 50 MHz Interferer

Rev. 0 | Page 8 of 28

AD9515

Parameter Min Typ Max Unit Test Conditions/Comments

CMOS OUTPUT ADDITIVE TIME JITTER Delay off

CLK = 400 MHz 290 fs rms Calculated from SNR of ADC method

CMOS (OUT1) = 100 MHz Divide = 4

CLK = 400 MHz 315 fs rms Calculated from SNR of ADC method

CMOS (OUT1) = 100 MHz Divide = 4 LVPECL (OUT0) = 50 MHz Interferer

DELAY BLOCK ADDITIVE TIME JITTER

Delay FS = 1.5 ns Fine Adj. 00000 0.71 ps rms Delay FS = 1.5 ns Fine Adj. 11111 1.2 ps rms Delay FS = 5 ns Fine Adj. 00000 1.3 ps rms Delay FS = 5 ns Fine Adj. 11111 2.7 ps rms Delay FS = 10 ns Fine Adj. 00000 2.0 ps rms Delay FS = 10 ns Fine Adj. 11111 2.8 ps rms

1

This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter

should be added to this value using the root sum of the squares (RSS) method.

SYNCB, VREF, AND SETUP PINS

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

SYNCB

Logic High 2.7 V Logic Low 0.40 V Capacitance 2 pF

VREF

Output Voltage 0.62 V

S0 TO S10

Levels

0 0.1 V 1/3 0.2 V 2/3 0.55 V 1 0.9 V

1

S

100 MHz output; incremental additive jitter

0.76 V

0.45 V

0.8 V

S

V Minimum − maximum from 0 mA to 1 mA load

S

V V

S

V

Rev. 0 | Page 9 of 28

Analog Devices AD9515 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

CLOCK INPUT

CLOCK OUTPUTS

TIMING CHARACTERISTICS

CLOCK OUTPUT PHASE NOISE

CLOCK OUTPUT ADDITIVE TIME JITTER

SYNCB, VREF, AND SETUP PINS