Analog Devices AD9515 Service Manual

1.6 GHz Clock Distribution IC, Dividers,

FEATURES

1.6 GHz differential clock input 2 programmable dividers

Divide-by in range from1 to 32 Phase select for coarse delay adjust

1.6 GHz LVPECL clock output Additive output jitter 225 fs rms

800 MHz/250 MHz LVDS/CMOS clock output

Additive output jitter 300 fs rms/290 fs rms Time delays up to 10 ns

Device configured with 4-level logic pins Space-saving, 32-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure AT E

GENERAL DESCRIPTION

Delay Adjust, Two Outputs

FUNCTIONAL BLOCK DIAGRAM

RSET VS GND

AD9515

/1. . . /32

CLK

CLKB

SYNCB

VREF S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

/1. . . /32

SETUP LOGIC

Figure 1.

AD9515

LVPECL

OUT0

OUT0B

LVDS/CMOS

Δ

t

OUT1

OUT1B

05597-001

The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

There are two independent clock outputs. One output is LVPECL, while the other output can be set to either LVDS or CMOS levels. The LVPECL output operates to 1.6 GHz. The other output operates to 800 MHz in LVDS mode and to 250 MHz in CMOS mode.

Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to the other clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The LVDS/CMOS output features a delay element with three selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each with 16 steps of fine adjustment.

The AD9515 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ⅓ V ⅔ V

. VS (3.3 V) and GND (0 V) provide the other two logic levels.

S

. The VREF pin provides a level of

S

The AD9515 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.

The AD9515 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is −40°C to +85°C.

AD9515

REVISION HISTORY

7/05—Revision 0: Initial Version

Power and Grounding Considerations and Power Supply

Rejection...................................................................................... 26

Phase Noise and Jitter Measurement Setups........................... 27

Outline Dimensions .......................................................................28

Ordering Guide .......................................................................... 28

Rev. 0 | Page 2 of 28

AD9515

SPECIFICATIONS

Typical (typ) is given for VS = 3.3 V ± 5%, TA = 25°C, R and maximum (max) values are given over full V

S

CLOCK INPUT

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

CLOCK INPUT (CLK)

Input Frequency Input Sensitivity Input Common-Mode Voltage, V Input Common-Mode Range, V

1

CM

CMR

0 1.6 GHz 150 mV p-p

1.5 1.6 1.7 V Self-biased; enables ac coupling

1.3 1.8 V With 200 mV p-p signal applied; dc-coupled Input Sensitivity, Single-Ended 150 mV p-p CLK ac-coupled; CLKB ac-bypassed to RF ground Input Resistance 4.0 4.8 5.6 kΩ Self-biased Input Capacitance 2 pF

1

A slew rate of 1 V/ns is required to meet jitter, phase noise, and propagation delay specifications.

CLOCK OUTPUTS

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL CLOCK OUTPUT Termination = 50 Ω to VS − 2 V

(OUT0) Differential Output Frequency 0 1.6 GHz Output High Voltage (VOH) VS − 1.1 VS − 0.96 VS − 0.82 V Output Low Voltage (VOL) VS − 1.90 VS − 1.76 VS − 1.52 V Output Differential Voltage (VOD) 640 790 960 mV

LVDS CLOCK OUTPUT Termination = 100 Ω differential

(OUT1) Differential Output Frequency 0 800 MHz Differential Output Voltage (VOD) 250 350 450 mV Delta V

OD

Output Offset Voltage (VOS) 1.125 1.23 1.375 V Delta V

OS

Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND

CMOS CLOCK OUTPUT Single-ended measurements; termination open

(OUT1) Single-Ended Complementary output on (OUT1B) Output Frequency 0 250 MHz With 5 pF load Output Voltage High (VOH) VS − 0.1 V @ 1 mA load Output Voltage Low (VOL) 0.1 V @ 1 mA load

30 mV

25 mV

= 4.12 kΩ, LVPECL swing = 790 mV, unless otherwise noted. Minimum (min)

SET

and TA (−40°C to +85°C) variation.

Rev. 0 | Page 3 of 28

AD9515

TIMING CHARACTERISTICS

CLK input slew rate = 1 V/ns or greater.

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL Termination = 50 Ω to VS − 2 V

Output Rise Time, t Output Fall Time, t

PROPAGATION DELAY, t

RP

FP

, CLK-TO-LVPECL OUT

PECL

Divide = 1 355 480 635 ps Divide = 2 − 32 395 530 710 ps Variation with Temperature 0.5 ps/°C

OUTPUT SKEW, LVPECL OUTPUT

LVPECL OUT Across Multiple Parts, t

SKP_AB3

1

LVDS Termination = 100 Ω differential

Output Rise Time, t Output Fall Time, t

PROPAGATION DELAY, t

RL

FL

, CLK-TO-LVDS OUT Delay off on OUT4

LVDS

OUT3 to OUT4 Divide = 1 1.00 1.25 1.55 ns Divide = 2 − 32 1.05 1.30 1.60 ns Variation with Temperature 0.9 ps/°C

OUTPUT SKEW, LVDS OUTPUT Delay off on OUT4

LVDS OUT Across Multiple Parts, t

SKV_AB

1

CMOS B outputs are inverted; termination = open Output Rise Time, t Output Fall Time, t

PROPAGATION DELAY, t

RC

FC

, CLK-TO-CMOS OUT Delay off on OUT4

CMOS

Divide = 1 1.10 1.45 1.75 ns Divide = 2 − 32 1.15 1.50 1.80 ns Variation with Temperature 1 ps/°C

OUTPUT SKEW, CMOS OUTPUT Delay off on OUT4

CMOS OUT Across Multiple Parts, t

SKC_AB

1

LVPECL-TO-LVDS OUT Everything the same; different logic type Output Delay, t

SKP_V

LVPECL-TO-CMOS OUT Everything the same; different logic type

Output Delay, t

SKP_C

DELAY ADJUST (OUT2; LVDS AND CMOS)

S0 = 1/3

Zero Scale Delay Time

2

Zero Scale Variation with Temperature 0.20 ps/°C

Full Scale Time Delay

2

Full Scale Variation with Temperature −0.38 ps/°C

S0 = 2/3

Zero Scale Delay Time

2

Zero Scale Variation with Temperature 0.31 ps/°C

Full Scale Time Delay

2

Full Scale Variation with Temperature −1.3 ps/°C

60 100 ps 20% to 80%, measured differentially 60 100 ps 80% to 20%, measured differentially

125 ps

200 350 ps 20% to 80%, measured differentially 210 350 ps 80% to 20%, measured differentially

230 ps

650 865 ps 20% to 80%; C 650 990 ps 80% to 20%; C

LOAD

= 3 pF = 3 pF

300 ps

700 970 1150 ps LVPECL to LVDS on same part

0.88 1.14 1.43 ns LVPECL to CMOS on same part

0.34 ns

1.7 ns

0.45 ns

5.9 ns

Rev. 0 | Page 4 of 28

AD9515

Parameter Min Typ Max Unit Test Conditions/Comments

S0 = 1

Zero Scale Delay Time

Zero Scale Variation with Temperature 0.47 ps/°C

Full Scale Time Delay

Full Scale Variation with Temperature −5 ps/°C Linearity, DNL 0.2 LSB Linearity, INL 0.2 LSB

1

This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.

2

Incremental delay; does not include propagation delay.

CLOCK OUTPUT PHASE NOISE

CLK input slew rate = 1 V/ns or greater.

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

CLK-TO-LVPECL ADDITIVE PHASE NOISE

CLK = 622.08 MHz, OUT = 622.08 MHz

Divide = 1

@ 10 Hz Offset −125 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −148 dBc/Hz @ 100 kHz Offset −153 dBc/Hz >1 MHz Offset −154 dBc/Hz

CLK = 622.08 MHz, OUT = 155.52 MHz

Divide = 4

@ 10 Hz Offset −128 dBc/Hz @ 100 Hz Offset −140 dBc/Hz @ 1 kHz Offset −148 dBc/Hz @ 10 kHz Offset −155 dBc/Hz @ 100 kHz Offset −161 dBc/Hz >1 MHz Offset −161 dBc/Hz

CLK = 622.08 MHz, OUT = 38.88 MHz

Divide = 16

@ 10 Hz Offset −135 dBc/Hz @ 100 Hz Offset −145 dBc/Hz @ 1 kHz Offset −158 dBc/Hz @ 10 kHz Offset −165 dBc/Hz @ 100 kHz Offset −165 dBc/Hz >1 MHz Offset −166 dBc/Hz

CLK = 491.52 MHz, OUT = 61.44 MHz

Divide = 8

@ 10 Hz Offset −131 dBc/Hz @ 100 Hz Offset −142 dBc/Hz @ 1 kHz Offset −153 dBc/Hz @ 10 kHz Offset −160 dBc/Hz @ 100 kHz Offset −165 dBc/Hz > 1 MHz Offset −165 dBc/Hz

2

0.56 ns

11.4 ns

Rev. 0 | Page 5 of 28

AD9515

Parameter Min Typ Max Unit Test Conditions/Comments

CLK = 491.52 MHz, OUT = 245.76 MHz

Divide = 2

@ 10 Hz Offset −125 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −151 dBc/Hz @ 100 kHz Offset −157 dBc/Hz >1 MHz Offset −158 dBc/Hz

CLK = 245.76 MHz, OUT = 61.44 MHz

Divide = 4

@ 10 Hz Offset −138 dBc/Hz @ 100 Hz Offset −144 dBc/Hz @ 1 kHz Offset −154 dBc/Hz @ 10 kHz Offset −163 dBc/Hz @ 100 kHz Offset −164 dBc/Hz >1 MHz Offset −165 dBc/Hz

CLK-TO-LVDS ADDITIVE PHASE NOISE

CLK = 622.08 MHz, OUT= 622.08 MHz

Divide = 1

@ 10 Hz Offset −100 dBc/Hz @ 100 Hz Offset −110 dBc/Hz @ 1 kHz Offset −118 dBc/Hz @ 10 kHz Offset −129 dBc/Hz @ 100 kHz Offset −135 dBc/Hz @ 1 MHz Offset −140 dBc/Hz >10 MHz Offset −148 dBc/Hz

CLK = 622.08 MHz, OUT = 155.52 MHz

Divide = 4

@ 10 Hz Offset −112 dBc/Hz @ 100 Hz Offset −122 dBc/Hz @ 1 kHz Offset −132 dBc/Hz @ 10 kHz Offset −142 dBc/Hz @ 100 kHz Offset −148 dBc/Hz @ 1 MHz Offset −152 dBc/Hz >10 MHz Offset −155 dBc/Hz

CLK = 491.52 MHz, OUT = 245.76 MHz

Divide = 2

@ 10 Hz Offset −108 dBc/Hz @ 100 Hz Offset −118 dBc/Hz @ 1 kHz Offset −128 dBc/Hz @ 10 kHz Offset −138 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −148 dBc/Hz >10 MHz Offset −154 dBc/Hz

Rev. 0 | Page 6 of 28

AD9515

Parameter Min Typ Max Unit Test Conditions/Comments

CLK = 491.52 MHz, OUT = 122.88 MHz

Divide = 4

@ 10 Hz Offset −118 dBc/Hz @ 100 Hz Offset −129 dBc/Hz @ 1 kHz Offset −136 dBc/Hz @ 10 kHz Offset −147 dBc/Hz @ 100 kHz Offset −153 dBc/Hz @ 1 MHz Offset −156 dBc/Hz >10 MHz Offset −158 dBc/Hz

CLK = 245.76 MHz, OUT = 245.76 MHz

Divide = 1

@ 10 Hz Offset −108 dBc/Hz @ 100 Hz Offset −118 dBc/Hz @ 1 kHz Offset −128 dBc/Hz @ 10 kHz Offset −138 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −148 dBc/Hz >10 MHz Offset −155 dBc/Hz

CLK = 245.76 MHz, OUT = 122.88 MHz

Divide = 2

@ 10 Hz Offset −118 dBc/Hz @ 100 Hz Offset −127 dBc/Hz @ 1 kHz Offset −137 dBc/Hz @ 10 kHz Offset −147 dBc/Hz @ 100 kHz Offset −154 dBc/Hz @ 1 MHz Offset −156 dBc/Hz >10 MHz Offset −158 dBc/Hz

CLK-TO-CMOS ADDITIVE PHASE NOISE

CLK = 245.76 MHz, OUT = 245.76 MHz

Divide = 1

@ 10 Hz Offset −110 dBc/Hz @ 100 Hz Offset −121 dBc/Hz @ 1 kHz Offset −130 dBc/Hz @ 10 kHz Offset −140 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −149 dBc/Hz >10 MHz Offset −156 dBc/Hz

CLK = 245.76 MHz, OUT = 61.44 MHz

Divide = 4

@ 10 Hz Offset −125 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −143 dBc/Hz @ 10 kHz Offset −152 dBc/Hz @ 100 kHz Offset −158 dBc/Hz @ 1 MHz Offset −160 dBc/Hz >10 MHz Offset −162 dBc/Hz

Rev. 0 | Page 7 of 28

AD9515

Parameter Min Typ Max Unit Test Conditions/Comments

CLK = 78.6432 MHz, OUT = 78.6432 MHz

Divide = 1

@ 10 Hz Offset −122 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −150 dBc/Hz @ 100 kHz Offset −155 dBc/Hz @ 1 MHz Offset −158 dBc/Hz >10 MHz Offset −160 dBc/Hz

CLK = 78.6432 MHz, OUT = 39.3216 MHz

Divide = 2

@ 10 Hz Offset −128 dBc/Hz @ 100 Hz Offset −136 dBc/Hz @ 1 kHz Offset −146 dBc/Hz @ 10 kHz Offset −155 dBc/Hz @ 100 kHz Offset −161 dBc/Hz >1 MHz Offset −162 dBc/Hz

CLOCK OUTPUT ADDITIVE TIME JITTER

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

CLK = 622.08 MHz 40 fs rms BW = 12 kHz − 20 MHz (OC-12)

LVPECL (OUT0) = 622.08 MHz OUT1 off Divide = 1

CLK = 622.08 MHz 55 fs rms BW = 12 kHz − 20 MHz (OC-3)

LVPECL (OUT0) = 155.52 MHz OUT1 off Divide = 4

CLK = 400 MHz 215 fs rms Calculated from SNR of ADC method

LVPECL (OUT0) = 100 MHz OUT1 off Divide = 4

CLK = 400 MHz 215 fs rms Calculated from SNR of ADC method

LVPECL (OUT0) = 100 MHz Divide = 4 LVDS (OUT1) = 100 MHz Interferer

CLK = 400 MHz 225 fs rms Calculated from SNR of ADC method

LVPECL (OUT0) = 100 MHz Divide = 4 LVDS (OUT1) = 50 MHz Interferer

CLK = 400 MHz 230 fs rms Calculated from SNR of ADC method

LVPECL (OUT0) = 100 MHz Divide = 4 CMOS (OUT1) = 50 MHz Interferer

LVDS OUTPUT ADDITIVE TIME JITTER Delay off

CLK = 400 MHz 300 fs rms Calculated from SNR of ADC method

LVDS (OUT1) = 100 MHz OUT0 off Divide = 4

CLK = 400 MHz 350 fs rms Calculated from SNR of ADC method

LVDS (OUT1) = 100 MHz OUT0 off Divide = 4 LVPECL (OUT0)= 50 MHz Interferer

Rev. 0 | Page 8 of 28

AD9515

Parameter Min Typ Max Unit Test Conditions/Comments

CMOS OUTPUT ADDITIVE TIME JITTER Delay off

CLK = 400 MHz 290 fs rms Calculated from SNR of ADC method

CMOS (OUT1) = 100 MHz Divide = 4

CLK = 400 MHz 315 fs rms Calculated from SNR of ADC method

CMOS (OUT1) = 100 MHz Divide = 4 LVPECL (OUT0) = 50 MHz Interferer

DELAY BLOCK ADDITIVE TIME JITTER

Delay FS = 1.5 ns Fine Adj. 00000 0.71 ps rms Delay FS = 1.5 ns Fine Adj. 11111 1.2 ps rms Delay FS = 5 ns Fine Adj. 00000 1.3 ps rms Delay FS = 5 ns Fine Adj. 11111 2.7 ps rms Delay FS = 10 ns Fine Adj. 00000 2.0 ps rms Delay FS = 10 ns Fine Adj. 11111 2.8 ps rms

1

This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter

should be added to this value using the root sum of the squares (RSS) method.

SYNCB, VREF, AND SETUP PINS

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

SYNCB

Logic High 2.7 V Logic Low 0.40 V Capacitance 2 pF

VREF

Output Voltage 0.62 V

S0 TO S10

Levels

0 0.1 V 1/3 0.2 V 2/3 0.55 V 1 0.9 V

1

S

100 MHz output; incremental additive jitter

0.76 V

0.45 V

0.8 V

S

V Minimum − maximum from 0 mA to 1 mA load

S

V V

S

V

Rev. 0 | Page 9 of 28

AD9515

POWER

Table 7.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER-ON SYNCHRONIZATION

VS Transit Time from 2.2 V to 3.1 V

POWER DISSIPATION 215 285 380 mW

300 370 465 mW

330 405 510 mW Both outputs on. LVPECL, CMOS (divide = 2);

POWER DELTA

Divider (Divide = 2 to Divide = 1) 15 30 45 mW For each divider. No clock. LVPECL Output 65 90 125 mW For each output. No clock. LVDS Output 20 50 85 mW No clock. CMOS Output (Static) 30 40 50 mW No clock. CMOS Output (@ 62.5 MHz) 80 110 140 mW Single-ended. At 62.5 MHz out with 5 pF load. CMOS Output (@ 125 MHz) 110 150 190 mW Single-ended. At 125 MHz out with 5 pF load. Delay Block 30 45 65 mW Off to 1.5 ns fs, delay word = 60; output clocking at 62.5 MHz.

1

This is the rise time of the VS supply that is required to ensure that a synchronization of the outputs occurs on power-up. The critical factor is the time it takes the VS to

transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs will not be synchronized.

1

35 ms See the Power-On SYNC section.

Both outputs on. LVPECL (divide = 2), LVDS (divide = 2). No clock. Does not include power dissipated in external resistors.

Both outputs on. LVPECL (divide = 2), CMOS (divide = 2); at 62.5 MHz out (5 pF load).

at 125 MHz out (5 pF load).

Rev. 0 | Page 10 of 28

AD9515

TIMING DIAGRAMS

CLK

t

CLK

DIFFERENTIAL

t

PECL

t

LVDS

t

CMOS

Figure 2. CLK/CLKB to Clock Output Timing, Divide = 1 Mode

DIFFERENTIAL

80%

LVPECL

20%

t

RP

Figure 3. LVPECL Timing, Differential

80%

LVDS

20%

t

05597-002

RL

t

FL

05597-065

Figure 4. LVDS Timing, Differential

SINGLE-ENDED

80%

CMOS

3pF LOAD

20%

t

FP

05597-064

t

RC

t

FC

05597-066

Figure 5. CMOS Timing, Single-Ended, 3 pF Load

Rev. 0 | Page 11 of 28

AD9515

ABSOLUTE MAXIMUM RATINGS

Table 8.

With Respect

Parameter or Pin

to

Min Max Unit

VS GND −0.3 +3.6 V RSET GND −0.3 VS + 0.3 V CLK, CLKB GND −0.3 VS + 0.3 V CLK CLKB −1.2 +1.2 V OUT0, OUT0B, OUT1, OUT1B GND −0.3 VS + 0.3 V Junction Temperature

1

150 °C Storage Temperature −65 +150 °C Lead Temperature (10 sec) 300 °C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

2

Thermal Resistance

3

32-Lead LFCSP

θ

= 36.6°C/W

JA

1

See Thermal Characteristics for θJA.

2

Thermal impedance measurements were taken on a 4-layer board in still air

in accordance with EIA/JESD51-7.

3

The external pad of this package must be soldered to adequate copper land

on board.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 12 of 28

AD9515

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VS

GND

VS 30

29

AD9515

TOP VIEW

11

12 S5

S6

DNC 28

13 S4

RSET

31

32

1VS 2CLK 3CLKB 4VS

9

10

S8

S7

(Not to Scale)

5SYNCB 6VREF 7S10 8S9

Figure 6. 32-Lead LFCSP Pin Configuration

S0

DNC

VS

25

27

26

THE EXPOSED PADDLE

24 VS 23 OUT0 22 OUT0B 21 VS 20 VS 19 OUT1 18 OUT1B 17 VS

15

14

16

S2

S3

S1

05597-005

IS AN ELECTRICAL AND

THERMAL CONNECTION

25

24

EXPOSED PAD

(BOTTOM VIEW)

17

16

GND

32

1

8

9

05597-006

Figure 7. Exposed Paddle

Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be soldered to a PCB land that functions as both a heat dissipation path as well as an electrical ground (analog).

Table 9. Pin Function Descriptions

Pin No. Mnemonic Description

1, 4, 17, 20, 21, 24, 26, 29, 30 VS Power Supply (3.3 V). 2 CLK Clock Input. 3 CLKB Complementary Clock Input. Used in conjunction with CLK. 5 SYNCB Used to Synchronize the Outputs; Active Low Signal. 6 VREF Provides 2/3 VS Reference Voltage for Use with Programming Pins S0 to S10. 7 to 16, 25 S0 to S10 Programming Pins. These pins determine the operation of the AD9515; 4-state logic. 18 OUT1B Complementary LVDS/Inverted CMOS Output. Includes a delay block. 19 OUT1 LVDS/CMOS Output. Includes a delay block. 22 OUT0B Complementary LVPECL Output. 23 OUT0 LVPECL Output. 27, 28 DNC Do Not Connect. 31, Exposed Paddle GND Ground. The exposed paddle on the back of the chip is also GND. 32 RSET Current Sets Resistor to Ground. Nominal value = 4.12 kΩ.

Rev. 0 | Page 13 of 28

AD9515

TERMINOLOGY

Phase Jitter and Phase Noise

An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 degrees for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although there are many causes that can contribute to phase jitter, one major component is due to random noise that is characterized statistically as being Gaussian (normal) in distribution.

This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given.

It is also meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval.

Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways.

Time Jitter

Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings is seen to vary. For a square wave, the time jitter is seen as a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Since these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution.

Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the SNR and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter.

Additive Phase Noise

It is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device affects the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contribute their own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise.

Additive Time Jitter

It is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device will affect the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contribute their own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.

Rev. 0 | Page 14 of 28

AD9515

TYPICAL PERFORMANCE CHARACTERISTICS

0.3

0.5

0.2

POWER (W)

0.1

LVPECL (DIV ON)

LVPECL (DIV = 1)

LVDS (DIV ON)

OUTPUT FREQUENCY (MHz)

Figure 8. Power vs. Frequency—LVPECL, LVDS

0.4

POWER (W)

0.3

16001200800400

05597-009

0.2 0 12080 100604020

LVPECL (DIV ON) + CMOS (DIV ON)

LVPECL (DIV OFF) + CMOS (DIV OFF)

OUTPUT FREQUENCY (MHz)

05597-008

Figure 10. Power vs. Frequency—LVPECL, CMOS

START 300kHz STOP 5GHz

Figure 9. CLK Smith Chart (Evaluation Board)

05597-097

Rev. 0 | Page 15 of 28

AD9515

1.8

1.7

1.6

1.5

1.4

DIFFERENTIAL SWING (V p-p)

1.3

1.2

VERT 500mV/DIV HORIZ 200ps/DIV

Figure 11. LVPECL Differential Output @ 1600 MHz

05597-095

100 16001100600

OUTPUT FREQUENCY (MHz)

Figure 14. LVPECL Differential Output Swing vs. Frequency

750

700

05597-012

VERT 100mV/DIV HORIZ 500ps/DIV

Figure 12. LVDS Differential Output @ 800 MHz

650

600

550

DIFFERENTIAL SWING (mV p-p)

500

05597-010

100 900700500300

OUTPUT FREQUENCY (MHz)

05597-013

Figure 15. LVDS Differential Output Swing vs. Frequency

3.5 2pF

3.0

2.5

)

PK

2.0

1.5

OUTPUT (V

1.0

0.5

10pF

20pF

VERT 500mV/DIV HORIZ 1ns/DIV

Figure 13. CMOS Single-Ended Output @ 250 MHz with 10 pF Load

05597-011

Rev. 0 | Page 16 of 28

0

0 600500400300200100

OUTPUT FREQUENCY (MHz)

Figure 16. CMOS Single-Ended Output Swing vs. Frequency and Load

05597-014

AD9515

–110

–120

–130

–140

L(f) (dBc/Hz)

–150

–160

–170

10 10M1M100k10k1k100

OFFSET (Hz)

Figure 17. Additive Phase Noise—LVPECL, Divide = 1, 245.76 MHz

–80

–90

–100

–110

–120

–130

L(f) (dBc/Hz)

–140

–120

–130

–140

L(f) (dBc/Hz)

–150

–160

–170

10 10M1M100k10k1k100

05597-051

OFFSET (Hz)

05597-052

Figure 20. Additive Phase Noise—LVPECL, Divide = 1, 622.08 MHz

–80

–90

–100

–110

–120

–130

L(f) (dBc/Hz)

–140

–150

–160

–170

10 10M1M100k10k1k100

OFFSET (Hz)

Figure 18. Additive Phase Noise—LVDS, Divide = 1, 245.76 MHz

–100

–110

–120

–130

–140

L(f) (dBc/Hz)

–150

–160

–170

10 10M1M100k10k1k100

OFFSET (Hz)

Figure 19. Additive Phase Noise—CMOS, Divide = 1, 245.76 MHz

05597-048

05597-045

–150

–160

–170

10 10M1M100k10k1k100

OFFSET (Hz)

Figure 21. Additive Phase Noise—LVDS, Divide = 2, 122.88 MHz

–100

–110

–120

–130

–140

L(f) (dBc/Hz)

–150

–160

–170

10 10M1M100k10k1k100

OFFSET (Hz)

Figure 22. Additive Phase Noise—CMOS, Divide = 4, 61.44 MHz

05597-049

05597-046

Rev. 0 | Page 17 of 28

AD9515

S

FUNCTIONAL DESCRIPTION

OVERALL

The AD9515 provides for the distribution of its input clock on one or both of its outputs. OUT0 is an LVPECL output. OUT1 can be set to either LVDS or CMOS logic levels. Each output has its own divider that can be set for a divide ratio selected from a list of integer values from 1 (bypassed) to 32.

OUT1 includes an analog delay block that can be set to add an additional delay of 1.5 ns, 5 ns, or 10 ns full scale, each with 16 levels of fine adjustment.

CLK, CLKB—DIFFERENTIAL CLOCK INPUT

The CLK and CLKB pins are differential clock input pins. This input works up to 1600 MHz. The jitter performance is degraded by a slew rate below 1 V/ns. The input level should be between approximately 150 mV p-p to no more than 2 V p-p. Anything greater can result in turning on the protection diodes on the input pins.

Figure 23 for the CLK equivalent input circuit. This

See input is fully differential and self-biased. The signal should be ac-coupled using capacitors. If a single-ended input must be used, this can be accommodated by ac coupling to one side of the differential input only. The other side of the input should be bypassed to a quiet ac ground by a capacitor.

CLOCK INPUT

V

CLK

CLKB

S

2.5kΩ

5kΩ

2.5kΩ

Figure 23. Clock Input Equivalent Circuit

STAGE

05597-021

SYNCHRONIZATION

Power-On SYNC

A power-on sync (POS) is issued when the VS power supply is turned on to ensure that the outputs start in synchronization. The power-on sync works only if the V tions the region from 2.2 V to 3.1 V within 35 ms. The POS can occur up to 65 ms after V

crosses 2.2 V. Only outputs which are

S

not divide = 1 are synchronized.

power supply transi-

S

3.1V

2.2V

35ms

MAX

V

S

0V

CLK

CLOCK FREQUENCY

OUT

IS EXAMPLE ONLY

DIVIDE = 2 PHASE = 0

INTERNAL SYNC NODE

< 65ms

Figure 24. Power-On Sync Timing

SYNCB

If the setup configuration of the AD9515 is changed during operation, the outputs can become unsynchronized. The outputs can be re-synchronized to each other at any time. Synchronization occurs when the SYNCB pin is pulled low and released. The clock outputs (except where divide = 1) are forced into a fixed state (determined by the divide and phase settings) and held there in a static condition, until the SYNCB pin is returned to high. Upon release of the SYNCB pin, after four cycles of the clock signal at CLK, all outputs continue clocking in synchronicity (except where divide = 1).

When divide = 1 for an output, that output is not affected by SYNCB.

3 CLK CYCLES 4 CLK CYCLES

CLK

EXAMPLE: DIVIDE ≥ 8

OUT

PHASE = 0

YNCB

Figure 25. SYNCB Timing with Clock Present

4 CLK CYCLES

CLK

DEPENDS ON PREVIOUS STATE

OUT

SYNCB

MIN 5ns

§§§

DEPENDS ON PREVIOUS STATE AND DIVIDE RATIO

§

Figure 26. SYNCB Timing with No Clock Present

The outputs of the AD9515 can be synchronized by using the SYNCB pin. Synchronization aligns the phases of the clock outputs, respecting any phase offset that has been set on an output’s divider.

SYNCB

3.3V

EXAMPLE DIVIDE RATIO PHASE = 0

05597-094

05597-093

05597-092

05597-022

Figure 27. SYNCB Equivalent Input Circuit

Rev. 0 | Page 18 of 28

AD9515

V

Synchronization is initiated by pulling the SYNCB pin low for a minimum of 5 ns. The input clock does not have to be present at the time the command is issued. The synchronization occurs after four input clock cycles.

provided by the VREF pin. All setup pins requiring the ⅔V level must be tied to the VREF pin.

S

The synchronization applies to clock outputs:

• that are not turned OFF

• where the divider is not divide = 1 (divider bypassed)

An output with its divider set to divide = 1 (divider bypassed) is always synchronized with the input clock, with a propagation delay.

The SYNCB pin must be pulled up for normal operation. Do not let the SYNCB pin float.

R

RESISTOR

SET

The internal bias currents of the AD9515 are set by the

resistor. This resistor should be as close as possible to

R

SET

the value given as a condition in the (R

= 4.12 kΩ). This is a standard 1% resistor value and should

SET

Specifications section

be readily obtainable. The bias currents set by this resistor determine the logic levels and operating conditions of the internal blocks of the AD9515. The performance figures given in the

Specifications section assume that this resistor value is

used for R

SET

.

VREF

The VREF pin provides a voltage level of ⅔ VS. This voltage is one of the four logic levels used by the setup pins (S0 to S10). These pins set the operation of the AD9515. The VREF pin provides sufficient drive capability to drive as many of the setup pins as necessary, up to all on a single part. The VREF pin should be used for no other purpose.

SETUP CONFIGURATION

The specific operation of the AD9515 is set by the logic levels applied to the setup pins (S10 to S0). These pins use four-state logic. The logic levels used are V ⅔ V

. The ⅓ VS level is provided by the internal self-biasing on

S

each of the setup pins (S10 to S0). This is the level seen by a setup pin that is left not connected (NC). The ⅔ V

and GND, plus ⅓ VS and

S

level is

S

60kΩ

SETUP PIN

S0 TO S10

30kΩ

05597-023

Figure 28. Setup Pin (S0 to S10) Equivalent Circuit

The AD9515 operation is determined by the combination of logic levels present at the setup pins. The setup configurations for the AD9515 are shown in

Table 10 to Table 15. The four logic levels are referred to as 0, ⅓, ⅔, and 1. These numbers represent the fraction of the V levels. See the setup pin thresholds in

voltage that defines the logic

S

Table 6.

The meaning of some of the setup pins depends on the logic level set on other pins. For example, the effect of the S9/S10 pair of pins depends on the state of S8. S8 selects whether the phase value selected by S9/S10 affects either OUT0 or OUT1. In addition, if OUT1 is selected to have its phase controlled, the effect further depends on the state of S0. If S = 0, the delay block for OUT1 is bypassed, and the logic levels on S9/S10 set the phase value of the OUT1 divider. However, if S0 ≠ 0, then the full-scale delay for OUT1 is set by the logic level on S0, and S9/S10 set the delay block fine delay (fraction of full scale).

Additionally, if a nonzero phase value is selected by S2/S3/S4 (for OUT0) or S5/S6/S7 (for OUT1), this phase overrides the phase value selected by S9/S10. This allows a phase delay to be selected on OUT0 while also selecting a time delay on OUT1.

S1 selects the logic level of each output. OUT0 is LVPECL. The LVPECL output differential voltage (V

) can be selected from

OD

two levels: 400 mV or 780 mV. OUT1 can be set to either LVDS or CMOS levels.

OUT0 can be turned off (powered down) by setting S2/S3/S4 to 0/1/0. OUT1 can be turned off by setting S5/S6/S7 to 0/1/0.

Do not set S2/S3/S4/S5/S6/S7 to 1/1/1/1/1/1.

Rev. 0 | Page 19 of 28

AD9515

PROGRAMMING

Table 10. S0—OUT1 Delay Full Scale

S0 Delay

0 Bypassed 1/3 1.5 ns 2/3 5 ns 1 10 ns

Table 11. S1—Output Logic Configuration

S1 OUT0 OUT1

0 LVPECL 790 mV LVDS 1/3 LVPECL 400 mV LVDS 2/3 LVPECL 790 mV CMOS 1 LVPECL 400 mV CMOS

Table 12. S2, S3, and S4—OUT0

S2 S3 S4 OUT0

Divide (Duty Cycle1)

0 0 0 1 0 1/3 0 0 2 (50%) 0 2/3 0 0 3 (33%) 0 1 0 0 4 (50%) 0 0 1/3 0 5 (40%) 0 1/3 1/3 0 6 (50%) 0 2/3 1/3 0 7 (43%) 0 1 1/3 0 8 (50%) 0 0 2/3 0 9 (44%) 0 1/3 2/3 0 10 (50%) 0 2/3 2/3 0 11 (45%) 0 1 2/3 0 12 (50%) 0 0 1 0 OUT0 OFF 1/3 1 0 14 (50%) 0 2/3 1 0 15 (47%) 0 1 1 0 16 (50%) 0 0 0 1/3 17 (47%) 0 1/3 0 1/3 18 (50%) 0 2/3 0 1/3 19 (47%) 0 1 0 1/3 20 (50%) 0 0 1/3 1/3 21 (48%) 0 1/3 1/3 1/3 22 (50%) 0 2/3 1/3 1/3 23 (48%) 0 1 1/3 1/3 24 (50%) 0 0 2/3 1/3 25 (48%) 0

OUT0 Phase

S2 S3 S4 OUT0

Divide (Duty Cycle1)

1/3 2/3 1/3 26 (50%) 0 2/3 2/3 1/3 27 (48%) 0 1 2/3 1/3 28 (50%) 0 0 1 1/3 29 (48%) 0 1/3 1 1/3 30 (50%) 0 2/3 1 1/3 31 (48%) 0 1 1 1/3 32 (50%) 0 0 0 2/3 2 (50%) 1 1/3 0 2/3 4 (50%) 1 2/3 0 2/3 4 (50%) 2 1 0 2/3 4 (50%) 3 0 1/3 2/3 8 (50%) 1 1/3 1/3 2/3 8 (50%) 2 2/3 1/3 2/3 8 (50%) 3 1 1/3 2/3 8 (50%) 4 0 2/3 2/3 8 (50%) 5 1/3 2/3 2/3 8 (50%) 6 2/3 2/3 2/3 8 (50%) 7 1 2/3 2/3 16 (50%) 1 0 1 2/3 16 (50%) 2 1/3 1 2/3 16 (50%) 3 2/3 1 2/3 16 (50%) 4 1 1 2/3 16 (50%) 5 0 0 1 16 (50%) 6 1/3 0 1 16 (50%) 7 2/3 0 1 16 (50%) 8 1 0 1 16 (50%) 9 0 1/3 1 16 (50%) 10 1/3 1/3 1 16 (50%) 11 2/3 1/3 1 16 (50%) 12 1 1/3 1 16 (50%) 13 0 2/3 1 16 (50%) 14 1/3 2/3 1 16 (50%) 15 2/3 2/3 1 32 (50%) 1 1 2/3 1 32 (50%) 2 0 1 1 32 (50%) 3 1/3 1 1 32 (50%) 4 2/3 1 1 32 (50%) 5 1 1 1 Do not use

1

Duty cycle is the clock signal high time divided by the total period.

OUT0 Phase

Rev. 0 | Page 20 of 28

AD9515

Table 13. S5, S6, and S7—OUT1

S5 S6 S7 OUT1

Divide (Duty Cycle

1

)

OUT1 Phase

0 0 0 1 0 1/3 0 0 2 (50%) 0 2/3 0 0 3 (33%) 0 1 0 0 4 (50%) 0 0 1/3 0 5 (40%) 0 1/3 1/3 0 6 (50%) 0 2/3 1/3 0 7 (43%) 0 1 1/3 0 8 (50%) 0 0 2/3 0 9 (44%) 0 1/3 2/3 0 10 (50%) 0 2/3 2/3 0 11 (45%) 0 1 2/3 0 12 (50%) 0 0 1 0 OUT1 OFF 1/3 1 0 14 (50%) 0 2/3 1 0 15 (47%) 0 1 1 0 16 (50%) 0 0 0 1/3 17 (47%) 0 1/3 0 1/3 18 (50%) 0 2/3 0 1/3 19 (47%) 0 1 0 1/3 20 (50%) 0 0 1/3 1/3 21 (48%) 0 1/3 1/3 1/3 22 (50%) 0 2/3 1/3 1/3 23 (48%) 0 1 1/3 1/3 24 (50%) 0 0 2/3 1/3 25 (48%) 0 1/3 2/3 1/3 26 (50%) 0 2/3 2/3 1/3 27 (48%) 0 1 2/3 1/3 28 (50%) 0 0 1 1/3 29 (48%) 0 1/3 1 1/3 30 (50%) 0 2/3 1 1/3 31 (48%) 0 1 1 1/3 32 (50%) 0 0 0 2/3 2 (50%) 1 1/3 0 2/3 4 (50%) 1 2/3 0 2/3 4 (50%) 2 1 0 2/3 4 (50%) 3 0 1/3 2/3 8 (50%) 1 1/3 1/3 2/3 8 (50%) 2 2/3 1/3 2/3 8 (50%) 3 1 1/3 2/3 8 (50%) 4 0 2/3 2/3 8 (50%) 5 1/3 2/3 2/3 8 (50%) 6 2/3 2/3 2/3 8 (50%) 7 1 2/3 2/3 16 (50%) 1 0 1 2/3 16 (50%) 2 1/3 1 2/3 16 (50%) 3 2/3 1 2/3 16 (50%) 4 1 1 2/3 16 (50%) 5 0 0 1 16 (50%) 6

S5 S6 S7 OUT1

Divide (Duty Cycle

1

)

1/3 0 1 16 (50%) 7 2/3 0 1 16 (50%) 8 1 0 1 16 (50%) 9 0 1/3 1 16 (50%) 10 1/3 1/3 1 16 (50%) 11 2/3 1/3 1 16 (50%) 12 1 1/3 1 16 (50%) 13 0 2/3 1 16 (50%) 14 1/3 2/3 1 16 (50%) 15 2/3 2/3 1 32 (50%) 1 1 2/3 1 32 (50%) 2 0 1 1 32 (50%) 3 1/3 1 1 32 (50%) 4 2/3 1 1 32 (50%) 5 1 1 1 Do not use

1

Duty cycle is the clock signal high time divided by the total period.

Table 14. S8—OUT0/OUT1 Phase (Delay) Select (Used with S9 to S10)

S8 OUT0 OUT1 (Delay if S0 ≠ 0)

0 No Phase Phase (Delay) 1/3 Phase No Phase 2/3 No Phase Phase (Delay) (Start High) 1 Phase (Start High) No Phase

Table 15. S9 and S10

OUT0 or OUT1 Phase (Depends on S8)

S9 S10 Phase

1

OUT1 Delay (S0 ≠ 0) (Depends on S8)

Fine Delay

0 0 0 0 1/3 0 1 1/16 2/3 0 2 1/8 1 0 3 3/16 0 1/3 4 1/4 1/3 1/3 5 5/16 2/3 1/3 6 3/8 1 1/3 7 7/16 0 2/3 8 1/2 1/3 2/3 9 9/16 2/3 2/3 10 5/8 1 2/3 11 11/16 0 1 12 3/4 1/3 1 13 13/16 2/3 1 14 7/8 1 1 15 15/16

1

A phase > 0 in Table 12 or overrides the phase in Table 15.

OUT1 Phase

Rev. 0 | Page 21 of 28

AD9515

DIVIDER PHASE OFFSET

The phase offset of OUT0 and OUT1 can be selected (see Tabl e 1 2

Table 15). This allows the relative phase of OUT0 and OUT1

to to be set.

After a SYNC operation (see the phase offset word of each divider determines the number of input clock (CLK) cycles to wait before initiating a clock output edge. By giving each divider a different phase offset, output-tooutput delays can be set in increments of the fast clock period, t

Figure 29 shows four cases, each with the divider set to divide = 4. By incrementing the phase offset from 0 to 3, the output is offset from the initial edge by a multiple of t

CLOCK INPUT

DIVIDER OUTPUT

DIV = 4

PHASE = 0

PHASE = 1

014123 5 9678 10 1411 12 13

CLK

t

CLK

Synchronization section), the

CLK

.

CLK

5

.

The resolution of the phase offset is set by the fast clock period

) at CLK. The maximum unique phase offset is less than the

(t

CLK

divide ratio, up to a phase offset of 15.

Phase offsets can be related to degrees by calculating the phase step for a particular divide ratio:

Phase Step = 360°/Divide Ratio

Using some of the same examples:

Divide = 4

Phase Step = 360°/4 = 90°

Unique Phase Offsets in Degrees Are Phase = 0°, 90°,

180°, 270°

Divide = 9

Phase Step = 360°/9 = 40°

Unique Phase Offsets in Degrees Are Phase = 0°, 40°, 80°,

120°, 160°, 200°, 240°, 280°, 320°

PHASE = 2

PHASE = 3

t

CLK

2× t

3× t

CLK

Figure 29. Phase Offset—Divider Set for Divide = 4, Phase Set from 0 to 2

CLK

For example:

CLK = 491.52 MHz

= 1/491.52 = 2.0345 ns

t

CLK

For Divide = 4:

Phase Offset 0 = 0 ns

Phase Offset 1 = 2.0345 ns

Phase Offset 2 = 4.069 ns

Phase Offset 3 = 6.104 ns

The outputs can also be described as:

Phase Offset 0 = 0°

Phase Offset 1 = 90°

Phase Offset 2 = 180°

Phase Offset 3 = 270°

Setting the phase offset to Phase = 4 results in the same relative phase as Phase = 0° or 360°.

05597-024

DELAY BLOCK

OUT1 includes an analog delay element that gives variable time delays (ΔT) in the clock signal passing through that output.

CLOCK INPUT

OUT1 ONLY

÷N

∅SELECT

ΔT

FINE DELAY ADJUST

(16 STEPS)

FULL SCALE : 1.5ns, 5ns, 10ns

Figure 30. Analog Delay Block

The amount of delay that can be used is determined by the output frequency. The amount of delay is limited to less than one-half cycle of the clock period. For example, for a 10 MHz clock, the delay can extend to the full 10 ns maximum. However, for a 100 MHz clock, the maximum delay is less than 5 ns (or half of the period).

The AD9515 allows for the selection of three full-scale delays,

1.5 ns, 5 ns, and 10 ns, set by delay full scale (see of these full-scale delays can be scaled by 16 fine adjustment values, which are set by the delay word (see

The delay block adds some jitter to the output. This means that the delay function should be used primarily for clocking digital chips, such as FPGA, ASIC, DUC, and DDC, rather than for supplying a sample clock for data converters. The jitter is higher for longer full scales because the delay block uses a ramp and trip points to create the variable delay. A longer ramp means more noise has a chance of being introduced.

LVDS

CMOS

MUX

OUTPUT

DRIVER

Table 1 0). Each

Table 1 4 and Tab le 1 5).

05596-025

Rev. 0 | Page 22 of 28

AD9515

3

A

3

A

When the delay block is OFF (bypassed), it is also powered down.

OUTPUTS

The AD9515 offers three different output level choices: LVPECL, LVDS, and CMOS. OUT0/OUT0B offers an LVPECL differential output. The LVPECL differential voltage swing (V

) can be selected as either 400 mV or 790 mV (see Tabl e 1 1).

OD

POWER SUPPLY

The AD9515 requires a 3.3 V ± 5% power supply for VS. The tables in the expected from the AD9515 with the power supply voltage within this range. In no case should the absolute maximum range of −0.3 V to +3.6 V, with respect to GND, be exceeded on Pin VS.

Specifications section give the performance

OUT1/OUT1B can be selected as either an LVDS differential output or a pair of CMOS single-ended outputs. If selected as CMOS, OUT1 is a noninverted, single-ended output, and OUT1B is an inverted, single-ended output.

3.3V

OUT

OUTB

GND

Figure 31. LVPECL Output Simplified Equivalent Circuit

.5m

05597-026

Good engineering practice should be followed in the layout of power supply traces and the ground plane of the PCB. The power supply should be bypassed on the PCB with adequate capacitance (>10 μF). The AD9515 should be bypassed with adequate capacitors (0.1 μF) at all power pins as close as possible to the part. The layout of the AD9515 evaluation board (AD9515/PCB) is a good example.

OUT

OUTB

.5m

05597-027

Figure 32. LVDS Output Simplified Equivalent Circuit

V

S

OUT1/ OUT1B

Figure 33. CMOS Equivalent Output Circuit

05597-028

Rev. 0 | Page 23 of 28

AD9515

Exposed Metal Paddle

The exposed metal paddle on the AD9515 package is an electrical connection, as well as a thermal enhancement. For the device to function properly, the paddle must be properly attached to ground (GND).

POWER MANAGEMENT

In some cases, the AD9515 can be configured to use less power by turning off functions that are not being used.

The power-saving options include the following:

The exposed paddle of the AD9515 package must be soldered down. The AD9515 must dissipate heat through its exposed

paddle. The PCB acts as a heat sink for the AD9515. The PCB attachment must provide a good thermal path to a larger heat dissipation area, such as a ground plane on the PCB. This requires a grid of vias from the top layer down to the ground plane (see

Figure 34). The AD9515 evaluation board (AD9515/PCB)provides a good example of how the part should be attached to the PCB.

VIAS TO GND PLANE

05597-035

Figure 34. PCB Land for Attaching Exposed Paddle

• A divider is powered down when set to divide = 1

(bypassed).

• Adjustable delay block on OUT1 is powered down when in

off mode (S0 = 0).

• An unneeded output can be powered down (see

Table 13). This also powers down the divider for that

and

Table 1 2

output.

Rev. 0 | Page 24 of 28

AD9515

APPLICATIONS

USING THE AD9515 OUTPUTS FOR ADC CLOCK APPLICATIONS

Any high speed, analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought of as a sampling mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. Clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at ≥14-bit resolution being the most stringent. The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock. Considering an ideal ADC of infinite resolution where the step size and quantization error can be ignored, the available SNR can be expressed approximately by

1

⎤

SNR

f is the highest analog frequency being digitized.

where

t

is the rms jitter on the sampling clock.

j

Figure 35 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (ENOB).

110

100

90

80

70

SNR (dB)

60

50

40

30

10 1k100

f

FULL-SCALE SINE WAVE ANALOG FREQUENCY (MHz)

A

Figure 35. ENOB and SNR vs. Analog Input Frequency

⎡

×=

log20

⎢ ⎣

2π

⎥

ft

J

⎦

SNR = 20log

T

J

=

1

0

2

0

f

S

4

0

f

S

1

ps

2

ps

1

0

p

s

1

2πf

0

f

S

ATJ

18

16

14

12

ENOB

10

8

6

05597-091

Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB. (Distributing a single-ended clock on a noisy PCB can result in coupled noise on the sample clock. Differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment.) The AD9515 features both LVPECL and LVDS outputs that provide differential clock outputs, which enable clock solutions that maximize converter SNR performance. The input requirements of the ADC (differential or single-ended, logic level, termination) should be considered when selecting the best clocking/converter solution.

LVPECL CLOCK DISTRIBUTION

The low voltage, positive emitter-coupled, logic (LVPECL) outputs of the AD9515 provide the lowest jitter clock signals available from the AD9515. The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. The simplified equivalent circuit in the LVPECL output stage.

In most applications, a standard LVPECL far-end termination is recommended, as shown in

Figure 36. The resistor network is designed to match the transmission line impedance (50 Ω) and the switching threshold (V

V

S

LVPECL

V

S

SINGLE-ENDED

(NOT COUPLED)

V

= VS– 1.3V

T

Figure 36. LVPECL Far-End Termination

0.1nF

− 1.3 V).

S

50Ω

V

S

127Ω127Ω

83Ω83Ω

Figure 31 shows

V

S

LVPECL

V

S

05597-030

See Application Notes AN-756 and AN-501 at www.analog.com.

Rev. 0 | Page 25 of 28

LVPECL

200Ω 200Ω

100Ω DIFFERENTIAL

0.1nF

(COUPLED)

Figure 37. LVPECL with Parallel Transmission Line

100Ω

LVPECL

05597-031

AD9515

LVDS CLOCK DISTRIBUTION

The AD9515 provides one clock output (OUT2) that is selectable as either CMOS or LVDS levels. Low voltage differential signaling for OUT2. LVDS uses a current mode output stage. The current is 3.5 mA, which yields 350 mV output swing across a 100 Ω resistor. The LVDS output meets or exceeds all ANSI/TIA/EIA-644 specifications.

A recommended termination circuit for the LVDS outputs is shown in

Figure 38.

(LVDS) is a differential output option

Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9515 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in

Figure 40. The far-end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets.

V

S

V

S

LVDS

DIFFERENTIAL (COUPLED)

Figure 38. LVDS Output Termination

100Ω

V

S

LVDS

See Application Note AN-586 at www.analog.com for more information on LVDS.

CMOS CLOCK DISTRIBUTION

The AD9515 provides one output (OUT1) that is selectable as either CMOS or LVDS levels. When selected as CMOS, this output provides for driving devices requiring CMOS level logic at their clock inputs.

Whenever single-ended CMOS clocking is used, some of the following general guidelines should be used.

Point-to-point nets should be designed such that a driver has only one receiver on the net, if possible. This allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the net. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. The value of the resistor is dependent on the board design and timing requirements (typically 10 Ω to 100 Ω is used). CMOS outputs are also limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 3 inches are recommended to preserve signal rise/fall times and preserve signal integrity.

60.4Ω

1.0 INCH

CMOS

Figure 39. Series Termination of CMOS Output

10Ω

MICROSTRIP

5pF

GND

05597-033

CMOS

05597-032

10Ω

OUT1/OUT1B SELECTED AS CMOS

Figure 40. CMOS Output with Far-End Termination

50Ω

100Ω

3pF

05597-034

Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9515 offers both LVPECL and LVDS outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters.

SETUP PINS (S0 TO S10)

The setup pins that require a logic level of ⅓ VS (internal selfbias) should be tied together and bypassed to ground via a capacitor.

The setup pins that require a logic level of ⅔ V

should be tied

S

together, along with the VREF pin, and bypassed to ground via a capacitor.

POWER AND GROUNDING CONSIDERATIONS AND POWER SUPPLY REJECTION

Many applications seek high speed and performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the PCB is as important as the circuit design. Proper RF techniques must be used for device selection, placement, and routing, as well as power supply bypassing and grounding to ensure optimum performance.

Rev. 0 | Page 26 of 28

AD9515

PHASE NOISE AND JITTER MEASUREMENT SETUPS

WENZEL

OSCILLATOR

SPLITTER ZESC-2-11

0°

EVALUATION BOARD

D

A

1

K

L

C

BALUN

EVALUATION BOARD

D

A

1

K

L

C

BALUN

5

1

9

TERM

1

T

U

O

TERM

1

B

T

U

O

5

1

9

TERM

1

T

U

O

TERM

B

1

T

U

O

ZFL1000VH2

AMP

+28dB

ZFL1000VH2

AMP

+28dB

ATTENUATOR

–12dB

ATTENUATOR

–7dB

VARIABLE DELAY

COLBY PDL30A

0.01ns STEP TO 10ns

SIG IN

REF IN

AGILENT E5500B

PHASE NOISE MEASUREMENT SYSTEM

05597-041

Figure 41. Additive Phase Noise Measurement Configuration

WENZEL

OSCILLATOR

ANALOG

ADC

SOURCE

PC

FFT

SNR

t

J_RMS

WENZEL

OSCILLATOR

EVALUATION BOARD

D

A

1

K

L

C

BALUN

1

5

9

TERM

1

T

U

O

TERM

1

B

T

O

U

CLK

DATA CAPTURE CARD

FIFO

05597-042

Figure 42. Jitter Determination by Measuring SNR of ADC

2

A_RMS

SNR

20

⎤ ⎥

()

2

BWSND

()

⎥ ⎦

[]

2π

Vf

××

2

A_PKA

222

θθθ

++−×−

DNLTHERMALONQUANTIZATI

⎡

V

⎢ ⎢

10

t

J_RMS

⎣

=

where:

t

is the rms time jitter.

j_RMS

SNR is the signal-to-noise ratio. SND is the source noise density in nV/√Hz. BW is the SND filter bandwidth.

V

is the analog source voltage.

A

f

is the analog frequency.

A

The θ terms are the quantization, thermal, and DNL errors.

Rev. 0 | Page 27 of 28

AD9515

OUTLINE DIMENSIONS

0.60 MAX

25

24

EXPOSED

PAD

(BOTTOM VIEW)

17

16

32

1

8

9

3.50 REF

PIN 1 INDICATOR

3.25

3.10 SQ

2.95

0.25 MIN

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING PLANE

5.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

4.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

0.08

Figure 43. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad (CP-32-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9515BCPZ AD9515BCPZ-REEL7 AD9515/PCB Evaluation Board

1

Z = Pb-free part.

1

−40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2

1

−40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2

D05597–0–7/05(0)

Rev. 0 | Page 28 of 28

Analog Devices AD9515 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

CLOCK INPUT

CLOCK OUTPUTS

TIMING CHARACTERISTICS

CLOCK OUTPUT PHASE NOISE

CLOCK OUTPUT ADDITIVE TIME JITTER

SYNCB, VREF, AND SETUP PINS

POWER

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

OVERALL

CLK, CLKB—DIFFERENTIAL CLOCK INPUT

SYNCHRONIZATION

Power-On SYNC

SYNCB

VREF

SETUP CONFIGURATION

PROGRAMMING

DIVIDER PHASE OFFSET

DELAY BLOCK

OUTPUTS

Exposed Metal Paddle

POWER MANAGEMENT

APPLICATIONS

USING THE AD9515 OUTPUTS FOR ADC CLOCK APPLICATIONS

LVPECL CLOCK DISTRIBUTION

LVDS CLOCK DISTRIBUTION

CMOS CLOCK DISTRIBUTION

SETUP PINS (S0 TO S10)

POWER AND GROUNDING CONSIDERATIONS AND POWER SUPPLY REJECTION

PHASE NOISE AND JITTER MEASUREMENT SETUPS

OUTLINE DIMENSIONS

ORDERING GUIDE