Analog Devices AD9513 Service Manual

800 MHz Clock Distribution IC, Dividers,

V

B

FEATURES

1.6 GHz differential clock input 3 programmable dividers

Divide-by in range from1 to 32 Phase select for coarse delay adjust

Three 800 MHz/250 MHz LVDS/CMOS clock outputs

Additive output jitter 300 fs rms

Time delays up to 11.6 ns Device configured with 4-level logic pins Space-saving, 32-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure AT E

Delay Adjust, Three Outputs

AD9513

FUNCTIONAL BLOCK DIAGRAM

RSET

CLK

CLKB

SYNCB

VREF S10S9S8S7S6S5S4S3S2S1S0

SGND

/1. . . /32

SETUP LOGIC

Figure 1.

AD9513

∆

t

LVDS/CMOS

OUT0

OUT1

OUT2

05595-001

GENERAL DESCRIPTION

The AD9513 features a three-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

There are three independent clock outputs that can be set to either LVDS or CMOS levels. These outputs operate to 800 MHz in LVDS mode and to 250 MHz in CMOS mode.

Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to the other clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment.

One of the outputs features a delay element with three selectable full-scale delay values (1.8 ns, 6.0 ns, and 11.6 ns), each with 16 steps of fine adjustment.

The AD9513 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ⅓ V ⅔ V

. VS (3.3 V) and GND (0 V) provide the other two logic levels.

S

. The VREF pin provides a level of

S

The AD9513 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.

The AD9513 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is −40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9513

SPECIFICATIONS

Typical (typ) is given for VS = 3.3 V ± 5%; TA = 25°C, R values are given over full V

and TA (−40°C to +85°C) variation.

S

CLOCK INPUT

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

CLOCK INPUT (CLK)

Input Frequency 0 1.6 GHz Input Sensitivity

1

150 mV p-p Input Common-Mode Voltage, VCM 1.5 1.6 1.7 V Self-biased; enables ac coupling Input Common-Mode Range, V

1.3 1.8 V With 200 mV p-p signal applied; dc-coupled

CMR

Input Sensitivity, Single-Ended 150 mV p-p CLK ac-coupled; CLKB ac-bypassed to RF ground Input Resistance 4.0 4.8 5.6 kΩ Self-biased Input Capacitance 2 pF

1

A slew rate of 1 V/ns is required to meet jitter, phase noise, and propagation delay specifications.

CLOCK OUTPUTS

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

LVDS CLOCK OUTPUT Termination = 100 Ω differential

Differential Output Frequency 0 800 MHz Differential Output Voltage (VOD) 250 350 450 mV Delta VOD 30 mV Output Offset Voltage (VOS) 1.125 1.23 1.375 V Delta VOS 25 mV Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND

CMOS CLOCK OUTPUT Single-ended measurements; termination open

Single-Ended Complementary output on (OUT1B) Output Frequency 0 250 MHz With 5 pF load Output Voltage High (VOH) VS − 0.1 V @ 1 mA load Output Voltage Low (VOL) 0.1 V @ 1 mA load

= 4.12 kΩ, unless otherwise noted. Minimum (min) and maximum (max)

SET

Rev. 0 | Page 3 of 28

AD9513

TIMING CHARACTERISTICS

CLK input slew rate = 1 V/ns or greater.

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

LVDS Termination = 100 Ω differential

Output Rise Time, tRL 200 350 ps 20% to 80%, measured differentially Output Fall Time, tFL 210 350 ps 80% to 20%, measured differentially

PROPAGATION DELAY, t

OUT0, OUT1, OUT2

Divide = 1 1.03 1.29 1.62 ns Divide = 2 − 32 1.09 1.35 1.68 ns Variation with Temperature 0.9 ps/°C

OUT2

Divide = 1 1.07 1.35 1.69 ns Divide = 2 − 32 1.13 1.41 1.75 ns Variation with Temperature 0.9 ps/°C

OUTPUT SKEW, LVDS OUTPUTS Delay off on OUT2

OUT0 to OUT1 on Same Part, t OUT0 to OUT2 on Same Part, t All LVDS OUTs Across Multiple Parts, t Same LVDS OUTs Across Multiple Parts, t

CMOS B outputs are inverted; termination = open

Output Rise Time, tRC 650 865 ps 20% to 80%; C Output Fall Time, tFC 650 990 ps 80% to 20%; C

PROPAGATION DELAY, t

OUT0, OUT1

Divide = 1 1.14 1.46 1.89 ns Divide = 2 − 32 1.19 1.51 1.94 ns Variation with Temperature 1 ps/°C

OUT2

Divide = 1 1.20 1.53 1.97 ns Divide = 2 − 32 1.24 1.57 2.01 ns Variation with Temperature 1 ps/°C

OUTPUT SKEW, CMOS OUTPUTS Delay off on OUT2

All CMOS OUTs on Same Part, t All CMOS OUTs Across Multiple Parts, t Same CMOS OUTs Across Multiple Parts, t

LVDS-TO-CMOS OUT Everything the same; different logic type

Output Skew, t

SKV_C

DELAY ADJUST (OUT2; LVDS AND CMOS)

S0 = 1/3

Zero-Scale Delay Time

Zero-Scale Variation with Temperature 0.20 ps/°C

Full-Scale Time Delay

Full-Scale Variation with Temperature −0.38 ps/°C

S0 = 2/3

Zero-Scale Delay Time

Zero-Scale Variation with Temperature 0.31 ps/°C

Full-Scale Time Delay

Full-Scale Variation with Temperature −1.3 ps/°C

, CLK-TO-LVDS OUT Delay off on OUT2

LVDS

1

SKV

1

SKV

, CLK-TO-CMOS OUT Delay off on OUT2

CMOS

1

SKC

SKV_AB

SKC_AB

2

SKV_AB

2

SKC_AB

−135 −20 +125 ps

−205 −65 +90 ps 375 ps

2

300 ps

−230 +135 ps 415 ps

2

330 ps

LOAD

= 3 pF = 3 pF

510 ps LVDS to CMOS on same part

3

0.35 ns

1.8 ns

0.48 ns

6.0 ns

Rev. 0 | Page 4 of 28

AD9513

Min Typ Max Unit Test Conditions/Comments Parameter

S0 = 1

Zero-Scale Delay Time

Zero-Scale Variation with Temperature 0.47 ps/°C

Full-Scale Time Delay

Full-Scale Variation with Temperature −5 ps/°C Linearity, DNL 0.2 LSB Linearity, INL 0.2 LSB

1

This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature.

2

This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.

3

Incremental delay; does not include propagation delay.

3

0.59 ns

11.6 ns

Rev. 0 | Page 5 of 28

AD9513

CLOCK OUTPUT PHASE NOISE

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

CLK-TO-LVDS ADDITIVE PHASE NOISE

CLK = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1

@ 10 Hz Offset −100 dBc/Hz @ 100 Hz Offset −110 dBc/Hz @ 1 kHz Offset −118 dBc/Hz @ 10 kHz Offset −129 dBc/Hz @ 100 kHz Offset −135 dBc/Hz @ 1 MHz Offset −140 dBc/Hz

>10 MHz Offset −148 dBc/Hz CLK = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4

@ 10 Hz Offset −112 dBc/Hz

@ 100 Hz Offset −122 dBc/Hz

@ 1 kHz Offset −132 dBc/Hz

@ 10 kHz Offset −142 dBc/Hz

@ 100 kHz Offset −148 dBc/Hz

@ 1 MHz Offset −152 dBc/Hz

>10 MHz Offset −155 dBc/Hz CLK = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2

@ 10 Hz Offset −108 dBc/Hz

@ 100 Hz Offset −118 dBc/Hz

@ 1 kHz Offset −128 dBc/Hz

@ 10 kHz Offset −138 dBc/Hz

@ 100 kHz Offset −145 dBc/Hz

@ 1 MHz Offset −148 dBc/Hz

>10 MHz Offset −154 dBc/Hz CLK = 491.52 MHz, OUT = 122.88 MHz Divide Ratio = 4

@ 10 Hz Offset −118 dBc/Hz

@ 100 Hz Offset −129 dBc/Hz

@ 1 kHz Offset −136 dBc/Hz

@ 10 kHz Offset −147 dBc/Hz

@ 100 kHz Offset −153 dBc/Hz

@ 1 MHz Offset −156 dBc/Hz

>10 MHz Offset −158 dBc/Hz CLK = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1

@ 10 Hz Offset −108 dBc/Hz

@ 100 Hz Offset −118 dBc/Hz

@ 1 kHz Offset −128 dBc/Hz

@ 10 kHz Offset −138 dBc/Hz

@ 100 kHz Offset −145 dBc/Hz

@ 1 MHz Offset −148 dBc/Hz

>10 MHz Offset −155 dBc/Hz

Rev. 0 | Page 6 of 28

AD9513

Min Typ Max Unit Test Conditions/Comments Parameter

CLK = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = 2

@ 10 Hz Offset −118 dBc/Hz @ 100 Hz Offset −127 dBc/Hz @ 1 kHz Offset −137 dBc/Hz @ 10 kHz Offset −147 dBc/Hz @ 100 kHz Offset −154 dBc/Hz @ 1 MHz Offset −156 dBc/Hz >10 MHz Offset −158 dBc/Hz

CLK-TO-CMOS ADDITIVE PHASE NOISE

CLK = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1

@ 10 Hz Offset −110 dBc/Hz @ 100 Hz Offset −121 dBc/Hz @ 1 kHz Offset −130 dBc/Hz @ 10 kHz Offset −140 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −149 dBc/Hz

>10 MHz Offset −156 dBc/Hz CLK = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4

@ 10 Hz Offset −125 dBc/Hz

@ 100 Hz Offset −132 dBc/Hz

@ 1 kHz Offset −143 dBc/Hz

@ 10 kHz Offset −152 dBc/Hz

@ 100 kHz Offset −158 dBc/Hz

@ 1 MHz Offset −160 dBc/Hz

>10 MHz Offset −162 dBc/Hz CLK = 78.6432 MHz, OUT = 78.6432 MHz Divide Ratio = 1

@ 10 Hz Offset −122 dBc/Hz

@ 100 Hz Offset −132 dBc/Hz

@ 1 kHz Offset −140 dBc/Hz

@ 10 kHz Offset −150 dBc/Hz

@ 100 kHz Offset −155 dBc/Hz

@ 1 MHz Offset −158 dBc/Hz

>10 MHz Offset −160 dBc/Hz CLK = 78.6432 MHz, OUT = 39.3216 MHz Divide Ratio = 2

@ 10 Hz Offset −128 dBc/Hz

@ 100 Hz Offset −136 dBc/Hz

@ 1 kHz Offset −146 dBc/Hz

@ 10 kHz Offset −155 dBc/Hz

@ 100 kHz Offset −161 dBc/Hz

>1 MHz Offset −162 dBc/Hz

Rev. 0 | Page 7 of 28

AD9513

CLOCK OUTPUT ADDITIVE TIME JITTER

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

LVDS OUTPUT ADDITIVE TIME JITTER Calculated from SNR of ADC method

CLK= 400 MHz 300 fs rms

LVDS (OUT0) = 100 MHz Divide Ratio = 4

LVDS (OUT1, OUT2) = 100 MHz Interferer

CLK = 400 MHz 300 fs rms

LVDS (OUT0) = 100 MHz Divide Ratio = 4

LVDS (OUT1, OUT2) = 50 MHz Interferer

CLK = 400 MHz 305 fs rms

LVDS (OUT1) = 100 MHz Divide Ratio = 4 LVDS (OUT0, OUT2) = 100 MHz Interferer

CLK = 400 MHz 310 fs rms

LVDS (OUT1) = 100 MHz Divide Ratio = 4 LVDS (OUT0, OUT2) = 50 MHz Interferer

CLK = 400 MHz 310 fs rms

LVDS (OUT2) = 100 MHz Divide Ratio = 4 LVDS (OUT0, OUT1) = 100 MHz Interferer

CLK = 400 MHz 315 fs rms

LVDS (OUT2) = 100 MHz Divide Ratio = 4 LVDS (OUT0, OUT1) = 50 MHz Interferer

CLK = 400 MHz 345 fs rms

LVDS (OUT2) = 100 MHz Divide Ratio = 4 CMOS (OUT0, OUT1) = 50 MHz Interferer

CMOS OUTPUT ADDITIVE TIME JITTER Calculated from SNR of ADC method

CLK = 400 MHz 300 fs rms

CMOS (OUT0) = 100 MHz Divide Ratio = 4 LVDS (OUT2) = 100 MHz Interferer

CLK = 400 MHz 300 fs rms

CMOS (OUT0) = 100 MHz Divide Ratio = 4 CMOS (OUT1, OUT2) = 50 MHz Interferer

CLK = 400 MHz 335 fs rms

CMOS (OUT1) = 100 MHz Divide Ratio = 4

CMOS (OUT0, OUT2) = 50 MHz Interferer

CLK = 400 MHz 355 fs rms

CMOS (OUT2) = 100 MHz Divide Ratio = 4 CMOS (OUT0, OUT1) = 50 MHz Interferer

CLK = 400 MHz 340 fs rms

CMOS (OUT2) = 100 MHz Divide Ratio = 4 LVDS (OUT0, OUT1) = 50 MHz Interferer

Rev. 0 | Page 8 of 28

AD9513

Parameter Min Typ Max Unit Test Conditions/Comments

DELAY BLOCK ADDITIVE TIME JITTER

Delay FS = 1.8 ns Fine Adj. 00000 0.71 ps rms Delay FS = 1.8 ns Fine Adj. 11111 1.2 ps rms Delay FS = 6.0 ns Fine Adj. 00000 1.3 ps rms Delay FS = 6.0 ns Fine Adj. 11111 2.7 ps rms Delay FS = 11.6 ns Fine Adj. 00000 2.0 ps rms Delay FS = 11.6 ns Fine Adj. 11111 2.8 ps rms

1

This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter

should be added to this value using the root sum of the squares (RSS) method.

SYNCB, VREF, AND SETUP PINS

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

SYNCB

Logic High 2.7 V Logic Low 0.40 V Capacitance 2 pF

VREF

Output Voltage 0.62·VS 0.76·VS V Minimum − maximum from 0 mA to 1 mA load

S0 TO S10

Levels

0 0.1·VS V 1/3 0.2·VS 0.45·VS V 2/3 0.55·VS 0.8·VS V 1 0.9·VS V

1

100 MHz output; incremental additive jitter

1

POWER

Table 7.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER-ON SYNCHRONIZATION

VS Transit Time from 2.2 V to 3.1 V

POWER DISSIPATION 175 325 575 mW

240 460 615 mW All three outputs on. CMOS (divide = 2); 62.5 MHz out (5 pF load). 320 605 840 mW All three outputs on. CMOS (divide = 2); 125 MHz out (5 pF load). POWER DELTA

Divider (Divide = 2 to Divide = 1) 15 30 45 mW For each divider. No clock. LVDS Output 20 50 85 mW No clock. CMOS Output (Static) 30 40 50 mW No clock. CMOS Output (@ 62.5 MHz) 65 110 155 mW Single-ended. At 62.5 MHz out with 5 pF load. CMOS Output (@ 125 MHz) 70 145 220 mW Single-ended. At 125 MHz out with 5 pF load. Delay Block 30 45 65 mW Off to 1.8 ns fs, delay word = 60; output clocking at 62.5 MHz.

1

This is the rise time of the VS supply that is required to ensure that a synchronization of the outputs occurs on power-up. The critical factor is the time it takes the VS to

transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs are not synchronized.

1

35 ms See the Power-On SYNC section.

All three outputs on. LVDS (divide = 2). No clock. Does not include power dissipated in external resistors.

Rev. 0 | Page 9 of 28

Analog Devices AD9513 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

CLOCK INPUT

CLOCK OUTPUTS

TIMING CHARACTERISTICS

CLOCK OUTPUT PHASE NOISE

CLOCK OUTPUT ADDITIVE TIME JITTER

SYNCB, VREF, AND SETUP PINS

POWER