Analog Devices AD9512 pra Datasheet
V
800 MHz Clock Distribution IC,1.5 GHz
Inputs, Dividers, Delay Adjust, Five Outputs
Preliminary Technical Data
FEATURES
Two 1.5 GHz, differential clock inputs
5 programmable dividers, 1 to 32, all integers
Phase select for output-to-output coarse delay adjust
3 independent 800 MHz LVPECL outputs
Additive output jitter 225 fs rms
2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs
Additive output jitter 275 fs rms
Fine delay adjust on 1 output, 6-bit delay word
4-wire or 3-wire serial control port
Space-saving, 48-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
GENERAL DESCRIPTION
The AD9512 provides a multi-output clock distribution in a
design that emphasizes low jitter and phase noise in order to
maximize data converter performance. Other applications with
demanding phase noise and jitter requirements also benefit
from this part.
AD9512
FUNCTIONAL BLOCK DIAGRAM
SGND
FUNCTION
DSYNC
DSYNCB
CLK1
CLK1B
CLK2
CLK2B
SCLK
SDIO
SDO
CSB
SYNCB,
RESETB PDB
DETECT
SYNC
SERIAL
CONTROL
PORT
The AD9512 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9512 is available in a 48-lead LFCSP and may be
operated from a single 3.3 V supply. The temperature range is
−40°C to +85°C.
RSET
AD9512
VREF
PROGRAMMABLE DIVIDERS
& PHASE ADJUST
/1,/2,/3... /31,/32
/1,/2,/3... /31,/32
/1,/2,/3... /31,/32
/1,/2,/3... /31,/32
/1,/2,/3... /31,/32
Figure 1.
SYNC
STATUS
DELAY ADJUST
∆T
LVPECL
LVPECL
LVPECL
LVDS/CMOS
LVDS/CMOS
STATUS
OUT0
OUT0B
OUT1
OUT1B
OUT2B
OUT3B
OUT4B
OUT2
OUT3
OUT4
There are five independent clock outputs. Three outputs are
LVPECL, and two are selectable as either LVDS or CMOS levels.
The LVPECL and LVDS outputs operate to 800 MHz, and the
CMOS outputs operate to 250 MHz.
Each output has a programmable divider, which may be
bypassed or set to divide by any integer up to 32. The phase of
one clock output relative to another clock output may be varied
by means of a divider phase select function that serves as a
coarse timing adjustment.
One of the LVDS/CMOS outputs also features a programmable
delay element with a range of up to 10 ns of delay. This fine
tuning delay block has 6-bit resolution, giving 64 possible delays
from which to choose.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
AD9512 Preliminary Technical Data
PR05287-0-11/04(PrA)
PIN CONFIGURATION
B
T
D
S
S
V
V
48
1
Y
S
D
C
N
Y
S
D
C
N
B
2
3
S
V
4
V
S
C
D
N
5
V
S
6
C
L
2
K
7
8
L
C
K
2
B
V
S
9
L
C
1
K
10
C
F
U
C
N
11
L
K
1
B
T
N
O
I
12
E
N
S
S
V
R
G
47
46
45
44
pin 1
indicator
AD9512
(Not to scale)
48-leadLFCSP7 x 7 x 0.85
0
D
T
N
U
G
O
43
42
Top View
0
T
U
O
41
S
S
V
V
40
39
D
D
N
N
G
G
38
37
S
36
V
35
OUT3
34
OUT3B
S
33
V
S
V
32
U
O
T
31
30
29
28
27
26
25
4
O
U
B
T
4
S
V
V
S
O
U
1
T
O
U
B
1
T
V
S
13
14
15
16
17
18
S
K
U
T
A
T
S
O
I
L
D
C
S
S
B
O
S
D
C
S
19
S
D
V
N
G
21
20
B
2
T
U
O
22
23
24
2
S
T
V
U
O
D
S
N
V
G
Figure 2.
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to
function properly, the paddle must be attached to ground, GND.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
Rev. 0 | Page 2 of 2
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