Analog Devices AD9511 Service Manual

T

VSV

1.2 GHz Clock Distribution IC, PLL Core,

FEATURES

Low phase noise phase-locked loop core

Reference input frequencies to 250 MHz Programmable dual-modulus prescaler Programmable charge pump (CP) current

Separate CP supply (VCP Two 1.6 GHz, differential clock inputs 5 programmable dividers, 1 to 32, all integers Phase select for output-to-output coarse delay adjust 3 independent 1.2 GHz LVPECL outputs

Additive output jitter 225 fs rms 2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs

Additive output jitter 275 fs rms

Fine delay adjust on 1 LVDS/CMOS output Serial control port Space-saving 48-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure

GENERAL DESCRIPTION

The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

The PLL section consists of a programmable reference divider (R); a low noise phase frequency detector (PFD); a precision charge pump (CP); and a programmable feedback divider (N). By connecting an external VCXO or VCO to the CLK2/CLK2B pins, frequencies up to 1.6 GHz may be synchronized to the input reference.

There are five independent clock outputs. Three outputs are LVPECL (1.2 GHz), and two are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels.

) extends tuning range

S

Dividers, Delay Adjust, Five Outputs

AD9511

FUNCTIONAL BLOCK DIAGRAM

RSE

GND

REFIN

REFINB

FUNCTION

CLK1

CLK1B

SCLK

SDIO

SDO CSB

SYNCB, RESETB

PDB

SERIAL

CONTROL

PORT

DISTRIBUTION

REF

R DIVIDER

N DIVIDER

PROGRAMMABLE

PHASE ADJUST /1, /2, /3... /31, /32

/1, /2, /3... /31, /32

AD9511

FREQUENCY

DIVIDERS AND

PHASE

DETECTOR

Figure 1.

Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output may be varied by means of a divider phase select function that serves as a coarse timing adjustment. One of the LVDS/CMOS outputs features a programmable delay element with full-scale ranges up to 10 ns of delay. This fine tuning delay block has 5-bit resolution, giving 32 possible delays from which to choose for each full-scale setting.

The AD9511 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.

The AD9511 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. The temperature range is −40°C to +85°C.

Δ

T

DELAY

ADJUST

CPRSE

PLL REF

CHARGE

PUMP

PLL

SETTINGS

LVPECL

LVDS/CMOS

CP

STATUS

CLK2 CLK2B

OUT0 OUT0B

OUT1 OUT1B

OUT2 OUT2B

OUT3 OUT3B

OUT4 OUT4B

05286-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9511

REVISION HISTORY

6/05—Rev. 0 to Rev. A

Changes to Features..........................................................................1

Changes to General Description .....................................................1

Changes to Table 1 and Table 2 .......................................................5

Changes to Table 4 ............................................................................7

Changes to Table 5 ............................................................................9

Changes to Table 6 ..........................................................................14

Changes to Table 8 and Table 9 .....................................................15

Changes to Table 11 ........................................................................16

Changes to Table 13 ........................................................................20

Changes to Figure 19 to Figure 23 ................................................24

Changes to Figure 30 and Figure 31 .............................................26

Changes to Figure 32 ......................................................................27

Changes to Figure 33 ......................................................................28

Changes to VCO/VCXO Clock Input—CLK2 Section ..............29

Changes to PLL Reference Divider—P Section...........................29

Changes to A and B Counters Section .........................................30

Changes to PLL Digital Lock Detect Section ..............................31

Changes to PLL Analog Lock Detect Section..............................32

Changes to Loss of Reference Section ..........................................32

Changes to FUNCTION Pin Section ...........................................32

Changes to RESETB: 58h<6:5> = 00b (Default) Section...........32

Changes to SYNCB: 58h<6:5> = 01b Section..............................32

Changes to CLK1 and CLK2 Clock Inputs Section....................33

Register Map Description..........................................................47

Power Supply ...................................................................................54

Power Management ....................................................................54

Applications.....................................................................................55

Using the AD9511 Outputs for ADC Clock Applications ....55

CMOS Clock Distribution.........................................................55

LVPECL Clock D i s t r ibu t i o n ......................................................56

LVDS Clock Distribution...........................................................56

Power and Grounding Considerations and Power Supply

Rejection.......................................................................................56

Outline Dimensions........................................................................57

Ordering Guide...........................................................................57

Changes to Divider Phase Offset Section ....................................37

Changes to Individual Clock Output Power-Down Section.....39

Changes to Individual Circuit Block Power-Down Section......39

Changes to Soft Reset via the Serial Port Section .......................40

Changes to Multichip Synchronization Section..........................40

Changes to Serial Control Port Section .......................................41

Changes to Serial Control Port Pin Descriptions Section.........41

Changes to General Operation of Serial

Control Port Section.......................................................................41

Added Framing a Communication Cycle with CSB Section ....41

Added Communication Cycle—Instruction Plus

Data Section.....................................................................................41

Changes to Write Section ............................................................... 41

Changes to Read Section................................................................42

Changes to Instruction Word (16 Bits) Section ..........................42

Changes to Table 20 ........................................................................42

Changes to MSB/LSB First Transfers Section..............................42

Added Figure 52; Renumbered Sequentially...............................44

Changes to Table 23 ........................................................................45

Changes to Table 24 ........................................................................47

Changes to Power Supply...............................................................54

4/05—Revision 0: Initial Version

Rev. A | Page 3 of 60

AD9511

SPECIFICATIONS

Typical (typ) is given for VS = 3.3 V ± 5%; VS ≤ VCPS ≤ 5.5 V, TA = 25°C, R Minimum (min) and maximum (max) values are given over full V

and TA (−40°C to +85°C) variation.

S

PLL CHARACTERISTICS

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE INPUTS (REFIN)

Input Frequency 0 250 MHz Input Sensitivity 150 mV p-p Self-Bias Voltage, REFIN 1.45 1.60 1.75 V Self-bias voltage of REFIN1. Self-Bias Voltage, REFINB 1.40 1.50 1.60 V Self-bias voltage of REFINB1. Input Resistance, REFIN 4.0 4.9 5.8 kΩ Self-biased1. Input Resistance, REFINB 4.5 5.4 6.3 kΩ Self-biased1. Input Capacitance 2 pF

PHASE/FREQUENCY DETECTOR (PFD)

PFD Input Frequency 100 MHz Antibacklash pulse width 0Dh<1:0> = 00b. PFD Input Frequency 100 MHz Antibacklash pulse width 0Dh<1:0> = 01b. PFD Input Frequency 45 MHz Antibacklash pulse width 0Dh<1:0> = 10b. Antibacklash Pulse Width 1.3 ns 0Dh<1:0> = 00b. (This is the default setting.) Antibacklash Pulse Width 2.9 ns 0Dh<1:0> = 01b. Antibacklash Pulse Width 6.0 ns 0Dh<1:0> = 10b.

CHARGE PUMP (CP)

ICP Sink/Source Programmable.

High Value 4.8 mA Low Value 0.60 mA Absolute Accuracy 2.5 % VCP = VCPS/2. CPR

Range 2.7/10 kΩ

SET

ICP Three-State Leakage 1 nA Sink-and-Source Current Matching 2 % 0.5 < VCP < VCPS − 0.5 V. ICP vs. V

CP

ICP vs. Temperature 2 % VCP = VCPS/2 V.

RF CHARACTERISTICS (CLK2)

2

Input Frequency 1.6 GHz

Input Sensitivity 150 mV p-p Input Common-Mode Voltage, V Input Common-Mode Range, V

CM

CMR

Input Sensitivity, Single-Ended 150 mV p-p

Input Resistance 4.0 4.8 5.6 kΩ Self-biased.

Input Capacitance 2 pF CLK2 VS. REFIN DELAY 500 ps Difference at PFD. PRESCALER (PART OF N DIVIDER)

Prescaler Input Frequency

P = 2 DM (2/3) 600 MHz P = 4 DM (4/5) 1000 MHz P = 8 DM (8/9) 1600 MHz P = 16 DM (16/17) 1600 MHz P = 32 DM (32/33) 1600 MHz

CLK2 Input Frequency for PLL 300 MHz A, B counter input frequency.

1.5 % 0.5 < VCP < VCPS − 0.5 V.

1.5 1.6 1.7 V Self-biased; enables ac coupling.

1.3 1.8 V With 200 mV p-p signal applied.

= 4.12 kΩ, CPR

SET

= 5.1 kΩ, unless otherwise noted.

SET

With CPR

= 5.1 kΩ.

SET

Frequencies > 1200 MHz (LVPECL) or 800 MHz (LVDS) require a minimum divide-by-2 (see the

Distribution Section).

CLK2 ac-coupled; CLK2B capacitively bypassed to RF ground.

VCO/VCXO Feedback Divider—N (P, A, B)

See the section.

Rev. A | Page 4 of 60

AD9511

Parameter Min Typ Max Unit Test Conditions/Comments

NOISE CHARACTERISTICS

In-Band Noise of the Charge Pump/ Phase Frequency Detector (In-Band Means Within the LBW of the PLL)

@ 50 kHz PFD Frequency −172 dBc/Hz @ 2 MHz PFD Frequency −156 dBc/Hz @ 10 MHz PFD Frequency −149 dBc/Hz @ 50 MHz PFD Frequency −142 dBc/Hz

PLL Figure of Merit

PLL DIGITAL LOCK DETECT WINDOW

Required to Lock

(Coincidence of Edges) Low Range (ABP 1.3 ns, 2.9 ns Only) 3.5 ns <5> = 1b. High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns <5> = 0b. High Range (ABP 6 ns) 3.5 ns <5> = 0b.

To Unlock After Lock (Hysteresis)

4

Low Range (ABP 1.3 ns, 2.9 ns Only) 7 ns <5> = 1b. High Range (ABP 1.3 ns, 2.9 ns) 15 ns <5> = 0b. High Range (ABP 6 ns) 11 ns <5> = 0b.

1

REFIN and REFINB self-bias points are offset slightly to avoid chatter on an open input condition.

2

CLK2 is electrically identical to CLK1; the distribution only input can be used as differential or single-ended input (see the Clock Inputs section).

3

Example: −218 + 10 × log(f

4

For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

) + 20 × log(N) should give the values for the in-band noise at the VCO output.

PFD

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).

−218 + 10 × log (f

dBc/Hz

)

PFD

Approximation of the PFD/CP phase noise floor (in the flat region) inside the PLL loop bandwidth. When running closed loop this phase noise is gained up by 20 × log(N)

4

Signal available at STATUS pin when selected by 08h<5:2>.

Selected by Register ODh.

Selected by Register 0Dh.

3

.

CLOCK INPUTS

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

CLOCK INPUTS (CLK1, CLK2)

Input Frequency 0 1.6 GHz Input Sensitivity 1502 mV p-p

Input Level 2

Input Common-Mode Voltage, V Input Common-Mode Range, V Input Sensitivity, Single-Ended 150 mV p-p CLK2 ac-coupled; CLK2B ac bypassed to RF ground. Input Resistance 4.0 4.8 5.6 kΩ Self-biased. Input Capacitance 2 pF

1

CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input.

2

With a 50 Ω termination, this is −12.5 dBm.

3

With a 50 Ω termination, this is +10 dBm.

1

Jitter performance can be improved with higher slew rates (greater swing).

3

V p-p

Larger swings turn on the protection diodes and can degrade jitter performance.

CM

CMR

1.5 1.6 1.7 V Self-biased; enables ac coupling.

1.3 1.8 V With 200 mV p-p signal applied; dc-coupled.

Rev. A | Page 5 of 60

AD9511

CLOCK OUTPUTS

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL CLOCK OUTPUTS Termination = 50 Ω to VS − 2 V

OUT0, OUT1, OUT2; Differential Output level 3Dh (3Eh) (3Fh)<3:2> = 10b

Output Frequency 1200 MHz See Figure 21

Output High Voltage (VOH) VS − 1.22 VS − 0.98 VS − 0.93 V

Output Low Voltage (VOL) VS − 2.10 VS − 1.80 VS − 1.67 V

Output Differential Voltage (VOD) 660 810 965 mV LVDS CLOCK OUTPUTS Termination = 100 Ω differential; default

OUT3, OUT4; Differential

Output Frequency 800 MHz See Figure 22

Differential Output Voltage (VOD) 250 360 450 mV

Delta V

OD

Output Offset Voltage (VOS) 1.125 1.23 1.375 V

Delta V

OS

Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND CMOS CLOCK OUTPUTS

OUT3, OUT4

Output Frequency 250 MHz With 5 pF load each output; see Figure 23

Output Voltage High (VOH) VS-0.1 V @ 1 mA load

Output Voltage Low (VOL) 0.1 V @ 1 mA load

25 mV

Output level 40h (41h)<2:1> = 01b

3.5 mA termination current

Single-ended measurements; B outputs: inverted, termination open

Rev. A | Page 6 of 60

AD9511

TIMING CHARACTERISTICS

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL

Termination = 50 Ω to V

Output level 3Dh (3Eh) (3Fh)<3:2> = 10b Output Rise Time, t Output Fall Time, t

RP

FP

PROPAGATION DELAY, t

, CLK-TO-LVPECL OUT

PECL

1

130 180 ps 20% to 80%, measured differentially 130 180 ps 80% to 20%, measured differentially

Divide = Bypass 335 490 635 ps Divide = 2 − 32 375 545 695 ps Variation with Temperature 0.5 ps/°C

OUTPUT SKEW, LVPECL OUTPUTS

OUT1 to OUT0 on Same Part, t OUT1 to OUT2 on Same Part, t OUT0 to OUT2 on Same Part, t All LVPECL OUT Across Multiple Parts, t Same LVPECL OUT Across Multiple Parts, t

LVDS

SKP

2

3

SKP_AB

3

SKP_AB

70 100 140 ps 15 45 80 ps 45 65 90 Ps 275 ps 130 ps

Termination = 100 Ω differential

Output level 40h (41h) <2:1> = 01b

3.5 mA termination current Output Rise Time, t Output Fall Time, t

RL

FL

PROPAGATION DELAY, t

, CLK-TO-LVDS OUT

LVDS

1

200 350 ps 20% to 80%, measured differentially 210 350 ps 80% to 20%, measured differentially Delay off on OUT4

OUT3 to OUT4

Divide = Bypass 0.99 1.33 1.59 ns Divide = 2 − 32 1.04 1.38 1.64 ns Variation with Temperature 0.9 ps/°C

OUTPUT SKEW, LVDS OUTPUTS Delay off on OUT4

OUT3 to OUT4 on Same Part, t All LVDS OUTs Across Multiple Parts, t Same LVDS OUT Across Multiple Parts, t

SKV

2

3

SKV_AB

3

SKV_AB

−85 +270 ps 450 ps 325 ps

CMOS B outputs are inverted; termination = open

Output Rise Time, t Output Fall Time, t

RC

FC

PROPAGATION DELAY, t

, CLK-TO-CMOS OUT

CMOS

1

681 865 ps 20% to 80%; C 646 992 ps 80% to 20%; C

LOAD

Delay off on OUT4 Divide = Bypass 1.02 1.39 1.71 ns Divide = 2 − 32 1.07 1.44 1.76 ns Variation with Temperature 1 ps/°C

OUTPUT SKEW, CMOS OUTPUTS Delay off on OUT4

OUT3 to OUT4 on Same Part, t All CMOS OUT Across Multiple Parts, t Same CMOS OUT Across Multiple Parts, t

SKC

2

3

SKC_AB

3

SKC_AB

−140 +145 +300

650 ps

500 ps

LVPECL-TO-LVDS OUT Everything the same; different logic type

Output Skew, t

SKP_V

0.74 0.92 1.14 ns LVPECL to LVDS on same part

LVPECL-TO-CMOS OUT Everything the same; different logic type

Output Skew, t

SKP_C

0.88 1.14 1.43 ns LVPECL to CMOS on same part

LVDS-TO-CMOS OUT Everything the same; different logic type

Output Skew, t

SKV_C

158 353 506 ps LVDS to CMOS on same part

= 3 pF = 3 pF

− 2 V

S

Rev. A | Page 7 of 60

AD9511

Parameter Min Typ Max Unit Test Conditions/Comments

DELAY ADJUST OUT4; LVDS and CMOS

Shortest Delay Range

Zero Scale 0.05 0.36 0.68 ns 36h <5:1> 00000b Full Scale 0.72 1.12 1.51 ns 36h <5:1> 11111b Linearity, DNL 0.5 LSB Linearity, INL 0.8 LSB

Longest Delay Range

Zero Scale 0.20 0.57 0.95 ns 36h <5:1> 00000b Full Scale 9.0 10.2 11.6 ns 36h <5:1> 11111b Linearity, DNL 0.3 LSB Linearity, INL 0.6 LSB

Delay Variation with Temperature

Long Delay Range, 10 ns

Zero Scale 0.35 ps/°C Full Scale −0.14 ps/°C

Short Delay Range, 1 ns

Zero Scale 0.51 ps/°C Full Scale 0.67 ps/°C

1

The measurements are for CLK1. For CLK2, add approximately 25 ps.

2

This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature.

3

This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.

4

Incremental delay; does not include propagation delay.

5

All delays between zero scale and full scale can be estimated by linear interpolation.

4

5

35h <5:1> 11111b

35h <5:1> 00000b

Rev. A | Page 8 of 60

AD9511

CLOCK OUTPUT PHASE NOISE

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

CLK1-TO-LVPECL ADDITIVE PHASE NOISE

CLK1 = 622.08 MHz, OUT = 622.08 MHz Input slew rate > 1 V/ns

Divide Ratio = 1

@ 10 Hz Offset −125 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −148 dBc/Hz @ 100 kHz Offset −153 dBc/Hz >1 MHz Offset −154 dBc/Hz

CLK1 = 622.08 MHz, OUT = 155.52 MHz

Divide Ratio = 4

@ 10 Hz Offset −128 dBc/Hz @ 100 Hz Offset −140 dBc/Hz @ 1 kHz Offset −148 dBc/Hz @ 10 kHz Offset −155 dBc/Hz @ 100 kHz Offset −161 dBc/Hz >1 MHz Offset −161 dBc/Hz

CLK1 = 622.08 MHz, OUT = 38.88 MHz

Divide Ratio = 16

@ 10 Hz Offset −135 dBc/Hz @ 100 Hz Offset −145 dBc/Hz @ 1 kHz Offset −158 dBc/Hz @ 10 kHz Offset −165 dBc/Hz @ 100 kHz Offset −165 dBc/Hz >1 MHz Offset −166 dBc/Hz

CLK1 = 491.52 MHz, OUT = 61.44 MHz

Divide Ratio = 8

@ 10 Hz Offset −131 dBc/Hz @ 100 Hz Offset −142 dBc/Hz @ 1 kHz Offset −153 dBc/Hz @ 10 kHz Offset −160 dBc/Hz @ 100 kHz Offset −165 dBc/Hz >1 MHz Offset −165 dBc/Hz

CLK1 = 491.52 MHz, OUT = 245.76 MHz

Divide Ratio = 2

@ 10 Hz Offset −125 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −151 dBc/Hz @ 100 kHz Offset −157 dBc/Hz >1 MHz Offset −158 dBc/Hz

CLK1 = 245.76 MHz, OUT = 61.44 MHz

Divide Ratio = 4

@ 10 Hz Offset −138 dBc/Hz @ 100 Hz Offset −144 dBc/Hz @ 1 kHz Offset −154 dBc/Hz @ 10 kHz Offset −163 dBc/Hz @ 100 kHz Offset −164 dBc/Hz >1 MHz Offset −165 dBc/Hz

Distribution Section only; does not include PLL or external VCO/VCXO

Rev. A | Page 9 of 60

AD9511

Parameter Min Typ Max Unit Test Conditions/Comments

CLK1-TO-LVDS ADDITIVE PHASE NOISE

CLK1 = 622.08 MHz, OUT= 622.08 MHz

Divide Ratio = 1

@ 10 Hz Offset −100 dBc/Hz @ 100 Hz Offset −110 dBc/Hz @ 1 kHz Offset −118 dBc/Hz @ 10 kHz Offset −129 dBc/Hz @ 100 kHz Offset −135 dBc/Hz @ 1 MHz Offset −140 dBc/Hz >10 MHz Offset −148 dBc/Hz

CLK1 = 622.08 MHz, OUT = 155.52 MHz

Divide Ratio = 4

@ 10 Hz Offset −112 dBc/Hz @ 100 Hz Offset −122 dBc/Hz @ 1 kHz Offset −132 dBc/Hz @ 10 kHz Offset −142 dBc/Hz @ 100 kHz Offset −148 dBc/Hz @ 1 MHz Offset −152 dBc/Hz >10 MHz Offset −155 dBc/Hz

CLK1 = 491.52 MHz, OUT = 245.76 MHz

Divide Ratio = 2

@ 10 Hz Offset −108 dBc/Hz @ 100 Hz Offset −118 dBc/Hz @ 1 kHz Offset −128 dBc/Hz @ 10 kHz Offset −138 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −148 dBc/Hz >10 MHz Offset −154 dBc/Hz

CLK1 = 491.52 MHz, OUT = 122.88 MHz

Divide Ratio = 4

@ 10 Hz Offset −118 dBc/Hz @ 100 Hz Offset −129 dBc/Hz @ 1 kHz Offset −136 dBc/Hz @ 10 kHz Offset −147 dBc/Hz @ 100 kHz Offset −153 dBc/Hz @ 1 MHz Offset −156 dBc/Hz >10 MHz Offset −158 dBc/Hz

CLK1 = 245.76 MHz, OUT = 245.76 MHz

Divide Ratio = 1

@ 10 Hz Offset −108 dBc/Hz @ 100 Hz Offset −118 dBc/Hz @ 1 kHz Offset −128 dBc/Hz @ 10 kHz Offset −138 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −148 dBc/Hz >10 MHz Offset −155 dBc/Hz

CLK1 = 245.76 MHz, OUT = 122.88 MHz

Divide Ratio = 2

@ 10 Hz Offset −118 dBc/Hz @ 100 Hz Offset −127 dBc/Hz @ 1 kHz Offset −137 dBc/Hz @ 10 kHz Offset −147 dBc/Hz

Distribution Section only; does not include PLL or external VCO/VCXO

Rev. A | Page 10 of 60

AD9511

Parameter Min Typ Max Unit Test Conditions/Comments

@ 100 kHz Offset −154 dBc/Hz @ 1 MHz Offset −156 dBc/Hz >10 MHz Offset −158 dBc/Hz

CLK1-TO-CMOS ADDITIVE PHASE NOISE

CLK1 = 245.76 MHz, OUT = 245.76 MHz

Divide Ratio = 1

@ 10 Hz Offset −110 dBc/Hz @ 100 Hz Offset −121 dBc/Hz @ 1 kHz Offset −130 dBc/Hz @ 10 kHz Offset −140 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −149 dBc/Hz > 10 MHz Offset −156 dBc/Hz

CLK1 = 245.76 MHz, OUT = 61.44 MHz

Divide Ratio = 4

@ 10 Hz Offset −122 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −143 dBc/Hz @ 10 kHz Offset −152 dBc/Hz @ 100 kHz Offset −158 dBc/Hz @ 1 MHz Offset −160 dBc/Hz >10 MHz Offset −162 dBc/Hz

CLK1 = 78.6432 MHz, OUT = 78.6432 MHz

Divide Ratio = 1

@ 10 Hz Offset −122 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −150 dBc/Hz @ 100 kHz Offset −155 dBc/Hz @ 1 MHz Offset −158 dBc/Hz >10 MHz Offset −160 dBc/Hz

CLK1 = 78.6432 MHz, OUT = 39.3216 MHz

Divide Ratio = 2

@ 10 Hz Offset −128 dBc/Hz @ 100 Hz Offset −136 dBc/Hz @ 1 kHz Offset −146 dBc/Hz @ 10 kHz Offset −155 dBc/Hz @ 100 kHz Offset −161 dBc/Hz >1 MHz Offset −162 dBc/Hz

Distribution Section only; does not include PLL or external VCO/VCXO

Rev. A | Page 11 of 60

AD9511

CLOCK OUTPUT ADDITIVE TIME JITTER

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

CLK1 = 622.08 MHz 40 fs rms BW = 12 kHz − 20 MHz (OC-12)

Any LVPECL (OUT0 to OUT2) = 622.08 MHz Divide Ratio = 1

CLK1 = 622.08 MHz 55 fs rms BW = 12 kHz − 20 MHz (OC-3)

Any LVPECL (OUT0 to OUT2) = 155.52 MHz Divide Ratio = 4

CLK1 = 400 MHz 215 fs rms

Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4

CLK1 = 400 MHz 215 fs rms

Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 100 MHz Interferer(s) Both LVDS (OUT3, OUT4) = 100 MHz Interferer(s)

CLK1 = 400 MHz 222 fs rms

Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Interferer(s) Both LVDS (OUT3, OUT4) = 50 MHz Interferer(s)

CLK1 = 400 MHz 225 fs rms

Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Interferer(s) Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs Off) Interferer(s)

CLK1 = 400 MHz 225 fs rms

Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Interferer(s) Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs On) Interferer(s)

LVDS OUTPUT ADDITIVE TIME JITTER

CLK1 = 400 MHz 264 fs rms

LVDS (OUT3) = 100 MHz Divide Ratio = 4

CLK1 = 400 MHz 319 fs rms

LVDS (OUT4) = 100 MHz Divide Ratio = 4

Distribution Section only; does not include PLL or external VCO/VCXO

Calculated from SNR of ADC method;

= 100 MHz with AIN = 170 MHz

F

C

Calculated from SNR of ADC method; F

= 100 MHz with AIN = 170 MHz

C

Calculated from SNR of ADC method; F

= 100 MHz with AIN = 170 MHz

C

Calculated from SNR of ADC method; F

= 100 MHz with AIN = 170 MHz

C

Calculated from SNR of ADC method;

= 100 MHz with AIN = 170 MHz

F

C

Distribution Section only; does not include PLL or external VCO/VCXO

Calculated from SNR of ADC method;

= 100 MHz with AIN = 170 MHz

F

C

Calculated from SNR of ADC method;

= 100 MHz with AIN = 170 MHz

F

C

Rev. A | Page 12 of 60

AD9511

Parameter Min Typ Max Unit Test Conditions/Comments

CLK1 = 400 MHz 395 fs rms

LVDS (OUT3) = 100 MHz Divide Ratio = 4 LVDS (OUT4) = 50 MHz Interferer(s) All LVPECL = 50 MHz Interferer(s)

CLK1 = 400 MHz 395 fs rms

LVDS (OUT4) = 100 MHz Divide Ratio = 4 LVDS (OUT3) = 50 MHz Interferer(s) All LVPECL = 50 MHz Interferer(s)

CLK1 = 400 MHz 367 fs rms

LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs Off) Interferer(s) All LVPECL = 50 MHz Interferer(s)

CLK1 = 400 MHz 367 fs rms

LVDS (OUT4) = 100 MHz Divide Ratio = 4 CMOS (OUT3) = 50 MHz (B Outputs Off) Interferer(s) All LVPECL = 50 MHz Interferer(s)

CLK1 = 400 MHz 548 fs rms

LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs On) Interferer(s) All LVPECL = 50 MHz Interferer(s)

CLK1 = 400 MHz 548 fs rms

LVDS (OUT4) = 100 MHz Divide Ratio = 4 CMOS (OUT3) = 50 MHz (B Outputs On) Interferer(s) All LVPECL = 50 MHz Interferer(s)

CMOS OUTPUT ADDITIVE TIME JITTER

CLK1 = 400 MHz 275 fs rms

Both CMOS (OUT3, OUT4) = 100 MHz (B Output On) Divide Ratio = 4

CLK1 = 400 MHz 400 fs rms

CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz Interferer(s) LVDS (OUT4) = 50 MHz Interferer(s)

CLK1 = 400 MHz 374 fs rms

CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz Interferer(s) CMOS (OUT4) = 50 MHz (B Output Off) Interferer(s)

Calculated from SNR of ADC method;

= 100 MHz with AIN = 170 MHz

F

C

Calculated from SNR of ADC method; F

= 100 MHz with AIN = 170 MHz

C

Calculated from SNR of ADC method; F

= 100 MHz with AIN = 170 MHz

C

Calculated from SNR of ADC method; F

= 100 MHz with AIN = 170 MHz

C

Calculated from SNR of ADC method;

= 100 MHz with AIN = 170 MHz

F

C

Calculated from SNR of ADC method;

= 100 MHz with AIN = 170 MHz

F

C

Distribution Section only; does not include PLL or external VCO/VCXO

Calculated from SNR of ADC method;

= 100 MHz with AIN = 170 MHz

F

C

Calculated from SNR of ADC method;

= 100 MHz with AIN = 170 MHz

F

C

Calculated from SNR of ADC method;

= 100 MHz with AIN = 170 MHz

F

C

Rev. A | Page 13 of 60

AD9511

Parameter Min Typ Max Unit Test Conditions/Comments

CLK1 = 400 MHz 555 fs rms

CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz Interferer(s) CMOS (OUT4) = 50 MHz (B Output On) Interferer(s)

DELAY BLOCK ADDITIVE TIME JITTER

1

Incremental additive jitter

100 MHz Output

Delay FS = 1 ns (1600 A, 1C) Fine Adj. 00000 0.61 ps Delay FS = 1 ns (1600 A, 1C) Fine Adj. 11111 0.73 ps Delay FS = 2 ns (800 A, 1C) Fine Adj. 00000 0.71 ps Delay FS = 2 ns (800 A, 1C) Fine Adj. 11111 1.2 ps Delay FS = 3 ns (800 A, 4C) Fine Adj. 00000 0.86 ps Delay FS = 3 ns (800 A, 4C) Fine Adj. 11111 1.8 ps Delay FS = 4 ns (400 A, 4C) Fine Adj. 00000 1.2 ps Delay FS = 4 ns (400 A, 4C) Fine Adj. 11111 2.1 ps Delay FS = 5 ns (200 A, 1C) Fine Adj. 00000 1.3 ps Delay FS = 5 ns (200 A, 1C) Fine Adj. 11111 2.7 ps Delay FS = 11 ns (200 A, 4C) Fine Adj. 00000 2.0 ps Delay FS = 11 ns (200 A, 4C) Fine Adj. 00100 2.8 ps

1

This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter

should be added to this value using the root sum of the squares (RSS) method.

Calculated from SNR of ADC method;

= 100 MHz with AIN = 170 MHz

F

C

PLL AND DISTRIBUTION PHASE NOISE AND SPURIOUS

Table 7.

Parameter Min Typ Max Unit Test Conditions/Comments

PHASE NOISE AND SPURIOUS

VCXO = 245.76 MHz,

F

= 1.2288 MHz; R = 25, N = 200

PFD

VCXO is Toyocom TCO-2112 245.76.

245.76 MHz Output Divide by 1. Phase Noise @100 kHz Offset <−145 dBc/Hz Dominated by VCXO phase noise. Spurious <−97 dBc

61.44 MHz Output Divide by 4. Phase Noise @100 kHz Offset <−155 dBc/Hz Dominated by VCXO phase noise. Spurious <−97 dBc

Depends on VCO/VCXO selection. Measured at LVPECL clock outputs; ABP = 6 ns; I

First and second harmonics of F

= 5 mA; Ref = 30.72 MHz.

CP

.

PFD

Below measurement floor.

First and second harmonics of F

PFD

.

Below measurement floor.

Rev. A | Page 14 of 60

AD9511

SERIAL CONTROL PORT

Table 8.

Parameter Min Typ Max Unit Test Conditions/Comments

CSB, SCLK (INPUTS)

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 110 µA Input Logic 0 Current 1 µA Input Capacitance 2 pF

SDIO (WHEN INPUT)

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 10 nA Input Logic 0 Current 10 nA Input Capacitance 2 pF

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V

TIMING

Clock Rate (SCLK, 1/t Pulse Width High, t Pulse Width Low, t SDIO to SCLK Setup, t SCLK to SDIO Hold, t SCLK to Valid SDIO and SDO, t CSB to SCLK Setup and Hold, tS, t CSB Minimum Pulse Width High, t

) 25 MHz

SCLK

PWH

PWL

DS

DH

DV

H

PWH

16 ns 16 ns 2 ns 1 ns 6 ns 2 ns 3 ns

CSB and SCLK have 30 kΩ internal pull-down resistors

FUNCTION PIN

Table 9.

Parameter Min Typ Max Unit Test Conditions/Comments

INPUT CHARACTERISTICS

Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 110 µA Logic 0 Current 1 µA Capacitance 2 pF

RESET TIMING

Pulse Width Low 50 ns

SYNC TIMING

Pulse Width Low 1.5 High speed clock cycles

The FUNCTION pin has a 30 kΩ internal pull-down resistor. This pin should normally be held high. Do not leave NC.

High speed clock is CLK1 or CLK2, whichever is used for distribution.

Rev. A | Page 15 of 60

AD9511

STATUS PIN

Table 10.

Parameter Min Typ Max Unit Test Conditions/Comments

OUTPUT CHARACTERISTICS

Output Voltage High (VOH) 2.7 V Output Voltage Low (VOL) 0.4 V

MAXIMUM TOGGLE RATE 100 MHz

ANALOG LOCK DETECT

Capacitance 3 pF

POWER

Table 11.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER-UP DEFAULT MODE POWER DISSIPATION 550 600 mW

POWER DISSIPATION 800 mW

850 mW

Full Sleep Power-Down 35 60 mW

Power-Down (PDB) 60 80 mW

POWER DELTA

CLK1, CLK2 Power-Down 10 15 25 mW Divider, DIV 2 − 32 to Bypass 23 27 33 mW For each divider. LVPECL Output Power-Down (PD2, PD3) 50 65 75 mW

LVDS Output Power-Down 80 92 110 mW For each output. CMOS Output Power-Down (Static) 56 70 85 mW For each output. Static (no clock). CMOS Output Power-Down (Dynamic) 115 150 190 mW

CMOS Output Power-Down (Dynamic) 125 165 210 mW

Delay Block Bypass 20 24 60 mW

PLL Section Power-Down 5 15 40 mW

When selected as a digital output (CMOS); there are other modes in which the STATUS pin is not CMOS digital output. See

Applies when PLL mux is set to any divider or counter output, or PFD up/down pulse. Also applies in analog lock detect mode.

Usually debug mode only. Beware that spurs may couple to output when this pin is toggling.

On-chip capacitance; used to calculate RC time constant for analog lock detect readback. Use a pull-up resistor.

Power-up default state; does not include power dissipated in output load resistors. No clock.

All outputs on. Three LVPECL outputs @ 800 MHz, two CMOS out @ 62 MHz (5 pF load). Does not include power dissipated in external resistors.

All outputs on. Three LVPECL outputs @ 800 MHz, two CMOS out @ 125 MHz (5 pF load). Does not include power dissipated in external resistors.

Maximum sleep is entered by setting 0Ah<1:0> = 01b and 58h<4> = 1b. This powers off the PLL BG and the distribution BG references. Does not include power dissipated in terminations.

Set FUNCTION pin for PDB operation by setting 58h<6:5> = 11b. Pull PDB low. Does not include power dissipated in terminations.

For each output. Does not include dissipation in termination (PD2 only).

For each CMOS output, single-ended. Clocking at 62 MHz with 5 pF load.

For each CMOS output, single-ended. Clocking at 125 MHz with 5 pF load.

Vs. delay block operation at 1 ns fs with maximum delay; output clocking at 25 MHz.

Figure 37.

Rev. A | Page 16 of 60

AD9511

C

TIMING DIAGRAMS

LK1

t

CLK1

DIFFERENTIAL

t

PECL

t

LVDS

t

CMOS

Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode

DIFFERENTIAL

80%

LVPECL

20%

t

RP

Figure 3. LVPECL Timing, Differential

80%

LVDS

20%

t

05286-002

RL

t

FL

05286-065

Figure 4. LVDS Timing, Differential

SINGLE-ENDED

80%

CMOS

3pF LOAD

20%

t

FP

05286-064

t

RC

t

FC

05286-066

Figure 5. CMOS Timing, Single-Ended, 3 pF Load

Rev. A | Page 17 of 60

AD9511

ABSOLUTE MAXIMUM RATINGS

Table 12.

With Respect

Parameter or Pin

VS GND −0.3 +3.6 V VCP GND −0.3 +5.8 V VCP V REFIN, REFINB GND −0.3 VS + 0.3 V RSET GND −0.3 VS + 0.3 V CPRSET GND −0.3 VS + 0.3 V CLK1, CLK1B, CLK2, CLK2B GND −0.3 VS + 0.3 V CLK1 CLK1B −1.2 +1.2 V CLK2 CLK2B −1.2 +1.2 V SCLK, SDIO, SDO, CSB GND −0.3 VS + 0.3 V OUT0, OUT1, OUT2, OUT3,

OUT4 FUNCTION GND −0.3 VS + 0.3 V STATUS GND −0.3 VS + 0.3 V Junction Temperature 150 °C Storage Temperature −65 +150 °C Lead Temperature (10 sec) 300 °C

to

S

Min Max Unit

−0.3 +5.8 V

GND −0.3 V

+ 0.3 V

S

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

Thermal Resistance

48-Lead LFCSP

θ

= 28.5°C/W

JA

1

Thermal impedance measurements were taken on a 4-layer board in still air,

in accordance with EIA/JESD51-7.

1

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 18 of 60

Analog Devices AD9511 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

PLL CHARACTERISTICS

CLOCK INPUTS

CLOCK OUTPUTS

TIMING CHARACTERISTICS

CLOCK OUTPUT PHASE NOISE

CLOCK OUTPUT ADDITIVE TIME JITTER

PLL AND DISTRIBUTION PHASE NOISE AND SPURIOUS

SERIAL CONTROL PORT

FUNCTION PIN

STATUS PIN

POWER

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION