ANALOG DEVICES AD9484 Service Manual

8-Bit, 500 MSPS,

V

A

FEATURES

SNR = 47 dBFS at fIN up to 250 MHz at 500 MSPS ENOB of 7.5 bits at f SFDR = 79 dBc at f Integrated input buffer Excellent linearity

DNL = ±0.1 LSB typical

INL = ±0.1 LSB typical LVDS at 500 MSPS (ANSI-644 levels) 1 GHz full power analog bandwidth On-chip reference, no external decoupling required Low power dissipation

670 mW at 500 MSPS—LVDS SDR output Programmable (nominal) input voltage range

1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal

1.8 V analog and digital supply operation Selectable output data format (offset binary, twos

complement, Gray code) Clock duty cycle stabilizer Integrated data capture clock

up to 250 MHz at 500 MSPS (−1.0 dBFS)

IN

up to 250 MHz at 500 MSPS (−1.0 dBFS)

IN

1.8 V Analog-to-Digital Converter

AD9484

FUNCTIONAL BLOCK DIAGRAM

AGNDPWDN

8 8

ADC

CORE

SERIAL PORT

SDIO CSB

Figure 1.

VDD

AD9484

OUTPUT

STAGING

LVDS

DRVDD DRGND

D7± TO D0±

OR+ OR–

DCO+ DCO–

CML

VIN+ VIN–

CLK+ CLK–

REF

REFERENCE

TRACK-AND-HOLD

CLOCK

MANAGEMENT

SCLK/DFS

09615-001

APPLICATIONS

Wireless and wired broadband communications Cable reverse path Communications test equipment Low cost digital oscilloscopes Satellite subsystems Power amplifier linearization

GENERAL DESCRIPTION

The AD9484 is an 8-bit, monolithic, sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The part operates at up to a 500 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution. The VREF pin can be used to monitor the internal reference or provide an external voltage reference (external reference mode must be enabled through the SPI port).

The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Fabricated on an advanced BiCMOS process, the AD9484 is available in a 56-lead LFCSP, and is specified over the industrial temperature range (−40°C to +85°C). This product is protected by a U.S. patent.

PRODUCT HIGHLIGHTS

1. High Performance.

Maintains 47 dBFS SNR at 500 MSPS with a 250 MHz input.

2. Ease of Use.

LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design.

3. Serial Port Control.

Standard serial port interface supports various product functions, such as data formatting, power-down, gain adjust, and output test pattern generation.

AD9484

REVISION HISTORY

6/11—Rev. 0 to Rev. A

Change to General Description Section ........................................ 1

Change to Aperture Time Parameter in Table 4 ........................... 6

Change to Figure 34 ....................................................................... 16

Changes to Register 17 and Register 18 in Table 12 .................. 20

3/11—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD9484

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 1.

Parameter1 Temp Min Typ Max Unit

RESOLUTION 8 Bits ACCURACY

No Missing Codes Full Guaranteed Offset Error 25°C 0 mV Full −3.0 +3.0 mV Gain Error 25°C 1.0 % FS Full −5.0 +7.0 % FS Differential Nonlinearity (DNL) 25°C ±0.13 LSB Full −0.25 +0.25 LSB Integral Nonlinearity (INL) 25°C ±0.1 LSB Full −0.15 +0.15 LSB

INTERNAL REFERENCE

VREF Full 0.71 0.75 0.78 V

TEMPERATURE DRIFT

Offset Error Full 18 μV/°C Gain Error Full 0.07 %/°C

ANALOG INPUTS (VIN+, VIN−)

Differential Input Voltage Range2 Full 1.18 1.5 1.6 V p-p Input Common-Mode Voltage Full 1.7 V Input Resistance (Differential) Full 1 kΩ Input Capacitance (Differential) Full 1.3 pF

POWER SUPPLY

AVDD Full 1.75 1.8 1.9 V DRVDD Full 1.75 1.8 1.9 V Supply Currents

3

I

Full 283 300 mA

AVDD

3

I

/SDR Mode4 Full 89 100 mA

DRVDD

Power Dissipation

SDR Mode4 Full 670 720 mW Standby Mode Full 40 50 mW Power-Down Mode Full 2.5 7 mW

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the section. Memory Map

3

I

and I

AVDD

4

Single data rate mode; this is the default mode of the AD9484.

are measured with a −1 dBFS, 10.3 MHz sine input at a rated sample rate.

DRVDD

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.

MAX

Rev. A | Page 3 of 24

AD9484

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.

MAX

Table 2.

Parameter

1, 2

Temp Min Typ Max Unit

SNR

fIN = 30.3 MHz 25°C 47.0 dBFS fIN = 70.3 MHz 25°C 47.0 dBFS fIN = 100.3 MHz 25°C 47.0 dBFS Full 46.5 dBFS fIN = 250.3 MHz 25°C 47.0 dBFS fIN = 450.3 MHz 25°C 46.9 dBFS

SINAD

fIN = 30.3 MHz 25°C 47.0 dBFS fIN = 70.3 MHz 25°C 47.0 dBFS fIN = 100.3 MHz 25°C 47.0 dBFS Full 46.4 dBFS fIN = 250.3 MHz 25°C 47.0 dBFS fIN = 450.3 MHz 25°C 46.9 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 30.3 MHz 25°C 7.5 Bits fIN = 70.3 MHz 25°C 7.5 Bits fIN = 100.3 MHz 25°C 7.5 Bits fIN = 250.3 MHz 25°C 7.5 Bits fIN = 450.3 MHz 25°C 7.5 Bits

WORST HARMONIC (SECOND or THIRD)

fIN = 30.3 MHz 25°C −87 dBc fIN = 70.3 MHz 25°C −86 dBc fIN = 100.3 MHz 25°C −87 dBc Full −75 dBc fIN = 250.3 MHz 25°C 83 dBc fIN = 450.3 MHz 25°C 70 dBc

SFDR

fIN = 30.3 MHz 25°C 82 dBc fIN = 70.3 MHz 25°C 81 dBc fIN = 100.3 MHz 25°C 82 dBc Full 75 dBc fIN = 250.3 MHz 25°C 79 dBc fIN = 450.3 MHz 25°C 70 dBc

WORST OTHER HARMONIC (SFDR EXCLUDING SECOND and THIRD)

fIN = 30.3 MHz 25°C −82 dBc fIN = 70.3 MHz 25°C −81 dBc fIN = 100.3 MHz 25°C −82 dBc Full −75 dBc fIN = 250.3 MHz 25°C 79 dBc fIN = 450.3 MHz 25°C 77 dBc

TWO-TONE IMD

f

= 119.5 MHz, f

IN1

= 122.5 MHz 25°C −77 dBc

IN2

ANALOG INPUT BANDWIDTH

Full Power 25°C 1 GHz

1

All ac specifications tested by driving CLK+ and CLK− differentially.

2

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

Rev. A | Page 4 of 24

AD9484

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 3.

Parameter1 Temp Min Typ Max Unit

CLOCK INPUTS

Logic Compliance Full CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage

High Level Input (VIH) Full 0.2 1.8 V p-p

Low Level Input (VIL) Full −1.8 −0.2 V p-p High Level Input Current (IIH) Full −10 +10 μA Low Level Input Current (IIL) Full −10 +10 μA Input Resistance (Differential) Full 8 10 12 kΩ Input Capacitance Full 4 pF

LOGIC INPUTS

Logic 1 Voltage Full 0.8 × DRVDD V Logic 0 Voltage Full 0.2 × DRVDD V Logic 1 Input Current (SDIO, CSB) Full 0 μA Logic 0 Input Current (SDIO, CSB) Full −60 μA Logic 1 Input Current (SCLK, PDWN) Full 50 μA Logic 0 Input Current (SCLK, PDWN) Full 0 μA Input Capacitance Full 4 pF

LOGIC OUTPUTS2

VOD Differential Output Voltage Full 247 454 mV VOS Output Offset Voltage Full 1.125 1.375 V Output Coding

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

LVDS R

TERMINATION

= 100 Ω.

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.

MAX

Rev. A | Page 5 of 24

AD9484

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 4.

Parameter Temp Min Typ Max Unit

Maximum Conversion Rate Full 500 Minimum Conversion Rate Full

1

CLK+ Pulse Width High (tCH) CLK+ Pulse Width Low (tCL)1 Full 0.9 11 ns Output (LVDS—SDR)1

Data Propagation Delay (tPD) Full 0.85 ns Rise Time (tR) (20% to 80%) 25°C 0.15 ns Fall Time (tF) (20% to 80%) 25°C 0.15 ns DCO Propagation Delay (t Data to DCO Skew (t

CPD

) Full −0.07 +0.07 ns

SKEW

Latency Full 15 Clock cycles Aperture Time (tA) 25°C 0.85 ns Aperture Uncertainty (Jitter, tJ) 25°C 80 fs rms

1

See . Figure 2

Timing Diagram

N – 1

VIN+, VIN–

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.

MAX

50 MSPS

MSPS

Full 0.9 11 ns

) Full 0.6 ns

t

A

N

N + 3

N + 1

N + 2

N + 4

N + 5

CLK+

CLK–

DCO+

DCO–

Dx+

Dx–

t

CH

t

CPD

1/

CL

f

S

t

SKEW

t

PD

N – 15 N – 14 N – 13 N – 12 N – 11

09615-002

Figure 2. Timing Diagram

Rev. A | Page 6 of 24

AD9484

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Electrical

AVDD to AGND −0.3 V to +2.0 V DRVDD to DRGND −0.3 V to +2.0 V AGND to DRGND −0.3 V to +0.3 V AVDD to DRVDD −2.0 V to +2.0 V D0+/D0− through D7+/D7−

to DRGND DCO+, DCO− to DRGND −0.3 V to DRVDD + 0.2 V OR+, OR− to DRGND −0.3 V to DRVDD + 0.2 V CLK+ to AGND −0.3 V to AVDD + 0.2 V CLK− to AGND −0.3 V to AVDD + 0.2 V VIN+ to AGND −0.3 V to AVDD + 0.2 V VIN− to AGND −0.3 V to AVDD + 0.2 V SDIO/DCS to DRGND −0.3 V to DRVDD + 0.2 V PDWN to AGND −0.3 V to DRVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.2 V SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V CML to AGND −0.3 V to AVDD + 0.2 V VREF to AGND −0.3 V to AVDD + 0.2 V

Environmental

Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature

(Soldering, 10 sec)

Junction Temperature 150°C

−0.3 V to DRVDD + 0.2 V

300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the PCB increases the reliability of the solder joints, maximizing the thermal capability of the package.

Table 6.

Package Type θJA θ

56-Lead LFCSP_VQ (CP-56-5) 23.7 1.7 °C/W

Unit

JC

Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θ

JA

. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the θ

.

JA

ESD CAUTION

Rev. A | Page 7 of 24

AD9484

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DNC

55

56

54

1DNC 2DNC 3D0– 4D0+ 5D1– 6D1+ 7DRVDD 8DRGND

9D2– 10D2+ 11D3– 12D3+ 13D4– 14D4+

NOTES

1. DNC = DO NOT CONNECT. DO NOT CO NNECT TO THIS PI N.

2. AGND AND DRGND SHO ULD BE TI ED TO A CO MMON QUIET G ROUND PLANE.

3. THE EXPOSED PADDLE MUST BE SOLDERED T O A GROUND PLANE .

PIN 1 INDICATOR

PIN 0 (EXPOSED PADDLE ) = AGND

16

17

15

D5–

D6–

D5+

DCO+

DNC

52

53

50

51

AD9484

TOP VIEW

(Not to Scale)

21

19

20

18

D7–

D7+

D6+

OR–

CO–

CLK–

AVDD

DRVDD

D

48 DRGND

49

22

23

OR+

DRGND

CLK+

AVDD

44

43

45

46

47

42 AVDD 41 AVDD 40 CML 39 AVDD 38 AVDD 37 AVDD 36 VIN– 35 VIN+ 34 AVDD 33 AVDD 32 AVDD 31 VREF 30 AVDD 29 PWDN

24

25

26

27

28

CSB

DNC

SDIO

DRVDD

SCLK/DFS

09615-003

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

0 AGND1 Analog Ground. The exposed paddle must be soldered to a ground plane. 30, 32 to 34, 37 to 39,

AVDD 1.8 V Analog Supply.

41 to 43, 46 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 8, 23, 48 DRGND1 Digital Output Ground. 35 VIN+ Analog Input—True. 36 VIN− Analog Input—Complement. 40 CML

Common-Mode Output. Enabled through the SPI, this pin provides a reference for the

optimized internal bias voltage for VIN+/VIN−. 44 CLK+ Clock Input—True. 45 CLK− Clock Input—Complement. 31 VREF Voltage Reference Internal/Input/Output. Nominally 0.75 V. 1, 2, 28, 51 to 56 DNC Do Not Connect. Do not connect to this pin. This pin should be left floating. 25 SDIO Serial Port Interface (SPI) Data Input/Output. 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 29 PWDN Chip Power-Down. 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 3 D0− D0 Complement Output (LSB). 4 D0+ D0 True Output (LSB). 5 D1− D1 Complement Output. 6 D1+ D1 True Output. 9 D2− D2 Complement Output. 10 D2+ D2 True Output. 11 D3− D3 Complement Output. 12 D3+ D3 True Output. 13 D4− D4 Complement Output.

Rev. A | Page 8 of 24

ANALOG DEVICES AD9484 Service Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

Timing Diagram

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS