ANALOG DEVICES AD9484 Service Manual

8-Bit, 500 MSPS,

V

A

FEATURES

SNR = 47 dBFS at fIN up to 250 MHz at 500 MSPS
ENOB of 7.5 bits at f
SFDR = 79 dBc at f
Integrated input buffer
Excellent linearity

DNL = ±0.1 LSB typical

INL = ±0.1 LSB typical
LVDS at 500 MSPS (ANSI-644 levels)
1 GHz full power analog bandwidth
On-chip reference, no external decoupling required
Low power dissipation

670 mW at 500 MSPS—LVDS SDR output
Programmable (nominal) input voltage range

1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal

1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos

complement, Gray code)
Clock duty cycle stabilizer
Integrated data capture clock

up to 250 MHz at 500 MSPS (−1.0 dBFS)

IN

up to 250 MHz at 500 MSPS (−1.0 dBFS)

IN

1.8 V Analog-to-Digital Converter

AD9484

FUNCTIONAL BLOCK DIAGRAM

AGNDPWDN

8 8

ADC

CORE

SERIAL PORT

SDIO CSB

Figure 1.

VDD

AD9484

OUTPUT

STAGING

LVDS

DRVDD
DRGND

D7± TO D0±

OR+
OR–

DCO+
DCO–

CML

VIN+
VIN–

CLK+
CLK–

REF

REFERENCE

TRACK-AND-HOLD

CLOCK

MANAGEMENT

SCLK/DFS

09615-001

APPLICATIONS

Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Low cost digital oscilloscopes
Satellite subsystems
Power amplifier linearization

GENERAL DESCRIPTION

The AD9484 is an 8-bit, monolithic, sampling analog-to-digital
converter (ADC) optimized for high performance, low power,
and ease of use. The part operates at up to a 500 MSPS conver­sion rate and is optimized for outstanding dynamic performance
in wideband carrier and broadband systems. All necessary
functions, including a sample-and-hold and voltage reference,
are included on the chip to provide a complete signal conversion
solution. The VREF pin can be used to monitor the internal
reference or provide an external voltage reference (external
reference mode must be enabled through the SPI port).

The ADC requires a 1.8 V analog voltage supply and a differen­tial clock for full performance operation. The digital outputs are
LVDS (ANSI-644) compatible and support twos complement,
offset binary format, or Gray code. A data clock output is available
for proper output data timing.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

Fabricated on an advanced BiCMOS process, the AD9484 is availa­ble in a 56-lead LFCSP, and is specified over the industrial
temperature range (−40°C to +85°C). This product is protected
by a U.S. patent.

PRODUCT HIGHLIGHTS

1. High Performance.

Maintains 47 dBFS SNR at 500 MSPS with a 250 MHz input.

2. Ease of Use.

LVDS output data and output clock signal allow interface
to current FPGA technology. The on-chip reference and
sample-and-hold provide flexibility in system design. Use
of a single 1.8 V supply simplifies system power supply design.

3. Serial Port Control.

Standard serial port interface supports various product
functions, such as data formatting, power-down, gain
adjust, and output test pattern generation.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

AD9484

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications .......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ........................................... 10

Equivalent Circuits ......................................................................... 13

Theory of Operation ...................................................................... 14

Analog Input and Voltage Reference ....................................... 14

Clock Input Considerations ...................................................... 15

Power Dissipation and Power-Down Mode ........................... 16

Digital Outputs ........................................................................... 16

Timing ......................................................................................... 17

VREF ............................................................................................ 17

AD9484 Configuration Using the SPI ..................................... 18

Hardware Interface ..................................................................... 18

Configuration Without the SPI ................................................ 18

Memory Map .................................................................................. 20

Reading the Memory Map Table .............................................. 20

Reserved Locations .................................................................... 20

Default Values ............................................................................. 20

Logic Levels ................................................................................. 20

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 23

REVISION HISTORY

6/11—Rev. 0 to Rev. A

Change to General Description Section ........................................ 1

Change to Aperture Time Parameter in Table 4 ........................... 6

Change to Figure 34 ....................................................................... 16

Changes to Register 17 and Register 18 in Table 12 .................. 20

3/11—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD9484

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 1.

Parameter1 Temp Min Typ Max Unit

RESOLUTION 8 Bits
ACCURACY

No Missing Codes Full Guaranteed
Offset Error 25°C 0 mV
Full −3.0 +3.0 mV
Gain Error 25°C 1.0 % FS
Full −5.0 +7.0 % FS
Differential Nonlinearity (DNL) 25°C ±0.13 LSB
Full −0.25 +0.25 LSB
Integral Nonlinearity (INL) 25°C ±0.1 LSB
Full −0.15 +0.15 LSB

INTERNAL REFERENCE

VREF Full 0.71 0.75 0.78 V

TEMPERATURE DRIFT

Offset Error Full 18 μV/°C
Gain Error Full 0.07 %/°C

ANALOG INPUTS (VIN+, VIN−)

Differential Input Voltage Range2 Full 1.18 1.5 1.6 V p-p
Input Common-Mode Voltage Full 1.7 V
Input Resistance (Differential) Full 1 kΩ
Input Capacitance (Differential) Full 1.3 pF

POWER SUPPLY

AVDD Full 1.75 1.8 1.9 V
DRVDD Full 1.75 1.8 1.9 V
Supply Currents

3

I

Full 283 300 mA

AVDD

3

I

/SDR Mode4 Full 89 100 mA

DRVDD

Power Dissipation

SDR Mode4 Full 670 720 mW
Standby Mode Full 40 50 mW
Power-Down Mode Full 2.5 7 mW

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the section. Memory Map

3

I

and I

AVDD

4

Single data rate mode; this is the default mode of the AD9484.

are measured with a −1 dBFS, 10.3 MHz sine input at a rated sample rate.

DRVDD

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.

MAX

Rev. A | Page 3 of 24

AD9484

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.

MAX

Table 2.

Parameter

1, 2

Temp Min Typ Max Unit

SNR

fIN = 30.3 MHz 25°C 47.0 dBFS
fIN = 70.3 MHz 25°C 47.0 dBFS
fIN = 100.3 MHz 25°C 47.0 dBFS
Full 46.5 dBFS
fIN = 250.3 MHz 25°C 47.0 dBFS
fIN = 450.3 MHz 25°C 46.9 dBFS

SINAD

fIN = 30.3 MHz 25°C 47.0 dBFS
fIN = 70.3 MHz 25°C 47.0 dBFS
fIN = 100.3 MHz 25°C 47.0 dBFS
Full 46.4 dBFS
fIN = 250.3 MHz 25°C 47.0 dBFS
fIN = 450.3 MHz 25°C 46.9 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 30.3 MHz 25°C 7.5 Bits
fIN = 70.3 MHz 25°C 7.5 Bits
fIN = 100.3 MHz 25°C 7.5 Bits
fIN = 250.3 MHz 25°C 7.5 Bits
fIN = 450.3 MHz 25°C 7.5 Bits

WORST HARMONIC (SECOND or THIRD)

fIN = 30.3 MHz 25°C −87 dBc
fIN = 70.3 MHz 25°C −86 dBc
fIN = 100.3 MHz 25°C −87 dBc
Full −75 dBc
fIN = 250.3 MHz 25°C 83 dBc
fIN = 450.3 MHz 25°C 70 dBc

SFDR

fIN = 30.3 MHz 25°C 82 dBc
fIN = 70.3 MHz 25°C 81 dBc
fIN = 100.3 MHz 25°C 82 dBc
Full 75 dBc
fIN = 250.3 MHz 25°C 79 dBc
fIN = 450.3 MHz 25°C 70 dBc

WORST OTHER HARMONIC (SFDR EXCLUDING SECOND and THIRD)

fIN = 30.3 MHz 25°C −82 dBc
fIN = 70.3 MHz 25°C −81 dBc
fIN = 100.3 MHz 25°C −82 dBc
Full −75 dBc
fIN = 250.3 MHz 25°C 79 dBc
fIN = 450.3 MHz 25°C 77 dBc

TWO-TONE IMD

f

= 119.5 MHz, f

IN1

= 122.5 MHz 25°C −77 dBc

IN2

ANALOG INPUT BANDWIDTH

Full Power 25°C 1 GHz

1

All ac specifications tested by driving CLK+ and CLK− differentially.

2

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

Rev. A | Page 4 of 24

AD9484

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 3.

Parameter1 Temp Min Typ Max Unit

CLOCK INPUTS

Logic Compliance Full CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 0.9 V
Differential Input Voltage

High Level Input (VIH) Full 0.2 1.8 V p-p

Low Level Input (VIL) Full −1.8 −0.2 V p-p
High Level Input Current (IIH) Full −10 +10 μA
Low Level Input Current (IIL) Full −10 +10 μA
Input Resistance (Differential) Full 8 10 12 kΩ
Input Capacitance Full 4 pF

LOGIC INPUTS

Logic 1 Voltage Full 0.8 × DRVDD V
Logic 0 Voltage Full 0.2 × DRVDD V
Logic 1 Input Current (SDIO, CSB) Full 0 μA
Logic 0 Input Current (SDIO, CSB) Full −60 μA
Logic 1 Input Current (SCLK, PDWN) Full 50 μA
Logic 0 Input Current (SCLK, PDWN) Full 0 μA
Input Capacitance Full 4 pF

LOGIC OUTPUTS2

VOD Differential Output Voltage Full 247 454 mV
VOS Output Offset Voltage Full 1.125 1.375 V
Output Coding

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

LVDS R

TERMINATION

= 100 Ω.

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.

MAX

Rev. A | Page 5 of 24

AD9484

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 4.

Parameter Temp Min Typ Max Unit

Maximum Conversion Rate Full 500
Minimum Conversion Rate Full

1

CLK+ Pulse Width High (tCH)
CLK+ Pulse Width Low (tCL)1 Full 0.9 11 ns
Output (LVDS—SDR)1

Data Propagation Delay (tPD) Full 0.85 ns
Rise Time (tR) (20% to 80%) 25°C 0.15 ns
Fall Time (tF) (20% to 80%) 25°C 0.15 ns
DCO Propagation Delay (t
Data to DCO Skew (t

CPD

) Full −0.07 +0.07 ns

SKEW

Latency Full 15 Clock cycles
Aperture Time (tA) 25°C 0.85 ns
Aperture Uncertainty (Jitter, tJ) 25°C 80 fs rms

1

See . Figure 2

Timing Diagram

N – 1

VIN+, VIN–

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.

MAX

50 MSPS

MSPS

Full 0.9 11 ns

) Full 0.6 ns

t

A

N

N + 3

N + 1

N + 2

N + 4

N + 5

CLK+

CLK–

DCO+

DCO–

Dx+

Dx–

t

CH

t

t

CPD

1/

CL

f

S

t

SKEW

t

PD

N – 15 N – 14 N – 13 N – 12 N – 11

09615-002

Figure 2. Timing Diagram

Rev. A | Page 6 of 24

AD9484

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Electrical

AVDD to AGND −0.3 V to +2.0 V
DRVDD to DRGND −0.3 V to +2.0 V
AGND to DRGND −0.3 V to +0.3 V
AVDD to DRVDD −2.0 V to +2.0 V
D0+/D0− through D7+/D7−

to DRGND
DCO+, DCO− to DRGND −0.3 V to DRVDD + 0.2 V
OR+, OR− to DRGND −0.3 V to DRVDD + 0.2 V
CLK+ to AGND −0.3 V to AVDD + 0.2 V
CLK− to AGND −0.3 V to AVDD + 0.2 V
VIN+ to AGND −0.3 V to AVDD + 0.2 V
VIN− to AGND −0.3 V to AVDD + 0.2 V
SDIO/DCS to DRGND −0.3 V to DRVDD + 0.2 V
PDWN to AGND −0.3 V to DRVDD + 0.2 V
CSB to AGND −0.3 V to DRVDD + 0.2 V
SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V
CML to AGND −0.3 V to AVDD + 0.2 V
VREF to AGND −0.3 V to AVDD + 0.2 V

Environmental

Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature

(Soldering, 10 sec)

Junction Temperature 150°C

−0.3 V to DRVDD + 0.2 V

300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the PCB
increases the reliability of the solder joints, maximizing the
thermal capability of the package.

Table 6.

Package Type θJA θ

56-Lead LFCSP_VQ (CP-56-5) 23.7 1.7 °C/W

Unit

JC

Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θ

JA

. In
addition, metal in direct contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the θ

.

JA

ESD CAUTION

Rev. A | Page 7 of 24

AD9484

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DNC

DNC

DNC

55

56

54

1DNC
2DNC
3D0–
4D0+
5D1–
6D1+
7DRVDD
8DRGND

9D2–
10D2+
11D3–
12D3+
13D4–
14D4+

NOTES

1. DNC = DO NOT CONNECT. DO NOT CO NNECT TO THIS PI N.

2. AGND AND DRGND SHO ULD BE TI ED TO A CO MMON
QUIET G ROUND PLANE.

3. THE EXPOSED PADDLE MUST BE SOLDERED T O
A GROUND PLANE .

PIN 1
INDICATOR

PIN 0 (EXPOSED PADDLE ) = AGND

16

17

15

D5–

D6–

D5+

DCO+

DNC

DNC

DNC

52

53

50

51

AD9484

TOP VIEW

(Not to Scale)

21

19

20

18

D7–

D7+

D6+

OR–

CO–

CLK–

AVDD

DRVDD

D

48 DRGND

49

22

23

OR+

DRGND

CLK+

AVDD

44

43

45

46

47

42 AVDD
41 AVDD
40 CML
39 AVDD
38 AVDD
37 AVDD
36 VIN–
35 VIN+
34 AVDD
33 AVDD
32 AVDD
31 VREF
30 AVDD
29 PWDN

24

25

26

27

28

CSB

DNC

SDIO

DRVDD

SCLK/DFS

09615-003

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

0 AGND1 Analog Ground. The exposed paddle must be soldered to a ground plane.
30, 32 to 34, 37 to 39,

AVDD 1.8 V Analog Supply.

41 to 43, 46
7, 24, 47 DRVDD 1.8 V Digital Output Supply.
8, 23, 48 DRGND1 Digital Output Ground.
35 VIN+ Analog Input—True.
36 VIN− Analog Input—Complement.
40 CML

Common-Mode Output. Enabled through the SPI, this pin provides a reference for the

optimized internal bias voltage for VIN+/VIN−.
44 CLK+ Clock Input—True.
45 CLK− Clock Input—Complement.
31 VREF Voltage Reference Internal/Input/Output. Nominally 0.75 V.
1, 2, 28, 51 to 56 DNC Do Not Connect. Do not connect to this pin. This pin should be left floating.
25 SDIO Serial Port Interface (SPI) Data Input/Output.
26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode).
27 CSB Serial Port Chip Select (Active Low).
29 PWDN Chip Power-Down.
49 DCO− Data Clock Output—Complement.
50 DCO+ Data Clock Output—True.
3 D0− D0 Complement Output (LSB).
4 D0+ D0 True Output (LSB).
5 D1− D1 Complement Output.
6 D1+ D1 True Output.
9 D2− D2 Complement Output.
10 D2+ D2 True Output.
11 D3− D3 Complement Output.
12 D3+ D3 True Output.
13 D4− D4 Complement Output.

Rev. A | Page 8 of 24

AD9484

Pin No. Mnemonic Description

14 D4+ D4 True Output.
15 D5− D5 Complement Output.
16 D5+ D5 True Output.
17 D6− D6 Complement Output.
18 D6+ D6 True Output.
19 D7− D7 Complement Output (MSB).
20 D7+ D7 True Output (MSB).
21 OR− Overrange Complement Output.
22 OR+ Overrange True Output.

1

Tie AGND and DRGND to a common quiet ground plane.

Rev. A | Page 9 of 24

AD9484

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, TA = 25°C, 1.5 V p-p differential input, AIN = −1 dBFS, unless otherwise noted.

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBFS)

–70

–80

–90

–100

0 20 40 60 80 100 120 140 160 180

FREQUENC Y (MHz)

500MSPS

30.3M Hz AT –1.0dBFS
SNR: 46.0dB
ENOB: 7.5 BITS
SFDR: 82dBc

Figure 4. 64k Point Single-Tone FFT; 500 MSPS, 30.3 MHz

200 220 240

09615-106

0

500MSPS

–10

270.3M Hz AT –1.0dBFS
SNR: 46.0dB

–20

ENOB: 7.5 BITS
SFDR: 79dBc

–30

–40

–50

–60

AMPLITUDE (dBFS)

–70

–80

–90

–100

0 20 40 60 80 100 120 140 160 180

FREQUENC Y (MHz)

200 220 240

Figure 7. 64k Point Single-Tone FFT; 500 MSPS, 270.3 MHz

09615-109

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBFS)

–70

–80

–90

–100

0 20 40 60 80 100 120 140 160 180

FREQUENC Y (MHz)

500MSPS

100.3M Hz AT –1.0dBFS
SNR: 46.0dB
ENOB: 7.5 BITS
SFDR: 83dBc

200 220 240

Figure 5. 64k Point Single-Tone FFT; 500 MSPS, 100.3 MHz

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBFS)

–70

–80

–90

–100

0 20 40 60 80 100 120 140 160 180

FREQUENC Y (MHz)

500MSPS

140.3M Hz AT –1.0dBFS
SNR: 46.0dB
ENOB: 7.5 BITS
SFDR: 82dBc

200 220 240

Figure 6. 64k Point Single-Tone FFT; 500 MSPS, 140.3 MHz

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBFS)

–70

–80

–90

–100

0 20 40 60 80 100 120 140 160 180

09615-107

FREQUENC Y (MHz)

500MSPS

450.3M Hz AT –1.0dBFS
SNR: 45.9dB
ENOB: 7.5 BITS
SFDR: 70dBc

200 220 240

09615-110

Figure 8. 64k Point Single-Tone FFT; 500 MSPS, 450.3 MHz

85

80

75

70

65

60

SNR/SFDR (d B)

55

50

45

40

09615-108

SFDR (dBc), T

SNR (dBFS), T
SNR (dBFS), T
SNR (dBFS), T

0 100 200 300 400 500

ANALOG INPU T FREQUECY (MHz )

A

A

= –40°C
= +25°C

A

= +85°C

A

=+85°C

SFDR (d Bc), T

SFDR (dBc) , TA= –40°C

Figure 9. Single-Tone SNR/SFDR vs. Input Frequency (f

=+25°C

A

) and Temperature;

IN

09615-111

500 MSPS

Rev. A | Page 10 of 24

AD9484

85

SFDR (dBc) , 30.3MHz

80

75

70

65

60

SNR/SFDR (dB)

55

SNR (dBFS), 30.3MHz

50

SNR (dBFS), 100. 3M

45

40

50 100 150 200 250 300 350 400 450 500 550

SAMPLE RATE (MSPS)

SFDR (d Bc), 100. 3MHz

Hz

Figure 10. SNR/SFDR vs. Sample Rate; 30.3 MHz, 100.3 MHz

09615-112

0.10

0.08

0.06

0.04

0.02

0

DNL (LSB)

–0.02

–0.04

–0.06

–0.08

–0.10

0 64 128 192 256

OUTPUT CODE

Figure 13. DNL, 500 MSPS

09615-115

100

90

SFDR (dBFS)

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0
–50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0

SNR (dB)

AMPLIT UDE (d B)

SFDR (dBc)

SNR (dBF S)

Figure 11. SNR/SFDR vs. Input Amplitude; 500 MSPS,140.3 MHz

0.10

0.08

0.06

0.04

0.02

0

INL (LSB)

–0.02

–0.04

–0.06

–0.08

–0.10

0 64 128 192 256

OUTPUT CODE

Figure 12. INL, 500 MSPS

4.0

0.29 LSB rms

3.5

3.0

2.5

2.0

1.5

NUMBER OF HITS (M)

1.0

0.5

0

N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3

09615-211

BINS

09615-116

Figure 14. Grounded Input Histogram, 500 MSPS

0

–10

–20

–30

–40

–50

–60

AMPLIT UDE (dBFS)

–70

–80

–90

–100

0

09615-114

20 40 60 80 100 120 140 160 180

FREQUENC Y (MHz)

500MSPS

119.5MHz AT –7.0dBFS

122.5M Hz AT –7.0dBFS
SFDR: 77dBc

200 220 240

09615-215

Figure 15. 64k Point, Two-Tone FFT; 500 MSPS,

119.2 MHz, 122.5 MHz

Rev. A | Page 11 of 24

AD9484

100

90

80

70

60

50

SFDR (dB)

40

30

20

10

0
–90 –80 –70 –60 –50 –40 –30 –20 –10 0

IMD3 (dBF S)

SFDR (dBFS)

SFDR (dBc)

AMPLIT UDE (dBFS)

Figure 16. Two-Tone SFDR vs. Input Amplitude; 500 MSPS,

119.5 MHz, 122.5 MHz

90

SFDR (dBc)

80

70

09615-118

80

75

70

SFDR (dBc)

65

60

55

50

SNR/SFDR (d B)

45

SNR (dBFS)

40

35

30

500 600 700 800 900 1000

FREQUENCY (MHz)

Figure 19. SNR/SFDR at 500 MSPS; AIN Sweep at −1.0 dBFS

09615-121

60

SNR/SFDR (d B)

50

40

30

1.5 1.6 1.7 1.8 1.9 2.0

SNR (dBFS)

VCM (V)

Figure 17. SNR/SFDR vs. Common-Mode Voltage; 500 MSPS,

AIN = 140.3 MHz

350

300

250

200

CURRENT (mA)

150

100

50

50

75

100

125

150

TOTAL POWER

175

200

225

250

275

SAMPLE RATE (MSPS)

300

I

AVDD

I

DRVDD

325

350

375

400

425

450

475

Figure 18. Current and Power vs. Sample Rate, AIN = 30.3 MHz

09615-119

800

700

600

500

400

POWER (mW)

300

200

100

0

500

525

550

09615-120

Rev. A | Page 12 of 24

AD9484

C

V

V

V

V

V

R

V

A

V

EQUIVALENT CIRCUITS

AVDD

CSB

DRVDD

350Ω

DRVDD

30kΩ

DRVDD

AVDD AVDD

LK+

0.9V

15kΩ 15kΩ

CLK–

Figure 20. Clock Inputs

AVDD

CML

AVDD

IN+

500Ω

IN+

AVDD

SPI

CONTROLLED

500Ω

Figure 21. Analog Input DC Equivalent Circuit (V

DRVDD

SCLK/DFS

350Ω

30kΩ

A

A

+

IN

–

IN

CML

DRVDD

BOOST

DC

= ~1.7 V)

09615-006

09615-009

Figure 24. Equivalent CSB Input Circuit

D

DD

V+

Dx–

V–

V–

Dx+

V+

9615-010

Figure 25. LVDS Outputs (Dx+, Dx−, OR+, OR−, DCO+, DCO−)

DD

20kΩ

(00)

(01)

09615-007

VREF

(10)

NOT USED

(11)

SPI CTRL V
00 = INTERNAL V
01 = IMPORT V
10 = EXPORT V
11 = NOT USED

REF

SELECT

REF

REF

REF

09615-011

Figure 26. Equivalent VREF Input/Output Circuit

09615-008

Figure 22. Equivalent SCLK/DFS, PDWN Input Circuit

IN+

1.3pF 1kΩ

IN–

09615-025

Figure 23. Analog Input AC EquivalentCircuit

DRVDD

SDIO

Figure 27. Equivalent SDIO Input Circuit

350Ω

DRVDD

30kΩ

CTRL

9615-012

Rev. A | Page 13 of 24

AD9484

THEORY OF OPERATION

The AD9484 architecture consists of a front-end sample-and­hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 8-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample, whereas the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.

The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended mode. The output
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
enter a high impedance state.

ANALOG INPUT AND VOLTAGE REFERENCE

The analog input to the AD9484 is a differential buffer. For best
dynamic performance, match the source impedances driving
VIN+ and VIN− such that common-mode settling errors are
symmetrical. The analog input is optimized to provide superior
wideband performance and requires that the analog inputs be
driven differentially. SNR and SINAD performance degrades
significantly if the analog input is driven with a single-ended
signal.

A wideband transformer, such as Mini-Circuits® ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip reference to a nominal 1.7 V.

An internal differential voltage reference creates positive and
negative reference voltages that define the 1.5 V p-p fixed span
of the ADC core. This internal voltage reference can be adjusted
by means of SPI control. See the AD9484 Configuration Using
the SPI section for more details.

Differential Input Configurations

Optimum performance is achieved while driving the AD9484
in a differential input configuration. For baseband applications,
the AD8138 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the
driver can be configured in a Sallen-Key filter topology to pro­vide band limiting of the input signal.

49.9Ω1V p-p

499Ω

0.1µF

Figure 28. Differential Input Configuration Using the AD8138

523Ω

499Ω

AD8138

499Ω

33Ω

33Ω

20pF

AVDD

VIN+

AD9484

VIN–

CML

09615-013

At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers may not be adequate to achieve
the true performance of the AD9484. This is especially true in
IF undersampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The signal characteristics must be considered
when selecting a transformer. Most RF transformers saturate at
frequencies below a few megahertz (MHz), and excessive signal
power can cause core saturation, which leads to distortion.

In any configuration, the value of the shunt capacitor, C (see
Figure 30), is dependent on the input frequency and may need
to be reduced or removed.

15Ω

50Ω1.5V p-p

Figure 29. Differential Transformer—Coupled Configuration

0.1µF

2pF

15Ω

VIN+

AD9484

VIN–

09615-014

As an alternative to using a transformer-coupled input at frequen­cies in the second Nyquist zone, the AD8352 differential driver
can be used (see Figure 30).

Rev. A | Page 14 of 24

AD9484

V

A

A

A

A

CC

NALOG INPUT

NALOG INPUT

0.1µF

C

DRDRG

0.1µF

0Ω

16

1

2

3

4

5

0Ω

8, 13

AD8352

14

0.1µF

0.1µF

11

10

0.1µF

0.1µF

200Ω

200Ω

R

C

R

0.1µF

VIN+

AD9484

VIN–

CML

09615-015

Figure 30. Differential Input Configuration Using the AD8352

D9510/AD9511/
AD9512/AD9513/
AD9514/AD9515

CLOCK

INPUT

CLOCK

INPUT

50Ω

1

50Ω RESISTORS ARE OPTIONAL.

0.1µF

CLK

0.1µF

50Ω

CLK

1

1

PECL DRIVER

0.1µF

CLK+

100Ω

0.1µF

240Ω240 Ω

ADC

AD9484

CLK–

09615-017

Figure 31. Differential PECL Sample Clock

D9510/AD9511/
AD9512/AD9513/
AD9514/AD9515

CLOCK

INPUT

CLOCK

INPUT

50Ω

0.1µF

CLK

LVDS DRIVER

0.1µF

50Ω

CLK

1

1

0.1µF

100Ω

0.1µF

CLK+

ADC

AD9484

CLK–

1

50Ω RESISTORS ARE OPTIONAL.

Figure 32. Differential LVDS Sample Clock

CLOCK INPUT CONSIDERATIONS

For optimum performance, drive the AD9484 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased at ~0.9 V
internally and require no additional bias. If the clock signal is
dc-coupled, then the common-mode voltage should remain
within a range of 0.9 V.

Figure 33 shows one preferred method for clocking the AD9484.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9484 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9484 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.

09615-018

MINI-CIRCUIT S

CLOCK

INPUT

50Ω

ADT1–1WT, 1: 1Z

100Ω

XFMR

0.1µF

0.1µF0.1µF

0.1µF

SCHOTTKY

DIODES:

HSM2812

CLK+

ADC

AD9484

CLK–

09615-016

Figure 33. Transformer-Coupled Differential Clock

If a low jitter clock is available, another option is to ac couple a
differential PECL signal to the sample clock input pins, as
shown in Figure 31. The AD9510/AD9511/AD9512/AD9513/

AD9514/AD9515 family of clock drivers offers excellent jitter

performance.

In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate,
and bypass the CLK− pin to ground with a 0.1 F capacitor in
parallel with a 39 k resistor (see Figure 34).

Rev. A | Page 15 of 24

AD9484

V

CC

0.1µF

1kΩ

1kΩ

AD951x
CMOS DRIVER

CLOCK

INPUT

1

50Ω RESISTOR IS OPTIONAL.

Figure 34. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

50Ω

1

OPTIONAL

100Ω

0.1µF

0.1µF
CLK+

ADC

AD9484

CLK–

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. A 5% tolerance is commonly
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9484 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9484. When the DCS is on, noise and distortion perfor­mance are nearly flat for a wide range of duty cycles.

The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 15 clock cycles
to allow the DLL to acquire and lock to the new rate.

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency

) due only to aperture jitter (tJ) can be calculated by

(f

A

SNR Degradation = 20 × log

(1/2 × π × fA × tJ)

10

In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 35).

Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9484. Separate the
power supplies for clock drivers from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
Low jitter, crystal-controlled oscillators make the best clock
sources. If the clock is generated from another type of source
(by gating, dividing, or other methods), it should be retimed by
the original clock at the last step.

Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs (visit www.analog.com).

130

RMS CLOCK JI TTER REQUIREMENT

120

110

100

90

80

SNR (dB)

09615-024

70

10 BITS

60

8 BITS

50

40

30

1 10 100 1000

Figure 35. Ideal SNR vs. Input Frequency and Jitter

ANALOG INP UT FREQUENCY (MHz)

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

16 BITS

14 BITS

12 BITS

9615-019

POWER DISSIPATION AND POWER-DOWN MODE

As shown in Figure 18, the power dissipated by the AD9484 is
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.

By asserting PDWN (Pin 29) high, the AD9484 is placed in
standby mode or full power-down mode, as determined by the
contents of Serial Port Register 08. Reasserting the PDWN pin
low returns the AD9484 to its normal operational mode.

An additional standby mode is supported by means of varying
the clock input. When the clock rate falls below 50 MHz, the
AD9484 assumes a standby state. In this case, the biasing network
and internal reference remain on, but digital circuitry is powered
down. Upon reactivating the clock, the AD9484 resumes normal
operation after allowing for the pipeline latency.

DIGITAL OUTPUTS

Digital Outputs and Timing

The AD9484 differential outputs conform to the ANSI-644
LVDS standard on default power-up. This can be changed to a
low power, reduced signal option similar to the IEEE 1596.3
standard using the SPI. This LVDS standard can further reduce
the overall power dissipation of the device, which reduces the
power by ~39 mW. See the Memory Map section for more infor­mation. The LVDS driver current is derived on chip and sets
the output current at each output equal to a nominal 3.5 mA.
A 100 Ω differential termination resistor placed at the LVDS
receiver inputs results in a nominal 350 mV swing at the receiver.

The AD9484 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments.
Single point-to-point net topologies are recommended with a
100 Ω termination resistor placed as close to the receiver as
possible. No far-end receiver termination or poor differential
trace routing may result in timing errors. It is recommended
that the trace length be no longer than 24 inches and that the

Rev. A | Page 16 of 24

AD9484

differential output traces be kept close together and at equal
lengths.

An example of the LVDS output using the ANSI standard (default)
data eye and a time interval error (TIE) jitter histogram with
trace lengths less than 24 inches on regular FR-4 material is
shown in Figure 36. Figure 37 shows an example of when the
trace lengths exceed 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position. It is up to
the user to determine if the waveforms meet the timing budget
of the design when the trace lengths exceed 24 inches.

14

500

400

300

200

100

0

–100

–200

–300

EYE DIAGRAM: VOLTAGE (mV)

–400

–500

–3 –2 –1 0 1 2 3

TIME (ns)

12

10

8

6

4

TIE JIT TER HIST OGRAM (Hi ts)

2

0

–40 –20 0 20 40

TIME (ps)

09615-020

Figure 36. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less

Than 24 Inches on Standard FR-4

600

400

200

0

–200

EYE DIAGRAM: VOLTAGE (mV)

–400

–600

–3–2–10123

TIME (ns)

12

10

8

6

4

TIE JITTER HISTOGRAM (Hits)

2

0

–100 0 100

TIME (ps)

09615-021

Figure 37. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths

Greater Than 24 Inches on Standard FR-4

The format of the output data is offset binary by default. An
example of the output coding format can be found in Tabl e 11.
If it is desired to change the output data format to twos comple­ment, see the AD9484 Configuration Using the SPI section.

An output clock signal is provided to assist in capturing data
from the AD9484. The DCO is used to clock the output data
and is equal to the sampling clock (CLK) rate. In single data
rate mode (SDR), data is clocked out of the AD9484 and must
be captured on the rising edge of the DCO. See the timing
diagram shown in Figure 2 for more information.

Output Data Rate and Pinout Configuration

The output data of the AD9484 can be configured to drive
12 pairs of LVDS outputs at the same rate as the input clock
signal (SDR mode).

Out-of-Range (OR)

An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR+ and OR− (OR±)
are digital outputs that are updated along with the data output
corresponding to the particular sampled input voltage. Thus,
OR± has the same pipeline latency as the digital data. OR± is
low when the analog input voltage is within the analog input
range and high when the analog input voltage exceeds the input
range, as shown in Figure 38. OR± remains high until the analog
input returns to within the input range and another conversion
is completed. By logically AND’ing OR± with the MSB and its
complement, overrange high or underrange low conditions can
be detected.

OR± DATA OUTPUTS

1
0
0

0
0
1

1111
1111
1111

0000
0000
0000

1111
1111
1110

0001
0000
0000

OR±

–FS + 1/2 L SB

–FS – 1/2 L SB

Figure 38. OR± Relation to Input Voltage and Output Data

+FS – 1 LSB

+FS–FS

+FS – 1/2 LSB

09615-022

TIMING

The AD9484 provides latched data outputs with a pipeline delay
of 15 clock cycles. Data outputs are available one propagation
delay (t

) after the rising edge of the clock signal.

PD

Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9484. These transi­ents can degrade the dynamic performance of the converter.
The AD9484 also provides a data clock output (DCO) intended
for capturing the data in an external register. The data outputs
are valid on the rising edge of DCO.

The lowest conversion rate of the AD9484 is 50 MSPS. At clock
rates below 1 MSPS, the AD9484 assumes the standby mode.

VREF

The AD9484 VREF pin (Pin 31) allows the user to monitor the
on-board voltage reference, or provide an external reference
(requires configuration through the SPI). The three optional
settings are internal V
export V

, and import V

REF

to this pin. VREF is internally compensated and additional
loading may impact performance.

(pin is connected to 20 kΩ to ground),

REF

. Do not attach a bypass capacitor

REF

Rev. A | Page 17 of 24

AD9484

AD9484 CONFIGURATION USING THE SPI

The AD9484 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space inside the ADC. This gives the user added flexibility to
customize device operation depending on the application.
Addresses are accessed (programmed or readback) serially in
1-byte words. Each byte can be further divided into fields,
which are documented in the Memory Map section.

There are three pins that define the serial port interface (SPI) to
this particular ADC. They are the SCLK/DFS, SDIO and CSB
pins. The SCLK/DFS (serial clock) is used to synchronize the
read and write data presented the ADC. The SDIO (serial data
input/output) is a dual-purpose pin that allows data to be sent
to and read from the internal ADC memory map registers. The
CSB is an active low control that enables or disables the read
and write cycles (see Tab l e 8 ).

Table 8. Serial Port Pins

Mnemonic Function

SCLK

SDIO

CSB

The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 39
and Tabl e 10 .

During an instruction phase, a 16-bit instruction is transmitted.
Data then follows the instruction phase and is determined by
the W0 and W1 bits, which is one or more bytes of data. All
data is composed of 8-bit words. The first bit of each individual
byte of serial data indicates whether this is a read or write

SCLK (serial clock) is the serial shift clock in.
SCLK is used to synchronize serial interface
reads and writes.

SDIO (serial data input/output) is a dual-purpose
pin. The typical role for this pin is an input and
output depending on the instruction being sent
and the relative position in the timing frame.

CSB (chip select) is an active low control that
gates the read and write cycles.

command. This allows the serial data input/output (SDIO) pin
to change direction from an input to an output.

Data can be sent in MSB or in LSB first mode. MSB first is
default on power-up and can be changed by changing the
configuration register. For more information about this feature
and others, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI at www.analog.com.

HARDWARE INTERFACE

The pins described in Ta b l e 8 comprise the physical interface
between the programming device of the user and the serial port
of the AD9484. The SCLK pin and the CSB pin function as
inputs when using the SPI interface. The SDIO pin is bidirec­tional, functioning as an input during the write phase and as an
output during readback.

This interface is flexible enough to be controlled by either
PROMs or PIC® microcontrollers as well. This provides the user
with an alternate method to program the ADC other than a SPI
controller.

If the user chooses not to use the SPI interface, some pins serve
a dual function and are associated with a specific function when
strapped externally to AVDD or ground during device power­on. The Configuration Without the SPI section describes the
strappable functions supported on the AD9484.

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers,
the SCLK/DFS pin can alternately serve as a standalone CMOS­compatible control pin. Connect the CSB pin to AVDD, which
disables the serial port interface.

Table 9. Mode Selection

External

Mnemonic

Voltage Configuration

AVDD Twos complement enabled SCLK/DFS
AGND Offset binary enabled

CSB

SCLK DON’T CARE

SDIO DON’ T CARE

t

t

DS

S

W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0

R/W

t

HIGH

t

DH

Figure 39. Serial Port Interface Timing Diagram

t

CLK

t

LOW

Rev. A | Page 18 of 24

t

H

DON’T CARE

DON’T CARE

09615-023

AD9484

Table 10. Serial Timing Definitions

Parameter Minimum (ns) Description

tDS 5 Setup time between the data and the rising edge of SCLK
tDH 2 Hold time between the data and the rising edge of SCLK
t

40 Period of the clock

CLK

tS 5 Setup time between CSB and SCLK
tH 2 Hold time between CSB and SCLK
t

16 Minimum period that SCLK should be in a logic high state

HIGH

t

16 Minimum period that SCLK should be in a logic low state

LOW

t

1

EN_SDIO

t

5

DIS_SDIO

Table 11. Output Data Format

Input (V) Condition (V) Offset Binary Output Mode, D7± to D0± Twos Complement Mode, D7± to D0± OR±

VIN+ − VIN− < −0.75 − 0.5 LSB 0000 0000 1000 0000 1
VIN+ − VIN− = −0.75 0000 0000 1000 0000 0
VIN+ − VIN− = 0 1000 0000 0000 0000 0
VIN+ − VIN− = 0.75 1111 1111 0111 1111 0
VIN+ − VIN− > 0.75 + 0.5 LSB 1111 1111 0111 1111 1

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling
edge (not shown in Figure 39)

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising
edge (not shown in Figure 39)

Rev. A | Page 19 of 24

AD9484

MEMORY MAP

READING THE MEMORY MAP TABLE

Each row in the memory map table (see Ta b l e 1 2 ) has eight
address locations. The memory map is roughly divided into
three sections: chip configuration register map (Address 0x00 to
Address 0x02), transfer register map (Address 0xFF), and ADC
functions register map (Address 0x08 to Address 0x2A).

The Addr. (Hex) column of the memory map indicates the register
address in hexadecimal, and the Default Value (Hex) column
shows the default hexadecimal value that is already written into
the register. The Bit 7 (MSB) column is the start of the default
hexadecimal value given. For example, Hexadecimal Address
0x2A, OVR_CONFIG, has a hexadecimal default value of 0x01.
This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0,
Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The
default value enables the OR± output. Overwriting this default so
that Bit 0 = 0 disables the OR± output. For more information on
this and other functions, consult the AN-877 Application Note,
Interfacing to High-Speed ADCs via SPI® user manual at

www.analog.com.

RESERVED LOCATIONS

Undefined memory locations should not be written to other
than with the default values suggested in this data sheet. Addresses
that have values marked as 0 should be considered reserved and
have a 0 written into their registers during power-up.

DEFAULT VALUES

Coming out of reset, critical registers are preloaded with default
values. These values are indicated in Tab le 1 2 . Other registers
do not have default values and retain the previous value when
exiting reset.

LOGIC LEVELS

An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”

Table 12. Memory Map Register

Default
Addr.
(Hex) Register Name

Chip Configuration Registers
00 CHIP_PORT_CONFIG 0 LSB

01 CHIP_ID 8-bit chip ID, Bits[7:0] = 0x6C Read

02 CHIP_GRADE 0 0 0 Speed grade:

Transfer Register
FF DEVICE_UPDATE 0 0 0 0 0 0 0 SW

ADC Functions Registers
08 Modes 0 0 PDWN:

Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

first

Soft
reset

0 = full
(default)
1 =
standby

1 1 Soft

reset

X1 XX1 X

00 = 500 MSPS

0 0 Internal power-down mode:

Note that external PDWN pin

LSB
first

000 = normal (power-up,

default)

001 = full power-down

010 = standby

011 = normal (power-up)

overrides this setting

Bit 0
(LSB)

0 0x18 The nibbles

1

Read

transfer

Value

(Hex)

only

only

0x00 Synchronously

0x00 Determines

Default Notes/
Comments

should be
mirrored by the
user so that LSB
or MSB first
mode registers
correctly,
regardless of
shift mode.

Default is a
unique chip ID,
different for
each device.
This is a read­only register.

Child ID used to
differentiate
graded devices.

transfers data
from the master
shift register to
the slave.

various generic
modes of chip
operation.

Rev. A | Page 20 of 24

AD9484

Default
Addr.
(Hex)

10 Offset 8-bit device offset adjustment [7:0]

0D TEST_IO (For user-defined

0F AIN_CONFIG 0 0 0 0 0 Analog

14 OUTPUT_MODE 0 0 0 Output

15 OUTPUT_ADJUST 0 0 0 0 LVDS

16 OUTPUT_PHASE Output

17 FLEX_OUTPUT_DELAY 0 0 0 0 Output clock delay:

Register Name

Bit 7
(MSB)

mode only, set

Bits[3:0] = 1000)

00 = Pattern 1 only

01 = toggle P1/P2

11 = toggle P1/P2/

clock
polarity
1 =
inverted
0 =
normal
(default)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

10 = toggle

P1/0000

0000

0 0 0 0 0 0 0 0x00

Reset
PN23
gen:
1 = on
0 = off
(default)

0111 111 = +127 codes

0000 0000 = 0 codes

1000 0000 = −128 codes

Reset
PN9
gen:
1 = on
0 = off
(default)

enable:
0 =
enable
(default)

1 =
disable

0100 = checker board output

0111 = one/zero word toggle

(Format determined by OUTPUT_MODE)

0 Output

course
adjust:
0 =

3.5 mA
(default)
1 =

2.0 mA

Output test mode:

0000 = off (default)

0001 = midscale short

0010 = +FS short
0011 = −FS short

0101 = PN23 sequence

0110 = PN9

1000 = user defined

1001 = unused
1010 = unused
1011 = unused
1100 = unused

input
disable:

1 = on
0 = off
(default)

invert:
1 = on
0 = off
(default)

0100 = reserved

0 0 0x00

Data format select:

00 = offset binary

(default)

01 = twos

complement

10 = Gray code

LVDS fine adjust:

001 = 3.50 mA
010 = 3.25 mA
011 = 3.00 mA
100 = 2.75 mA
101 = 2.50 mA
110 = 2.25 mA
111 = 2.00 mA

0000 = 0
0001 = −1/10
0010 = −2/10
0011 = −3/10

0101 = +5/10
0110 = +4/10
0111 = +3/10
1000 = +2/10
1001 = +1/10

Bit 0
(LSB)

Value
(Hex)

0x00 Device offset

0x00 When set, the

0x00 0

0x00 0

0x00 Shown as

Default Notes/
Comments

trim: codes are
relative to the
output
resolution.

test data is
placed on the
output pins in
place of normal
data.
Set pattern
values:
P1 = Reg 0x19,
Reg 0x1A

P2 = Reg 0x1B,
Reg 0x1C

fractional value
of sampling
clock period
that is
subtracted or
added to initial
t

, see

SKEW

Figure 2.

Rev. A | Page 21 of 24

AD9484

Default
Addr.
(Hex)

Register Name

18 FLEX_VREF VREF select

Bit 7
(MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

00 = internal V

(20 kΩ pull-down)

01 = import V

REF

(0.59 V to 0.8 V on

VREF pin)

10 = export V

REF

(from internal

reference)

11 = not used

0 Input voltage range setting:

REF

11100 = 1.60
11101 = 1.58
11110 = 1.55
11111 = 1.52
00000 = 1.50
00001 = 1.47
00010 = 1.44
00011 = 1.42
00100 = 1.39
00101 = 1.36

Bit 0
(LSB)

00110 = 1.34
00111 = 1.31
01000 = 1.28
01001 = 1.26
01010 = 1.23

01011= 1.20
01011= 1.18

19 USER_PATT1_LSB

1A USER_PATT1_MSB

1B USER_PATT2_LSB

1C USER_PATT2_MSB

B7 B6 B5 B4 B3 B2 B1 B0

B7 B6 B5 B4 B3 B2 B1 B0

B7 B6 B5 B4 B3 B2 B1 B0

B7 B6 B5 B4 B3 B2 B1 B0

2A OVR_CONFIG 0 0 0 0 0 0 0 OR±

enable:
1 = on
(default)
0 = off

2C Input coupling 0 0 0 0 0 DC

0 0 0x00 Default is
coupling
enable

1

X = don’t care.

Value
(Hex)

Default Notes/
Comments

0x00

0x00 User-defined

pattern, 1 LSB.

0x00 User-defined

pattern, 1 MSB.

0x00 User-defined

pattern, 2 LSBs.

0x00 User-defined

pattern, 2 MSBs.

0x01

ac coupling.

Rev. A | Page 22 of 24

AD9484

OUTLINE DIMENSIONS

EXPOSED

PAD

0.30

0.23

0.18

N

I

1

P

R

O

D

C

I

A

T

N

56

I

1

5.25

5.10 SQ

4.95

PIN 1

INDICATOR

8.10

8.00 SQ

7.90

7.85

7.75 SQ

7.65

0.60

MAX

0.50

BSC

0.60 MAX

43

42

14

15

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

0.25 MIN

081809-B

1.00

0.85

0.80

SEATING

PLANE

12° MAX

TOP VI EW

29

0.08

28

BOTTOM VIEW

6.50 REF

0.50

0.40

0.80 MAX

0.65 TYP

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2

0.30

0.05 MAX

0.02 NOM
COPLANARITY

Figure 40. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

8 mm × 8 mm Body, Very Thin Quad

(CP-56-5)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD9484BCPZ-500 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-5
AD9484BCPZRL7-500 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-5
AD9484-500EBZ Evaluation Board

1

Z = RoHS Compliant Part.

Rev. A | Page 23 of 24

AD9484

NOTES

©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09615-0-6/11(A)

Rev. A | Page 24 of 24