Analog Devices AD9480 Service Manual

8-Bit, 250 MSPS

C

FEATURES

DNL = ± 0.25 LSB
INL = ± 0.26 LSB
Single 3.3 V supply operation (3.0 V to 3.6 V)
Power dissipation of 590 mW at 250 MSPS
1 V p-p analog input range
Internal 1.0 V reference
Single-ended or differential analog inputs
LVDS outputs (ANSI 644 levels)
Power-down mode
Clock duty-cycle stabilizer

APPLICATIONS

Digital oscilloscopes
Instrumentation and measurement
Communications

Point-to-point radios
Predistortion loops

VIN+
VIN–

LK+

CLK–

3.3 V A/D Converter

FUNCTIONAL BLOCK DIAGRAM

VREF SENSE

REFERENCE

T&H

CLOCK

MGMT

AGND DrGND DRVDD AVDD

AD9480

8-BIT

ADC

PIPELINE

CORE

Figure 1.

8

LOGIC

LVDSBIASPDWN S1

AD9480

16

LVDS

D7–D0
(LVDS)

DCO+
DCO-

(LVDS)

04619-001

GENERAL DESCRIPTION

The AD9480 is an 8-bit, monolithic analog-to-digital converter
(ADC) optimized for high speed and low power consumption.
Small in size and easy to use, the product operates at a
250 MSPS conversion rate, with excellent linearity and dynamic
performance over its full operating range.

To minimize system cost and power dissipation, the AD9480
includes an internal reference and track-and-hold circuit. The
user only provides a 3.3 V power supply and a differential
encode clock. No external reference or driver components are
required for many applications.

The digital outputs are LVDS (ANSI 644) compatible with an
option of twos complement or binary output format. The
output data bits are provided in parallel fashion along with an
LVDS output clock, which simplifies data capture.

Fabricated on an advanced BiCMOS process, the AD9480 is
available in a 44-lead surface-mount package (TQFP) specified
over the industrial temperature range −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Superior linearity. A DNL of ±0.25 makes the AD9480

suitable for instrumentation and measurement
applications.

2. Power-down mode. A power-down function may be

exercised to bring total consumption down to 15 mW.

3. LVDS outputs (ANSI-644). LVDS outputs simplify timing

and improve noise performance

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] ©2005 Analog Devices, Inc. All rights reserved.

www.analog.com

AD9480

TABLE OF CONTENTS

DC Specifications ............................................................................. 3

Interleaving Two AD9480s........................................................ 18

Digital Specifications........................................................................ 4

AC Specifications.............................................................................. 5

Switching Specifications .................................................................. 6

Timing Diagram ........................................................................... 6

Absolute Maximum Ratings............................................................ 7

Explanation of Test Levels........................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Te r mi n ol o g y ...................................................................................... 9

Typical Performance Characteristics ........................................... 11

Equivalent Circuits......................................................................... 15

Application Notes ........................................................................... 16

Clocking the AD9480 ................................................................ 16

Analog Inputs.............................................................................. 16

Volt a ge R e fer e nce ....................................................................... 17

Data Clock Out........................................................................... 18

Power-Down ............................................................................... 18

AD9480 Evaluation Board ............................................................ 19

Power Connector ........................................................................ 19

Analog Inputs ............................................................................. 19

Gain.............................................................................................. 19

Optional Operational Amplifier .............................................. 19

Clock ............................................................................................ 19

Optional Clock Buffer ............................................................... 19

Optional XTAL ........................................................................... 19

Volt a ge R e fer e nce ....................................................................... 20

Data Outputs............................................................................... 20

Evaluation Board Bill of Materials (BOM) ................................. 21

PCB Schematics .............................................................................. 22

PCB Layers ...................................................................................... 24

Digital Outputs ........................................................................... 18

Output Coding............................................................................ 18

REVISION HISTORY

4/05—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Features.......................................................................... 1

Changes to Table 3............................................................................ 5

Changes to Table 7............................................................................ 8

Changes to Analog Inputs .............................................................16

Changes to Figure 30...................................................................... 16

Added Power Down Section ......................................................... 18

Changes to Table 12........................................................................ 21

7/04—Revision 0: Initial Version

Outline Dimensions ....................................................................... 26

Ordering Guide .......................................................................... 26

Rev. A | Page 2 of 28

AD9480

DC SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, T
clock inputs, unless otherwise noted.

Table 1.

AD9480-250
Parameter Temp Test Level Min Typ Max Unit

RESOLUTION 8 Bits
ACCURACY

No Missing Codes Full VI Guaranteed
Offset Error 25°C I −40 +40 mV
Gain Error

1

Differential Nonlinearity (DNL)

AD9480BSUZ-250 Full VI −0.5 ±0.28 +0.5 LSB
AD9480ASUZ-250 Full VI −0.85 ±0.35 +0.85 LSB

Integral Nonlinearity (INL) Full VI −0.9 ±0.26 +0.9 LSB

TEMPERATURE DRIFT

Offset Error Full V 30 µV/°C
Gain Error Full V 0.03 %FS/°C
Reference Full V ±0.025 mV/°C

REFERENCE

Internal Reference Voltage Full VI 0.97 1.0 1.03 V
Output Current
I

Input Current

VREF

I

Input Current2 25°C I 10 µA

SENSE

2

3

ANALOG INPUTS (VIN+, VIN−)

Differential Input Voltage Range (FS = 1)
Common-Mode Voltage Full VI 1.7 1.9 2.1 V
Input Resistance 25°C I 8.6 10 10.7 kΩ
Full VI 8.4 10 11.2 kΩ
Input Capacitance 25°C V 4 pF
Analog Bandwidth, Full Power 25°C V 750 MHz

POWER SUPPLY

AVDD Full IV 3.0 3.3 3.6 V
DRVDD Full IV 3.0 3.3 3.6 V
Power Dissipation

5

Power-Down Dissipation 25°C V 15 mW

5

I

AVDD

5

I

DRVDD

Power Supply Rejection Ratio (PSRR) 25°C V −4.2 mV/V

1

Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1 V external reference and a 1 V p-p differential analog input).

2

Internal reference mode; SENSE = AGND.

3

External reference mode; VREF driven by external 1.0 V reference; SENSE = AVDD.

4

In FS = 1 V, both analog inputs are 500 mV p-p and out of phase with each other.

5

Power dissipation and current measured with rated encode and a dc analog input (outputs static). See for active operation. Figure 13

= −40°C, T

MIN

= +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and

MAX

25°C I −6.0 +6.0 % FS

25°C IV 1.5 mA
25°C I 100 µA

4

Full V 1 V p-p

25°C V 590 mW

Full VI 145 156 mA
Full VI 34 38 mA

Rev. A | Page 3 of 28

AD9480

DIGITAL SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, T
clock inputs, unless otherwise noted.

Table 2.

AD9480-250
Parameter Temp Test Level Min Typ Max Unit

CLOCK INPUTS (CLK+, CLK−)

Differential Input Full IV 200 mV p-p
Common-Mode Voltage

1

Input Resistance Full VI 4.2 5.5 6.0 kΩ
Input Capacitance 25°C V 4 pF

LOGIC INPUTS (PDWN, S1)

2

PDWN Logic 1 Voltage Full IV 2.0 V
PDWN Logic 0 Voltage Full IV 0.8 V
PDWN Logic 1 Input Current Full VI ±160 µA
PDWN Logic 0 input Current Full VI 10 µA
PDWN, S1 Input Resistance 25°C V 30 kΩ
PDWN, S1 Input Capacitance 25°C V 4 pF

DIGITAL OUTPUTS

Differential Output Voltage (VOD)
Output Offset Voltage (VOS) Full VI 1.125 1.375 V
Output Coding Full IV Twos complement or binary

1

The common mode for CLOCK inputs can be externally set, such that 0.9 V < CLK ± < 2.6 V.

2

S1 is a multilevel logic input, see Ta . ble 8

3

LVDSBIAS resistor = 3.74 kΩ.

= −40°C, T

MIN

3

= +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and

MAX

Full VI 1.4 1.5 1.68 V

Full VI 247 454 mV

Rev. A | Page 4 of 28

AD9480

AC SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, T
clock inputs, unless otherwise noted.

Table 3.

AD9480-250
Parameter Temp Test Level Min Typ Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 19.7 MHz 25°C V 47 dB
fIN = 70.1 MHz 25°C I 45 47 dB
fIN = 170 MHz 25°C I 45 46 dB

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 19.7 MHz 25°C V 46.5 dB
fIN = 70.1 MHz 25°C I 44.8 46.5 dB
fIN = 170 MHz 25°C I 44.8 46.5 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 19.7 MHz 25°C V 7.6 Bits
fIN = 70.1 MHz 25°C I 7.3 7.6 Bits
fIN = 170 MHz 25°C I 7.3 7.6 Bits

WORST SECOND OR THIRD HARMONIC DISTORTION

fIN = 19.7 MHz 25°C V −65 dBc
fIN = 70.1 MHz 25°C I −65 −60 dBc
fIN = 170 MHz 25°C I −65 −60 dBc

WORST OTHER

fIN = 19.7 MHz 25°C V −70 dBc
fIN = 70.1 MHz 25°C I −70 −63 dBc
fIN = 170 MHz 25°C I −70 −63 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 19.7 MHz 25°C V −65 dBc
fIN = 70.1 MHz 25°C I −65 −60 dBc
fIN = 170 MHz 25°C I −65 −60 dBc

TWO-TONE INTERMODULATION DISTORTION (IMD)

f

= 69.3 MHz, f

IN1

1

Nyquist bin energy ignored.

= 70.3 MHz 25°C V −68 dBc

IN2

= –40°C, T

MIN

1

= +85°C, AIN = –1 dBFS, full scale = 1.0 V, internal reference, differential analog and

MAX

Rev. A | Page 5 of 28

AD9480

SWITCHING SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, differential clock input, DCS enabled, unless otherwise noted.

Table 4.

AD9480-250
Parameter Temp Test Level Min Typ Max Unit

CLOCK

Maximum Conversion Rate Full VI 250 MSPS
Minimum Conversion Rate Full VI 20 MSPS
Clock Pulse Width High (tEH) Full IV 1.2 2 ns
Clock Pulse Width Low (tEL) Full IV 1.2 2 ns

OUTPUT PARAMETERS

Valid Time (tV)
Propagation Delay (tPD) Full VI 2.8 3.8 ns
Rise Time (tR) 20% to 80% Full V 0.5 ns
Fall Time (tF) 20% to 80% Full V 0.5 ns
DCO Propagation Delay (t
Data-to-DCO Skew (tPD − t
Pipeline Latency 25°C VI 8 Cycles

APERTURE

Aperture Delay (tA) 25°C V 1.5 ns
Aperture Uncertainty (Jitter) 25°C V 0.25 ps rms

1

Valid time is approximately equal to minimum tPD. C

1

) Full VI 1.9 2.7 3.7 ns

CPD

) Full IV 0 0.1 0.6 ns

CPD

equals 5 pF maximum.

LOAD

Full VI 1.9 ns

TIMING DIAGRAM

AIN

CLK+

CLK–

DATA

OUT

DCO+
DCO–

N–1

t

A

N

N+9

N+1

8 CYCLES

t

t

EH

EL

t

CPD

1/f

S

t

PD

N–8

t

V

N–7 N N+1 N+2

N+8

N+10

N+11

04619-002

Figure 2. Timing Diagram

Rev. A | Page 6 of 28

AD9480

ABSOLUTE MAXIMUM RATINGS

Thermal impedance (θJA) = 46.4°C/W (4-layer PCB).

Table 5.

Parameter Min Rating Max Rating

ELECTRICAL

AVDD

(With Respect to AGND)

DRVDD

(With Respect to DRGND)

AGND

(With Respect to DRGND)

Digital I/O

(With Respect to DRGND)

Analog Inputs

(With Respect to AGND)

ENVIRONMENTAL

Operating Temperature −40°C 85°C
Junction Temperature 150°C
Case Temperature 150°C
Storage Temperature 150°C

−0.5 V +4.0 V

−0.5 V +4.0 V

−0.5 V +0.5 V

−0.5 V DRVDD + 0.5 V

−0.5 V AVDD + 0.5 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

EXPLANATION OF TEST LEVELS

Table 6.

Level Descriptions

I 100% production tested.
II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 7 of 28

AD9480

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

CLK+

2

CLK–

3

AVDD

4

AGND

D1_C

D1_T

D2_C

5
6
7
8

9
10
11

DRVDD

DRGND
D0_C (LSB)
D0_T (LSB)

NC = NO CONNECT

AGND43NC42LVDSBIAS

44

12

D2_T

AVDD40AGND39VIN+38VIN–37AGND36AVDD35AGND34VREF

41

PIN 1

AD9480

TOP VIEW

(Not to Scale)

13

14

15

16

17

18

D3_T

D3_C

DCO–

DRGND

DCO+

19

D4_C

DRVDD

33

SENSE

32

AGND

31

AVDD

30

AGND

29

PDWN

28

S1

27

DRGND

26

D7_T (MSB)

25

D7_C (MSB)

24

D6_T

23

D6_C

20

21

22

D4_T

D5_T

D5_C

04619-003

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin
No. Mnemonic Description

Pin
No. Mnemonic Description

1 CLK+ Input Clock—True 23 D6_C Data Output Bit 6—Complement
2 CLK− Input Clock—Complement 24 D6_T Data Output Bit 6—True
3 AVDD 3.3 V Analog Supply 25 D7_C Data Output Bit 7—Complement (MSB)
4 AGND Analog Ground 26 D7_T Data Output Bit 7—True (MSB)
5 DRVDD 3.3 V Digital Output Supply 27 DRGND Digital Ground
6 DRGND Digital Ground 28 S1

Data Format Select and Duty-Cycle Stabilizer Selection

(See Table 8)
7 D0_C Data Output Bit 0—Complement (LSB) 29 PDWN Power-Down Selection (AVDD = Power Down)
8 D0_T Data Output Bit 0—True (LSB) 30 AGND Analog Ground
9 D1_C Data Output Bit 1—Complement 31 AVDD 3.3 V Analog Supply
10 D1_T Data Output Bit 1—True 32 AGND Analog Ground
11 D2_C Data Output Bit 2—Complement 33 SENSE Reference Mode Selection (See Table 9)
12 D2_T Data Output Bit 2—True 34 VREF Voltage Reference Input/Output
13 D3_C Data Output Bit 3—Complement 35 AGND Analog Ground
14 D3_T Data Output Bit 3—True 36 AVDD 3.3 V Analog Supply
15 DRGND Digital Ground 37 AGND Analog Ground
16 DCO− Data Clock Output—Complement 38 VIN− Analog Input—Complement
17 DCO+ Data Clock Output—True 39 VIN+ Analog Input—True
18 DRVDD 3.3 V Digital Output Supply 40 AGND Analog Ground
19 D4_C Data Output Bit 4—Complement 41 AVDD 3.3 V Analog Supply
20 D4_T Data Output Bit 4—True 42 LVDSBIAS LVDS Output Current Adjust
21 D5_C Data Output Bit 5—Complement 43 NC

1

No Connect (Leave Floating)
22 D5_T Data Output Bit 5—True 44 AGND Analog Ground

1

Pin 43 will self-bias to 1.5 V. It can be left floating (as recommended) or tied to AVDD or ground with no ill effects.

Rev. A | Page 8 of 28

AD9480

TERMINOLOGY

Analog Bandwidth

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

Aperture Delay

The delay between the 50% point of the rising edge of the
encode command and the instant the analog input is sampled.

Full-Scale Input Power

Expressed in dBm. Computed by

2

⎛
⎜

Power

FULLSCALE

=

10

log

⎜
⎜
⎜
⎜

⎝

FULLSCALE

Z

INPUT

0010

.

⎞

rmsV

⎟
⎟
⎟
⎟

⎟
⎠

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Clock Pulse Width/Duty Cycle

Pulse width high is the minimum amount of time that the
clock pulse should be left in a Logic 1 state to achieve rated
performance; pulse width low is the minimum time that the
clock pulse should be left in a low state. See the timing
implications of changing t

in the Clocking the AD9480

EH

section. At a given clock rate, these specifications define an
acceptable clock duty cycle.

Crosstalk

Coupling onto one channel being driven by a low level
(−40 dBFS) signal when the adjacent interfering channel
is driven by a full-scale signal.

Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance

The real and complex impedances measured at each analog
input port. The resistance is measured statically, and the
capacitance and differential input impedances are measured
with a network analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the inputs phase 180° and taking the peak measurement again.
The difference is then computed between both peak
measurements.

Differential Nonlinearity

The deviation of any code width from an ideal 1 LSB step.

Effective Number of Bits

The effective number of bits (ENOB) is calculated by the
measured SINAD based on (assuming full-scale input)

ENOB

SINAD

=

MEASURED

6.02

dB1.76−

Gain Error

The difference between the measured and ideal full-scale input
voltage range of the ADC.

Harmonic Distortion, Second

The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.

Harmonic Distortion, Third

The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.

Integral Nonlinearity

The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a differential crossing of CLK+ and
CLK− and the time when all output data bits are within
valid logic levels.

Noise (For Any Range Within the ADC)

This value includes both thermal and quantization noise.

SignalSNRFS

noise

ZV .

⎛

××=

10001

⎜

⎜
⎝

10

−−

⎞

dBFSdBcdBm

⎟

⎟
⎠

where:

Z is the input impedance.
FS is the full scale of the device for the frequency in question.
SNR is the value for the particular input level.
Signal is the signal level within the ADC reported in dB below

full scale.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in
power supply voltage.

Rev. A | Page 9 of 28

AD9480

Signal-to-Noise and Distortion (SINAD)

The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics, but excluding dc.

Signal-to-Noise Ratio (Without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious
component may or may not be a harmonic. It also may be
reported in dBc (that is, degrades as signal level is lowered) or
dBFS (that is, always related back to converter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value
of the worst third-order intermodulation product in dBc.

Two -Tone SFDR

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. It also may be reported in
dBc (that is, degrades as signal level is lowered) or in dBFS (that
is, always relates back to converter full scale).

Worst Other Spur

The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic), reported in dBc.

Transi ent Res p onse T i m e

The time it takes for the ADC to reacquire the analog input
after a transient from 10% above negative full scale to 10%
below positive full scale.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input
after a transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.

Rev. A | Page 10 of 28

AD9480

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD, DRVDD = 3.3 V, T = 25°C, AIN differential drive, FS = 1, unless otherwise noted.

–10

–20

0

SNR = 46.2dB
H2 = 72.8dBc
H3 = 73.2dBc
SFDR = 69.8dBc

0

–10

–20

SNR = 45.9dB
H2 = 71.9dBc
H3 = 67dBc
SFDR = 67dBc

–30

–40

dB

–50

–60

–70

–80

–90

0604020 80 100 120

Figure 4. FFT: f

0

SNR = 46.1dB
H2 = 71.4dBc

–10

H3 = 74.3dBc
SFDR = 68.7dBc

–20

–30

–40

dB

–50

–60

–70

–80

–90

0604020 80 100 120

Figure 5. FFT: f

0

SNR = 45.9dB
H2 = 67dBc

–10

H3 = 73.3dBc
SFDR = 67dBc

–20

–30

–40

dB

–50

–60

–70

–80

–90

0604020 80 100 120

Figure 6. FFT: f

S

= 250 MSPS, AIN = 10.3 MHz @ −1 dBFS

S

= 250 MSPS, AIN = 70 MHz @ –1 dBFS

S

= 250 MSPS, AIN = 70 MHz @ –1 dBFS, Single-Ended Input

MHz

MHz

MHz

04619-020

04619-021

04619-022

–30

–40

dB

–50

–60

–70

–80

–90

0604020 80 100 120

Figure 7. FFT: f

90

85

80
75

70

65

dB

60

55

50
45
40

0 50 200 250100 150 300 350 400

= 250 MSPS, AIN = 170 MHz @ −1 dBFS

S

H3

SFDR

AIN (MHz)

Figure 8. Analog Inp ut Frequency Sweep, A

80

75

70

dB

65

60

55

50

45

40

SFDR

0 50 200 250100 150 300 350 400

H3

AIN (MHz)

Figure 9. Analog Inp ut Frequency Sweep, A

FS = 0.75 V, f

= 250 MSPS

S

MHz

H2

SNR

SINAD

= −1 dBFS, FS = 1 V, fS = 250 MSPS

IN

H2

SNR

SINAD

= −1 dBFS,

IN

04619-023

04619-024

04619-025

Rev. A | Page 11 of 28

AD9480

75

180

70

65

60

dB

55

50

45

SINAD

40

0 50 150 200100 250 300

SFDR

SNR

SAMPLE CLOCK (MHz)

Figure 10. SNR, SINAD, SFDR vs. Sample Clock Frequency, A

80

70

SFDRdBFS

60

50

40

dB

30

20

SFDRdBc

10

0

–70 –60 –40–50 –30 –20 –10 0

Figure 11. SFDR vs. A

0

F1, F2 = –7dBFS
2F2-F1 = –71.1dBc

–10

2F1-F2 = –68dBc

–20

–30

65dB
REF LINE

ANALOG INPUT DRIVE LEVEL (dBFS)

Input Level; AIN = 70 MHz @ 250 MSPS

IN

= 70 MHz @ −1 dBFS

IN

160

140

120

100

80

CURRENT IN mA

60

40

20

04619-026

0

0 50 100 200 250150 300

Figure 13. I

dB

04619-027

AVDD

50

49
48

47

46

45
44

43

42

41
40

20 30 40 50 60 70 80

I

AVDD

ENCODE (MSPS)

and I

vs. Clock Rate, C

DRVDD

DCS ON

DCS OFF

CLOCK POSITIVE DUTY CYCLE (%)

I

DRVDD

= 5 pF AIN = 70 MHz @ –1 dBFS

LOAD

04619-029

046190-030

Figure 14. SNR, SINAD vs. Clock Pulse Width High,

= 70 MHz @ –1 dBFS, 250 MSPS, DCS On/Off

A

IN

50.0
SNR

47.5

80

75

SINAD

–40

dB

–50

–60

–70

–80

–90

0604020 80 100 120

MHz

Figure 12. Two-Tone Intermodulation Distortion

(69.3 MHz and 70.3 MHz; f

= 250 MSPS)

S

04619-028

Rev. A | Page 12 of 28

45.0

SNR, SINAD dB

42.5

40.0

0.5 1.10.90.7 1.51.3 1.7 1.9
EXTERNAL VREF VOLTAGE (V)

SFDR

Figure 15. SNR, SINAD, and SFDR vs. VREF in External Reference Mode,

A

= 70 MHz @ –1 dBFS, 250 MSPS

IN

70

SFDR dB

65

04619-031

50

AD9480

GAIN ERROR (%)

–1

3

2

1

FS = 1V INT REF

0

FS = 1V EXT REF

dB

70

65

60

55

SFDR

–2

–3

–40 0–20 20 40 60 80

TEMPERATURE (°C)

Figure 16. Full-Scale Gain Error vs. Temperature,

= 70.3 MHz @ −0.5 dBFS, 250 MSPS, FS = 1

A

IN

75

70

65

60

dB

55

50

SINAD 1V INT REF

45

40

–40 –20 2004060

Figure 17. SINAD, SFDR vs. Temperature, A

0.10

TEMPERATURE (°C)

IN

SFDR 1V INT REF

= 70 MHz @ −1 dBFS, 250 MSPS

04619-032

04619-033

80

50

SINAD

45

3.0 3.1 3.2 3.3 3.4 3.5 3.6

SNR

AVDD (V)

Figure 19. SNR, SINAD, and SFDR vs. Supply Voltage,

= 70.3 MHz @ −1 dBFS, 250 MSPS

A

IN

0.5

0.4

0.3

0.2

0.1

0

LSB

–0.1

–0.2
–0.3

–0.4
–0.5

0 10050 150 200 250

Figure 20. Typical DNL Plot, A

0.50

CODE

= 10.3 MHz @ –0.5 dBFS, 250 MSPS

IN

04619-035

04619-036

0.05

0

–0.05

CHANGE IN VREF (%)

–0.10

–0.15

2.7 2.8 2.9 3.1 3.53.43.33.23.0 3.6
AVDD (V)

Figure 18. VREF Sensitivity to AVDD

04619-034

Rev. A | Page 13 of 28

0.25

0

LSB

–0.25

–0.50

0 10050 150 200 250

Figure 21. Typical INL Plot, A

CODE

= 10.3 MHz @ −0.5 dBFS, 250 MSPS

IN

04619-037

AD9480

0.30

0.25

0.20

0.15

0.10

0.05

DELAY SENSITIVITY (nS)

0

–0.05

–0.10

–40 –20 2004060

Figure 22. Propagation Delay Adder vs. Temperature

TEMPERATURE (°C)

04619-038

80

900

800

700

600

500

400

VDIF (mV)

300

200

100

0

02468101214

V

OS

V

OD

RSET (kΩ)

Figure 23. LVDS Output Swing, Common-Mode Voltage vs. RSET,

Placed at LVDSBIAS

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

(V)

OS

V

04619-039

Rev. A | Page 14 of 28

AD9480

C

S

EQUIVALENT CIRCUITS

VIN+

LK+

16.7kΩ 16.7kΩ

150Ω

1.2pF

25kΩ

Figure 24. Analog Inputs

AVDD

12kΩ

150Ω 150Ω

10kΩ

Figure 25. Clock Inputs

25kΩ

12kΩ

10kΩ

150Ω

1.2pF

AVDD

VIN–

CLK–

04619-004

04619-005

PDWN

1.2V

LVDSBIAS

30kΩ

Figure 27. Power-Down Input

DRVDD DRVDD

3.7kΩ

Figure 28. LVDSBIAS Input

ILVDS

AVDD

K

OUT

04619-007

04619-008

VDD

30kΩ

V+

1

04619-006

DX–

V–

Figure 26. S1 Input

DRVDD

V–

DX+

V+

04619-009

Figure 29. LVDS Data, DCO Outputs

Rev. A | Page 15 of 28

AD9480

APPLICATION NOTES

The AD9480 uses a 1.5-bit per stage architecture. The analog
inputs drive an integrated high bandwidth track-and-hold
circuit that samples the signal prior to quantization by the 8-bit
core. For ease of use, the part includes an on-board reference
and input logic that accepts TTL, CMOS, or LVPECL levels.
The digital output logic levels are LVDS (ANSI 644 compatible).

CLOCKING THE AD9480

Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the A/D output.
Considerable care has been taken in the design of the CLOCK
input of the AD9480, and the user is advised to give
commensurate thought to the clock source.

The AD9480 has an internal clock duty-cycle stabilization
circuit that locks to the rising edge of CLOCK and optimizes
timing internally for sample rates between 100 MSPS and
250 MSPS. This allows for a wide range of input duty cycles at
the input without degrading performance. Jitter on the rising
edge of the input is still of paramount concern and is not
reduced by the internal stabilization circuit. The duty-cycle
control loop does not function for clock rates less than 70 MHz
nominally. The loop is associated with a time constant that
needs to be considered in applications where the clock rate can
change dynamically, requiring a wait time of 5 µs after a
dynamic clock frequency increase before valid data is available.
The clock duty-cycle stabilizer can be disabled at Pin 28 (S1).

The clock inputs are internally biased to 1.5 V (nominal) and
support either differential or single-ended signals. For best
dynamic performance, a differential signal is recommended. An
MC100LVEL16 performs well in the circuit to drive the clock
inputs (ac coupling is optional). If the clock buffer is greater
than 2 inches from the ADC, a standard LVPECL termination
may be required instead of the simple pull-down termination,
as shown in Figure 30.

AD9480

CLK+

CLK–

PECL
GATE

0.1µF

0.1µF

510Ω510Ω

ANALOG INPUTS

The analog input to the AD9480 is a differential buffer. For best
dynamic performance, impedances at VIN+ and VIN− should
match. Optimal performance is obtained when the analog
inputs are driven differentially. SNR and SINAD performance
can degrade if the analog input is driven with a single-ended
signal; however, performance can be adequate for some
applications (see Figure 6). The analog inputs self-bias to
approximately 1.9 V; this common-mode voltage can be
externally overdriven by approximately ±300 mV if required.

A wideband transformer, such as the Mini-Circuits® ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Note that the
filter and center-tap capacitor on the secondary side is optional
and dependent on application requirements. An RC filter at
the secondary side helps reduce any wideband noise aliased
by the ADC.

(R, C OPTIONAL)

33Ω

49.9Ω

0.1µF

Figure 31. Driving the ADC with an RF Transformer

10pF

33Ω

For dc-coupled applications, the AD8138/AD8139 or AD8351
can serve as a convenient ADC driver, depending on
requirements. Figure 32 shows an example with the AD8138.
The AD9480 PCB has an optional AD8351 on board, as shown
in Figure 41 and Figure 42. The AD8351 typically yields better
performance for frequencies greater than 30 MHz to 40 MHz.

0.1µF

49.9Ω

499Ω

1.3kΩ

2kΩ

523Ω

Figure 32. Driving the ADC with the AD8138

499Ω

AD8138

499Ω

33Ω

33Ω

20pF

AVDD

VIN+

AD9480

VIN–

AGND

AVDD

VIN+

AD9480

VIN–

AGND

04619-011

04619-012

04619-010

Figure 30. Clocking the AD9480

Table 8. S1 Voltage Levels

S1 Voltage Data Format Duty-Cycle Stabilizer

0.9 × AVDD −> AVDD Offset binary Disabled
2/3 AVDD ± (0.1 × AVDD) Offset binary Enabled
1/3 AVDD ± (0.1 × AVDD) Twos complement Enabled
AGND −> (0.1 × AVDD) Twos complement Disabled

Rev. A | Page 16 of 28

AD9480

The AD9480 can be easily configured for different full-scale
ranges. See the Voltage Reference section for more information.
Optimal performance is achieved with a 1 V p-p analog input.

SENSE = GND

VIN+

2.0V500mV 2.0V

VIN–

DIGITALOUT = ALL 1s DIGITALOUT = ALL 0s

Figure 33. Analog Input Full Scale

VOLTAGE REFERENCE

A stable and accurate 1.0 V reference is built into the AD9480.
Users can choose this internal reference or provide an external
reference for greater accuracy and flexibility. Figure 35 shows
the typical reference variation with temperature. Table 9
summarizes the available reference configurations.

VIN+
VIN–

ADC

CORE

VREF

+

0.1µF10µF
7kΩ

SELECT

LOGIC

04619-013

Fixed Reference

The internal reference can be configured for a differential span
of 1 V p-p (see Figure 37). It is recommended to place a 0.1 µF
capacitor as close as possible to the VREF pin; a 10 µF capacitor
is also required (see the PCB layout for guidance). If the
internal reference of the AD9480 is used to drive multiple
converters to improve gain matching, the loading of the
reference by the other converters must be considered. Figure 37
depicts how the internal reference voltage is affected by loading.

1.0085

1.0080

1.0075

1.0070

1.0065

1.0060

VREF (V)

1.0055

1.0050

1.0045

1.0040

1.0035
–40 –20 0 20 40 60 80

TEMPERATURE (°C)

Figure 35. Typical Reference Variation with Temperature

VREF

0.1µF10µF

SENSE

Figure 36. Internal Fixed Reference (1 V p-p)

0

–0.1

04619-016

04619-049

SENSE

7kΩ

0.5V

04619-014

–0.2

–0.3

% CHANGE IN VREF VOLTAGE

–0.4

Figure 34. Internal Reference Equivalent Circuit

–0.5

0 0.5 1.51.0 2.0 2.5 3.0

IREF (mA)

04619-017

Figure 37. Internal VREF vs. Load Current

Table 9. Reference Configurations

SENSE Voltage Resulting VREF Reference Differential Span

AVDD N/A (External Reference Input) External 1 × External Reference Voltage

0.5 V (Self-Biased) 0.5 × (1 + R1/R2) V Programmable 1 × VREF (0.75 V p-p to 1.5 V p-p)
AGND to 0.2 V 1.0 V Internal Fixed 1 V p-p

Rev. A | Page 17 of 28

AD9480

External Reference

An external reference can be used for greater accuracy and
temperature stability when required. The gain of the AD9480
can also be varied using this configuration. A voltage output
DAC can be used to set VREF, providing for a means to digitally
adjust the full-scale voltage. VREF can be externally set to
voltages from 0.75 V to 1.5 V; optimum performance is typically
obtained at VREF = 1 V. (See the Typical Performance
Characteristics section.)

MAY REQUIRE

RC FILTER

EXTERNAL

REFERENCE OR

DAC INPUT

AVDD

Figure 38. External Reference

Programmable Reference

The programmable reference can be used to set a differential
input span anywhere between 0.75 V p-p and 1.5 V p-p by
using an external resistor divider. The sense pin will self-bias to

0.5 V, and the resulting VREF is equal to 0.5 × (1 + R1/R2). It is
recommended to keep the sum of R1 + R2 ≥ 10 kΩ to limit
VREF loading (for VREF = 1.5 V, set R1 equal to 7 kΩ and R2
equal to 3.5 kΩ).

10µF

0.1µF

Figure 39. Programmable Reference

R1

R2

DIGITAL OUTPUTS

LVDS outputs are available when a 3.7 kΩ RSET resistor is
placed at Pin 42 (LVDSBIAS) to ground. The RSET resistor
current (~1.2 V/RSET) is ratioed on-chip, setting the output
current at each output equal to a nominal 3.5 mA with an RSET
of 3.74 kΩ. Varying the RSET current also linearly changes the
LVDS output current, resulting in a variable output swing for a
fixed termination resistance.

A 100 Ω differential termination resistor placed at the LVDS
receiver inputs results in a nominal 350 mV swing at the
receiver. LVDS mode facilitates interfacing with LVDS receivers
in custom ASICs and FPGAs that have LVDS capability for
superior switching performance in noisy environments. Single
point-to-point net topologies are recommended with a 100 Ω
termination resistor as close to the receiver as possible. Keep the

VREF

SENSE

VREF

SENSE

04619-018

04619-019

trace length 3 inches to 4 inches maximum and the differential
output trace lengths as equal as possible.

OUTPUT CODING

Table 10.

Code (VIN+) − (VIN−) Offset Binary Twos Complement

255 >+0.512 V 1111 1111 0111 1111
255 +0.512 V 1111 1111 0111 1111
254 +0.508 V 1111 1110 0111 1110

• • • •

• • • •
129 +0.004 V 1000 0001 0000 0001
128 +0.0 V 1000 0000 0000 0000
127 –0.004 V 0111 1111 1111 1111

• • • •

• • • •
2 −0.504 V 0000 0010 1000 0010
1 −0.508 V 0000 0001 1000 0001
0 −0.512 V 0000 0000 1000 0000
0 <−0.512 V 0000 0000 1000 0000

INTERLEAVING TWO AD9480s

Instrumentation applications may prefer to interleave or ping­pong two AD9480s to achieve twice the sample rate, or
500 MSPS. In these applications, it is important to match the
gain and offset of the two ADCs. Varying the reference voltage
allows the gain of the ADCs to be adjusted; external dc offset
compensation can be used to reduce offset mismatch between
two ADCs. The sampling phase offset between the two ADCs is
extremely important as well and requires very low skew
between clock signals driving the ADCs (<2 ps clock skew for a
100 MHz analog input frequency).

DATA CLOCK OUT

An LVDS data clock is available at DCO+ and DCO−. These
clocks can facilitate latching off-chip, providing a low skew
clocking solution. The on-chip delay of the DCO clocks tracks
with the on-chip delay of the data bits (under similar loading),
such that the variation between T

and T

PD

is minimized. It is

CPD

recommended to keep the trace lengths on the data and DCO
pins matched and to 3 inches to 4 inches maximum. The output
and DCO outputs should be designed for a differential
characteristic impedance of 100 Ω and terminated differentially
at the receiver with 100 Ω.

POWER-DOWN

The chip can be placed in a low power state by driving the
PDWN pin to logic high. Typical power-down dissipation is
15 mW. The data outputs and DCO outputs are high impedance
in power-down state. The time it takes to go into power-down
from assertion of PDWN is one cycle; recovery from power­down is accomplished in three cycles.

Rev. A | Page 18 of 28

AD9480

AD9480 EVALUATION BOARD

The AD9480 evaluation board offers an easy way to test the
device. It requires a clock source, an analog input signal, and a

3.3 V power supply. The clock source is buffered on the board
to provide the clocks for the ADC and a data-ready signal. The
digital outputs and output clocks are available at a 40-pin
connector, P10. The board has several modes of operation and
is shipped in the following configuration:

• Offset binary

• Internal voltage reference

POWER CONNECTOR

Power is supplied to the board via two detachable 4-pin
power strips.

Table 11. Power Connector

Terminal Comments

AVDD1 3.3 V Analog supply for ADC ~ 150 mA
DRVDD1 3.3 V Output supply for ADC ~ 40 mA

1, 2

VCTRL
Op Amp,

External Reference

1

2

3.3 V Supply for support clock circuitry ~ 50 mA
Optional supply for op amp and

ADR510 reference

AVDD, DRVDD, and VCTRL are the minimum required power connections.
LVEL16 clock buffer can be powered from AVDD or VCTRL LVEL16 buffer
jumper.

ANALOG INPUTS

The evaluation board accepts a 700 mV p-p analog input signal
centered at ground at SMB Connector J3. This signal is
terminated to ground through 50 Ω by R22. The input can be
alternatively terminated at the T1 transformer secondary by
R21 and R28. T1 is a wideband RF transformer that provides
the single-ended-to-differential conversion, allows the ADC to
be driven differentially, and minimizes even-order harmonics.
An optional transformer, T4, can be placed, if desired (remove
T1, as shown in Figure 41 and Figure 42).

with a 1.2 kΩ resistor and R42 with a 100 Ω resistor. Populate
R52 with a 10 kΩ resistor.

CLOCK

The clock input is terminated to ground through 50 Ω at SMA
Connector J1. The input is ac-coupled to a high speed
differential receiver (LVEL16) that provides the required low
jitter and fast edge rates needed for best performance. J1 input
should be >0.5 V p-p. Power to the LVEL16 is set to VCTRL
(default) or AVDD by jumper placement at the device.

OPTIONAL CLOCK BUFFER

The PCB has been designed to accommodate the SNLVDS1
line driver. The SNLVDS1 is used as a high speed LVDS-level
optional encode clock. To use this clock, remove C2, C5, and
C6. Place a 0.1 µF capacitor on C34, C35, and C26. Place a 10 Ω
resistor on R48, a 100 Ω resistor on R6, and a 0 Ω resistor on
R49 and R53. For best results using the LVDS line driver, J1
input should be >2.5 V p-p.

OPTIONAL XTAL

The PCB has been designed to accommodate an optional
crystal oscillator that can serve as a convenient clock source.
The footprint can accept both through-hole and surface-mount
devices, including Vectron XO-400 and Vectron VCC6 family
oscillators.

VCC

OUT+

The analog signal can be low-pass filtered by R31, C8, and
R29, C9 at the ADC input.

GAIN

Full scale is set by the sense jumper. This jumper applies a bias
to the SENSE pin to vary the full-scale range; the default
position is SENSE = ground, setting the full scale to 1 V p-p.

OPTIONAL OPERATIONAL AMPLIFIER

The PCB has been designed to accommodate an optional
AD8351 op amp, which can serve as a convenient solution for
dc-coupled applications. To use the AD8351 op amp, remove
R29, R31, and C3. Populate R40, R43, and R47 with 25 Ω
resistors, and populate C24, C28, C29, C30, C31, and C32 with

0.1 µF capacitors. Populate R38, R39, and R51 with a 10 Ω
resistor, and R44 and R45 with a 1 kΩ resistor. Populate R41

Rev. A | Page 19 of 28

OUT–

GND

VCC

Figure 40. XTAL Footprint

To use either crystal, populate C26 and C27 with 0.1 µF capaci­tors. Populate R49 and R53 with 0 Ω resistors. Place 1 kΩ
resistors on R54, R55, R56, and R57 and remove C6 and C5.
If the Vectron VCC6 family crystal is being used, populate
R48 with a 10 Ω resistor. If using the XO-400 crystal, place
Jumper E21 or Jumper E22 to Jumper E23.

04619-040

AD9480

VOLTAGE REFERENCE

The AD9480 has an internal 1 V reference mode. The ADC
uses the internal 1 V reference as the default when
to ground. An optional on-board external 1.0 V reference
(ADR510) can be used by setting the SENSE jumper to AVDD,
by placing a jumper on E20 to E3, and by placing a 0 Ω resistor
on R36. When using an external programmable reference
(R20, R30), the SENSE jumper must be removed.

SENSE is set

DATA OUTPUTS

The off-chip drivers provide LVDS-compatible output levels
with an LVDS RSET resistor of 3.74 kΩ.

The ADC digital outputs can be terminated on the board by
100 Ω resistors at the connector if receiving logic does not have
the required termination resistance. (The on-chip LVDS output
drivers require a far-end, 100 Ω differential termination.)

Rev. A | Page 20 of 28

AD9480

EVALUATION BOARD BILL OF MATERIALS (BOM)

Table 12.

No. Quantity Reference Designator Device Package Value

1 23

2 1 C13 Capacitor Tantalum (3528) 10 µF
3 4 C7, C14 to C16 Capacitors Tantalum (6032) 10 µF
4 2 J1, J3 SMAs
5 2 P12, P13 4-pin power connector posts Z5.531.3425.0 Wieland
6 2 P12, P13 4-pin power detachable connectors 25.602.5453.0 Wieland
7 2 R22, R27 Resistors 0603 50 Ω
8 10

9 6 R1, R44, R45, R50, R58, R59 Resistors 0603 1000 Ω
10 1 R41 Resistors 0603 1200 Ω
11 3 R40, R43, R47 Resistors 0603 25 Ω
12 3 R38, R39, R51 Resistors 0603 10 Ω
13 2 R25, R26 Resistors 0603 82 Ω
14 2 R23, R24 Resistors 0603 510 Ω
15 2 R32, R34 Resistors 0603 130 Ω
16 2 R29, R31 Resistors 0603 0 Ω
17 2 R33, R52 Resistors 0603 10 kΩ
18 1 R63 Resistor 0603 3.74 kΩ
19 1 T1 Transformer CD542 Mini-Circuits T1-1WT
20 1 U13 AD8351 MSOP-10
21 1 U2 SN65LVDS1 SN65LVDS1 DBV Not placed
22 1 U14 ADR510 SOT-23 Not placed
23 1 U15 VCC6PECL6 VCC6-QAB-250M000 Not placed
24 1 U1 XO-400 Dip4(14) Not placed
25 1 U12 AD9480 TQFP-44
26 1 U11 MC100LVEL16D S08NB
27 1 T2 ETC1-1-13 1-1 TX Not placed
28 7

29 12

30 18

31 1 P10 Output Data Connector 40-pin right angle

C1 to C6, C10 to C12,
C17 to C23, C26 to C28,
C31 to C33, C35

R2 to R5, R7 to R10, R15, R42
(All not placed)

C8, C9, C24, C25, C29, C30,
and C34 (All not placed)

R6, R20, R21, R28, R30, R36,
R46, R48, R49, and R55 to
R57 (All not placed)

E5 to E8, E17,
E35, E73 to E84

Capacitors 0402 0.1 µF

Resistors 0603 100 Ω

Capacitors 0402 Not placed

Resistors 0603 User-determined

Jumpers

Digi-Key
S2131-20-ND

Rev. A | Page 21 of 28

AD9480

PCB SCHEMATICS

1

P1

2

P2

3

P3

4

P4

P12

PTMICRO4

1

P1

2

P2

3

POWER CONN.

P3

4

P4

P13

PTMICRO4

GND
VAMP
GND
DRVDD
GND
AVDD
GND

VCTRL

D7T

DR–

D6T

D7T

GND

GND

39

P31P32

P33P34

P35P36

P37P38

P39

P40

40

OUTPUT DATA CONN.

D7C

D6C

DR+

GND

GND

D5T

D6C

D6T

D7C

R2

100Ω

R3

100Ω

GND
S1

PWDN
GND

AVDD
GND

D5C

D4T

DR+

D4C

DR–

D3T

R4

100Ω

R5

100Ω

R15

100Ω

GND

DRVDD

16

D5C

D4T

AVDD

AGND

D4C

DRVDD

AGND

VIN–

1718192021

DCO–

DCO+

AD9480

VIN+

AGND

15

DRGNDAVDD

D3T

LVDSBIAS

D3C

NC

22

D6C

D5T

D6T
D7C
D7T

DRGND

S1

PWDN

AGND

AVDD

AGND

SENSE

33 32 31 30 29 28 27 26 25 24 23

VREF

D5T

29

P29

P30

303132333435363738

D5C

R7

121314

D2T

AGND

4443424140393837363534

D4T

P27P28

D4C

100Ω

D3T

P25P26

D3C

D3C

D2T

P23P24

D2C

D2T

D1T

P21P22

D1C

R10

D2C
D1T

D0T
D0C
DRGND

CLK–
CLK+

U12

D0T

19

P17P18

P19

P20

202122232425262728

D0C

D2C

100Ω

D1C

DRVDD
AGND
AVDD

1234567891011

P15P16

D1T

P13P14

56789

1

3

P1

P3

P5P6

P7P8

P9

P11P12

P10

101112131415161718

P10

C40MS

P2

P4

2

4

GND GND

D0T

D0C

D1C

R9

100Ω

R8

100Ω

GND

DRVDD

GND

AVDD

E78

E77

PROBE POINTS

GND

GND

E79

E81

GND

GND

PADS FOR SHORTING EL16,

CLK–

CLK+

E80

GND

P15P14

E82

GND

R6

D+

CLK

X

E83

GND

P17P16

E84

GND

D–

CLKN

C33

P6

E4

AVDD

0.1µF

E70

AVDD

GND

E35

E12

GND

E32

VCTRL

P7

FOR ON BOARD EXT. REF

JUMPER E13 TO 14 AND E20 TO E3

PLACE R36 0Ω AND R33 10kΩ

R20XXR30

GND

E16

E14

E15

TRIM/NC

V+

2

ADR510

V–

GND

R33

10kΩ

U14

E13

VCTRL

R36

GND

X

C1

3

1

E20 E3

EXTVREF

VAMP

GND

C12

0.1µF

GND

+

XX

C13

GND

10µF

E1

E2

0.1µF
GND

AVDD

GND

E17

R36

1kΩ

GND

AVDD

R63

3.7kΩ
GND

E7

OPTIONAL

VCTRL

GND

C9

AMPOUT

C8

AMPOUT

T1+

123

654

TIN1

OPTIONAL

TRANSFORMER

CM

CM

E17

E17

C6

0.1µF

GND

VCTRL

C11

0.1µF

E9

R34

GND

E10

AVDD

VCTRL

82Ω

8

1

E11

VCTRL

J1

VCC
R

CLKINPUT

X

X

GND

T1–

GND

R31

00

T1–

123

654

GND

FOR OP AMP CONFIGURATION

C10

0.1µF

R28XR21

CM

CM

E8

50

R22

REMOVE RESISTORS R29, R31, AND C3

GND

X

T1+

J3

ANALOG

C10

INPUT

00

R29

0.1µF

AMPIN

GND

7

Q

CLK

2

CLK

R32

82Ω

R26

130Ω

6

Q

VEE

VBB

100LVEL16

CLKN

3

C11

0.1µF

GND

R25

C5

0.1µF

130Ω

GND

GND

U11

5

4

R24

R23

R27

GND

C4

0.1µF

510Ω

510Ω

50Ω

GND

04619-041

Figure 41. PCB Schematic (1 of 2)

Rev. A | Page 22 of 28

AD9480

CLK–

CLK+

XR57

X

R53

R49

5

213

VCTRL

X

GND

X

R54

VCTRL

OUT+

4

GND

X

R48

AVDD

C35

C20

C19

C18

C17

+

C7

C32

R56X

X

GND

GND

GNDVCTRL

GND

X

R55

OUT–

6

VCC 6 PECL6

C23

X

C23

+

VCTRL

+

DRVDD

C15

C22

C21

C14

0.1µF

10µF

GND

1

8

OUTVCC

0.1µF

0.1µF

10µF

GND

OPTIONAL XTALS

VEE –OUT

U1

XO-400

7

14

C27

E23

E22

E21

AVDD

VCTRL

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

10µF

GND

0.1µF

U2

E25

E24

D

VCC

AVDD

PWDNVCTRL

GND

2513

GND

4

Y

Z

C34

CLKINPUT

OPTIONAL

SN65LVDS1

X

VCTRL

R38

VAMP

P4 P3

OUT+

OUT+

E28

E26

X

VIVIS VAMPF

R59

+

C16

E34

E36

AMPOUT

AMPOUT

C25

X

VOCM
10

2

RGP1

C30

VAMPF

VPOS

OPHI

8

9

3

INHI

X

R46

R39

AMPIN

X

X

OPLO
7

4

INLO

X

C29

COMM
6

5

RPG2

R51

C31

X

GND

X

X

R40

X

R41

X

R42

GND

X

04619-042

10µF

GND

GNDVAMPF

R45

R44

R52

X

X

U13

C24

AD8351

1

PWUP

X

GND

C28

0.1µF

X= NOT NORMALLY POPULATED

XX = USER SELECTED, IS NOT NORMALLY POPULATED

S1

E29

E31

E27

E30

R50

R58

1kΩ

1kΩ

GND

1kΩ

OPTIONAL

VAMPF

Figure 42. PCB Schematic (2 of 2)

Rev. A | Page 23 of 28

AD9480

PCB LAYERS

Figure 43. PCB Top-Side Silkscreen

04619-045

04619-043

Figure 45. PCB Ground Layer

Figure 44. PCB Top-Side Copper Routing

04619-044

Rev. A | Page 24 of 28

Figure 46. PCB Split Power Plane

04619-046

AD9480

04619-047

Figure 47. PCB Bottom-Side Copper Routing

Figure 48. PCB Bottom-Side Silkscreen

04619-048

Rev. A | Page 25 of 28

AD9480

OUTLINE DIMENSIONS

0.75

0.60

0.45

1.20

MAX

44

1

12.00 BSC SQ

34

33

PIN 1

1.05

1.00

0.95

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0° MIN

0.20

0.09

7°

3.5°
0°

0.08 MAX
COPLANARITY

COMPLIANT TO JEDEC STANDARDS MS-026ACB

11

12

VIEW A

LEAD PITCH

TOP VIEW

(PINS DOWN)

0.80

BSC

0.45

0.37

0.30

10.00

BSC SQ

23

22

Figure 49. 44-Lead Thin Plastic Quad Flat Package [TQFP]

(SU-44)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Description Package Option

AD9480BSUZ-250
AD9480ASUZ-2501
AD9480-LVDS/PCB

1

Z = Pb-free part.

2

Optimized differential nonlinearity.

3

Evaluation board shipped with AD9480BSUZ-250 installed.

1, 2

3

−40°C to +85°C

−40

°C to +85°C

Evaluation Board

44-Lead Thin Plastic Quad Flat Package (TQFP) SU-44
44-Lead Thin Plastic Quad Flat Package (TQFP) SU-44

Rev. A | Page 26 of 28

AD9480

NOTES

Rev. A | Page 27 of 28

AD9480

NOTES

©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04619–0–4/05(A)

Rev. A | Page 28 of 28