Analog Devices AD9480 Service Manual

8-Bit, 250 MSPS

C

FEATURES

DNL = ± 0.25 LSB
INL = ± 0.26 LSB
Single 3.3 V supply operation (3.0 V to 3.6 V)
Power dissipation of 590 mW at 250 MSPS
1 V p-p analog input range
Internal 1.0 V reference
Single-ended or differential analog inputs
LVDS outputs (ANSI 644 levels)
Power-down mode
Clock duty-cycle stabilizer

APPLICATIONS

Digital oscilloscopes
Instrumentation and measurement
Communications

Point-to-point radios
Predistortion loops

VIN+
VIN–

LK+

CLK–

3.3 V A/D Converter

FUNCTIONAL BLOCK DIAGRAM

VREF SENSE

REFERENCE

T&H

CLOCK

MGMT

AGND DrGND DRVDD AVDD

AD9480

8-BIT

ADC

PIPELINE

CORE

Figure 1.

8

LOGIC

LVDSBIASPDWN S1

AD9480

16

LVDS

D7–D0
(LVDS)

DCO+
DCO-

(LVDS)

04619-001

GENERAL DESCRIPTION

The AD9480 is an 8-bit, monolithic analog-to-digital converter
(ADC) optimized for high speed and low power consumption.
Small in size and easy to use, the product operates at a
250 MSPS conversion rate, with excellent linearity and dynamic
performance over its full operating range.

To minimize system cost and power dissipation, the AD9480
includes an internal reference and track-and-hold circuit. The
user only provides a 3.3 V power supply and a differential
encode clock. No external reference or driver components are
required for many applications.

The digital outputs are LVDS (ANSI 644) compatible with an
option of twos complement or binary output format. The
output data bits are provided in parallel fashion along with an
LVDS output clock, which simplifies data capture.

Fabricated on an advanced BiCMOS process, the AD9480 is
available in a 44-lead surface-mount package (TQFP) specified
over the industrial temperature range −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Superior linearity. A DNL of ±0.25 makes the AD9480

suitable for instrumentation and measurement
applications.

2. Power-down mode. A power-down function may be

exercised to bring total consumption down to 15 mW.

3. LVDS outputs (ANSI-644). LVDS outputs simplify timing

and improve noise performance

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] ©2005 Analog Devices, Inc. All rights reserved.

www.analog.com

AD9480

TABLE OF CONTENTS

DC Specifications ............................................................................. 3

Interleaving Two AD9480s........................................................ 18

Digital Specifications........................................................................ 4

AC Specifications.............................................................................. 5

Switching Specifications .................................................................. 6

Timing Diagram ........................................................................... 6

Absolute Maximum Ratings............................................................ 7

Explanation of Test Levels........................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Te r mi n ol o g y ...................................................................................... 9

Typical Performance Characteristics ........................................... 11

Equivalent Circuits......................................................................... 15

Application Notes ........................................................................... 16

Clocking the AD9480 ................................................................ 16

Analog Inputs.............................................................................. 16

Volt a ge R e fer e nce ....................................................................... 17

Data Clock Out........................................................................... 18

Power-Down ............................................................................... 18

AD9480 Evaluation Board ............................................................ 19

Power Connector ........................................................................ 19

Analog Inputs ............................................................................. 19

Gain.............................................................................................. 19

Optional Operational Amplifier .............................................. 19

Clock ............................................................................................ 19

Optional Clock Buffer ............................................................... 19

Optional XTAL ........................................................................... 19

Volt a ge R e fer e nce ....................................................................... 20

Data Outputs............................................................................... 20

Evaluation Board Bill of Materials (BOM) ................................. 21

PCB Schematics .............................................................................. 22

PCB Layers ...................................................................................... 24

Digital Outputs ........................................................................... 18

Output Coding............................................................................ 18

REVISION HISTORY

4/05—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Features.......................................................................... 1

Changes to Table 3............................................................................ 5

Changes to Table 7............................................................................ 8

Changes to Analog Inputs .............................................................16

Changes to Figure 30...................................................................... 16

Added Power Down Section ......................................................... 18

Changes to Table 12........................................................................ 21

7/04—Revision 0: Initial Version

Outline Dimensions ....................................................................... 26

Ordering Guide .......................................................................... 26

Rev. A | Page 2 of 28

AD9480

DC SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, T
clock inputs, unless otherwise noted.

Table 1.

AD9480-250
Parameter Temp Test Level Min Typ Max Unit

RESOLUTION 8 Bits
ACCURACY

No Missing Codes Full VI Guaranteed
Offset Error 25°C I −40 +40 mV
Gain Error

1

Differential Nonlinearity (DNL)

AD9480BSUZ-250 Full VI −0.5 ±0.28 +0.5 LSB
AD9480ASUZ-250 Full VI −0.85 ±0.35 +0.85 LSB

Integral Nonlinearity (INL) Full VI −0.9 ±0.26 +0.9 LSB

TEMPERATURE DRIFT

Offset Error Full V 30 µV/°C
Gain Error Full V 0.03 %FS/°C
Reference Full V ±0.025 mV/°C

REFERENCE

Internal Reference Voltage Full VI 0.97 1.0 1.03 V
Output Current
I

Input Current

VREF

I

Input Current2 25°C I 10 µA

SENSE

2

3

ANALOG INPUTS (VIN+, VIN−)

Differential Input Voltage Range (FS = 1)
Common-Mode Voltage Full VI 1.7 1.9 2.1 V
Input Resistance 25°C I 8.6 10 10.7 kΩ
Full VI 8.4 10 11.2 kΩ
Input Capacitance 25°C V 4 pF
Analog Bandwidth, Full Power 25°C V 750 MHz

POWER SUPPLY

AVDD Full IV 3.0 3.3 3.6 V
DRVDD Full IV 3.0 3.3 3.6 V
Power Dissipation

5

Power-Down Dissipation 25°C V 15 mW

5

I

AVDD

5

I

DRVDD

Power Supply Rejection Ratio (PSRR) 25°C V −4.2 mV/V

1

Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1 V external reference and a 1 V p-p differential analog input).

2

Internal reference mode; SENSE = AGND.

3

External reference mode; VREF driven by external 1.0 V reference; SENSE = AVDD.

4

In FS = 1 V, both analog inputs are 500 mV p-p and out of phase with each other.

5

Power dissipation and current measured with rated encode and a dc analog input (outputs static). See for active operation. Figure 13

= −40°C, T

MIN

= +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and

MAX

25°C I −6.0 +6.0 % FS

25°C IV 1.5 mA
25°C I 100 µA

4

Full V 1 V p-p

25°C V 590 mW

Full VI 145 156 mA
Full VI 34 38 mA

Rev. A | Page 3 of 28

AD9480

DIGITAL SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, T
clock inputs, unless otherwise noted.

Table 2.

AD9480-250
Parameter Temp Test Level Min Typ Max Unit

CLOCK INPUTS (CLK+, CLK−)

Differential Input Full IV 200 mV p-p
Common-Mode Voltage

1

Input Resistance Full VI 4.2 5.5 6.0 kΩ
Input Capacitance 25°C V 4 pF

LOGIC INPUTS (PDWN, S1)

2

PDWN Logic 1 Voltage Full IV 2.0 V
PDWN Logic 0 Voltage Full IV 0.8 V
PDWN Logic 1 Input Current Full VI ±160 µA
PDWN Logic 0 input Current Full VI 10 µA
PDWN, S1 Input Resistance 25°C V 30 kΩ
PDWN, S1 Input Capacitance 25°C V 4 pF

DIGITAL OUTPUTS

Differential Output Voltage (VOD)
Output Offset Voltage (VOS) Full VI 1.125 1.375 V
Output Coding Full IV Twos complement or binary

1

The common mode for CLOCK inputs can be externally set, such that 0.9 V < CLK ± < 2.6 V.

2

S1 is a multilevel logic input, see Ta . ble 8

3

LVDSBIAS resistor = 3.74 kΩ.

= −40°C, T

MIN

3

= +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and

MAX

Full VI 1.4 1.5 1.68 V

Full VI 247 454 mV

Rev. A | Page 4 of 28

AD9480

AC SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, T
clock inputs, unless otherwise noted.

Table 3.

AD9480-250
Parameter Temp Test Level Min Typ Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 19.7 MHz 25°C V 47 dB
fIN = 70.1 MHz 25°C I 45 47 dB
fIN = 170 MHz 25°C I 45 46 dB

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 19.7 MHz 25°C V 46.5 dB
fIN = 70.1 MHz 25°C I 44.8 46.5 dB
fIN = 170 MHz 25°C I 44.8 46.5 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 19.7 MHz 25°C V 7.6 Bits
fIN = 70.1 MHz 25°C I 7.3 7.6 Bits
fIN = 170 MHz 25°C I 7.3 7.6 Bits

WORST SECOND OR THIRD HARMONIC DISTORTION

fIN = 19.7 MHz 25°C V −65 dBc
fIN = 70.1 MHz 25°C I −65 −60 dBc
fIN = 170 MHz 25°C I −65 −60 dBc

WORST OTHER

fIN = 19.7 MHz 25°C V −70 dBc
fIN = 70.1 MHz 25°C I −70 −63 dBc
fIN = 170 MHz 25°C I −70 −63 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 19.7 MHz 25°C V −65 dBc
fIN = 70.1 MHz 25°C I −65 −60 dBc
fIN = 170 MHz 25°C I −65 −60 dBc

TWO-TONE INTERMODULATION DISTORTION (IMD)

f

= 69.3 MHz, f

IN1

1

Nyquist bin energy ignored.

= 70.3 MHz 25°C V −68 dBc

IN2

= –40°C, T

MIN

1

= +85°C, AIN = –1 dBFS, full scale = 1.0 V, internal reference, differential analog and

MAX

Rev. A | Page 5 of 28

AD9480

SWITCHING SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, differential clock input, DCS enabled, unless otherwise noted.

Table 4.

AD9480-250
Parameter Temp Test Level Min Typ Max Unit

CLOCK

Maximum Conversion Rate Full VI 250 MSPS
Minimum Conversion Rate Full VI 20 MSPS
Clock Pulse Width High (tEH) Full IV 1.2 2 ns
Clock Pulse Width Low (tEL) Full IV 1.2 2 ns

OUTPUT PARAMETERS

Valid Time (tV)
Propagation Delay (tPD) Full VI 2.8 3.8 ns
Rise Time (tR) 20% to 80% Full V 0.5 ns
Fall Time (tF) 20% to 80% Full V 0.5 ns
DCO Propagation Delay (t
Data-to-DCO Skew (tPD − t
Pipeline Latency 25°C VI 8 Cycles

APERTURE

Aperture Delay (tA) 25°C V 1.5 ns
Aperture Uncertainty (Jitter) 25°C V 0.25 ps rms

1

Valid time is approximately equal to minimum tPD. C

1

) Full VI 1.9 2.7 3.7 ns

CPD

) Full IV 0 0.1 0.6 ns

CPD

equals 5 pF maximum.

LOAD

Full VI 1.9 ns

TIMING DIAGRAM

AIN

CLK+

CLK–

DATA

OUT

DCO+
DCO–

N–1

t

A

N

N+9

N+1

8 CYCLES

t

t

EH

EL

t

CPD

1/f

S

t

PD

N–8

t

V

N–7 N N+1 N+2

N+8

N+10

N+11

04619-002

Figure 2. Timing Diagram

Rev. A | Page 6 of 28

AD9480

ABSOLUTE MAXIMUM RATINGS

Thermal impedance (θJA) = 46.4°C/W (4-layer PCB).

Table 5.

Parameter Min Rating Max Rating

ELECTRICAL

AVDD

(With Respect to AGND)

DRVDD

(With Respect to DRGND)

AGND

(With Respect to DRGND)

Digital I/O

(With Respect to DRGND)

Analog Inputs

(With Respect to AGND)

ENVIRONMENTAL

Operating Temperature −40°C 85°C
Junction Temperature 150°C
Case Temperature 150°C
Storage Temperature 150°C

−0.5 V +4.0 V

−0.5 V +4.0 V

−0.5 V +0.5 V

−0.5 V DRVDD + 0.5 V

−0.5 V AVDD + 0.5 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

EXPLANATION OF TEST LEVELS

Table 6.

Level Descriptions

I 100% production tested.
II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 7 of 28

AD9480

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

CLK+

2

CLK–

3

AVDD

4

AGND

D1_C

D1_T

D2_C

5
6
7
8

9
10
11

DRVDD

DRGND
D0_C (LSB)
D0_T (LSB)

NC = NO CONNECT

AGND43NC42LVDSBIAS

44

12

D2_T

AVDD40AGND39VIN+38VIN–37AGND36AVDD35AGND34VREF

41

PIN 1

AD9480

TOP VIEW

(Not to Scale)

13

14

15

16

17

18

D3_T

D3_C

DCO–

DRGND

DCO+

19

D4_C

DRVDD

33

SENSE

32

AGND

31

AVDD

30

AGND

29

PDWN

28

S1

27

DRGND

26

D7_T (MSB)

25

D7_C (MSB)

24

D6_T

23

D6_C

20

21

22

D4_T

D5_T

D5_C

04619-003

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin
No. Mnemonic Description

Pin
No. Mnemonic Description

1 CLK+ Input Clock—True 23 D6_C Data Output Bit 6—Complement
2 CLK− Input Clock—Complement 24 D6_T Data Output Bit 6—True
3 AVDD 3.3 V Analog Supply 25 D7_C Data Output Bit 7—Complement (MSB)
4 AGND Analog Ground 26 D7_T Data Output Bit 7—True (MSB)
5 DRVDD 3.3 V Digital Output Supply 27 DRGND Digital Ground
6 DRGND Digital Ground 28 S1

Data Format Select and Duty-Cycle Stabilizer Selection

(See Table 8)
7 D0_C Data Output Bit 0—Complement (LSB) 29 PDWN Power-Down Selection (AVDD = Power Down)
8 D0_T Data Output Bit 0—True (LSB) 30 AGND Analog Ground
9 D1_C Data Output Bit 1—Complement 31 AVDD 3.3 V Analog Supply
10 D1_T Data Output Bit 1—True 32 AGND Analog Ground
11 D2_C Data Output Bit 2—Complement 33 SENSE Reference Mode Selection (See Table 9)
12 D2_T Data Output Bit 2—True 34 VREF Voltage Reference Input/Output
13 D3_C Data Output Bit 3—Complement 35 AGND Analog Ground
14 D3_T Data Output Bit 3—True 36 AVDD 3.3 V Analog Supply
15 DRGND Digital Ground 37 AGND Analog Ground
16 DCO− Data Clock Output—Complement 38 VIN− Analog Input—Complement
17 DCO+ Data Clock Output—True 39 VIN+ Analog Input—True
18 DRVDD 3.3 V Digital Output Supply 40 AGND Analog Ground
19 D4_C Data Output Bit 4—Complement 41 AVDD 3.3 V Analog Supply
20 D4_T Data Output Bit 4—True 42 LVDSBIAS LVDS Output Current Adjust
21 D5_C Data Output Bit 5—Complement 43 NC

1

No Connect (Leave Floating)
22 D5_T Data Output Bit 5—True 44 AGND Analog Ground

1

Pin 43 will self-bias to 1.5 V. It can be left floating (as recommended) or tied to AVDD or ground with no ill effects.

Rev. A | Page 8 of 28

AD9480

TERMINOLOGY

Analog Bandwidth

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

Aperture Delay

The delay between the 50% point of the rising edge of the
encode command and the instant the analog input is sampled.

Full-Scale Input Power

Expressed in dBm. Computed by

2

⎛
⎜

Power

FULLSCALE

=

10

log

⎜
⎜
⎜
⎜

⎝

FULLSCALE

Z

INPUT

0010

.

⎞

rmsV

⎟
⎟
⎟
⎟

⎟
⎠

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Clock Pulse Width/Duty Cycle

Pulse width high is the minimum amount of time that the
clock pulse should be left in a Logic 1 state to achieve rated
performance; pulse width low is the minimum time that the
clock pulse should be left in a low state. See the timing
implications of changing t

in the Clocking the AD9480

EH

section. At a given clock rate, these specifications define an
acceptable clock duty cycle.

Crosstalk

Coupling onto one channel being driven by a low level
(−40 dBFS) signal when the adjacent interfering channel
is driven by a full-scale signal.

Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance

The real and complex impedances measured at each analog
input port. The resistance is measured statically, and the
capacitance and differential input impedances are measured
with a network analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the inputs phase 180° and taking the peak measurement again.
The difference is then computed between both peak
measurements.

Differential Nonlinearity

The deviation of any code width from an ideal 1 LSB step.

Effective Number of Bits

The effective number of bits (ENOB) is calculated by the
measured SINAD based on (assuming full-scale input)

ENOB

SINAD

=

MEASURED

6.02

dB1.76−

Gain Error

The difference between the measured and ideal full-scale input
voltage range of the ADC.

Harmonic Distortion, Second

The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.

Harmonic Distortion, Third

The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.

Integral Nonlinearity

The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a differential crossing of CLK+ and
CLK− and the time when all output data bits are within
valid logic levels.

Noise (For Any Range Within the ADC)

This value includes both thermal and quantization noise.

SignalSNRFS

noise

ZV .

⎛

××=

10001

⎜

⎜
⎝

10

−−

⎞

dBFSdBcdBm

⎟

⎟
⎠

where:

Z is the input impedance.
FS is the full scale of the device for the frequency in question.
SNR is the value for the particular input level.
Signal is the signal level within the ADC reported in dB below

full scale.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in
power supply voltage.

Rev. A | Page 9 of 28