ANALOG DEVICES AD9467 Service Manual

16-Bit, 200 MSPS/250 MSPS

A

Data Sheet

FEATURES

75.5 dBFS SNR to 210 MHz at 250 MSPS 90 dBFS SFDR to 300 MHz at 250 MSPS SFDR at 170 MHz at 250 MSPS

92 dBFS at −1 dBFS

100 dBFS at −2 dBFS 60 fs rms jitter Excellent linearity at 250 MSPS

DNL = ±0.5 LSB typical

INL = ±3.5 LSB typical 2 V p-p to 2.5 V p-p (default) differential

full-scale input (programmable) Integrated input buffer External reference support option Clock duty cycle stabilizer Output clock available Serial port control

Built-in selectable digital test pattern generation

Selectable output data format LVDS outputs (ANSI-644 compatible)

1.8 V and 3.3 V supply operation

APPLICATIONS

Multicarrier, multimode cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar Infrared imaging Communications instrumentation

GENERAL DESCRIPTION

The AD9467 is a 16-bit, monolithic, IF sampling analog-todigital converter (ADC). It is optimized for high performance over wide bandwidths and ease of use. The product operates at a 250 MSPS conversion rate and is designed for wireless receivers, instrumentation, and test equipment that require a high dynamic range.

The ADC requires 1.8 V and 3.3 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Analog-to-Digital Converter

AD9467

FUNCTIONAL BLOCK DIAGRAM

VDD1

GND DRVDD DRGND

AD9467

VIN+

VIN–

CLK+

CLK–

BUFFER

CLOCK

AND TIMIN G

MANAGEMENT

A data clock output (DCO) for capturing data on the output is provided for signaling a new output bit.

The internal power-down feature supported via the SPI typically consumes less than 5 mW when disabled.

Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data test patterns.

The AD9467 is available in a Pb-free, 72-lead, LFCSP specified over the −40°C to +85°C industrial temperature range.

PRODUCT HIGHLIGHTS

1. IF optimization capability used to improve SFDR.

2. Outstanding SFDR performance for IF sampling

applications such as multicarrier, multimode 3G, and 4G cellular base station receivers.

3. Ease of use: on-chip reference, high input impedance

buffer, adjustable analog input range, and an output clock to simplify data capture.

4. Packaged in a Pb-free, 72-lead LFCSP package.

5. Clock duty cycle stabilizer (DCS) maintains overall ADC

performance over a wide range of input clock pulse widths.

6. Standard serial port interface (SPI) supports various

product features and functions, such as data formatting (offset binary, twos complement, or Gray coding).

VDD2 AVDD3 SPIVDD

PIPELINE

16

ADC

REF

XVREF

Figure 1.

LVDS

OUTPUT

STAGING

2

16

2

CSB

SDIO

SCLK

OR+/OR–

D15+/D15– TO D0+/D0–

DCO+/DCO–

09029-001

AD9467 Data Sheet

REVISION HISTORY

9/11—Rev. B to Rev. C

Changes to Figure 44 and Figure 45............................................. 17

3/11—Rev. A to Rev. B

Change Parameter Name to Full Power Bandwidth, Table 1...... 3

Changes to Switching Specifications, Table 4 ............................... 7

Change to VIN+, VIN− Parameter, Table 5.................................. 8

Deleted Figure 43............................................................................ 17

Added New Figure 43..................................................................... 17

2/11—Rev. 0 to Rev. A

Changes to Features Section............................................................ 1

Added Figure 24 and Figure 25; Renumbered Sequentially ..... 14

Changes to Differential Configurations Section and

Figure 54 ..........................................................................................21

Added Figure 55 to Figure 57........................................................ 21

Changes to Figure 65 and Figure 66............................................. 24

Changes to Addr. (Hex) 15, Bits[2:0], Addr. (Hex) 10, Bits[7:0],

and Addr. (Hex) 10, Default Notes Column............................... 29

Changes to Addr. (Hex) 36, Default Value (Hex) Column and

Addr. (Hex) 107, Default Value (Hex) Column.......................... 30

10/10—Revision 0: Initial Version

Rev. C | Page 2 of 32

Data Sheet AD9467

SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted.

Table 1.

AD9467BCPZ-200 AD9467BCPZ-250

Parameter1 Temp Min Typ Max Min Typ Max Unit

RESOLUTION 16 16 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed

Offset Error Full −150 0 +150 −150 0 +150 LSB

Gain Error Full −3.5 −0.2 +2.5 −3.5 −0.1 +2.5 %FSR

Differential Nonlinearity (DNL)2 Full −0.8 ±0.4 +0.7 −0.6 ±0.5 +1.3 LSB

Integral Nonlinearity (INL)2 Full −9.5 ±5 +9.5 −11.8 ±3.5 +9.5 LSB

TEMPERATURE DRIFT

Offset Error Full ±0.020 ±0.023 %FSR/°C

Gain Error Full ±0.011 ±0.036 %FSR/°C

ANALOG INPUTS

Differential Input Voltage Range (Internal VREF = 1 V to 1.25 V) Full 2 2.5 2.5 2 2.5 2.5 V p-p

Common-Mode Voltage

Differential Input Resistance

Differential Input Capacitance

Full Power Bandwidth

25°C 25°C 25°C 25°C

2.3 2.15 V 530 530 Ω

3.5 3.5 pF 900 900 MHz

XVREF INPUT

Input Voltage Full 1 1.25 1 1.25 V

Input Capacitance Full 3 3 pF

POWER SUPPLY

AVDD1 Full 1.75 1.8 1.85 1.75 1.8 1.85 V

AVDD2 Full 3.0 3.3 3.6 3.0 3.3 3.6 V

AVDD3 Full 1.7 1.8 1.9 1.7 1.8 1.9 V

DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V

I

Full 485 536 580 514 567 618 mA

AVDD1

I

Full 49 55 61 49 55 61 mA

AVDD2

I

Full 21 24 27 27 31 35 mA

AVDD3

I

Full 35 38 41 36 40 43 mA

DRVDD

Total Power Dissipation (Including Output Drivers) Full 1.14 1.26 1.37 1.2 1.33 1.45 W

Power-Down Dissipation Full 4.4 90 4.4 90 mW

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

Rev. C | Page 3 of 32

AD9467 Data Sheet

AC SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input,

1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted.

Table 2.

AD9467BCPZ-200 AD9467BCPZ-250 Parameter1 Temp Min Typ Max Min Typ Max Unit

ANALOG INPUT FULL SCALE 2.5 2/2.5 2.5 2/2.5 V p-p SIGNAL-TO-NOISE RATIO (SNR)

fIN = 5 MHz 25°C 74.6/76.4 74.7/76.4 dBFS fIN = 97 MHz 25°C 75.1 74.5/76.2 74.5/76.1 dBFS fIN = 97 MHz Full 73.8 dBFS fIN = 140 MHz 25°C 74.3/76.0 74.4/76.0 dBFS fIN = 170 MHz 25°C 74.2/75.8 74.7 74.3/75.8 dBFS fIN = 170 MHz Full 72.3 dBFS fIN = 210 MHz 25°C 73.9/75.5 74.0/75.5 dBFS fIN = 300 MHz 25°C 73.5/74.7 73.3/74.6 dBFS

SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)

fIN = 5 MHz 25°C 74.6/76.3 74.6/76.3 dBFS fIN = 97 MHz 25°C 74.7 74.5/76.2 74.4/76.0 dBFS fIN = 97 MHz Full 73.1 dBFS fIN = 140 MHz 25°C 74.3/75.9 74.4/76.0 dBFS fIN = 170 MHz 25°C 74.1/75.6 74.4 74.2/75.8 dBFS fIN = 170 MHz Full 71.8 dBFS fIN = 210 MHz 25°C 73.9/75.3 73.9/75.4 dBFS fIN = 300 MHz 25°C 73.3/74.3 73.1/74.4 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 5 MHz 25°C 12.1/12.4 12.1/12.4 Bits fIN = 97 MHz 25°C 12.1/12.4 12.1/12.3 Bits fIN = 97 MHz Full Bits fIN = 140 MHz 25°C 12.1/12.3 12.1/12.3 Bits fIN = 170 MHz 25°C 12.0/12.3 12.0/12.3 Bits fIN = 170 MHz Full Bits fIN = 210 MHz 25°C 12.0/12.2 12.0/12.2 Bits fIN = 300 MHz 25°C 11.9/12.0 11.9/12.1 Bits

SPURIOUS-FREE DYNAMIC RANGE (SFDR) (INCLUDING

SECOND AND THIRD HARMONIC DISTORTION) fIN = 5 MHz 25°C 95/95 98/97 dBFS fIN = 97 MHz 25°C 86 95/95 95/93 dBFS fIN = 97 MHz Full 83 dBFS fIN = 140 MHz 25°C 94/93 94/95 dBFS fIN = 170 MHz 25°C 95/90 84 93/92 dBFS fIN = 170 MHz Full 84 dBFS fIN = 210 MHz 25°C 93/88 93/92 dBFS fIN = 300 MHz 25°C 92/86 93/90 dBFS

SPURIOUS-FREE DYNAMIC RANGE (SFDR) (INCLUDING SECOND

AND THIRD HARMONIC DISTORTION) fIN = 5 MHz @ −2 dB Full Scale Full 100/96 100/100 dBFS fIN = 97 MHz @ −2 dB Full Scale Full 100/98 97/97 dBFS fIN = 140 MHz @ −2 dB Full Scale Full 98/96 100/95 dBFS fIN = 170 MHz @ −2 dB Full Scale Full 96/93 100/100 dBFS fIN = 210 MHz @ −2 dB Full Scale Full 94/93 93/93 dBFS fIN = 300 MHz @ −2 dB Full Scale Full 90/89 90/90 dBFS

2

Rev. C | Page 4 of 32

Data Sheet AD9467

AD9467BCPZ-200 AD9467BCPZ-250 Parameter1 Temp Min Typ Max Min Typ Max Unit

WORST OTHER (EXCLUDING SECOND AND THIRD HARMONIC

DISTORTION)

2

fIN = 5 MHz 25°C 96/98 98/97 dBFS

fIN = 97 MHz 25°C 86 97/97 97/93 dBFS

fIN = 97 MHz Full 83 dBFS

fIN = 140 MHz 25°C 97/96 97/95 dBFS

fIN = 170 MHz 25°C 98/98 90 97/93 dBFS

fIN = 170 MHz Full 87 dBFS

fIN = 210 MHz 25°C 96/97 97/95 dBFS

fIN = 300 MHz 25°C 95/95 97/95 dBFS

TWO-TONE INTERMODULATION DISTORTION (IMD)—

AIN1 AND AIN2 = −7.0 dBFS @ 2.5 V p-p FS

f

= 70 MHz, f

IN1

f

= 170 MHz, f

IN1

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

See the SFDR Optimization—Buffer Current Adjustment section for optimum settings.

= 72 MHz 25°C 95 97 dBFS

IN2

= 172 MHz 25°C 93 91 dBFS

IN2

Rev. C | Page 5 of 32

AD9467 Data Sheet

DIGITAL SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted.

Table 3.

AD9467BCPZ-200 AD9467BCPZ-250

Parameter1 Temp Min Typ Max Min Typ Max Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Differential Input Voltage2 Full 250 250 mV p-p Input Common-Mode Voltage Full 0.8 0.8 V Input Resistance (Differential) 25°C 20 20 kΩ Input Capacitance 25°C 2.5 2.5 pF

LOGIC INPUTS (SCLK, CSB, SDIO)

Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V Logic 0 Voltage Full 0.3 0.3 V Input Resistance 25°C 30 30 kΩ Input Capacitance 25°C 0.5 0.5 pF

LOGIC OUTPUT (SDIO)3

Logic 1 Voltage (IOH = 800 μA) Full 1.7/3.1 1.7/3.1 V Logic 0 Voltage (IOL = 50 μA) Full 0.3 0.3 V

DIGITAL OUTPUTS (D0+ to D15+, D0− to

D15−, DCO+, DCO−, OR+, OR−) Logic Compliance LVDS LVDS Differential Output Voltage (VOD) Full 247 545 247 545 mV Output Offset Voltage (VOS) Full 1.125 1.375 1.125 1.375 V Output Coding (Default)

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

This is specified for LVDS and LVPECL only.

3

This depends on if SPIVDD is tied to a 1.8 V or 3.3 V supply.

Offset binary Offset binary

Rev. C | Page 6 of 32

Data Sheet AD9467

SWITCHING SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted.

Table 4.

AD9467BCPZ-200 AD9467BCPZ-250 Parameter1 Temp Min Typ Max Min Typ Max Unit

CLOCK2

Clock Rate Full 50 200 50 250 MSPS

Clock Pulse Width High (tCH) Full 2.5 2 ns

Clock Pulse Width Low (tCL) Full 2.5 2 ns

OUTPUT PARAMETERS

Propagation Delay (tPD) 25°C 3 3 ns

Rise Time (tR) (20% to 80%) 25°C 200 200 ps

Fall Time (tF) (20% to 80%) 25°C 200 200 ps

DCO Propagation Delay (t

DCO to Data Delay (t

Wake-Up Time (Power-Down) Full 100 100 ms

Pipeline Latency Full 16 16 Clock cycles

APERTURE

Aperture Delay (tA) 25°C 1.2 1.2 ns

Aperture Uncertainty (Jitter) 25°C 60 60 fs rms

Out-of-Range Recovery Time 25°C 1 1 Clock cycles

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

Can be adjusted via the SPI interface.

3

Measurements were made using a part soldered to FR-4 material.

Timing Diagrams

D14–/D15– (MSB)

D14+/D15+ (MS B)

2, 3

SKEW

VIN±

CLK+

CLK–

DCO+

DCO–

. . .

D0–/D1– (MSB)

D0+/D1+ (MSB)

) 25°C 3 3 ns

CPD

) Full −200 +200 −200 +200 ps

N – 1

t

CHtCL

D15 D14 D15 D14 D15 D14 D15 D14 D15 D14 D15 D14

D1 D0 D1 D0 D1 D0 D1 D0 D1 D0 D1 D0

t

A

N

1/fs

t

CPD

t t

N + 1

SKEW

PD

N + 2

N + 3

Figure 2. 16-Bit Output Data Timing

N + 4

N + 5

09029-002

Rev. C | Page 7 of 32

AD9467 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter

Electrical

AVDD1, AVDD3 AGND −0.3 V to +2.0 V AVDD2, SPIVDD AGND −0.3 V to +3.9 V DRVDD DRGND −0.3 V to +2.0 V AGND DRGND −0.3 V to +0.3 V AVDD2, SPIVDD AVDD1,

AVDD1, AVDD3 DRVDD −2.0 V to +2.0 V AVDD2, SPIVDD DRVDD −2.0 V to +3.9 V Digital Outputs (Dx+,

Dx−, OR+, OR−, DCO+, DCO−)

CLK+, CLK− AGND −0.3 V to AVDD1 + 0.2 V VIN+, VIN− AGND −0.3 V to +0.3 V XVREF AGND −0.3 V to AVDD1 + 0.2 V SCLK, CSB, SDIO AGND −0.3 V to SPIVDD + 0.2 V

Environmental

Operating Temperature

Range (Ambient)

Maximum Junction

Temperature

Lead Temperature

(Soldering, 10 sec)

Storage Temperature

Range (Ambient)

With Respect To Rating

−2.0 V to +3.9 V

AVDD3

DRGND −0.3 V to DRVDD + 0.2 V

−40°C to +85°C

150°C

300°C

−65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL IMPEDANCE

Table 6.

Air Flow Velocity (m/sec) θ

0.0 15.7°C/W 7.5°C/W 0.5° °C/W

1.0 13.7°C/W N/A N/A °C/W

2.5 12.3°C/W N/A N/A °C/W

1

Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per JEDEC JESD51-8 (still air).

4

N/A = not applicable.

5

Per MIL-STD 883, Method 1012.1.

1, 2

θ

JA

JB

1, 3, 4

1, 5

θ

JC

Unit

ESD CAUTION

Rev. C | Page 8 of 32

Data Sheet AD9467

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD1

AVDD2

VIN–

VIN+

AVDD2

AVDD1

XVREF

AVDD1

AVDD1 AVDD1 AVDD1 AVDD1

CLK+

CLK– AVDD1 AVDD1 AVDD1

AGND AVDD1 AVDD1 AVDD1

AGND AVDD1

AGND

7271706968676665646362616059585756

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17DRGND 18DRVDD

PIN 1 INDICATOR

AD9467

TOP VIEW

(Not to Scale)

55

54

AVDD1

53

AVDD1 AVDD1

52

SPIVDD

51 50

CSB SCLK

49

SDIO

48

DNC

47 46

AVDD1 AGND

45

AVDD3

44

AGND

43 42

AVDD3

41

AGND OR+

40

OR–

39 38

DRGND DRVDD

37

192021222324252627282930313233

DCO–

D1–/D0–

D3–/D2–

D5–/D4–

D1+/D0+

NOTES

1. DNC = DO NO T CONNECT.

2. EXPOSED THERMAL PAD MUST BE CONNECT ED TO AGND.

D3+/D2+

D5+/D4+

DCO+

D7–/D6–

D9–/D8–

D7+/D6+

D9+/D8+

34

35D15–/D14–

36D15+/D14+

D11–/D10–

D13–/D12–

D11+/D10+

D13+/D12+

09029-003

Figure 3. Pin Configuration, Top View

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

0 EPAD Exposed Paddle. The exposed paddle must be connected to AGND. 10, 14, 16, 41, 43, 45 AGND Analog Ground. 1, 2, 3, 4, 7, 8, 9, 11, 12, 13, 15, 46, 52, 53, 54, 55,

AVDD1 1.8 V Analog Supply.

56, 58, 59, 60, 61, 62, 63, 70, 71, 72 64, 65, 68, 69 AVDD2 3.3 V Analog Supply. 42, 44 AVDD3 1.8 V Analog Supply. 51 SPIVDD 1.8 V or 3.3 V SPI Supply 17, 38 DRGND Digital Output Driver Ground. 18, 37 DRVDD 1.8 V Digital Output Driver Supply. 67 VIN− Analog Input Complement. 66 VIN+ Analog Input True. 6 CLK− Clock Input Complement. 5 CLK+ Clock Input True. 19 D1−/D0− D1 and D0 (LSB) Digital Output Complement. 20 D1+/D0+ D1 and D0 (LSB) Digital Output True. 21 D3−/D2− D3 and D2 Digital Output Complement. 22 D3+/D2+ D3 and D2 Digital Output True. 23 D5−/D4− D5 and D4 Digital Output Complement. 24 D5+/D4+ D5 and D4 Digital Output True. 25 D7−/D6− D7 and D6 Digital Output Complement. 26 D7+/D6+ D7 and D6 Digital Output True. 29 D9−/D8− D9 and D8 Digital Output Complement. 30 D9+/D8+ D9 and D8 Digital Output True. 31 D11−/D10− D11 and D10 Digital Output Complement. 32 D11+/D10+ D11 and D10 Digital Output True. 33 D13−/D12− D13 and D12 Digital Output Complement. 34 D13+/D12+ D13 and D12 Digital Output True. 35 D15−/D14− D15 (MSB) and D14 Digital Output Complement.

Rev. C | Page 9 of 32

AD9467 Data Sheet

Pin No. Mnemonic Description

36 D15+/D14+ D15 (MSB) and D14 Digital Output True. 27 DCO− Data Clock Digital Output Complement. 28 DCO+ Data Clock Digital Output True. 39 OR− Out-of-Range Digital Output Complement. 40 OR+ Out-of-Range Digital Output True. 47 DNC Do Not Connect (Leave Pin Floating). 48 SDIO Serial Data Input/Output. 49 SCLK Serial Clock. 50 CSB Chip Select Bar. 57 XVREF External VREF Option.

Rev. C | Page 10 of 32

ANALOG DEVICES AD9467 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL IMPEDANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS