Analog Devices AD9460 Service Manual

A

A

16-Bit, 80 MSPS/105 MSPS ADC

FEATURES

105 MSPS guaranteed sampling rate (AD9460-105)

79.4 dBFS SNR/91 dBc SFDR with 10 MHz input
(3.4 V p-p input, 80 MSPS)

78.3 dBFS SNR/ with 170 MHz input
(4.0 V p-p input, 80 MSPS)

77.8 dBFS SNR/87 dBc SFDR with 170 MHz input
(3.4 V p-p input, 80 MSPS)

77.2 dBFS SNR/84 dBc SFDR with 170 MHz input
(3.4 V p-p input, 105 MSPS)

90 dBFS two-tone SFDR with 139 MHz/140 MHz input

(3.4 V p-p input, 105 MSPS)

60 fsec rms jitter
Excellent linearity

DNL = ±0.5 LSB typical
INL = ±3.0 LSB typical

2.0 V p-p to 4.0 V p-p differential full-scale input

Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output data capture clock available

3.3 V and 5 V supply operation

APPLICATIONS

MRI receivers
Multicarrier, multimode, cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Communications instrumentation

AD9460

FUNCTIONAL BLOCK DIAGRAM

GND DRGND DRVDD

VDD1AVDD2

2

32

2

DFS

DCS MODE

OUTPUT MODE

OR

D15 TO D0

DCO

AD9460

VIN+

VIN–

CLK+

CLK–

BUFFER

CLOCK

AND TIMI NG

MANAGEMENT

T/H

VREF

PIPELINE

ADC

REF

Figure 1.

16

CMOS

OR

LVDS

OUTPUT

STAGING

REFBSENSE REFT

Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
and output data mode.

The AD9460 is available in a Pb-free, 100-lead, surface-mount,
plastic package (TQFP_EP) specified over the industrial tem­perature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. True 16-bit linearity.

06006-001

GENERAL DESCRIPTION

The AD9460 is a 16-bit, monolithic, sampling, analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit. It is
optimized for performance, small size, and ease of use. The
AD9460 operates up to 105 MSPS, providing a superior signal­to-noise ratio (SNR) for instrumentation, medical imaging, and

2. High performance: outstanding SNR performance for

baseband IFs in data acquisition, instrumentation,
magnetic resonance imaging, and radar receivers.

3. Ease of use: on-chip reference and high input impedance,

track-and-hold with adjustable analog input range, and an
output clock simplifies data capture.

radar receivers using baseband (<100 MHz) and IF frequencies.

The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for

4. Packaged in a Pb-free, 100-lead TQFP/EP.

5. Clock duty cycle stabilizer (DCS) maintains overall ADC

performance over a wide range of clock pulse widths.
many applications. Data outputs are CMOS or LVDS compatible
(ANSI-644 compatible) and include the means to reduce the
overall current needed for short trace distances.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

6. Out-of-range (OR) outputs indicate when the signal is

beyond the selected input range.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD9460

TABLE OF CONTENTS

Features.............................................................................................. 1

Pin Configurations and Function Descriptions............................8

Functional Block Diagram .............................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications.............................................................. 5

Timing Diagrams.......................................................................... 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Equivalent Circuits......................................................................... 12

Typical Performance Characteristics........................................... 13

Terminology.................................................................................... 19

Theory of Operation ...................................................................... 20

Analog Input and Reference Overview ................................... 20

Clock Input Considerations...................................................... 21

Power Considerations................................................................ 22

Digital Outputs........................................................................... 23

Timing ......................................................................................... 23

Operational Mode Selection ..................................................... 23

Evaluation Board............................................................................ 24

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

REVISION HISTORY

7/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD9460

SPECIFICATIONS

DC SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.4 V p-p differential input, internal
trimmed reference (1.0 V mode), analog input amplitude = −1.0 dBFS, DCS = AGND (on), SFDR = AGND, unless otherwise noted.

Table 1.

AD9460BSVZ-80 AD9460BSVZ-105
Parameter Te mp Min Typ Max Min Typ Max Unit

RESOLUTION Full 16 16 Bits
ACCURACY

No Missing Codes Full Guaranteed Guaranteed
Offset Error Full −5.0 ±0.1 +5.0 −5.0 ±0.1 +5.0 mV
Gain Error 25°C −3 ±0.5 +3 −3 ±0.5 +3 % FSR
Full −3.4 +3.4 −3.4 +3.4 % FSR
Differential Nonlinearity (DNL)
Full −0.9 +0.9 −1 +1.2
Integral Nonlinearity (INL)1 25°C −6 ±3 +6 −6 ±3 +6 LSB

VOLTAGE REFERENCE

Output Voltage VREF = 1.7 V Full 1.7 1.7 V
Load Regulation @ 1.0 mA Full ±2 ±2 mV

Reference Input Current (External VREF = 1.7 V) Full 350 350 µA
INPUT REFERRED NOISE 25°C 2.4 2.5 LSB rms
ANALOG INPUT

Input Span

VREF = 1.7 V Full 3.4 3.4 V p-p

VREF = 1.0 V Full 2.0 2.0 V p-p
Internal Input Common-Mode Voltage Full 3.5 3.5 V
External Input Common-Mode Voltage Full 3.2
Input Resistance
Input Capacitance

2

2

POWER SUPPLIES

Supply Voltages

AVDD1 Full 3.14 3.3 3.46 3.14 3.3 3.46 V

AVDD2 Full 4.75 5.0 5.25 4.75 5.0 5.25 V

DRVDD—LVDS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 V

DRVDD—CMOS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 V
Supply Currents

1

AVDD1 Full 290 310 337 373 mA

1, 3

AVDD2

1

I

—LVDS Outputs Full 70 78.5 71 81 mA

DRVDD

1

I

—CMOS Outputs Full 14 14 mA

DRVDD

PSRR

Offset Full 1 1 mV/V

Gain Full 0.2 0.2 %/V

POWER CONSUMPTION

3

LVDS Outputs Full 1.7 1.8
CMOS Outputs (DC Input) Full 1.5

1

Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and

approximately 5 pF loading on each output bit for CMOS output mode.

2

Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.

3

For SFDR = AVDD1, I

power increases by ~70 mW for the AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105.

AVDD2

1

25°C −0.8 ±0.5 +0.8 −0.85 ±0.5 +0.85 LSB

3.9 3.2

3.9 V
Full 1 1 kΩ
Full 6 6 pF

Full 101 110 116 133 mA

1.9

1.7

2.2 W

W

Rev. 0 | Page 3 of 32

AD9460

AC SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 3.4 V p-p differential input, internal
trimmed reference (1.7 V mode), A

Table 2.

Parameter Temp

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 10 MHz 25°C 77.6 78.4 77.2 78.1 dB
Full 77.4 76.9
fIN = 170 MHz 25°C 76.1 76.8 75.0 76.2 dB
Full 75.0 74.5
fIN = 225 MHz 25°C 75.7 75.2 dB

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 10 MHz 25°C 76.1 78.0 75.2 77.4 dB
Full 74.4 74.5
fIN = 170 MHz 25°C 74.0 76.1 72.0 75.1 dB
Full 72.1 71.2
fIN = 225 MHz 25°C 74.6 73.6 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 10 MHz 25°C 12.8 12.7 bits
fIN = 170 MHz 25°C 12.5 12.4 bits
fIN = 225 MHz 25°C 12.3 12.1 bits

SPURIOUS-FREE DYNAMIC RANGE (SFDR, SECOND

OR THIRD HARMONIC)
fIN = 10 MHz 25°C 80 91 80 88 dBc
Full 78 76
fIN = 170 MHz 25°C 80 87 78 84 dBc
Full 78 74
fIN = 225 MHz 25°C 82 81 dBc

WORST SPUR EXCLUDING SECOND OR

THIRD HARMONICS
fIN = 10 MHz 25°C 94 100 92 98 dBc
Full 91 91
fIN = 170 MHz 25°C 90 98 89 98 dBc
Full 88 85
fIN = 225 MHz 25°C 97 92 dBc

TWO-TONE SFDR

fIN = 139.6 MHz @ −7 dBFS, 140.6 MHz @ −7 dBFS 25°C 89 90 dBFS

ANALOG BANDWIDTH Full 615 615 MHz

= −1.0 dBFS, DCS = AGND (on), SFDR = AGND, unless otherwise noted.

IN

AD9460BSVZ-80 AD9460BSVZ-105

Min Typ Max Min Typ Max Unit

Rev. 0 | Page 4 of 32

AD9460

DIGITAL SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, R

Table 3.

AD9460BSVZ-80/105
Parameter Te mp Min Typ Max Unit

CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)

High Level Input Voltage Full 2.0 V
Low Level Input Voltage Full 0.8 V
High Level Input Current Full 200 µA
Low Level Input Current Full −10
Input Capacitance Full

DIGITAL OUTPUT BITS—CMOS MODE (D0 to D15, OTR)

DRVDD = 3.3 V

High Level Output Voltage Full 3.25
Low Level Output Voltage Full

DIGITAL OUTPUT BITS—LVDS MODE (D0 to D15, OTR)

VOD Differential Output Voltage

2

VOS Output Offset Voltage Full 1.125

CLOCK INPUTS (CLK+, CLK−)

Differential Input Voltage Full 0.2
Common-Mode Voltage Full 1.3 1.5 1.6 V
Input Resistance Full 1.1 1.4 1.7 kΩ
Input Capacitance Full

1

Output voltage levels measured with 5 pF load on each output.

2

LVDS R

= 100 Ω.

TERM

= 3.74 kΩ, unless otherwise noted.

LVD S_ BI AS

1

Full 247

2

+10 µA

0.2 V

2

545 mV

1.375 V

pF

V

V

pF

SWITCHING SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.

Table 4.

AD9460BSVZ-80 AD9460BSVZ-105
Parameter Te mp Min Typ Max Min Typ Max Unit

CLOCK INPUT PARAMETERS

Maximum Conversion Rate Full 80 105 MSPS
Minimum Conversion Rate Full 1 1 MSPS
CLK Period Full 12.5 9.5 ns
CLK Pulse Width High1 (t
CLK Pulse Width Low1 (t

DATA OUTPUT PARAMETERS

Output Propagation Delay—CMOS (tPD)2 (Dx, DCO+) Full 3.35 3.35 ns
Output Propagation Delay—LVDS (tPD)3 (Dx+), (t
Pipeline Delay (Latency) Full 13 13 cycles
Aperture Delay (tA) Full ns
Aperture Uncertainty (Jitter, tJ) Full 60 60 fs, rms

1

With duty cycle stabilizer (DCS) enabled.

2

Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.

3

LVDS R

= 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.

TERM

) Full 5.0 3.8 ns

CLKH

) Full 5.0 3.8 ns

CLKL

)3 (DCO+) Full 2.3 3.6 4.8 2.3 3.6 4.8 ns

CPD

Rev. 0 | Page 5 of 32

AD9460

TIMING DIAGRAMS

VIN

CLK+

CLK–

N – 1

t

CLKH

t

CLKL

N

N + 1

f

1/

S

t

PD

N + 13

N + 14

N + 15

DCO+

DCO–

VIN

CLK–

CLK+

DCO+

DCO–

N – 12

13 CLOCK CYCLES

t

N – 13

CPD

Dx

N

N + 1

06006-002

Figure 2. LVDS Mode Timing Diagram

N – 1

t

CLKH

Dx

N

N + 1

t

CLKL

t

PD

N – 13 N – 12 N – 1 N

N + 2

13 CLOCK CYCLES

06006-003

Figure 3. CMOS Timing Diagram

Rev. 0 | Page 6 of 32

AD9460

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

ELECTRICAL

AVDD1 to AGND −0.3 V to +4 V
AVDD2 to AGND −0.3 V to +6 V
DRVDD to DGND −0.3 V to +4 V
AGND to DGND −0.3 V to +0.3 V
AVDD1 to DRVDD −4 V to +4 V
AVDD2 to DRVDD −4 V to +6 V
AVDD2 to AVDD1 −4 V to +6 V
D0± Through D15± to DGND −0.3 V to DRVDD + 0.3 V
CLK+/CLK− to AGND −0.3 V to AVDD1 + 0.3 V
OUTPUT MODE, DCS MODE, and

−0.3 V to AVDD1 + 0.3 V

DFS to AGND
VIN+, VIN− to AGND −0.3 V to AVDD2 + 0.3 V
VREF to AGND −0.3 V to AVDD1 + 0.3 V
SENSE to AGND −0.3 V to AVDD1 + 0.3 V
REFT, REFB to AGND −0.3 V to AVDD1 + 0.3 V

ENVIRONMENTAL

Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

The heat sink of the AD9460 package must be soldered to
ground.

Airflow increases heat dissipation, effectively reducing θ
more metal directly in contact with the package leads from
metal traces through holes, ground, and power planes reduces
the θ

. It is required that the exposed heat sink be soldered to

JA

the ground plane.

Table 6.

Package Type θ

1

JA

2

θ

JB

3

θ

JC

100-Lead TQFP_EP 19.8 8.3 2 °C/W

1

Typical θJA = 19.8°C/W (heat sink soldered) for a multilayer board in still air.

2

Typical θJB = 8.3°C/W (heat sink soldered) for a multilayer board in still air.

3

Typical θJC = 2°C/W (junction to exposed heat sink) represents the thermal

resistance through heat sink path

. Also,

JA

Unit

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 7 of 32

AD9460

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SFDR99AGND98AGND97AVDD196AVDD195AVDD194AVDD193AVDD192AVDD191AGND90OR+89OR–88DRVDD87DRGND86D15+ (MSB)85D15–84D14+83D14–82D13+81D13–80D12+79D12–78D11+77D11–76DRVDD

100

75

DRGND

74

D10+

73

D10–

72

D9+

71

D9–

70

D8+

69

D8–

68

DCO+

67

DCO–

66

D7+

65

D7–

64

DRVDD

63

DRGND

62

D6+

61

D6–

60

D5+

59

D5–

58

D4+

57

D4–

56

D3+

55

D3–

54

D2+

53

D2–

52

D1+

51

D1–

49

50

D0+

D0– (LSB)

06006-004

DNC

DFS

AVDD1

SENSE

VREF

AGND

REFT

REFB

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD1

AVDD1

AVDD1

AGND

VIN+

VIN–

AGND

AVDD2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

DCS MODE

OUTPUT MODE

LVDS_BIAS

DNC = DO NOT CONNECT

PIN 1

AD9460

LVDS MODE

TOP VIEW

(Not to Scale)

26

AVDD227AVDD228AVDD229AVDD230AVDD231AVDD232AVDD133AVDD134AVDD135AVDD236AVDD137AVDD238AVDD1

39

40

41

42

43

46

47

48

CLK–

CLK+

AGND

AGND

AVDD144AVDD145AVDD1

AGND

DRVDD

DRGND

Figure 4. 100-Lead TQFP_EP Pin Configuration in LVDS Mode

Table 7. Pin Function Descriptions—100-Lead TQFP_EP in LVDS Mode

Pin No. Mnemonic Description

1 DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible.
DCS = low (AGND) to enable DCS (recommended).
DCS = high (AVDD1) to disable DCS.
2 DNC Do Not Connect. This pin should float.
3 OUTPUT MODE CMOS-Compatible Output Logic Mode Control Pin.
OUTPUT MODE = 0 for CMOS mode.
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data.
DFS = high (AVDD1) for twos complement
DFS = low (ground) for offset binary format.
5 LVDS_BIAS Set Pin for LVDS Output Current. Place a 3.7 kΩ resistor terminated to DRGND.
6, 18 to 20, 32 to 34, 36, 38,

AVDD1 3.3 V (±5%) Analog Supply.

43 to 45, 92 to 97
7 SENSE

Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog
input range); connect to AVDD1 for external reference.

8 VREF

1.7 V Reference I/O. The function is dependent on the SENSE pin and external
programming resistors. Decouple to ground with 0.1 µF and 10 µF capacitors.

9, 21, 24, 39, 42, 46, 91, 98,
99, Exposed Heat Sink

AGND

Analog Ground. The exposed heat sink on the bottom of the package must be connected
to AGND.

Rev. 0 | Page 8 of 32

AD9460

Pin No. Mnemonic Description

10 REFT

11 REFB

12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (±5%).
22 VIN+ Analog Input—True.
23 VIN− Analog Input—Complement.
40 CLK+ Clock Input—True.
41 CLK− Clock Input—Complement.
47, 63, 75, 87 DRGND Digital Output Ground.
48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).
49 D0− (LSB) D0 Complement Output Bit (LVDS Levels).
50 D0+ D0 True Output Bit.
51 D1− D1 Complement Output Bit.
52 D1+ D1 True Output Bit.
53 D2− D2 Complement Output Bit.
54 D2+ D2 True Output Bit.
55 D3− D3 Complement Output Bit.
56 D3+ D3 True Output Bit.
57 D4− D4 Complement Output Bit.
58 D4+ D4 True Output Bit.
59 D5− D5 Complement Output Bit.
60 D5+ D5 True Output Bit.
61 D6− D6 Complement Output Bit.
62 D6+ D6 True Output Bit.
65 D7− D7 Complement Output Bit.
66 D7+ D7 True Output Bit.
67 DCO− Data Clock Output—Complement.
68 DCO+ Data Clock Output—True.
69 D8− D8 Complement Output Bit.
70 D8+ D8 True Output Bit.
71 D9− D9 Complement Output Bit.
72 D9+ D9 True Output Bit.
73 D10− D10 Complement Output Bit.
74 D10+ D10 True Output Bit.
77 D11− D11 Complement Output Bit.
78 D11+ D11 True Output Bit.
79 D12− D12 Complement Output Bit.
80 D12+ D12 True Output Bit.
81 D13− D13 Complement Output Bit.
82 D13+ D13 True Output Bit.
83 D14− D14 Complement Output Bit.
84 D14+ D14 True Output Bit.
85 D15− D15 Complement Output Bit.
86 D15+ (MSB) D15 True Output Bit.
89 OR− Out-of-Range Complement Output Bit.
90 OR+ Out-of-Range True Output Bit.
100 SFDR

Differential Reference Output. Decoupled to ground with 0.1 µF capacitor and to REFB
(Pin 11) with 0.1 µF and 10 µF capacitors.

Differential Reference Output. Decoupled to ground with a 0.1 µF capacitor and to REFT
(Pin 10) with 0.1 µF and 10 µF capacitors.

SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the
AD9460 analog front end. Connecting SFDR to AGND optimizes SFDR performance for
applications with analog input frequencies <200 MHz for 80 MSPS and 105 MSPS speed
grades. For applications with analog inputs >200 MHz, connect this pin to AVDD1 for
optimum SFDR performance; power dissipation from AVDD2 increases by ~70 mW for the
AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105.

Rev. 0 | Page 9 of 32

AD9460

SFDR99AGND98AGND97AVDD196AVDD195AVDD194AVDD193AVDD192AVDD191AGND90OR+89D15+ (MSB)88DRVDD87DRGND86D14+85D13+84D12+83D11+82D10+81D9+80D8+79D7+78D6+77D5+76DRVDD

100

49

DNC50DNC

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DRGND

D4+

D3+

D2+

D1+

D0+ (LSB )

DNC

DCO+

DCO–

DNC

DNC

DRVDD

DRGND

DNC

DNC

DNC

DNC

DNC

DNC

DNC

DNC

DNC

DNC

DNC

DNC

06006-005

DNC

DFS

AVDD1

SENSE

VREF

AGND

REFT

REFB

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD1

AVDD1

AVDD1

AGND

VIN+

VIN–

AGND

AVDD2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

DCS MODE

OUTPUT MODE

LVDS_BIAS

DNC = DO NOT CONNE CT

PIN 1

AD9460

CMOS MODE

TOP VIEW

(Not to Scale)

26

AVDD227AVDD228AVDD229AVDD230AVDD231AVDD232AVDD133AVDD134AVDD135AVDD236AVDD137AVDD238AVDD1

39

40

41

42

43

46

47

48

CLK–

CLK+

AGND

AGND

AVDD144AVDD145AVDD1

AGND

DRGND

DRVDD

Figure 5. 100-Lead TQFP_EP Pin Configuration in CMOS Mode

Table 8. Pin Function Descriptions—100-Lead TQFP_EP in CMOS Mode

Pin No. Mnemonic Description

1 DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible.
DCS = low (AGND) to enable DCS (recommended).
DCS = high (AVDD1) to disable DCS.
2, 49 to 62, 65 to 66, 69 DNC Do Not Connect. These pins should float.
3 OUTPUT MODE CMOS-Compatible Output Logic Mode Control Pin.
OUTPUT MODE = 0 for CMOS mode.
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data.
DFS = high (AVDD1) for twos complement.
DFS = low (ground) for offset binary format.
5 LVDS_BIAS Set Pin for LVDS Output Current. Place a 3.7 kΩ resistor terminated to DRGND.
6, 18 to 20, 32 to 34, 36,

AVDD1 3.3 V (±5%) Analog Supply.

38, 43 to 45, 92 to 97
7 SENSE

Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog
input range); connect to AVDD1 for external reference.

8 VREF

1.7 V Reference I/O. The function is dependent on the SENSE pin and external programming
resistors. Decouple to ground with 0.1 µF and 10 µF capacitors.

9, 21, 24, 39, 42, 46, 91, 98,
99, Exposed Heat Sink

10 REFT

AGND

Analog Ground. The exposed heat sink on the bottom of the package must be connected
to AGND.

Differential Reference Output. Decoupled to ground with 0.1 µF capacitor and to REFB (Pin

11) with 0.1 µF and 10 µF capacitors.

Rev. 0 | Page 10 of 32

AD9460

Pin No. Mnemonic Description

11 REFB

12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (±5%).
22 VIN+ Analog Input—True.
23 VIN− Analog Input—Complement.
40 CLK+ Clock Input—True.
41 CLK− Clock Input—Complement.
47, 63, 75, 87 DRGND Digital Output Ground.
48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).
67 DCO− Data Clock Output—Complement.
68 DCO+ Data Clock Output—True.
70 D0+ (LSB) D0 True Output Bit (CMOS Levels).
71 D1+ D1 True Output Bit.
72 D2+ D2 True Output Bit.
73 D3+ D3 True Output Bit.
74 D4+ D4 True Output Bit.
77 D5+ D5 True Output Bit.
78 D6+ D6 True Output Bit.
79 D7+ D7 True Output Bit.
80 D8+ D8 True Output Bit.
81 D9+ D9 True Output Bit.
82 D10+ D10 True Output Bit.
83 D11+ D11 True Output Bit.
84 D12+ D12 True Output Bit.
85 D13+ D13 True Output Bit.
86 D14+ D14 True Output Bit.
89 D15+ (MSB) D15 True Output Bit.
90 OR+ Out-of-Range True Output Bit.
100 SFDR

Differential Reference Output. Decoupled to ground with a 0.1 µF capacitor and to REFT (Pin

10) with 0.1 µF and 10 µF capacitors.

SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the
AD9460 analog front end. Connecting SFDR to AGND optimizes SFDR performance for
applications with analog input frequencies <200 MHz for 80 MSPS and 105 MSPS speed
grades. For applications with analog inputs >200 MHz, connect this pin to AVDD1 for
optimum SFDR performance; power dissipation from AVDD2 increases by ~70 mW for the
AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105.

Rev. 0 | Page 11 of 32

AD9460

V

A

EQUIVALENT CIRCUITS

AVDD2

DRVDD

VIN+

VIN–

3.5V

6pF

6pF

X1

AVDD2

1kΩ

1kΩ

Figure 6. Equivalent Analog Input Circuit

DRVDD DRVDD

1.2V

LVDS_BIAS

3.74kΩ

Figure 7. Equivalent LVDS_BIAS Circuit

T/H

I

LVDSOUT

Dx

06006-009

06006-006

Figure 9. Equivalent CMOS Digital Output Circuit

DD

K

DCS MODE,

OUTPUT MODE,

06006-007

DFS

30kΩ

06006-010

Figure 10. Equivalent Digital Input Circuit, DFS, DCS MODE, OUTPUT MODE

DRVDD

V

Dx– Dx+

V

V

V

06006-008

Figure 8. Equivalent LVDS Digital Output Circuit

CLK+

Ω

2.5k

Figure 11. Equivalent Sample Clock Input Circuit

VDD1

3kΩ3kΩ

CLK–

2.5kΩ

06006-011

Rev. 0 | Page 12 of 32

AD9460

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, rated sample rate, LVDS mode, DCS enabled, TA = 25°C, 3.4 V p-p differential input,
AIN = −1 dBFS, internal trimmed reference (nominal VREF = 1.7 V), unless otherwise noted.

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE ( dBFS)

–90

–100

–110

–120

–130

0 52. 500

13.125 26.250 39.375

FREQUENCY (MHz )

105MSPS

10.3MHz @ –1.0dBFS
SNR = 78.1dB
ENOB = 12.9 BI TS
SFDR = 88dBc

Figure 12. 105 MSPS, 64k Point, Single-Tone FFT, 10.3 MHz

06006-012

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE ( dBFS)

–90

–100

–110

–120

–130

0 52. 500

13.125 26.250 39.375

FREQUENCY (MHz )

105MSPS

225.3MHz @ –1.0d BFS
SNR = 75.2dB
ENOB = 12.6 BITS
SFDR = 81dBc

Figure 15. 105 MSPS, 64k Point, Single-Tone FFT, 225.3 MHz

06006-051

0

105MSPS

–10

170.3MHz @ –1.0d BFS
SNR = 76.2dB

–20

ENOB = 12.6 BI TS
SFDR = 84dBc

–30

–40

–50

–60

–70

–80

AMPLITUDE ( dBFS)

–90

–100

–110

–120

–130

0 52. 500

13.125 26.250 39.375

FREQUENCY (MHz )

Figure 13. 105 MSPS, 64k Point, Single-Tone FFT, 170.3 MHz

0

105MSPS

–10

70.3MHz @ –1.0d BFS
SNR = 77.8dB

–20

ENOB = 12.6 BITS
SFDR = 86dBc

–30

–40

–50

–60

–70

–80

AMPLITUDE ( dBFS)

–90

–100

–110

–120

–130

0 52. 500

13.125 26.250 39.375

FREQUENCY (MHz )

Figure 14. 105 MSPS, 64k Point, Single-Tone FFT, 70.3 MHz

0.6

0.4

0.2

0

DNL (MSB)

–0.2

–0.4

–0.6

0 65536

8192 16384 24576 32768 40960 49152 57344

06006-050

OUTPUT CODE

06006-016

Figure 16. 105 MSPS, DNL Error vs. Output Code, 10.3 MHz

4

3

2

1

0

INL (MSB)

–1

–2

–3

–4

8192 16384 24576 32768 40960 49152 57344

0 65536

06006-014

OUTPUT CODE

06006-017

Figure 17. 105 MSPS, INL Error vs. Output Code, 10.3 MHz

Rev. 0 | Page 13 of 32

AD9460

AMPLITUDE ( dBFS)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

0

0

12.5 25.0 37.5

FREQUENCY (MHz )

80MSPS

10.3MHz @ –1.0dBFS
SNR = 78.4dB
ENOB = 12.9 BITS
SFDR = 91dBc

Figure 18. 80 MSPS, 64k Point Single-Tone FFT, 10.3 MHz

AMPLITUDE ( dBFS)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

0

0

12.5 25.0 37.5

FREQUENCY (MHz )

80MSPS

170.3MHz @ –1.0d BFS
SNR = 76.8dB
ENOB = 12.5 BITS
SFDR = 87dBc

Figure 19. 80 MSPS, 64k Point, Single-Tone FFT, 170.3 MHz

06006-018

06006-019

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE ( dBFS)

–90

–100

–110

–120

–130

04

10 20 30

FREQUENCY (MHz )

80MSPS

225.3MHz @ –1.0d BFS
SNR = 75.7dB
ENOB = 12.6 BI TS
SFDR = 82dBc

0

06006-052

Figure 21. 80 MSPS, 64k Point Single-Tone FFT, 225.3 MHz

0.6

0.4

0.2

0

DNL (MSB)

–0.2

–0.4

–0.6

0 65536

8192 16384 24576 32768 40960 49152 57344

OUTPUT CODE

06006-022

Figure 22. 80 MSPS, DNL Error vs. Output Code, 10.3 MHz

AMPLITUDE ( dBFS)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

0

0

12.5 25.0 37.5

FREQUENCY (MHz )

80MSPS

70.3MHz @ –1.0dBFS
SNR = 77.8dB
ENOB = 12.5 BITS
SFDR = 86dBc

Figure 20. 80 MSPS, 64k Point, Single-Tone FFT, 70.3 MHz

06006-020

Rev. 0 | Page 14 of 32

4

3

2

1

0

INL (MSB)

–1

–2

–3

–4

8192 16384 24576 32768 40960 49152 57344

0 65536

OUTPUT CODE

Figure 23. 80 MSPS, INL Error vs. Output Code, 10.3 MHz

06006-023

AD9460

95

90

85

(dB)

80

75

70

SNR +25°C

0

SFDR +85°C

SFDR +25°C

SNR +85°C

50 100 150 200

ANALOG INPUT FREQUENCY (MHz)

SFDR –40°C

SNR –40°C

Figure 24. 105 MSPS, SNR/SFDR vs. Analog Input Frequency, 3.4 V p-p

95

SFDR +85°C

90

SFDR +25°C

85

(dB)

80

SFDR –40°C

SNR –40°C

90

85

80

(dB)

75

70

65

2.9

06006-024

ANALOG INPUT COMMON-MODE VOLTAGE (V)

SFDR dBc

SNR dB

4.13 .1 3.3 3.5 3.7 3.9

06006-028

Figure 27. 105 MSPS, SNR/SFDR vs. Analog Input Common Mode

120

100

80

60

(dB)

40

SFDR dBFS

SNR dBFS

SFDR dBc

75

SNR +25°C

SNR +85°C

70

0

50 100 150 200

ANALOG INPUT FREQUENCY (MHz)

Figure 25. 105 MSPS, SNR/SFDR vs. Analog Input Frequency,

3.4 V p-p, CMOS Mode

120

SFDR dBFS

100

80

60

(dB)

40

20

0

–100

SNR dBFS

SFDR dBc

SNR dB

–90 –80 –70 –60 –50 –40 –30 –20 – 10

ANALOG INPUT AMPLITUDE (dB)

Figu re 26. 105 MSPS, 170.3 MHz SNR/S FDR vs. Anal og Input Lev el

20

SNR dB

0

–90

–80 –70 –60 –50 –40 –30 –20 –10

06006-025

ANALOG INPUT AMPLITUDE (dB)

0

06006-029

Figu re 28. 105 MSPS, 170.3 MHz SNR/ SFDR vs. Ana log Input Le vel,

CMOS Output Mode

95

90

85

(dB)

80

75

0

06006-026

70

SNR +25°C

0

SFDR +85°C

50 100 150 200

ANALOG INPUT FREQUENCY (MHz)

SFDR +25°C

SNR –40°C

SNR +85°C

SFDR –40°C

06006-030

Figure 29. 80 MSPS, SNR/SFDR vs. Analog Input Frequency,

3.4 V p-p, CMOS Mode

Rev. 0 | Page 15 of 32

AD9460

120

100

80

SFDR dBFS

SNR dBFS

120

100

SFDR dBFS

SNR dBFS

80

60

(dB)

40

SFDR dBc

20

SNR dB

0

–100

–90 –80 – 70 –60 –50 –40 –30 –20 –10

ANALOG INPUT AMPLITUDE (dB)

Figure 30. 80 MSPS, 170.3 MHz SNR/SFDR vs. Analog Input Level

95

SFDR +25°C

90

85

(dB)

80

75

70

0

SNR +25°C

SNR +85°C

SNR –40°C

50 100 150 200

ANALOG INPUT FREQUENCY (MHz)

SFDR –40°C

SFDR +85°C

Figure 31. 80 MSPS, SNR/SFDR vs. Analog Input Frequency, 3.4 V p-p

60

(dB)

40

20

0

06006-031

SFDR dBc

SNR dB

0

–90

–80 –70 –60 –50 –40 –30 –20 –10

ANALOG INPUT AMPLITUDE (dB)

0

06006-034

Figure 33. 80 MSPS, 170.3 MHz SNR/SFDR vs. Analog Input Level,

CMOS Output Mode

0

–20

–40

–60

(dBFS)

–80

–100

–120

–140

04

06006-032

10 20 30

FREQUENCY (MHz)

80MSPS

139.63MHz @ –7dBF S

140.63MHz @ –7dBF S
SFDR = 89dBFS

0

06006-035

Figure 34. 80 MSPS, 64k Point Two-Tone FFT, 139.6 MHz, 140.6 MHz

95

90

85

80

(dB)

75

70

65

2.9

ANALOG INPUT COMMON-MODE VOLTAGE (V)

SFDR dBc

SNR dB

3.1 3.3 3.5 3.7 3.9

Figure 32. 80 MSPS, SNR/SFDR vs. Analog Input Common Mode

4.1

06006-033

Rev. 0 | Page 16 of 32

0

–10

–20

–30

–40

–50

–60

WORST IMD3 dBc

–70

–80

–90

SFDR AND IMD3 (dB)

–100

–110

–120

–130

–100

–90 –80 –70 –60 –50 –40 –30 –20 –10

SFDR dBFS

ANALOG INPUT AMPLITUDE (dBFS)

SFDR dBc

WORST IMD3 dBFS

0

Figure 35. 80 MSPS, 64k Point Two-Tone FFT, 139.6 MHz, 140.6 MHz

06006-036

AD9460

0

105MSPS

139.63MHz @ –7dBF S

140.63MHz @ –7dBF S

–20

SFDR = 90dBFS

–40

–60

(dBFS)

–80

–100

–120

FREQUENCY

6000

5000

4000

3000

2000

1000

–140

0 52 .500

13.125 26.250 39.375

FREQUENCY (MHz)

Figure 36. 105 MSPS, 64k Point Two-Tone FFT, 139.6 MHz, 140.6 MHz

0

–10

–20

–30

–40

–50

–60

–70

–80

SFDR AND IMD3 (dB)

–90

–100

–110

–120

–100

SFDR dBFS

ANALOG INPUT AMPLITUDE (dBFS)

WORST IMD3 dBc

WORST IMD3 dBFS

SFDR dBc

0–90 –80 –70 –60 –50 –40 –30 –20 –10

Figure 37. 105 MSPS, Two-Tone SFDR vs. Analog Input Level,

139.6 MHz, 140.6 MHz

0

N–9

N–8

N–7

N–6

N–5

N–4

N–3

N–2

N–1

N+0

N+1

N+2

N+3

N+4

N+5

N+6

N+7

N+8

N+9

06006-040

BIN

N+10

06006-042

Figure 38. 80 MSPS, Grounded Input Histogram

6000

5000

4000

3000

FREQUENCY

2000

1000

0

N–9

N–8

N–7

N–6

N–5

N–4

N–3

N–2

N–1

N+0

N+1

N+2

N+3

N+4

N+5

N+6

N+7

N+8

06006-041

N–10

BIN

N+9

N+10

06006-045

Figure 39 105 MSPS, Grounded Input Histogram

Rev. 0 | Page 17 of 32

AD9460

0.6

0.5

0.4

0.3

0.2

0.1

0

GAIN ERROR (%FS)

–0.1

–0.2

–0.3

–0.4

–40 –20 0 20 806040

105MSPS

TEMPERATURE (° C)

Figure 40. Gain vs. Temperature

79

78

170.3MHz, 80MSPS

77

76

(dBFS)

75

170.3MHz, 105MS PS

80MSPS

06006-048

96

94

92

90

88

(dBc)

86

84

82

80

1.8

170.3MHz, 105MSPS

170.3MHz, 80M SPS

ANALOG INPUT RANGE (V p-p )

4.22.0 2 .2 2.4 2. 6 2. 8 3. 0 3.2 3. 4 3. 6 3. 8 4. 0

06006-065

Figure 42. SFDR vs. Analog Input Range

90

85

80 SFDR dBc

80

(dB)

75

80 SNR dB

105 SFDR dBc

105 SNR dB

74

73

1.8

2.0 2 .2 2.4 2. 6 2. 8 3. 0 3.2 3. 4 3. 6 3. 8 4. 0

ANALOG INPUT RANGE (V p-p )

Figure 41. SNR vs. Analog Input Range

4.2

06006-064

70

65

45

55 65 75 85 95 105 115 125 135

SAMPLE RATE (MSPS)

Figure 43. Single-Tone SNR/SFDR vs. Sample Rate, 170.3 MHz

145

06006-053

Rev. 0 | Page 18 of 32

AD9460

(

TERMINOLOGY

Analog Bandwidth (Full Power Bandwidth)

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

Two -Tone SFDR

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.

Aperture Delay (t

)

A

The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter, t

)

J

The sample-to-sample variation in aperture delay.

Clock Pulse Width and Duty Cycle

Pulse width high is the minimum amount of time that the
clock pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 16-bit resolution indicates that all 65,536
codes must be present over all operating ranges.

Integral Nonlinearity (INL)

INL is the deviation of each individual code from a line drawn
from negative full scale through positive full scale. The point
used as negative full scale occurs ½ LSB before the first code
transition. Positive full scale is defined as a level 1½ LSB beyond
the last code transition. The deviation is measured from the
middle of each particular code to the true straight line.

Signal-to-Noise and Distortion (SINAD)

SINAD is the ratio of the rms input signal amplitude to the rms
value of the sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms input signal amplitude to the rms
value of the sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of the rms signal amplitude to the rms value
of the peak spurious spectral component. The peak spurious
component may be a harmonic. SFDR can be reported in dBc (that
is, degrades as signal level is lowered) or dBFS (always related back
to converter full scale).

Total Harmonic Distortion (THD)

The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.

Effective Number of Bits (ENOB)

The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured
SINAD using the following formula:

)

SINAD

=

ENOB

1.76−

6.02

Gain Error

The first code transition should occur at an analog value of
½ LSB above negative full scale. The last transition should occur
at an analog value of 1½ LSB below the positive full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.

Maximum Conversion Rate

The clock rate at which parametric testing is performed.

Minimum Conversion Rate

The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.

Offset Error

The major carry transition should occur for an analog value of
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.

Output Propagation Delay (tPD)

The delay between the clock rising edge and the time when all
bits are within valid logic levels.

Power-Supply Rejection Ratio

The change in full scale from the value with the supply
at the minimum limit to the value with the supply at the
maximum limit.

Tem p er at u re Dr i ft

The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at T

MIN

or T

MAX

.

Rev. 0 | Page 19 of 32

AD9460

F

F

THEORY OF OPERATION

The AD9460 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated, high bandwidth
track-and-hold circuit that samples the signal prior to quantization
by the 16-bit pipeline ADC core. The device includes an on-board
reference and input logic that accepts TTL, CMOS, or LVPECL
levels. The digital output logic levels are user selectable as standard
3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT
MODE pin.

ANALOG INPUT AND REFERENCE OVERVIEW

A stable and accurate 0.5 V band gap voltage reference is built
into the AD9460. The input range can be adjusted by varying
the reference voltage applied to the AD9460, using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly.

Internal Reference Connection

A comparator within the AD9460 detects the potential at the
SENSE pin and configures the reference into three possible states,
summarized in
amplifier switch is connected to the internal resistor divider (see
Figure 44), setting VREF to ~1.7 V. If a resistor divider is
connected as shown in
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as

VREF = 0.5 V ×

In all reference configurations, REFT and REFB drive the
analog-to-digital conversion core and establish its input span.
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.

Internal Reference Trim

The internal reference voltage is trimmed during the production
test; therefore, there is little advantage to the user supplying an
external voltage reference to the AD9460. The gain trim is
performed with the AD9460 input range set to 3.4 V p-p
nominal (SENSE connected to AGND). Because of this trim,
and the maximum ac performance provided by the 3.4 V p-p
analog input range, there is little benefit to using analog input

Tabl e 9 . If SENSE is grounded, the reference

Figure 45, the switch again sets to the

R2

⎞

⎛

+

1

⎟

⎜

R1

⎠

⎝

ranges <2 V p-p. However, reducing the range can improve SFDR
performance in some applications. Likewise, increasing the
range up to 3.4 V p-p can improve SNR. Users are cautioned
that the differential nonlinearity of the ADC varies with the
reference voltage. Configurations that use <2.0 V p-p can
exhibit missing codes and, therefore, degraded noise and
distortion performance.

VIN+

10µ

10µ

VIN–

CORE

VREF

+

0.1µF

SENSE

Figure 44. Internal Reference Configuration

+

0.1µF

R2

SENSE

R1

Figure 45. Programmable Reference Configuration

VIN+

VIN–

VREF

SELECT

LOGIC

AD9460

SELECT

LOGIC

0.5V

0.5V

AD9460

ADC

ADC

CORE

REFT

0.1µF

0.1µF 10µF

REFB

0.1µF

REFT

0.1µF

0.1µF 10µF

REFB

0.1µF

+

+

06006-054

06006-055

Rev. 0 | Page 20 of 32

AD9460

A

Table 9. Reference Configuration Summary

Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p)

External Reference AVDD N/A 2 × external reference
Programmable Reference 0.2 V to VREF

Programmable Reference

0.2 V to VREF

(Set for 2 V p-p)

Internal Fixed Reference AGND to 0.2 V 1.7 3.4

R2

(See Figure 45)

+1×0.5

R1

R2

⎞

⎛

10.5

⎜
⎝

+×

⎟

R1

⎠

, R1 = R2 = 1 kΩ

2 × VREF

2.0

External Reference Operation

When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer continues to generate the positive
and negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 2.0 V. See

Figure 40 for gain variation vs. temperature.

Analog Inputs

As with most new high speed, high dynamic range ADCs, the
analog input to the AD9460 is differential. Differential inputs
improve on-chip performance because signals are processed
through attenuation and gain stages. Most of the improvement
is a result of differential analog stages having high rejection of
even-order harmonics. There are also benefits at the PCB level.
First, differential inputs have high common-mode rejection of
stray signals, such as ground and power noise. Second, they
provide good rejection of common-mode signals, such as local
oscillator feedthrough. The specified noise and distortion of the
AD9460 cannot be realized with a single-ended analog input;
therefore, such configurations are discouraged. Contact sales for
recommendations of other 16-bit ADCs that support single-ended
analog input configurations.

With the 1.7 V reference, which is the nominal value (see the
Internal Reference Trim section), the differential input range of
the AD9460 analog input is nominally 3.4 V p-p or 1.7 V p-p on
each input (VIN+ or VIN−).

VIN+

1.7V p-p

3.5V

The AD9460 analog input voltage range is offset from ground
by 3.5 V. Each analog input connects through a 1 kΩ resistor
to the 3.5 V bias voltage and to the input of a differential buffer.
The internal bias network on the input properly biases the
buffer for maximum linearity and range (see the

section). Therefore, the analog source driving the

Circuits

Equivalent

AD9460 should be ac-coupled to the input pins. The recom­mended method for driving the analog input of the AD9460 is
to use an RF transformer to convert single-ended signals to

R

T

Figure 47).

DT1–1WT

0.1µF

R

S

VIN+

AD9460

R

S

VIN–

06006-057

differential signals (see

ANALOG

INPUT

SIGNAL

Figure 47. Transformer-Coupled Analog Input Circuit

Series resistors between the output of the transformer and the
AD9460 analog inputs help isolate the analog input source from
switching transients caused by the internal sample-and-hold
circuit. The series resistors, along with the 1 kΩ resisters
connected to the internal 3.5 V bias, must be considered in
impedance matching the transformer input. For example, if R
is set to 51 Ω, R

is set to 33 Ω, and there is a 1:1 impedance ratio

S

T

transformer, then the input matches a 50 Ω source with a full­scale drive of 16.0 dBm. The 50 Ω impedance matching can also
be incorporated on the secondary side of the transformer, as
shown in the evaluation board schematic (see

Figure 50).

CLOCK INPUT CONSIDERATIONS

Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock combines with the desired signal at the analog-to­digital output. For that reason, considerable care was taken in
the design of the clock inputs of the AD9460, and the user is
advised to give careful thought to the clock source.

VIN–

Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, can be sensitive

DIGITAL OUT = ALL 1s DIGITAL OUT = ALL 0s

to the clock duty cycle. Commonly a 5% tolerance is required on
the clock duty cycle to maintain dynamic performance charac-

06006-056

Figure 46. Differential Analog Input Range for VREF = 1.7 V

Rev. 0 | Page 21 of 32

teristics. The AD9460 contains a clock duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock

AD9460

V

signal with a nominal ~50% duty cycle. Noise and distortion per­formance are nearly flat for a 30% to 70% duty cycle with the DCS
enabled. The DCS circuit locks to the rising edge of CLK+ and
optimizes timing internally. This allows for a wide range of input
duty cycles at the input without degrading performance. Jitter in
the rising edge of the input is still of paramount concern and is
not reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates of less than 30 MHz
nominally. The loop is associated with a time constant that
should be considered in applications where the clock rate can
change dynamically, requiring a wait time of 1.5 μs to 5 μs after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the time that the
loop is not locked, the DCS loop is bypassed, and the internal
device timing is dependent on the duty cycle of the input clock
signal. In such an application, it can be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.

The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the duty cycle stabilizer,
and logic high (AVDD1 = 3.3 V) disables the controller.

The AD9460 input sample clock signal must be a high quality,
extremely low phase noise source to prevent degradation of per­formance. Maintaining 16-bit accuracy places a premium on the
encode clock phase noise. SNR performance can easily degrade
by 3 dB to 4 dB with 70 MHz analog input signals when using a
high jitter clock source. See the

AN-501 Application Note,

Aperture Uncertainty and ADC System Performance, for more
information. For optimum performance, the AD9460 must be
clocked differentially. The sample clock inputs are internally
biased to ~1.5 V, and the input signal is usually ac-coupled into
the CLK+ and CLK− pins via a transformer or capacitors.
Figure 48 shows one preferred method for clocking the AD9460.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary of the transformer limit clock
excursions into the AD9460 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9460 and
limits the noise presented to the sample clock inputs.

CRYSTAL

SINE

SOURCE

Figure 48. Crystal Clock Oscillator, Differential Encode

0.1µF

ADT1–1WT

HSMS2812

DIODES

CLK+

AD9460

CLK–

6006-058

If a low jitter clock is available, it helps to band-pass filter the
clock reference before driving the ADC clock inputs. Another
option is to ac couple a differential ECL/PECL signal to the encode
input pins, as shown in

Figure 49.

T

0.1µF

ECL/

PECL

VT

Figure 49. Differential ECL for Encode

0.1µF

ENCODE

AD9460

ENCODE

06006-059

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (f
(t

) can be calculated using the following equation:

J

SNR = 20 log[2

) and rms amplitude due only to aperture jitter

INPUT

πf

× tJ]

INPUT

In the equation, the rms aperture jitter represents the root-mean­square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specification. IF undersampling
applications are particularly sensitive to jitter.

The clock input should be treated as an analog signal in cases
where aperture jitter can affect the dynamic range of the AD9460.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
synchronized by the original clock during the last step.

POWER CONSIDERATIONS

Care should be taken when selecting a power source. The use of
linear dc supplies is highly recommended. Switching supplies
tend to have radiated components that can be received by the
AD9460. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1 μF chip capacitors.

The AD9460 has separate digital and analog power supply pins.
The analog supplies are denoted AVDD1 (3.3 V) and AVDD2
(5 V), and the digital supply pins are denoted DRVDD. Although
the AVDD1 and DRVDD supplies can be tied together, best per­formance is achieved when the supplies are separate. This is
because the fast digital output swings can couple switching
current back into the analog supplies. Note that both AVDD1
and AVDD2 must be held within 5% of the specified voltage.

The DRVDD supply of the AD9460 is a dedicated supply for the
digital outputs in either LVDS or CMOS output modes. When
in LVDS mode, the DRVDD should be set to 3.3 V. In CMOS
mode, the DRVDD supply can be connected from 2.5 V to 3.6 V
for compatibility with the receiving logic.

Rev. 0 | Page 22 of 32

AD9460

DIGITAL OUTPUTS

LVDS Mode

The off-chip drivers on the chip can be configured to provide
LVDS-compatible output levels via Pin 3 (OUTPUT MODE).
LVDS outputs are available when OUTPUT MODE is CMOS
logic high (or AVDD1 for convenience) and a 3.74 kΩ R
resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic
performance, including both SFDR and SNR, maximizes when
using the AD9460 in LVDS mode; designers are encouraged to
take advantage of this mode. The AD9460 outputs include com­plementary LVDS outputs for each data bit (Dx+/Dx−), the
overrange output (OR+/OR−), and the output data clock output
(DCO+/DCO−). The R

resistor current is multiplied on-chip,

SET

setting the output current at each output equal to a nominal

3.5 mA (11 × I

). A 100 Ω differential termination resistor

RSET

placed at the LVDS receiver inputs results in a nominal 350 mV
swing at the receiver. LVDS mode facilitates interfacing with
LVDS receivers in custom ASICs and FPGAs that have LVDS
capability for superior switching performance in noisy environ­ments. Single point-to-point net topologies are recommended,
with a 100 Ω termination resistor located as close to the receiver
as possible. It is recommended to keep the trace length less than
two inches and to keep differential output trace lengths as equal
as possible.

CMOS Mode

In applications that can tolerate a slight degradation in dynamic
performance, the AD9460 output drivers can be configured to
interface with 2.5 V or 3.3 V logic families by matching
DRVDD to the digital supply of the interfaced logic. CMOS
outputs are available when OUTPUT MODE is CMOS logic
low (or AGND for convenience). In this mode, the output data
bits, Dx, are single-ended CMOS, as is the overrange output,
OR+. The output clock serves as a differential CMOS signal,
DCO+/DCO−. Lower supply voltages are recommended to
avoid coupling switching transients back to the sensitive analog
sections of the ADC. Minimize the capacitive load to the CMOS
outputs and connect each output to a single gate through a
series resistor (220 Ω) to minimize switching transients caused
by the capacitive loading.

SET

TIMING

The AD9460 provides latched data outputs with a pipeline delay
of 13 clock cycles. Data outputs are available one propagation
delay (t

) after the rising edge of CLK+. Refer to Figure 2 and

PD

Figure 3 for detailed timing diagrams.

OPERATIONAL MODE SELECTION

Data Format Select

The data format select (DFS) pin of the AD9460 determines
the coding format of the output data. This pin is 3.3 V CMOS
compatible, with logic high (or AVDD1, 3.3 V) selecting twos
complement and DFS logic low (AGND) selecting offset binary

Tabl e 1 0 summarizes the output coding.

format.

Output Mode Select

The OUPUT MODE pin controls the logic compatibility,
as well as the pinout of the digital outputs. This pin is a CMOS­compatible input. With OUTPUT MODE = 0 (AGND), the
AD9460 outputs are CMOS compatible, and the pin assignment
for the device is as defined in
(AVDD1, 3.3 V), the AD9460 outputs are LVDS compatible, and
the pin assignment for the device is as defined in

Duty Cycle Stabilizer

The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the DCS, and logic
high (AVDD1, 3.3 V) disables the controller.

SFDR Enhancement

Under certain conditions, the SFDR performance of the AD9460
improves by adding some additional power to the core of the
ADC. The SFDR control pin (Pin 100) is a CMOS-compatible
control pin to optimize the configuration of the AD9460 analog
front end. Connecting SFDR to AGND optimizes SFDR
performance for applications with analog input frequencies
<200 MHz for 80 MSPS and 105 MSPS speed grades. For
applications with analog inputs >200 MHz, this pin should be
connected to AVDD1 for optimum SFDR performance; power
dissipation from AVDD2 increases by ~70 mW for the
AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105.

Tabl e 8 . With OUTPUT MODE = 1

Tabl e 7 .

Table 10. Digital Output Coding

VIN+ − VIN−

Code

65,536 +1.700 +1.000 1111 1111 1111 1111 0111 1111 1111 1111
32,768 0 0 1000 0000 0000 0000 0000 0000 0000 0000
32,767 −0.000052 −0.000031 0111 1111 1111 1111 1111 1111 1111 1111
0 −1.70 −1.00 0000 0000 0000 0000 1000 0000 0000 0000

Input Span = 3.4 V p-p (V)

VIN+ − VIN−
Input Span = 2 V p-p (V)

Digital Output
Offset Binary (D15…D0)

Digital Output
Twos Complement (D15…D0)

Rev. 0 | Page 23 of 32

AD9460

EVALUATION BOARD

Evaluation boards are offered to configure the AD9460 in either
CMOS mode or LVDS mode only. This design represents a
recommended configuration for using the device over a wide
range of sampling rates and analog input frequencies. These
evaluation boards provide all the support circuitry required to
operate the ADC in its various modes and configurations. Com­plete schematics are shown in
files are available from engineering applications demonstrating
the proper routing and grounding techniques that should be
applied at the system level.

Figure 50 through Figure 53. Gerber

The LVDS mode evaluation boards include an LVDS-to­CMOS translator, making them compatible with the high
speed ADC FIFO evaluation kit (HSC-ADC-EVALA-SC,

www.analog.com/FIFO). The kit includes a high speed data

capture board that provides a hardware solution for capturing
up to 32 kB samples of high speed ADC output data in a FIFO
memory chip (user upgradeable to 256 kB samples). Software
is provided to enable the user to download the captured data to
a PC via the USB port. This software also includes a behavioral
model of the AD9460 and many other high speed ADCs.

It is critical that signal sources with very low phase noise
(<60 fsec rms jitter) are used to realize the ultimate
performance of the converter. Proper filtering of the input
signal to remove harmonics and lower the integrated noise at
the input is also necessary to achieve the specified noise
performance.

The evaluation boards are shipped with a 115 V ac to 6 V dc
power supply. The evaluation boards include low dropout
regulators to generate the various dc supplies required by the
AD9460 and its support circuitry. Separate power supplies are
provided to isolate the DUT from the support circuitry. Each
input configuration can be selected by proper connection of
various jumpers (see

Figure 50).

Behavioral modeling of the AD9460 using ADIsimADC™
software is also available at
ADIsimADC software supports virtual ADC evaluation using ADI
proprietary behavioral modeling technology. This allows rapid
comparison between the AD9460 and other high speed ADCs
with or without hardware evaluation boards.

The user can choose to remove the translator and terminations
to access the LVDS outputs directly.

www.analog.com/ADIsimADC. The

Rev. 0 | Page 24 of 32

AD9460

P1

1

P2

2

P3

3

P21

P4

4

PTMICRO4

P1

1

P2

2

P3

3

P22

P4

4

PTMICRO4

GND

DRGND

XTALPWR

EXTREF

DRGND

DRVDD

GND

VCC

GND

5V

DRVDD

76
MTHOLE6
H4

MTHOLE6
H3

MTHOLE6
H1

MTHOLE6
H2

D11_C/D6_Y

77

D11_T/D7_Y

78

D12_C/D8_Y

79

D12_T/D9_Y

80

D13_C/D10_Y

81

D13_T/D11_Y

82

D14_C/D12_Y

83

D14_T/D13_Y

84

D15_C/D14_Y

85

(MSB) D15_T/D15_Y

86

DRGND

87

DRVDD

88

DOR_C

89

DOR_T/DOR_Y

90

GND

91

VCC

92

VCC

93

VCC

94

VCC

95

VCC

96

VCC

97

GND

98

99

100

101

DRVDD
D11_C
D11_T
D12_C
D12_T
D13_C
D13_T

D14_C
D14_T
D15_C
D15_T

DRGND

DRVDD

OR_C

OR_T

AGND

AVDD1
AVDD1

AVDD1
AVDD1
AVDD1
AVDD1

AGND
AGND

SFDR

EPAD

DRGND

D10_T/D5_Y

73

74

75

D10_T

DRGND

D8_C/D0_Y

D8_T/D1_Y

D9_C/D2_Y

D9_T/D3_Y

D10_C/D4_Y

72

69

70

71

D9_T

D8_T

D9_C

D8_C

D10_C

D7_C

D7_T

DR

DRB

68

67

DCO

DCOB

DRGND

DRVDD

65

66

64

63

D7_T

D7_C

DRVDD

DRGND

U1

AD9460

D5_C

D5_T

D6_T

D6_C

59

60

61

62

D6_T

D5_T

D6_C

D5_C

D3_C

D3_T

D4_C

D4_T

55

56

57

58

D4_T

D3_T

D4_C

D3_C

D1_C

D1_T

D2_T

D2_C

51

52

53

54

D2_T

D1_T

D2_C

D1_C

D0_T

50

D0_C

49

DRVDD

48

DRGND

47

AGND

46

AVDD1

45

AVDD1

44

AVDD1

43

AGND

42

ENCB

41

ENC

40

AGND

39

AVDD1

38

AVDD2

37

AVDD1

36

AVDD2

35

AVDD1

34

AVDD1

33

AVDD1

32

AVDD2

31

AVDD2

30

AVDD2

29

AVDD2

28

AVDD2

27

AVDD2

26

D0_T

D0_C (LSB)
DRVDD

DRGND

GND
VCC
VCC

VCC

GND

ENCB

ENC

GND

VCC

5V

VCC

5V

VCC
VCC
VCC

5V

DCS MODE

DNC

OUTPUT MODE

DFS

LVDSBIAS

AVDD1

SENSE

VREF

AGND

REFT

REFB

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD1

AVDD1

AVDD1

AGND

VIN+

VIN–

AGND

6

234

5

1

GND

E19

VCC

E4

E18

E36

VCC

GND

E10

E5

E6

E1

VCC

GND

SCLK

GND

R11

1kΩ

VCC

E3

E9

GND

E2

E14

VCC

GND

9

8

7

VCC

GND

GND

11

10

GND

C86

0.1µF

GND

E25

E27

E24

E26

E41

VCC

EXTREF

R1

DNP

R3

3.74kΩ

15

12

14

13

5V

5V

5V

5V

C2

0.1µF

C51

10µF

C9

C3

0.1µF

0.1µF

C40

0.1µF

+

C39

10µF

GND

GND

R2

DNP

GND

20

16

17

5V

GND

C98

21

19

18

5V

GND

VCC

VCC

VCC

GND

DNP

T1

ETC1-1-13

R5

DNP

GND

23

22

24

25

GND

R28

33Ω

C7

0.1µF

R4

GND

GND

TOUT

C12

0.1µF

CT

2

15

34

TINB

GND

C5

L1

10nH

J4

SMBMST

AVDD2

5V

25Ω

125

T2

3

PRISEC

TOUTB

PRI SEC

0.1µF

ANALOG

C13

R9

DNP

DNP

4

OPTIONAL

R35

33Ω

0.1µF
C91

C8

GND

GND

TOUT

624

153

GND

0.1µF

CT

PRI SEC

NC

TINB TOUTB

06006-060

DNP = DO NOT POPULATE

R6

25Ω

ETC1-1-13

E15

T5

ADT1-1WT

Figure 50. Evaluation Board Schematic

Rev. 0 | Page 25 of 32

AD9460

VIN

DRVDDX

DRGND

1

C41

0.1µF

DNP

C1

10µF

DNP

+

VXTAL

OPTIONAL ENCODE CIRCUITS

GND

5V

XTALPWR

C44

10µF

DNP

+

E30

E31

E20

VXTAL

ENC

CR1

2

1

XTALINPUT

8

1

OUTVCC

U2

ECLOSC

VEE ~OUT

7

14

GND

GND

VXTAL

ENCB

3

DRGNDGND

L2

0Ω

GND

OUT1

U3

3.3V

ADP3338-3.3

U7

ADP3338-3.3

OUT

DRVDDX

VCCX

GND

1

GND

OUT1

3.3V

OUT

VCCX

C4

10µF

+

342

IN

VIN

C6

10µF

+

342

IN

C88

+

C87

+

DRGND

10µF

DRGND

GND

10µF

GND

VIN

5VX

GND

GND

OUT1

OUT

5VX

GND

3

3

2

C34

10µF

+

342

IN

VIN

C33

10µF

+

1

1

C89

+

GND

10µF

GND

GND

DNP = DO NOT PO PULATE

06006-061

ENCODE

GND

GND

CR2

6

123

DNP

DNP

J1

5

NC

1

2

GND

C42

0.1µF

4

SEC

PRI

C26

R8

SMBMST

L5

0.1µF

GND

50Ω

VCCXVCC

DRVDDXDRVDD

L4

FERRITE

5VX5V

1

L3

FERRITE

FERRITE

U14

5V

ADP3338-5

XTALINPUT

POWER OPTIONS

2

P4

PJ-002A

3

LOADING SYMMETRICAL

CR2 TO MAKE LAYOUT AND PARASIT IC

T3

ADT1-1WT

0Ω

R39

C36

R7

DNP

J5

SMBMST

Figure 51. Evaluation Board Schematic, Encode, Optional Encode and Power Options

Rev. 0 | Page 26 of 32

AD9460

BYPASS CAPACITORS

VCC

+

C64

GND

VCC

GND

DRVDD

DRGND

GND

GND

GND

C43

10µF

0.1µF

+

C65

C47

10µF

0.1µF

5V

+

C56
10µF

5V

5V

C11

0.1µF

C85

0.1µF

C23

0.1µF

C35

0.1µF

C14
DNP

C53

0.1µF

C72
DNP

C94

0.1µF

C17
DNP

C52

0.1µF

C73
DNP

C95

0.1µF

C32

0.1µF

C21

0.1µF

C30

0.01µF

C16
DNP

C58

0.01µF

C22

0.1µF

C20

0.1µF

C15

0.1µF

C108
DNP

C59

0.1µF

C28

0.1µF

C27

0.1µF

C31
DNP

DRVDD

DRGND

C109
DNP

C93
DNP

C110
DNP

C96

0.1µF

C90

0.1µF

C38

0.1µF

C69
DNP

C37
DNP

C97

0.1µF

C50

0.1µF

C60

0.1µF

C29
DNP

C70
DNP

C48

0.1µF

C84

0.1µF

C10

0.1µF

C19
DNP

C45
DNP

C18

0.1µF

C46

0.1µF

C61
DNP

C49
DNP

EXTREF

GND

+

C75
DNP

C55
10µF
DNP

DNP = DO NOT POPULATE

06006-062

Figure 52. Evaluation Board Schematic, Bypass Capacitors

Rev. 0 | Page 27 of 32

AD9460

DRO

DRVDD

R190ΩR10

DRVDD

DRGND

D15O

D13O

D11O

D9O

D8O

GND

35

P35

P36

36

D14O

R3

33

P33

34

D13O

312

D14O

23

25

27

29

31

P23

P25

P27

P29

P31

P24

P26

P28

P30

P32

P34

24

26

28

30

32

D8O

D9O

D10O

D11O

D12O

9

R8

R7

R6

R5

R4

8

7

6

5

4

DRVDD

DRGND

DRVDD

DRO

DRGND

37

39

P37

P39

P38

P40

38

40

ORO

DRGND

D15O

16151413121110

220

R1

R2

RSO16ISO

RZ5

ORO

0Ω

DRVDD

DRVDD

DRVDD

DRGND

DRGND

DRVDD

D10O

D12O

D7O

17

19

21

P17

P19

P21

P18

P20

P22

18

20

22

D7O

16151413121110

220

RSO16ISO

DRVDD

DRGND

15

16

D6O

D6O

P15

P16

D4O

D3O

D5O

9

11

13

P9

P11

P13

P10

P12

P14

10

12

14

D4O

D5O

D3O

R6

R5

R4

R3R1R2

5

4

312

DRVDD

D0O

D2O

D1O

DRGND

1

3

5

7

P1

P3

P5

P7

P7

C40MS

P2

P4

P6

P8

8

D2O

6

DRVDD

2

4

6

DRGND

D1O

D0O

9

R8

R7

RZ4

8

7

DRGND

DRVDD

DRVDD

DRGND

91011

12

13

14

15

16

4Y

3Y

2Y

1Y

VCC

GND

EN_1_2

U15

2B

2A

1B

1A

SN75LVDT390

1

DR

DRB

EN_3_4

4B

4A

3B

3A

8765432

DOR_C

DRO_T/DOR_Y

64

D4Y

D3Y

D2Y

D1Y

C4Y

C3Y

C2Y

A1Y

VCC2

VCC1

A2A

A1B

D14_T/D13_Y

D15_C/D14_Y

DRGND

39

P39

P40

40

DRGND

ENA

GND1

A3A

A2B

D13_T/D11_Y

D14_C/D12_Y

DOR_C

37

P37

P38

38

DOR_T/DOR_Y

A3B

D13_C/D10_Y

D15_C/D14_Y

35

P35

36

D15_T/D15_Y

GND

U8

A1A

SN75LVDT386

D15_T/D14_Y

P36

A4A

D12_T/D9_Y

D14_C/D12_Y

33

P33

P34

34

D14_T/D13_Y

A4B

D12_C/D8_Y

987654321

31

32

B1A

10

D11_T/D7_Y

D13_C/D10_Y

P31

P32

D13_T/D11_Y

ENB

B1B

D11_C/D6_Y

B2A

11

D10_T/D5_Y

D12_C/D8_Y

29

P29

P30

30

D12_T/D9_Y

12

B2B

D10_C/D4_Y

27

28

13

D11_C/D6_Y

P27

P28

D11_T/D7_Y

B3A

D9_T/D3_Y

GND2

B4A

B3B

15

14

D8_T/D1_Y

D9_C/D2_Y

D10_C/D4_Y

25

P25

P26

26

D10_T/D5_Y

B4Y

B3Y

B2Y

B1Y

A4Y

A3Y

A2Y

C1Y

VCC4

VCC3

GND3

C2A

C1B

C1A

B4B

19

18

17

16

D7_T

D6_T

D7_C

D8_C/D0_Y

D8_C/DO_Y

DRB

D9_C/D2_Y

19

21

23

P19

P21

P23

P20

P22

P24

20

22

24

DR

D9_T/D3_Y

D8_T/D1_Y

20

C2B

D6_C

D7_C

17

P17

18

D7_T

21

P18

C3A

22

D5_T

15

16

C3B

23

D5_C

D6_C

P15

P16

D6_T

ENC

C4A

24

D4_T

D5_C

13

P13

P14

14

D5_T

C4B

D4_C

25

11

12

D1A

26

D3_T

D4_C

P11

P12

D4_T

D1B

D3_C

9

10

D2A

27

D2_T

D3_C

P9

P10

D3_T

28

7

8

END

D2B

29

D2_C

D2_C

P7

P8

D2_T

GND4

D3A

30

D1_T

D1_C

5

P5

P6

6

D1_T

VCC5

D3B

D1_C

31

VCC6

D4A

32

D0_T

D0_C

3

P3

P4

4

D0_T

GND5

D4B

D0_C

C78

0.1µF

C77

0.1µF

C82

0.1µF

C76

0.1µF

GND

GND

DRGND

1

P1

P6

C40MS

P2

2

DRGND

06006-063

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Figure 53. Evaluation Board Schematic

Rev. 0 | Page 28 of 32

AD9460

Table 11. AD9460 Customer Evaluation Board Bill of Materials

Item Qty. Reference Designator Description Package Value

1 7 C4, C6, C33, C34, C87, C88, C89 Capacitor TAJD 10 F

2 45

C2, C3, C5, C7, C8, C9, C10, C11,

Capacitor 402 0.1 F
C12, C15, C18, C20, C21, C22,
C23, C26, C27, C28, C32, C35,
C38, C40, C42, C43, C46, C47,
C48, C50, C52, C53, C59, C60,
C76, C77, C78, C82, C84, C85,
C86, C90, C91, C94, C95, C96,
C97

3 2 C30, C58 Capacitor 201 0.01 F

4 4 C39, C56, C64, C65 Capacitor TAJD 10 F

5 1 C51 Capacitor 805 10 F

6 1 CR1 Diode SOT23M5

7 1 CR2

8 20

1

E1, E2, E3, E4, E5, E6, E9, E10,

Diode SOT23M5 DNP

Header EHOLE
E14, E18, E19, E20, E24, E25, E26,
E27, E30, E31, E36, E41

9 2 J1, J4 SMA SMA

10 1 L1 Inductor 0603A 10 nH Coilcraft, Inc. 0603CS-10NXGBU
11 3 L3, L4, L5

EMIFIL®

1206MIL

BLM31PG500SN1L

12 1 P4 Power jack PJ-002A

13 1 P7 Header C40MS Samtec, Inc. TSW-120-08-L-D-RA
14 1 R3 Resistor 402 3.74 kΩ

15 1 R8 Resistor 402 50 Ω

16 4 R10, R19, R39, L2 Resistor 402 0 Ω

17 1 R11 BRES402 402 1 kΩ

18 2 R28, R35 Resistor 402 33 Ω

19 2 RZ4, RZ5 Resistor array 16-pin 22 Ω

20 1 T3 Transformer ADT1-1WT Mini-Circuits ADT1-1WT
21 1 U1 AD9460BSVZ SV-100-3

22 1 U14 ADP3338-5 SOT-223HS

23 2 U3, U7 ADP3338-3.3 SOT-223HS

24 1 U8 SN75LVDT386 TSSOP64

25 1 U15 SN75LVDT390 SOIC16PW

26 2 R4, R6 Resistor 402 25 Ω

1

Manufacturer Mfg. Part No.

Digi-Key

478-1699-2

Corporation
Digi-Key

PCC2146CT-ND

Corporation

Digi-Key

445-1796-1-ND

Corporation
Digi-Key

478-1699-2

Corporation
Digi-Key

490-1717-1-ND

Corporation
Digi-Key

MA3X71600LCT-ND

Corporation
Digi-Key

MA3X71600LCT-ND

Corporation
Mouser

517-6111TG

Electronics

Digi-Key

ARFX1231-ND

Corporation

Mouser

81-BLM31P500S

Electronics
Digi-Key

CP-002A-ND

Corporation

Digi-Key

P3.74KLCT-ND

Corporation
Digi-Key

P49.9LCT-ND

Corporation
Digi-Key

P0.0JCT-ND

Corporation
Digi-Key

P1.0KLCT-ND

Corporation
Digi-Key

P33JCT-ND

Corporation
Digi-Key

742C163220JCT-ND

Corporation

Analog Devices,

AD9460BSVZ

Inc.
Analog Devices,

ADP3338-5

Inc.
Analog Devices,

ADP3338-3.3

Inc.
Arrow

SN75LVDT386

Electronics, Inc.
Arrow

SN75LVDT390

Electronics, Inc.
Digi-Key

P36JCT-ND

Corporation

Rev. 0 | Page 29 of 32

AD9460

Item Qty. Reference Designator Description Package Value

27 2 C1, C44, C55

28 22

C13, C14, C16, C17, C19, C29,

1

Capacitor TAJD 10 F, DNP

CAP402 402 DNP
C31, C36, C37, C41, C45, C49,
C61, C69, C70, C72, C73, C75,
C93, C108, C109, C110

29 1 C98

30 E15

31 J5

32 P6
33 2 R1, R2
34 3 R5, R7, R9
35 1 U2
36 4 H1, H2, H3, H4
37 2 T1, T2
38 1 T5
39 2 P21, P22

1

DNP = do not populate. All items listed in this category are not populated.

1

1

1

1

1

1

1

1

1

1

1

1

Capacitor 805 DNP

Header EHOLE DNP

SMA SMA DNP

Header C40MS DNP Samtec, Inc. TSW-120-08-L-D-RA

BRES402 402 DNP

BRES402 402 DNP

ECLOSC DIP4(14) DNP

MTHOLE6 MTHOLE6 DNP

Balun transformer SM-22 DNP M/A-COM ETC1-1-13

Transformer ADT1-1WT DNP Mini-Circuits ADT1-WT

Term strip PTMICRO4 DNP

1

Manufacturer Mfg. Part No.

Digi-Key

478-1699-2

Corporation

Digi-Key

490-1717-1-ND

Corporation
Mouser

517-6111TG

Electronics
Digi-Key

ARFX1231-ND

Corporation

Newark
Electronics

Rev. 0 | Page 30 of 32

AD9460

OUTLINE DIMENSIONS

0.75

0.60

0.45

1.20
MAX

16.00 BSC SQ

1

PIN 1

14.00 BSC SQ

76100

76 100

75

75

1

1.05

1.00

0.95

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

TOP VIEW

(PINS DOWN)

0° MIN

0.20

0.09
7°

3.5°
0°

0.08 MAX
COPLANARIT Y

NOTES

1. CENTER FI GURES ARE TYPICAL UNL ESS OTHERWI SE NOTED.

2. THE PACKAGE HAS A CONDUCTIVE HE AT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELI ABLE OPER ATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHI P GROUND. IT IS RECOMM ENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTI ON TEMPERATURE OF THE
DEVICE WHI CH MAY BE BENEFICIAL I N HIGH TEMP ERATURE ENVIRONMENTS.

25

26 50

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD

51

51

EXPOSED

BOTTO M VIEW

0.50 BSC

LEAD PITCH

PAD

(PINS UP)

0.27

0.22

0.17

9.50 SQ

25

2650

040506-A

Figure 54. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-100-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9460BSVZ-80
AD9460BSVZ-105
AD9460-80LVDS/PCB AD9460-80LVDS Mode Evaluation Board
AD9460-105LVDS/PCB AD9460-105LVDS Mode Evaluation Board

1

Z = Pb-free part.

1

1

–40°C to +85°C 100-Lead TQFP_EP SV-100-3
–40°C to +85°C 100-Lead TQFP_EP SV-100-3

Rev. 0 | Page 31 of 32

AD9460

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06006-0-7/06(0)

Rev. 0 | Page 32 of 32