79.4 dBFS SNR/91 dBc SFDR with 10 MHz input
(3.4 V p-p input, 80 MSPS)
78.3 dBFS SNR/ with 170 MHz input
(4.0 V p-p input, 80 MSPS)
77.8 dBFS SNR/87 dBc SFDR with 170 MHz input
(3.4 V p-p input, 80 MSPS)
77.2 dBFS SNR/84 dBc SFDR with 170 MHz input
(3.4 V p-p input, 105 MSPS)
90 dBFS two-tone SFDR with 139 MHz/140 MHz input
(3.4 V p-p input, 105 MSPS)
60 fsec rms jitter
Excellent linearity
DNL = ±0.5 LSB typical
INL = ±3.0 LSB typical
2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output data capture clock available
Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
and output data mode.
The AD9460 is available in a Pb-free, 100-lead, surface-mount,
plastic package (TQFP_EP) specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.True 16-bit linearity.
06006-001
GENERAL DESCRIPTION
The AD9460 is a 16-bit, monolithic, sampling, analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit. It is
optimized for performance, small size, and ease of use. The
AD9460 operates up to 105 MSPS, providing a superior signalto-noise ratio (SNR) for instrumentation, medical imaging, and
2. High performance: outstanding SNR performance for
baseband IFs in data acquisition, instrumentation,
magnetic resonance imaging, and radar receivers.
3. Ease of use: on-chip reference and high input impedance,
track-and-hold with adjustable analog input range, and an
output clock simplifies data capture.
radar receivers using baseband (<100 MHz) and IF frequencies.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
performance over a wide range of clock pulse widths.
many applications. Data outputs are CMOS or LVDS compatible
(ANSI-644 compatible) and include the means to reduce the
overall current needed for short trace distances.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
6. Out-of-range (OR) outputs indicate when the signal is
AD9460BSVZ-80 AD9460BSVZ-105
Parameter Te mp Min Typ Max Min Typ Max Unit
RESOLUTION Full 16 16 Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed
Offset Error Full −5.0 ±0.1 +5.0 −5.0 ±0.1 +5.0 mV
Gain Error 25°C −3 ±0.5 +3 −3 ±0.5 +3 % FSR
Full −3.4 +3.4 −3.4 +3.4 % FSR
Differential Nonlinearity (DNL)
Full −0.9 +0.9 −1 +1.2
Integral Nonlinearity (INL)1 25°C −6 ±3 +6 −6 ±3 +6 LSB
VOLTAGE REFERENCE
Output Voltage VREF = 1.7 V Full 1.7 1.7 V
Load Regulation @ 1.0 mA Full ±2 ±2 mV
Reference Input Current (External VREF = 1.7 V) Full 350 350 µA
INPUT REFERRED NOISE 25°C 2.4 2.5 LSB rms
ANALOG INPUT
Input Span
VREF = 1.7 V Full 3.4 3.4 V p-p
VREF = 1.0 V Full 2.0 2.0 V p-p
Internal Input Common-Mode Voltage Full 3.5 3.5 V
External Input Common-Mode Voltage Full 3.2
Input Resistance
Input Capacitance
2
2
POWER SUPPLIES
Supply Voltages
AVDD1 Full 3.14 3.3 3.46 3.14 3.3 3.46 V
AVDD2 Full 4.75 5.05.254.75 5.05.25V
DRVDD—LVDS Outputs Full 3.03.3 3.63.03.3 3.6V
DRVDD—CMOS Outputs Full 3.03.33.63.03.33.6V
Supply Currents
1
AVDD1 Full 290310 337373mA
1, 3
AVDD2
1
I
—LVDS Outputs Full 7078.5 7181mA
DRVDD
1
I
—CMOS Outputs Full 14 14 mA
DRVDD
PSRR
Offset Full 1 1 mV/V
Gain Full 0.2 0.2 %/V
POWER CONSUMPTION
3
LVDS Outputs Full 1.71.8
CMOS Outputs (DC Input) Full 1.5
1
Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
2
Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.
3
For SFDR = AVDD1, I
power increases by ~70 mW for the AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105.
AVDD2
1
25°C −0.8±0.5 +0.8−0.85±0.5 +0.85LSB
3.9 3.2
3.9 V
Full 1 1 kΩ
Full 6 6 pF
Full 101110 116133mA
1.9
1.7
2.2 W
W
Rev. 0 | Page 3 of 32
AD9460
AC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 3.4 V p-p differential input, internal
trimmed reference (1.7 V mode), A
Table 2.
Parameter Temp
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 10 MHz 25°C 77.6 78.4 77.2 78.1 dB
Full 77.4 76.9
fIN = 170 MHz 25°C 76.1 76.8 75.0 76.2 dB
Full 75.0 74.5
fIN = 225 MHz 25°C 75.7 75.2 dB
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 10 MHz 25°C 76.1 78.0 75.2 77.4 dB
Full 74.4 74.5
fIN = 170 MHz 25°C 74.0 76.1 72.0 75.1 dB
Full 72.1 71.2
fIN = 225 MHz 25°C 74.6 73.6 dB
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz 25°C 12.8 12.7 bits
fIN = 170 MHz 25°C 12.5 12.4 bits
fIN = 225 MHz 25°C 12.3 12.1 bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR, SECOND
OR THIRD HARMONIC)
fIN = 10 MHz 25°C 80 91 80 88 dBc
Full 78 76
fIN = 170 MHz 25°C 80 87 78 84 dBc
Full 78 74
fIN = 225 MHz 25°C 82 81 dBc
WORST SPUR EXCLUDING SECOND OR
THIRD HARMONICS
fIN = 10 MHz 25°C 94 100 92 98 dBc
Full 91 91
fIN = 170 MHz 25°C 90 98 89 98 dBc
Full 88 85
fIN = 225 MHz 25°C 97 92 dBc
AD9460BSVZ-80/105
Parameter Te mp Min Typ Max Unit
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage Full 2.0 V
Low Level Input Voltage Full 0.8 V
High Level Input Current Full 200 µA
Low Level Input Current Full −10
Input Capacitance Full
DIGITAL OUTPUT BITS—CMOS MODE (D0 to D15, OTR)
DRVDD = 3.3 V
High Level Output Voltage Full 3.25
Low Level Output Voltage Full
DIGITAL OUTPUT BITS—LVDS MODE (D0 to D15, OTR)
VOD Differential Output Voltage
2
VOS Output Offset Voltage Full 1.125
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage Full 0.2
Common-Mode Voltage Full 1.31.51.6V
Input Resistance Full 1.1 1.41.7kΩ
Input Capacitance Full
1
Output voltage levels measured with 5 pF load on each output.
AD9460BSVZ-80 AD9460BSVZ-105
Parameter Te mp Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate Full 80 105 MSPS
Minimum Conversion Rate Full 1 1 MSPS
CLK Period Full 12.5 9.5 ns
CLK Pulse Width High1 (t
CLK Pulse Width Low1 (t
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (tPD)2 (Dx, DCO+) Full 3.35 3.35 ns
Output Propagation Delay—LVDS (tPD)3 (Dx+), (t
Pipeline Delay (Latency) Full 13 13 cycles
Aperture Delay (tA) Full ns
Aperture Uncertainty (Jitter, tJ) Full 60 60 fs, rms
1
With duty cycle stabilizer (DCS) enabled.
2
Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.
3
LVDS R
= 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
TERM
) Full 5.0 3.8 ns
CLKH
) Full 5.0 3.8 ns
CLKL
)3 (DCO+) Full 2.3 3.6 4.8 2.3 3.6 4.8 ns
CPD
Rev. 0 | Page 5 of 32
AD9460
TIMING DIAGRAMS
VIN
CLK+
CLK–
N – 1
t
CLKH
t
CLKL
N
N + 1
f
1/
S
t
PD
N + 13
N + 14
N + 15
DCO+
DCO–
VIN
CLK–
CLK+
DCO+
DCO–
N – 12
13 CLOCK CYCLES
t
N – 13
CPD
Dx
N
N + 1
06006-002
Figure 2. LVDS Mode Timing Diagram
N – 1
t
CLKH
Dx
N
N + 1
t
CLKL
t
PD
N – 13N – 12N – 1N
N + 2
13 CLOCK CYCLES
06006-003
Figure 3. CMOS Timing Diagram
Rev. 0 | Page 6 of 32
AD9460
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
ELECTRICAL
AVDD1 to AGND −0.3 V to +4 V
AVDD2 to AGND −0.3 V to +6 V
DRVDD to DGND −0.3 V to +4 V
AGND to DGND −0.3 V to +0.3 V
AVDD1 to DRVDD −4 V to +4 V
AVDD2 to DRVDD −4 V to +6 V
AVDD2 to AVDD1 −4 V to +6 V
D0± Through D15± to DGND −0.3 V to DRVDD + 0.3 V
CLK+/CLK− to AGND −0.3 V to AVDD1 + 0.3 V
OUTPUT MODE, DCS MODE, and
−0.3 V to AVDD1 + 0.3 V
DFS to AGND
VIN+, VIN− to AGND −0.3 V to AVDD2 + 0.3 V
VREF to AGND −0.3 V to AVDD1 + 0.3 V
SENSE to AGND −0.3 V to AVDD1 + 0.3 V
REFT, REFB to AGND −0.3 V to AVDD1 + 0.3 V
ENVIRONMENTAL
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The heat sink of the AD9460 package must be soldered to
ground.
Airflow increases heat dissipation, effectively reducing θ
more metal directly in contact with the package leads from
metal traces through holes, ground, and power planes reduces
the θ
. It is required that the exposed heat sink be soldered to
JA
the ground plane.
Table 6.
Package Type θ
1
JA
2
θ
JB
3
θ
JC
100-Lead TQFP_EP 19.8 8.3 2 °C/W
1
Typical θJA = 19.8°C/W (heat sink soldered) for a multilayer board in still air.
2
Typical θJB = 8.3°C/W (heat sink soldered) for a multilayer board in still air.
3
Typical θJC = 2°C/W (junction to exposed heat sink) represents the thermal
resistance through heat sink path
. Also,
JA
Unit
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Figure 4. 100-Lead TQFP_EP Pin Configuration in LVDS Mode
Table 7. Pin Function Descriptions—100-Lead TQFP_EP in LVDS Mode
Pin No. Mnemonic Description
1 DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible.
DCS = low (AGND) to enable DCS (recommended).
DCS = high (AVDD1) to disable DCS.
2 DNC Do Not Connect. This pin should float.
3 OUTPUT MODE CMOS-Compatible Output Logic Mode Control Pin.
OUTPUT MODE = 0 for CMOS mode.
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data.
DFS = high (AVDD1) for twos complement
DFS = low (ground) for offset binary format.
5 LVDS_BIAS Set Pin for LVDS Output Current. Place a 3.7 kΩ resistor terminated to DRGND.
6, 18 to 20, 32 to 34, 36, 38,
AVDD1 3.3 V (±5%) Analog Supply.
43 to 45, 92 to 97
7 SENSE
Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog
input range); connect to AVDD1 for external reference.
8 VREF
1.7 V Reference I/O. The function is dependent on the SENSE pin and external
programming resistors. Decouple to ground with 0.1 µF and 10 µF capacitors.
Differential Reference Output. Decoupled to ground with 0.1 µF capacitor and to REFB
(Pin 11) with 0.1 µF and 10 µF capacitors.
Differential Reference Output. Decoupled to ground with a 0.1 µF capacitor and to REFT
(Pin 10) with 0.1 µF and 10 µF capacitors.
SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the
AD9460 analog front end. Connecting SFDR to AGND optimizes SFDR performance for
applications with analog input frequencies <200 MHz for 80 MSPS and 105 MSPS speed
grades. For applications with analog inputs >200 MHz, connect this pin to AVDD1 for
optimum SFDR performance; power dissipation from AVDD2 increases by ~70 mW for the
AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105.
Figure 5. 100-Lead TQFP_EP Pin Configuration in CMOS Mode
Table 8. Pin Function Descriptions—100-Lead TQFP_EP in CMOS Mode
Pin No. Mnemonic Description
1 DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible.
DCS = low (AGND) to enable DCS (recommended).
DCS = high (AVDD1) to disable DCS.
2, 49 to 62, 65 to 66, 69 DNC Do Not Connect. These pins should float.
3 OUTPUT MODE CMOS-Compatible Output Logic Mode Control Pin.
OUTPUT MODE = 0 for CMOS mode.
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data.
DFS = high (AVDD1) for twos complement.
DFS = low (ground) for offset binary format.
5 LVDS_BIAS Set Pin for LVDS Output Current. Place a 3.7 kΩ resistor terminated to DRGND.
6, 18 to 20, 32 to 34, 36,
AVDD1 3.3 V (±5%) Analog Supply.
38, 43 to 45, 92 to 97
7 SENSE
Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog
input range); connect to AVDD1 for external reference.
8 VREF
1.7 V Reference I/O. The function is dependent on the SENSE pin and external programming
resistors. Decouple to ground with 0.1 µF and 10 µF capacitors.