Analog Devices AD9460 Service Manual

A
A
16-Bit, 80 MSPS/105 MSPS ADC

FEATURES

105 MSPS guaranteed sampling rate (AD9460-105)
79.4 dBFS SNR/91 dBc SFDR with 10 MHz input (3.4 V p-p input, 80 MSPS)
78.3 dBFS SNR/ with 170 MHz input (4.0 V p-p input, 80 MSPS)
77.8 dBFS SNR/87 dBc SFDR with 170 MHz input (3.4 V p-p input, 80 MSPS)
77.2 dBFS SNR/84 dBc SFDR with 170 MHz input (3.4 V p-p input, 105 MSPS)
90 dBFS two-tone SFDR with 139 MHz/140 MHz input
(3.4 V p-p input, 105 MSPS)
60 fsec rms jitter Excellent linearity
DNL = ±0.5 LSB typical INL = ±3.0 LSB typical
2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs LVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos complement) Output data capture clock available
3.3 V and 5 V supply operation

APPLICATIONS

MRI receivers Multicarrier, multimode, cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar Infrared imaging Communications instrumentation
AD9460

FUNCTIONAL BLOCK DIAGRAM

GND DRGND DRVDD
VDD1AVDD2
2
32
2
DFS
DCS MODE
OUTPUT MODE
OR
D15 TO D0
DCO
AD9460
VIN+
VIN–
CLK+
CLK–
BUFFER
CLOCK
AND TIMI NG
MANAGEMENT
T/H
VREF
PIPELINE
ADC
REF
Figure 1.
16
CMOS
OR
LVDS
OUTPUT
STAGING
REFBSENSE REFT
Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data mode.
The AD9460 is available in a Pb-free, 100-lead, surface-mount, plastic package (TQFP_EP) specified over the industrial tem­perature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. True 16-bit linearity.
06006-001

GENERAL DESCRIPTION

The AD9460 is a 16-bit, monolithic, sampling, analog-to-digital converter (ADC) with an on-chip track-and-hold circuit. It is optimized for performance, small size, and ease of use. The AD9460 operates up to 105 MSPS, providing a superior signal­to-noise ratio (SNR) for instrumentation, medical imaging, and
2. High performance: outstanding SNR performance for
baseband IFs in data acquisition, instrumentation, magnetic resonance imaging, and radar receivers.
3. Ease of use: on-chip reference and high input impedance,
track-and-hold with adjustable analog input range, and an output clock simplifies data capture.
radar receivers using baseband (<100 MHz) and IF frequencies.
The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for
4. Packaged in a Pb-free, 100-lead TQFP/EP.
5. Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths. many applications. Data outputs are CMOS or LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
6. Out-of-range (OR) outputs indicate when the signal is
beyond the selected input range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
AD9460

TABLE OF CONTENTS

Features.............................................................................................. 1
Pin Configurations and Function Descriptions............................8
Functional Block Diagram .............................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications.............................................................. 5
Timing Diagrams.......................................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Equivalent Circuits......................................................................... 12
Typical Performance Characteristics........................................... 13
Terminology.................................................................................... 19
Theory of Operation ...................................................................... 20
Analog Input and Reference Overview ................................... 20
Clock Input Considerations...................................................... 21
Power Considerations................................................................ 22
Digital Outputs........................................................................... 23
Timing ......................................................................................... 23
Operational Mode Selection ..................................................... 23
Evaluation Board............................................................................ 24
Outline Dimensions....................................................................... 31
Ordering Guide .......................................................................... 31

REVISION HISTORY

7/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD9460

SPECIFICATIONS

DC SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.4 V p-p differential input, internal trimmed reference (1.0 V mode), analog input amplitude = −1.0 dBFS, DCS = AGND (on), SFDR = AGND, unless otherwise noted.
Table 1.
AD9460BSVZ-80 AD9460BSVZ-105 Parameter Te mp Min Typ Max Min Typ Max Unit
RESOLUTION Full 16 16 Bits ACCURACY
No Missing Codes Full Guaranteed Guaranteed Offset Error Full −5.0 ±0.1 +5.0 −5.0 ±0.1 +5.0 mV Gain Error 25°C −3 ±0.5 +3 −3 ±0.5 +3 % FSR Full −3.4 +3.4 −3.4 +3.4 % FSR Differential Nonlinearity (DNL) Full −0.9 +0.9 −1 +1.2 Integral Nonlinearity (INL)1 25°C −6 ±3 +6 −6 ±3 +6 LSB
VOLTAGE REFERENCE
Output Voltage VREF = 1.7 V Full 1.7 1.7 V Load Regulation @ 1.0 mA Full ±2 ±2 mV
Reference Input Current (External VREF = 1.7 V) Full 350 350 µA INPUT REFERRED NOISE 25°C 2.4 2.5 LSB rms ANALOG INPUT
Input Span
VREF = 1.7 V Full 3.4 3.4 V p-p
VREF = 1.0 V Full 2.0 2.0 V p-p Internal Input Common-Mode Voltage Full 3.5 3.5 V External Input Common-Mode Voltage Full 3.2 Input Resistance Input Capacitance
2
2
POWER SUPPLIES
Supply Voltages
AVDD1 Full 3.14 3.3 3.46 3.14 3.3 3.46 V
AVDD2 Full 4.75 5.0 5.25 4.75 5.0 5.25 V
DRVDD—LVDS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 V
DRVDD—CMOS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 V Supply Currents
1
AVDD1 Full 290 310 337 373 mA
1, 3
AVDD2
1
I
—LVDS Outputs Full 70 78.5 71 81 mA
DRVDD
1
I
—CMOS Outputs Full 14 14 mA
DRVDD
PSRR
Offset Full 1 1 mV/V
Gain Full 0.2 0.2 %/V
POWER CONSUMPTION
3
LVDS Outputs Full 1.7 1.8 CMOS Outputs (DC Input) Full 1.5
1
Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
2
Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.
3
For SFDR = AVDD1, I
power increases by ~70 mW for the AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105.
AVDD2
1
25°C −0.8 ±0.5 +0.8 −0.85 ±0.5 +0.85 LSB
3.9 3.2
3.9 V Full 1 1 kΩ Full 6 6 pF
Full 101 110 116 133 mA
1.9
1.7
2.2 W
W
Rev. 0 | Page 3 of 32
AD9460

AC SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 3.4 V p-p differential input, internal trimmed reference (1.7 V mode), A
Table 2.
Parameter Temp
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 10 MHz 25°C 77.6 78.4 77.2 78.1 dB Full 77.4 76.9 fIN = 170 MHz 25°C 76.1 76.8 75.0 76.2 dB Full 75.0 74.5 fIN = 225 MHz 25°C 75.7 75.2 dB
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 10 MHz 25°C 76.1 78.0 75.2 77.4 dB Full 74.4 74.5 fIN = 170 MHz 25°C 74.0 76.1 72.0 75.1 dB Full 72.1 71.2 fIN = 225 MHz 25°C 74.6 73.6 dB
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz 25°C 12.8 12.7 bits fIN = 170 MHz 25°C 12.5 12.4 bits fIN = 225 MHz 25°C 12.3 12.1 bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR, SECOND
OR THIRD HARMONIC) fIN = 10 MHz 25°C 80 91 80 88 dBc Full 78 76 fIN = 170 MHz 25°C 80 87 78 84 dBc Full 78 74 fIN = 225 MHz 25°C 82 81 dBc
WORST SPUR EXCLUDING SECOND OR
THIRD HARMONICS fIN = 10 MHz 25°C 94 100 92 98 dBc Full 91 91 fIN = 170 MHz 25°C 90 98 89 98 dBc Full 88 85 fIN = 225 MHz 25°C 97 92 dBc
TWO-TONE SFDR
fIN = 139.6 MHz @ −7 dBFS, 140.6 MHz @ −7 dBFS 25°C 89 90 dBFS
ANALOG BANDWIDTH Full 615 615 MHz
= −1.0 dBFS, DCS = AGND (on), SFDR = AGND, unless otherwise noted.
IN
AD9460BSVZ-80 AD9460BSVZ-105
Min Typ Max Min Typ Max Unit
Rev. 0 | Page 4 of 32
AD9460

DIGITAL SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, R
Table 3.
AD9460BSVZ-80/105 Parameter Te mp Min Typ Max Unit
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage Full 2.0 V Low Level Input Voltage Full 0.8 V High Level Input Current Full 200 µA Low Level Input Current Full −10 Input Capacitance Full
DIGITAL OUTPUT BITS—CMOS MODE (D0 to D15, OTR)
DRVDD = 3.3 V
High Level Output Voltage Full 3.25 Low Level Output Voltage Full
DIGITAL OUTPUT BITS—LVDS MODE (D0 to D15, OTR)
VOD Differential Output Voltage
2
VOS Output Offset Voltage Full 1.125
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage Full 0.2 Common-Mode Voltage Full 1.3 1.5 1.6 V Input Resistance Full 1.1 1.4 1.7 kΩ Input Capacitance Full
1
Output voltage levels measured with 5 pF load on each output.
2
LVDS R
= 100 Ω.
TERM
= 3.74 kΩ, unless otherwise noted.
LVD S_ BI AS
1
Full 247
2
+10 µA
0.2 V
2
545 mV
1.375 V
pF
V
V
pF

SWITCHING SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
AD9460BSVZ-80 AD9460BSVZ-105 Parameter Te mp Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate Full 80 105 MSPS Minimum Conversion Rate Full 1 1 MSPS CLK Period Full 12.5 9.5 ns CLK Pulse Width High1 (t CLK Pulse Width Low1 (t
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (tPD)2 (Dx, DCO+) Full 3.35 3.35 ns Output Propagation Delay—LVDS (tPD)3 (Dx+), (t Pipeline Delay (Latency) Full 13 13 cycles Aperture Delay (tA) Full ns Aperture Uncertainty (Jitter, tJ) Full 60 60 fs, rms
1
With duty cycle stabilizer (DCS) enabled.
2
Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.
3
LVDS R
= 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
TERM
) Full 5.0 3.8 ns
CLKH
) Full 5.0 3.8 ns
CLKL
)3 (DCO+) Full 2.3 3.6 4.8 2.3 3.6 4.8 ns
CPD
Rev. 0 | Page 5 of 32
AD9460

TIMING DIAGRAMS

VIN
CLK+
CLK–
N – 1
t
CLKH
t
CLKL
N
N + 1
f
1/
S
t
PD
N + 13
N + 14
N + 15
DCO+
DCO–
VIN
CLK–
CLK+
DCO+
DCO–
N – 12
13 CLOCK CYCLES
t
N – 13
CPD
Dx
N
N + 1
06006-002
Figure 2. LVDS Mode Timing Diagram
N – 1
t
CLKH
Dx
N
N + 1
t
CLKL
t
PD
N – 13 N – 12 N – 1 N
N + 2
13 CLOCK CYCLES
06006-003
Figure 3. CMOS Timing Diagram
Rev. 0 | Page 6 of 32
AD9460

ABSOLUTE MAXIMUM RATINGS

Table 5.
Parameter Rating
ELECTRICAL
AVDD1 to AGND −0.3 V to +4 V AVDD2 to AGND −0.3 V to +6 V DRVDD to DGND −0.3 V to +4 V AGND to DGND −0.3 V to +0.3 V AVDD1 to DRVDD −4 V to +4 V AVDD2 to DRVDD −4 V to +6 V AVDD2 to AVDD1 −4 V to +6 V D0± Through D15± to DGND −0.3 V to DRVDD + 0.3 V CLK+/CLK− to AGND −0.3 V to AVDD1 + 0.3 V OUTPUT MODE, DCS MODE, and
−0.3 V to AVDD1 + 0.3 V
DFS to AGND VIN+, VIN− to AGND −0.3 V to AVDD2 + 0.3 V VREF to AGND −0.3 V to AVDD1 + 0.3 V SENSE to AGND −0.3 V to AVDD1 + 0.3 V REFT, REFB to AGND −0.3 V to AVDD1 + 0.3 V
ENVIRONMENTAL
Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering 10 sec) 300°C Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

The heat sink of the AD9460 package must be soldered to ground.
Airflow increases heat dissipation, effectively reducing θ more metal directly in contact with the package leads from metal traces through holes, ground, and power planes reduces the θ
. It is required that the exposed heat sink be soldered to
JA
the ground plane.
Table 6.
Package Type θ
1
JA
2
θ
JB
3
θ
JC
100-Lead TQFP_EP 19.8 8.3 2 °C/W
1
Typical θJA = 19.8°C/W (heat sink soldered) for a multilayer board in still air.
2
Typical θJB = 8.3°C/W (heat sink soldered) for a multilayer board in still air.
3
Typical θJC = 2°C/W (junction to exposed heat sink) represents the thermal
resistance through heat sink path
. Also,
JA
Unit

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 7 of 32
AD9460

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SFDR99AGND98AGND97AVDD196AVDD195AVDD194AVDD193AVDD192AVDD191AGND90OR+89OR–88DRVDD87DRGND86D15+ (MSB)85D15–84D14+83D14–82D13+81D13–80D12+79D12–78D11+77D11–76DRVDD
100
75
DRGND
74
D10+
73
D10–
72
D9+
71
D9–
70
D8+
69
D8–
68
DCO+
67
DCO–
66
D7+
65
D7–
64
DRVDD
63
DRGND
62
D6+
61
D6–
60
D5+
59
D5–
58
D4+
57
D4–
56
D3+
55
D3–
54
D2+
53
D2–
52
D1+
51
D1–
49
50
D0+
D0– (LSB)
06006-004
DNC
DFS
AVDD1
SENSE
VREF
AGND
REFT
REFB
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AGND
VIN+
VIN–
AGND
AVDD2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DCS MODE
OUTPUT MODE
LVDS_BIAS
DNC = DO NOT CONNECT
PIN 1
AD9460
LVDS MODE
TOP VIEW
(Not to Scale)
26
AVDD227AVDD228AVDD229AVDD230AVDD231AVDD232AVDD133AVDD134AVDD135AVDD236AVDD137AVDD238AVDD1
39
40
41
42
43
46
47
48
CLK–
CLK+
AGND
AGND
AVDD144AVDD145AVDD1
AGND
DRVDD
DRGND
Figure 4. 100-Lead TQFP_EP Pin Configuration in LVDS Mode
Table 7. Pin Function Descriptions—100-Lead TQFP_EP in LVDS Mode
Pin No. Mnemonic Description
1 DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable DCS (recommended). DCS = high (AVDD1) to disable DCS. 2 DNC Do Not Connect. This pin should float. 3 OUTPUT MODE CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode. OUTPUT MODE = 1 (AVDD1) for LVDS outputs. 4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos complement DFS = low (ground) for offset binary format. 5 LVDS_BIAS Set Pin for LVDS Output Current. Place a 3.7 kΩ resistor terminated to DRGND. 6, 18 to 20, 32 to 34, 36, 38,
AVDD1 3.3 V (±5%) Analog Supply.
43 to 45, 92 to 97 7 SENSE
Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog input range); connect to AVDD1 for external reference.
8 VREF
1.7 V Reference I/O. The function is dependent on the SENSE pin and external programming resistors. Decouple to ground with 0.1 µF and 10 µF capacitors.
9, 21, 24, 39, 42, 46, 91, 98, 99, Exposed Heat Sink
AGND
Analog Ground. The exposed heat sink on the bottom of the package must be connected to AGND.
Rev. 0 | Page 8 of 32
AD9460
Pin No. Mnemonic Description
10 REFT
11 REFB
12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (±5%). 22 VIN+ Analog Input—True. 23 VIN− Analog Input—Complement. 40 CLK+ Clock Input—True. 41 CLK− Clock Input—Complement. 47, 63, 75, 87 DRGND Digital Output Ground. 48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V). 49 D0− (LSB) D0 Complement Output Bit (LVDS Levels). 50 D0+ D0 True Output Bit. 51 D1− D1 Complement Output Bit. 52 D1+ D1 True Output Bit. 53 D2− D2 Complement Output Bit. 54 D2+ D2 True Output Bit. 55 D3− D3 Complement Output Bit. 56 D3+ D3 True Output Bit. 57 D4− D4 Complement Output Bit. 58 D4+ D4 True Output Bit. 59 D5− D5 Complement Output Bit. 60 D5+ D5 True Output Bit. 61 D6− D6 Complement Output Bit. 62 D6+ D6 True Output Bit. 65 D7− D7 Complement Output Bit. 66 D7+ D7 True Output Bit. 67 DCO− Data Clock Output—Complement. 68 DCO+ Data Clock Output—True. 69 D8− D8 Complement Output Bit. 70 D8+ D8 True Output Bit. 71 D9− D9 Complement Output Bit. 72 D9+ D9 True Output Bit. 73 D10− D10 Complement Output Bit. 74 D10+ D10 True Output Bit. 77 D11− D11 Complement Output Bit. 78 D11+ D11 True Output Bit. 79 D12− D12 Complement Output Bit. 80 D12+ D12 True Output Bit. 81 D13− D13 Complement Output Bit. 82 D13+ D13 True Output Bit. 83 D14− D14 Complement Output Bit. 84 D14+ D14 True Output Bit. 85 D15− D15 Complement Output Bit. 86 D15+ (MSB) D15 True Output Bit. 89 OR− Out-of-Range Complement Output Bit. 90 OR+ Out-of-Range True Output Bit. 100 SFDR
Differential Reference Output. Decoupled to ground with 0.1 µF capacitor and to REFB (Pin 11) with 0.1 µF and 10 µF capacitors.
Differential Reference Output. Decoupled to ground with a 0.1 µF capacitor and to REFT (Pin 10) with 0.1 µF and 10 µF capacitors.
SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the AD9460 analog front end. Connecting SFDR to AGND optimizes SFDR performance for applications with analog input frequencies <200 MHz for 80 MSPS and 105 MSPS speed grades. For applications with analog inputs >200 MHz, connect this pin to AVDD1 for optimum SFDR performance; power dissipation from AVDD2 increases by ~70 mW for the AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105.
Rev. 0 | Page 9 of 32
AD9460
SFDR99AGND98AGND97AVDD196AVDD195AVDD194AVDD193AVDD192AVDD191AGND90OR+89D15+ (MSB)88DRVDD87DRGND86D14+85D13+84D12+83D11+82D10+81D9+80D8+79D7+78D6+77D5+76DRVDD
100
49
DNC50DNC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DRGND
D4+
D3+
D2+
D1+
D0+ (LSB )
DNC
DCO+
DCO–
DNC
DNC
DRVDD
DRGND
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
06006-005
DNC
DFS
AVDD1
SENSE
VREF
AGND
REFT
REFB
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AGND
VIN+
VIN–
AGND
AVDD2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DCS MODE
OUTPUT MODE
LVDS_BIAS
DNC = DO NOT CONNE CT
PIN 1
AD9460
CMOS MODE
TOP VIEW
(Not to Scale)
26
AVDD227AVDD228AVDD229AVDD230AVDD231AVDD232AVDD133AVDD134AVDD135AVDD236AVDD137AVDD238AVDD1
39
40
41
42
43
46
47
48
CLK–
CLK+
AGND
AGND
AVDD144AVDD145AVDD1
AGND
DRGND
DRVDD
Figure 5. 100-Lead TQFP_EP Pin Configuration in CMOS Mode
Table 8. Pin Function Descriptions—100-Lead TQFP_EP in CMOS Mode
Pin No. Mnemonic Description
1 DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable DCS (recommended). DCS = high (AVDD1) to disable DCS. 2, 49 to 62, 65 to 66, 69 DNC Do Not Connect. These pins should float. 3 OUTPUT MODE CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode. OUTPUT MODE = 1 (AVDD1) for LVDS outputs. 4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos complement. DFS = low (ground) for offset binary format. 5 LVDS_BIAS Set Pin for LVDS Output Current. Place a 3.7 kΩ resistor terminated to DRGND. 6, 18 to 20, 32 to 34, 36,
AVDD1 3.3 V (±5%) Analog Supply.
38, 43 to 45, 92 to 97 7 SENSE
Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog input range); connect to AVDD1 for external reference.
8 VREF
1.7 V Reference I/O. The function is dependent on the SENSE pin and external programming resistors. Decouple to ground with 0.1 µF and 10 µF capacitors.
9, 21, 24, 39, 42, 46, 91, 98, 99, Exposed Heat Sink
10 REFT
AGND
Analog Ground. The exposed heat sink on the bottom of the package must be connected to AGND.
Differential Reference Output. Decoupled to ground with 0.1 µF capacitor and to REFB (Pin
11) with 0.1 µF and 10 µF capacitors.
Rev. 0 | Page 10 of 32
Loading...
+ 22 hidden pages