Analog Devices AD9445 Service Manual

14-Bit, 105/125 MSPS, IF Sampling ADC

FEATURES

125 MSPS guaranteed sampling rate (AD9445BSV-125)

78.3 dBFS SNR/92 dBFS SFDR with 30 MHz input (3.2 V p-p)

74.8 dBFS SNR/95 dBFS SFDR with 30 MHz input (2.0 V p-p)

77.0 dBFS SNR/87 dBFS SFDR with 170 MHz input (3.2 V p-p)

74.6 dBFS SNR/95 dBFS SFDR with 170 MHz input (2.0 V p-p)

73.0 dBFS SNR/88 dBFS SFDR with 300 MHz input (2.0 V p-p) 102 dBFS 2-tone SFDR with 30 MHz and 31 MHz 92 dBFS 2-tone SFDR with 170 MHz and 171 MHz 60 fsec rms jitter Excellent linearity

DNL = ±0.25 LSB typical INL = ±0.8 LSB typical

2.0 V p-p to 4.0 V p-p differential full-scale input Buffered analog inputs LVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos complement) Output clock available

3.3 V and 5 V supply operation

APPLICATIONS

Multicarrier, multimode cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar Infrared imaging Medical imaging Communications instrumentation

GENERAL DESCRIPTION

The AD9445 is a 14-bit, monolithic, sampling analog-to-digital converter (ADC) with an on-chip IF sampling track-and-hold circuit. It is optimized for performance, small size, and ease of use. The product operates at up to a 125 MSPS conversion rate and is designed for multicarrier, multimode receivers, such as those found in cellular infrastructure equipment.

The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are CMOS or LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances.

AD9445

FUNCTIONAL BLOCK DIAGRAM

AGND DRGND DRVDD

AVDD1 AVDD2

RF ENABLE DFS DCS MODE OUTPUT MODE OR

D13 TO D0

DCO

AD9445

VIN+ VIN–

CLK+ CLK–

BUFFER

CLOCK

AND TIMING

MANAGEMENT

T/H

PIPELINE

VREF

ADC

REF

Figure 1.

CMOS

LVDS

OUTPUT

STAGING

REFBSENSE REFT

Optional features allow users to implement various selectable operating conditions, including input range, data format select, high IF sampling mode, and output data mode.

The AD9445 is available in a Pb-free, 100-lead, surface-mount, plastic package (100-lead TQFP/EP) specified over the industrial temperature range −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. High performance: outstanding SFDR performance for IF

sampling applications such as multicarrier, multimode 3G, and 4G cellular base station receivers.

2. Ease of use: on-chip reference and high input impedance

track-and-hold with adjustable analog input range and an output clock simplifies data capture.

3. Packaged in a Pb-free, 100-lead TQFP/EP package.

4. Clock duty cycle stabilizer (DCS) maintains overall ADC

performance over a wide range of clock pulse widths.

5. OR (out-of-range) outputs indicate when the signal is

beyond the selected input range.

6. RF enable pin allows users to configure the device for

optimum SFDR when sampling frequencies above 210 MHz (AD9445-125) or 240 MHz (AD9445-105).

05489-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9445

TABLE OF CONTENTS

Features.............................................................................................. 1

Terminology.......................................................................................9

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 6

Switching Specifications.............................................................. 6

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Pin Configurations and Function Descriptions......................... 10

Equivalent Circuits......................................................................... 15

Typical Performance Characteristics........................................... 16

Theory of Operation ...................................................................... 24

Analog Input and Reference Overview ................................... 24

Clock Input Considerations...................................................... 26

Power Considerations................................................................ 27

Digital Outputs........................................................................... 27

Timing ......................................................................................... 27

Operational Mode Selection ..................................................... 28

Evaluation Board............................................................................ 29

Outline Dimensions....................................................................... 37

Ordering Guide .......................................................................... 37

REVISION HISTORY

10/05—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

AD9445

SPECIFICATIONS

DC SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 2.0 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = −1.0 dBFS, DCS on, unless otherwise noted. RF ENABLE = AGND.

Table 1.

AD9445BSVZ-105 AD9445BSVZ-125 Parameter Te mp Min Typ Max Min Typ Max Unit

RESOLUTION Full 14 14 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Offset Error Full −7 +7 −7 +7 mV 25°C ±3 ±3 mV Gain Error Full −3 +3 −3 +3 % FSR 25°C −2 +2 −2 +2 % FSR Differential Nonlinearity (DNL) 5 5 Integral Nonlinearity (INL)1 25°C ±0.65 ±0.8 LSB Full −1.6 +1.6 −2 +2 LSB

VOLTAGE REFERENCE

Output Voltage VREF = 1.0 V Full 0.9 1.0 1.1 0.9 1.0 1.1 V Load Regulation @ 1.0 mA Full ±2 ±2 mV

Reference Input Current (External VREF = 1.6 V) Full µA INPUT REFERRED NOISE 25°C 1.0 1.0 LSB rms ANALOG INPUT

Input Span

VREF = 1.6 V Full 3.2 3.2 V p-p

VREF = 1.0 V Full 2.0 2.0 V p-p Internal Input Common-Mode Voltage Full 3.5 3.5 V External Input Common-Mode Voltage Full 3.1 Input Resistance Input Capacitance

POWER SUPPLIES

Supply Voltage

AVDD1 Full 3.14 3.3 3.46 3.14 3.3 3.46 V

AVDD2 Full 4.75 5.0 5.25 4.75 5.0 5.25 V

DRVDD—LVDS Outputs Full 3.0

DRVDD—CMOS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 V Supply Current

AVDD1 Full 335 364 384 424 mA

1, 3

AVDD2

—LVDS Outputs Full 63 78 63 78 mA

DRVDD

—CMOS Outputs Full 14 14 mA

DRVDD

PSRR

Offset Full 1 1 mV/V

Gain Full 0.2 0.2 %/V

POWER CONSUMPTION

LVDS Outputs Full 2.2 2.4 2.3 2.6 W CMOS Outputs (DC Input) Full 2.0 2.1 W

Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and

approximately 5 pF loading on each output bit for CMOS output mode.

Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.

For RF ENABLE = AVDD1, I

AVDD2

Full −0.6 ±0.25 +0.65 −0.6 ±0.25 +0.65 LSB

Full 1 1 kΩ Full 6 6 pF

Full 169 196 172 199 mA

increases by ~30 mA, which increases power dissipation.

3.9 3.1 3.9 V

3.6 3.0 3.6 V

Rev. 0 | Page 3 of 40

AD9445

AC SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 2.0 V p-p differential input, internal trimmed reference (1.0 V mode), A

Table 2.

Parameter Temp

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 10 MHz 25°C 74.3 74.1 dB fIN = 30 MHz 25°C 73.3 74.3 72.9 73.8 dB Full 73 72.5 dB fIN = 170 MHz 25°C 72.9 73.6 72.3 73.2 dB fIN = 225 MHz

Full 72.2 71.4 dB fIN = 300 MHz fIN = 400 MHz fIN = 450 MHz

fIN = 10 MHz (3.2 V p-p Input) 25°C 77.6 77.3 dB fIN = 30 MHz (3.2 V p-p Input) 25°C 77.5 77.3 dB fIN = 170 MHz (3.2 V p-p Input) 25°C 76 76 dB fIN = 225 MHz (3.2 V p-p Input) fIN = 300 MHz (3.2 V p-p Input)

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 10 MHz 25°C 74.2 73.9 dB fIN = 30 MHz 25°C 73.2 74.2 72.8 73.7 dB Full 72.8 72.3 dB fIN = 170 MHz 25°C 72.3 73.3 72.4 73.0 dB fIN = 225 MHz

Full 71.3 70.7 dB fIN = 300 MHz fIN = 400 MHz fIN = 450 MHz

fIN = 10 MHz (3.2 V p-p Input) 25°C 77.4 76.9 dB fIN = 30 MHz (3.2 V p-p Input) 25°C 77.3 76.8 dB fIN = 170 MHz (3.2 V p-p Input) 25°C 75.7 75.4 dB fIN = 225 MHz (3.2 V p-p Input) fIN = 300 MHz (3.2 V p-p Input)

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 10 MHz 25°C 12.2 12.2 Bits fIN = 30 MHz 25°C 12.2 12.1 Bits fIN = 170 MHz 25°C 12.1 12.0 Bits fIN = 225 MHz fIN = 300 MHz fIN = 400 MHz fIN = 450 MHz

= −1.0 dBFS, DCS on, RF ENABLE = ground, unless otherwise noted.

AD9445BSVZ-105 AD9445BSVZ-125

Min Typ Max Min Typ Max Unit

25°C 72.2 73 72 72.9

25°C 71.4 72.1 71.3 72 dB 25°C 71 71 dB 25°C 70.5 70.5 dB

25°C 75.3 75.4 dB 25°C 73.7 73.5 dB

25°C 71.4 72.5 71.9 72.5

25°C 70.2 71.7 69.3 71.5 dB 25°C 67.2 66.3 dB 25°C 65.2 64.3 dB

25°C 75.1 75.2 dB 25°C 72.5 71.8 dB

25°C 12.0 12.0 Bits 25°C 11.8 11.8 Bits 25°C 11.7 11.7 Bits 25°C 11.6 11.6 Bits

Rev. 0 | Page 4 of 40

AD9445

AD9445BSVZ-105 AD9445BSVZ-125

Parameter Temp

SPURIOUS-FREE DYNAMIC RANGE

(SFDR, Second or Third Harmonic) fIN = 10 MHz 25°C 95 95 dBc fIN = 30 MHz 25°C 84 92 85 94 dBc Full 83 82 dBc fIN = 170 MHz 25°C 82 94 80 91 dBc fIN = 225 MHz

25°C 76 87 83 88 Full 75 75 dBc fIN = 300 MHz fIN = 400 MHz fIN = 450 MHz

25°C 76 87 75 87 dBc

25°C 75 73 dBc

25°C 70 69 dBc

fIN = 10 MHz (3.2 V p-p Input) 25°C 92 92 dBc fIN = 30 MHz (3.2 V p-p Input) 25°C 88 91 dBc fIN = 170 MHz (3.2 V p-p Input) 25°C 86 86 dBc fIN = 225 MHz (3.2 V p-p Input) fIN = 300 MHz (3.2 V p-p Input)

WORST SPUR EXCLUDING SECOND OR

25°C 81 80 dBc

25°C 77 76 dBc

THIRD HARMONICS fIN = 10 MHz 25°C −97 −97 dBc fIN = 30 MHz 25°C −99 −90 −98 −89 dBc Full −90 −88 dBc fIN = 170 MHz 25°C −99 −92 −93 −85 dBc fIN = 225 MHz

25°C −94 −88 −94 −84 dBc Full −86 −80 dBc fIN = 300 MHz fIN = 400 MHz fIN = 450 MHz

25°C −97 −90 −92 −82 dBc

25°C −93 −93 dBc

25°C −82 −87 dBc

fIN = 10 MHz (3.2 V p-p Input) 25°C −97 −95 dBc fIN = 30 MHz (3.2 V p-p Input) 25°C −97 −95 dBc fIN = 170 MHz (3.2 V p-p Input) 25°C −97 −95 dBc fIN = 225 MHz (3.2 V p-p Input) fIN = 300 MHz (3.2 V p-p Input)

25°C −95 −94 dBc

25°C −93 −91 dBc

TWO-TONE SFDR

fIN = 30.3 MHz @ −7 dBFS,

25°C 102 102 dBFS

31.3 MHz @ −7 dBFS

fIN = 170.3 MHz @ −7 dBFS,

25°C 92 91 dBFS

171.3 MHz @ −7 dBFS

ANALOG BANDWIDTH Full 615 615 MHz

RF ENABLE = low (AGND ) for AD9445-105; RF ENABLE = high (AVDD1) for AD9445-125.

RF ENABLE = high (AVDD1).

Min Typ Max Min Typ Max Unit

dBc

Rev. 0 | Page 5 of 40

AD9445

DIGITAL SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, R

Table 3.

AD9445BSVZ-105 AD9445BSVZ-125 Parameter Te mp Min Typ Max Min Typ Max Unit

CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)

High Level Input Voltage Full 2.0 2.0 V Low Level Input Voltage Full 0.8 0.8 V High Level Input Current Full Low Level Input Current Full −10 Input Capacitance Full

DIGITAL OUTPUT BITS—CMOS MODE (D0 to D13, OTR)

DRVDD = 3.3 V

High Level Output Voltage Full 3.25 Low Level Output Voltage Full

DIGITAL OUTPUT BITS—LVDS MODE (D0 to D13, OTR)

VOD Differential Output Voltage

VOS Output Offset Voltage Full 1.125

CLOCK INPUTS (CLK+, CLK−)

Differential Input Voltage Full 0.2 Common-Mode Voltage Full 1.3 1.5 1.6 1.3 1.5 1.6 V Differential Input Resistance Full 1.1 1.4 1.7 1.1 1.4 1.7 kΩ Differential Input Capacitance Full

Output voltage levels measured with 5 pF load on each output.

LVDS R

= 100 Ω.

TERM

= 3.74 kΩ, unless otherwise noted.

LVD S_ BI AS

Full 247

200 200 µA +10 −10 +10 µA

0.2 0.2 V

545 247 545 mV

1.375 1.125 1.375 V

2 pF

3.25 V

0.2 V

2 pF

SWITCHING SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.

Table 4.

AD9445BSVZ-105 AD9445BSVZ-125 Parameter Te mp Min Typ Max Min Typ Max Unit

CLOCK INPUT PARAMETERS

Maximum Conversion Rate Full 105 125 MSPS Minimum Conversion Rate Full 10 10 MSPS CLK Period Full 9.5 8.0 ns CLK Pulse Width High1 (t CLK Pulse Width Low1 (t

DATA OUTPUT PARAMETERS

Output Propagation Delay—CMOS (tPD)2 (Dx, DCO+) Full 3.35 3.35 ns Output Propagation Delay—LVDS (tPD)3 (Dx+), (t Pipeline Delay (Latency) Full 13 13 Cycles Aperture Delay (tA) Full Aperture Uncertainty (Jitter, tJ) Full 60 60

With duty cycle stabilizer (DCS) enabled.

Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.

LVDS R

= 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.

TERM

) Full 3.8 3.2 ns

CLKH

) Full 3.8

CLKL

)3 (DCO+) Full 2.1 3.6 4.8 2.3 3.6 4.8 ns

CPD

3.2 ns

fsec rms

Rev. 0 | Page 6 of 40

AD9445

TIMING DIAGRAMS

CLK+

CLK–

N–1

CLKH

CLKL

N + 1

DATA OUT

DCO+

DCO–

VIN

CLK–

CLK+

DCO+

DCO–

N–1

CLKH

N + 1

05489-002

CPD

N – 13

13 CLOCK CYCLES

N–12

Figure 2. LVDS Mode Timing Diagram

N + 1

CLKL

N – 13 N – 12 N – 1 N

N + 2

13 CLOCK CYCLES

05489-003

Figure 3. CMOS Timing Diagram

Rev. 0 | Page 7 of 40

AD9445

ABSOLUTE MAXIMUM RATINGS

Table 5.

With Respect

Parameter

ELECTRICAL

AVDD1 AGND −0.3 V to +4 V AVDD2 AGND −0.3 V to +6 V DRVDD DGND −0.3 V to +4 V AGND DGND −0.3 V to +0.3 V AVDD1 DRVDD −4 V to +4 V AVDD2 DRVDD −4 V to +6 V AVDD2 AVDD1 −4 V to +6 V D0± to D13± DGND –0.3 V to DRVDD + 0.3 V CLK+/CLK− AGND –0.3 V to AVDD1 + 0.3 V OUTPUT MODE, DCS

MODE, DFS, SFDR,

RF ENABLE VIN+, VIN− AGND –0.3 V to AVDD2 + 0.3 V VREF AGND –0.3 V to AVDD1 + 0.3 V SENSE AGND –0.3 V to AVDD1 + 0.3 V REFT, REFB AGND –0.3 V to AVDD1 + 0.3 V

ENVIRONMENTAL

Storage Temperature

Range Operating Temperature

Range Lead Temperature

(Soldering 10 sec) Junction Temperature 150°C

AGND –0.3 V to AVDD1 + 0.3 V

–65°C to +125°C

–40°C to +85°C

300°C

Rating

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

The heat sink of the AD9445 package must be soldered to ground.

Table 6.

Package Type θJA θ

100-lead TQFP/EP 19.8 8.3 2 °C/W

Typical θJA = 19.8°C/W (heat sink soldered) for multilayer board in still air.

Typical θ

= 8.3°C/W (heat sink soldered) for multilayer board

in still air.

Typical θ

= 2°C/W (junction to exposed heat sink) represents

the thermal resistance through heat sink path.

Airflow increases heat dissipation, effectively reducing θ more metal directly in contact with the package leads from metal traces through holes, ground, and power planes reduces the θ

. It is required that the exposed heat sink be soldered to

the ground plane.

θJC Unit

. Also,

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 8 of 40

AD9445

TERMINOLOGY

Analog Bandwidth (Full Power Bandwidth) Minimum Conversion Rate

The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.

The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.

Aperture Delay (t

) Offset Error

The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter, t

)

The sample-to-sample variation in aperture delay.

Clock Pulse Width and Duty Cycle

Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16,384 codes must be present over all operating ranges.

Effective Number of Bits (ENOB)

The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula:

ENOB

()

SINAD

6.02

1.76−

Gain Error

The first code transition should occur at an analog value of ½ LSB above negative full scale. The last transition should occur at an analog value of 1½ LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.

Integral Nonlinearity (INL)

The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.

Maximum Conversion Rate

The clock rate at which parametric testing is performed.

The major carry transition should occur for an analog value of ½ LSB below VIN+ = VIN−. Offset error is defined as the deviation of the actual transition from that point.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.

Output Propagation Delay (tPD)

The delay between the clock rising edge and the time when all bits are within valid logic levels.

Power-Supply Rejection Ratio

The change in full scale from the value with the supply at the minimum limit to the value with the supply at the maximum limit.

Signal-to-Noise and Distortion (SINAD)

The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc.

Signal-to-Noise Ratio (SNR)

The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may be a harmonic. SFDR can be reported in dBc (that is, degrades as signal level is lowered) or dBFS (always related back to converter full scale).

Tem p er at u re Dr i ft

The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at T

MIN

or T

MAX

Total Harmonic Distortion (THD)

The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components.

Two -Tone SFDR

The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product.

Rev. 0 | Page 9 of 40

AD9445

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

RF ENABLE99AGND98AGND97AVDD196AVDD195AVDD194AVDD193AVDD192AVDD191AGND90OR+89OR–88DRVDD87DRGND86D13+ (MSB)85D13–84D12+83D12–82D11+81D11–80D10+79D10–78D9+77D9–76DRVDD

100

DNC

DFS

AVDD1 SENSE

VREF

AGND

REFT

REFB AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD1 AVDD1 AVDD1

AGND

VIN+ VIN–

AGND

AVDD2

1 2 3 4 5 6 7 8 9

11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

DCS MODE

OUTPUT MODE

LVDS_BIAS

DNC = DO NOT CONNECT

PIN 1

AD9445

LVDS MODE

TOP VIEW

(Not to Scale)

AVDD227AVDD228AVDD229AVDD230AVDD231AVDD232AVDD133AVDD134AVDD135AVDD236AVDD137AVDD238AVDD1

AGND

CLK+

CLK–

AGND

Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode

AVDD144AVDD145AVDD1

AGND

DRVDD

DRGND

DNC50DNC

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

DRGND D8+ D8– D7+ D7– D6+ D6– DCO+ DCO– D5+ D5– DRVDD DRGND D4+ D4– D3+ D3– D2+ D2– D1+ D1– D0+ D0– (LSB) DNC DNC

05489-004

Rev. 0 | Page 10 of 40

AD9445

Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode

Pin No. Mnemonic Description

1 DCS MODE

2, 49 to 52 DNC Do Not Connect. These pins should float. 3 OUTPUT MODE

4 DFS

5 LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND. 6, 18 to 20, 32 to 34, 36, 38,

43 to 45, 92 to 97 7 SENSE

8 VREF

9, 21, 24, 39, 42, 46, 91, 98, 99, Exposed Heat Sink

10 REFT

11 REFB

12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (±5%). 22 VIN+ Analog Input—True. 23 VIN− Analog Input—Complement. 40 CLK+ Clock Input—True. 41 CLK− Clock Input—Complement. 47, 63, 75, 87 DRGND Digital Output Ground. 48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V). 53 D0− (LSB) D0 Complement Output Bit (LVDS Levels). 54 D0+ D0 True Output Bit. 55 D1− D1 Complement Output Bit. 56 D1+ D1 True Output Bit. 57 D2− D2 Complement Output Bit. 58 D2+ D2 True Output Bit. 59 D3− D3 Complement Output Bit. 60 D3+ D3 True Output Bit. 61 D4− D4 Complement Output Bit. 62 D4+ D4 True Output Bit. 65 D5− D5 Complement Output Bit. 66 D5+ D5 True Output Bit. 67 DCO− Data Clock Output—Complement. 68 DCO+ Data Clock Output—True. 69 D6− D6 Complement Output Bit. 70 D6+ D6 True Output Bit. 71 D7− D7 Complement Output Bit. 72 D7+ D7 True Output Bit. 73 D8− D8 Complement Output Bit. 74 D8+ D8 True Output Bit. 77 D9− D9 Complement Output Bit. 78 D9+ D9 True Output Bit. 79 D10− D10 Complement Output Bit. 80 D10+ D10 True Output Bit. 81 D11− D11 Complement Output Bit. 82 D11+ D11 True Output Bit.

AVDD1 3.3 V (±5%) Analog Supply.

AGND

Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable DCS (recommended); DCS = high (AVDD1) to disable DCS.

CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode; OUTPUT MODE = 1 (AVDD1) for LVDS outputs.

Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.

Reference Mode Selection. Connect to AGND for internal 1 V reference; connect to AVDD1 for external reference.

1.0 V Reference I/O. Function dependent on SENSE and external programming resistors. Decouple to ground with 0.1 µF and 10 µF capacitors.

Analog Ground. The exposed heat sink on the bottom of the package must be connected to AGND.

Differential Reference Output. Decoupled to ground with 0.1 µF capacitor and to REFB (Pin 14) with 0.1 µF and 10 µF capacitors.

Differential Reference Output. Decoupled to ground with a 0.1 µF capacitor and to REFT (Pin 13) with 0.1 µF and 10 µF capacitors.

Rev. 0 | Page 11 of 40

AD9445

Pin No. Mnemonic Description

83 D12− D12 Complement Output Bit. 84 D12+ D12 True Output Bit. 85 D13− D13 Complement Output Bit. 86 D13+ (MSB) D13 True Output Bit. 89 OR− Out-of-Range Complement Output Bit. 90 OR+ Out-of-Range True Output Bit. 100 RF ENABLE

RF ENABLE Control Pin. CMOS-compatible control pin to optimize the configuration of the AD9445 analog front end. Connecting RF ENABLE to AGND optimizes SFDR performance for applications with analog input frequencies <210 MHz for 125 MSPS speed grade and <230 MHz for the 105 MSPS speed grade. For applications with analog inputs >225 MHz for the 125 MSPS speed grade and >230 MHz for the 105 MSPS speed grade, this pin should be connected to AVDD1 for optimum SFDR performance. Power dissipation from AVDD2 increases by 150 mW to 200 mW.

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