Analog Devices AD9445 Service Manual

14-Bit, 105/125 MSPS, IF Sampling ADC

FEATURES

125 MSPS guaranteed sampling rate (AD9445BSV-125)

78.3 dBFS SNR/92 dBFS SFDR with 30 MHz input (3.2 V p-p)

74.8 dBFS SNR/95 dBFS SFDR with 30 MHz input (2.0 V p-p)

77.0 dBFS SNR/87 dBFS SFDR with 170 MHz input (3.2 V p-p)

74.6 dBFS SNR/95 dBFS SFDR with 170 MHz input (2.0 V p-p)

73.0 dBFS SNR/88 dBFS SFDR with 300 MHz input (2.0 V p-p)
102 dBFS 2-tone SFDR with 30 MHz and 31 MHz
92 dBFS 2-tone SFDR with 170 MHz and 171 MHz
60 fsec rms jitter
Excellent linearity

DNL = ±0.25 LSB typical
INL = ±0.8 LSB typical

2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output clock available

3.3 V and 5 V supply operation

APPLICATIONS

Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Medical imaging
Communications instrumentation

GENERAL DESCRIPTION

The AD9445 is a 14-bit, monolithic, sampling analog-to-digital
converter (ADC) with an on-chip IF sampling track-and-hold
circuit. It is optimized for performance, small size, and ease of
use. The product operates at up to a 125 MSPS conversion rate
and is designed for multicarrier, multimode receivers, such as
those found in cellular infrastructure equipment.

The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are CMOS or LVDS
compatible (ANSI-644 compatible) and include the means to
reduce the overall current needed for short trace distances.

AD9445

FUNCTIONAL BLOCK DIAGRAM

AGND DRGND DRVDD

AVDD1 AVDD2

2

28

2

RF ENABLE
DFS
DCS MODE
OUTPUT MODE
OR

D13 TO D0

DCO

AD9445

VIN+
VIN–

CLK+
CLK–

BUFFER

CLOCK

AND TIMING

MANAGEMENT

T/H

PIPELINE

VREF

ADC

REF

Figure 1.

14

CMOS

OR

LVDS

OUTPUT

STAGING

REFBSENSE REFT

Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
high IF sampling mode, and output data mode.

The AD9445 is available in a Pb-free, 100-lead, surface-mount,
plastic package (100-lead TQFP/EP) specified over the
industrial temperature range −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. High performance: outstanding SFDR performance for IF

sampling applications such as multicarrier, multimode 3G,
and 4G cellular base station receivers.

2. Ease of use: on-chip reference and high input impedance

track-and-hold with adjustable analog input range and an
output clock simplifies data capture.

3. Packaged in a Pb-free, 100-lead TQFP/EP package.

4. Clock duty cycle stabilizer (DCS) maintains overall ADC

performance over a wide range of clock pulse widths.

5. OR (out-of-range) outputs indicate when the signal is

beyond the selected input range.

6. RF enable pin allows users to configure the device for

optimum SFDR when sampling frequencies above 210 MHz
(AD9445-125) or 240 MHz (AD9445-105).

05489-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD9445

TABLE OF CONTENTS

Features.............................................................................................. 1

Terminology.......................................................................................9

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 6

Switching Specifications.............................................................. 6

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Pin Configurations and Function Descriptions......................... 10

Equivalent Circuits......................................................................... 15

Typical Performance Characteristics........................................... 16

Theory of Operation ...................................................................... 24

Analog Input and Reference Overview ................................... 24

Clock Input Considerations...................................................... 26

Power Considerations................................................................ 27

Digital Outputs........................................................................... 27

Timing ......................................................................................... 27

Operational Mode Selection ..................................................... 28

Evaluation Board............................................................................ 29

Outline Dimensions....................................................................... 37

Ordering Guide .......................................................................... 37

REVISION HISTORY

10/05—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

AD9445

SPECIFICATIONS

DC SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 2.0 V p-p differential input, internal
trimmed reference (1.0 V mode), AIN = −1.0 dBFS, DCS on, unless otherwise noted. RF ENABLE = AGND.

Table 1.

AD9445BSVZ-105 AD9445BSVZ-125
Parameter Te mp Min Typ Max Min Typ Max Unit

RESOLUTION Full 14 14 Bits
ACCURACY

No Missing Codes Full Guaranteed Guaranteed
Offset Error Full −7 +7 −7 +7 mV
25°C ±3 ±3 mV
Gain Error Full −3 +3 −3 +3 % FSR
25°C −2 +2 −2 +2 % FSR
Differential Nonlinearity (DNL)
5 5
Integral Nonlinearity (INL)1 25°C ±0.65 ±0.8 LSB
Full −1.6 +1.6 −2 +2 LSB

VOLTAGE REFERENCE

Output Voltage VREF = 1.0 V Full 0.9 1.0 1.1 0.9 1.0 1.1 V
Load Regulation @ 1.0 mA Full ±2 ±2 mV

Reference Input Current (External VREF = 1.6 V) Full µA
INPUT REFERRED NOISE 25°C 1.0 1.0 LSB rms
ANALOG INPUT

Input Span

VREF = 1.6 V Full 3.2 3.2 V p-p

VREF = 1.0 V Full 2.0 2.0 V p-p
Internal Input Common-Mode Voltage Full 3.5 3.5 V
External Input Common-Mode Voltage Full 3.1
Input Resistance
Input Capacitance

2

2

POWER SUPPLIES

Supply Voltage

AVDD1 Full 3.14 3.3 3.46 3.14 3.3 3.46 V

AVDD2 Full 4.75 5.0 5.25 4.75 5.0 5.25 V

DRVDD—LVDS Outputs Full 3.0

DRVDD—CMOS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 V
Supply Current

1

AVDD1 Full 335 364 384 424 mA

1, 3

AVDD2

1

I

—LVDS Outputs Full 63 78 63 78 mA

DRVDD

1

I

—CMOS Outputs Full 14 14 mA

DRVDD

PSRR

Offset Full 1 1 mV/V

Gain Full 0.2 0.2 %/V

POWER CONSUMPTION

LVDS Outputs Full 2.2 2.4 2.3 2.6 W
CMOS Outputs (DC Input) Full 2.0 2.1 W

1

Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and

approximately 5 pF loading on each output bit for CMOS output mode.

2

Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.

3

For RF ENABLE = AVDD1, I

AVDD2

1

Full −0.6 ±0.25 +0.65 −0.6 ±0.25 +0.65 LSB

Full 1 1 kΩ
Full 6 6 pF

Full 169 196 172 199 mA

increases by ~30 mA, which increases power dissipation.

3.9 3.1 3.9 V

3.6 3.0 3.6 V

Rev. 0 | Page 3 of 40

AD9445

AC SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 2.0 V p-p differential input, internal
trimmed reference (1.0 V mode), A

Table 2.

Parameter Temp

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 10 MHz 25°C 74.3 74.1 dB
fIN = 30 MHz 25°C 73.3 74.3 72.9 73.8 dB
Full 73 72.5 dB
fIN = 170 MHz 25°C 72.9 73.6 72.3 73.2 dB
fIN = 225 MHz

1

Full 72.2 71.4 dB
fIN = 300 MHz
fIN = 400 MHz
fIN = 450 MHz

2

2

2

fIN = 10 MHz (3.2 V p-p Input) 25°C 77.6 77.3 dB
fIN = 30 MHz (3.2 V p-p Input) 25°C 77.5 77.3 dB
fIN = 170 MHz (3.2 V p-p Input) 25°C 76 76 dB
fIN = 225 MHz (3.2 V p-p Input)
fIN = 300 MHz (3.2 V p-p Input)

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 10 MHz 25°C 74.2 73.9 dB
fIN = 30 MHz 25°C 73.2 74.2 72.8 73.7 dB
Full 72.8 72.3 dB
fIN = 170 MHz 25°C 72.3 73.3 72.4 73.0 dB
fIN = 225 MHz

1

Full 71.3 70.7 dB
fIN = 300 MHz
fIN = 400 MHz
fIN = 450 MHz

2

2

2

fIN = 10 MHz (3.2 V p-p Input) 25°C 77.4 76.9 dB
fIN = 30 MHz (3.2 V p-p Input) 25°C 77.3 76.8 dB
fIN = 170 MHz (3.2 V p-p Input) 25°C 75.7 75.4 dB
fIN = 225 MHz (3.2 V p-p Input)
fIN = 300 MHz (3.2 V p-p Input)

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 10 MHz 25°C 12.2 12.2 Bits
fIN = 30 MHz 25°C 12.2 12.1 Bits
fIN = 170 MHz 25°C 12.1 12.0 Bits
fIN = 225 MHz
fIN = 300 MHz
fIN = 400 MHz
fIN = 450 MHz

1

2

2

2

= −1.0 dBFS, DCS on, RF ENABLE = ground, unless otherwise noted.

IN

AD9445BSVZ-105 AD9445BSVZ-125

Min Typ Max Min Typ Max Unit

25°C 72.2 73 72 72.9

25°C 71.4 72.1 71.3 72 dB
25°C 71 71 dB
25°C 70.5 70.5 dB

1

2

25°C 75.3 75.4 dB
25°C 73.7 73.5 dB

25°C 71.4 72.5 71.9 72.5

25°C 70.2 71.7 69.3 71.5 dB
25°C 67.2 66.3 dB
25°C 65.2 64.3 dB

1

2

25°C 75.1 75.2 dB
25°C 72.5 71.8 dB

25°C 12.0 12.0 Bits
25°C 11.8 11.8 Bits
25°C 11.7 11.7 Bits
25°C 11.6 11.6 Bits

dB

dB

Rev. 0 | Page 4 of 40

AD9445

AD9445BSVZ-105 AD9445BSVZ-125

Parameter Temp

SPURIOUS-FREE DYNAMIC RANGE

(SFDR, Second or Third Harmonic)
fIN = 10 MHz 25°C 95 95 dBc
fIN = 30 MHz 25°C 84 92 85 94 dBc
Full 83 82 dBc
fIN = 170 MHz 25°C 82 94 80 91 dBc
fIN = 225 MHz

1

25°C 76 87 83 88
Full 75 75 dBc
fIN = 300 MHz
fIN = 400 MHz
fIN = 450 MHz

2

2

2

25°C 76 87 75 87 dBc

25°C 75 73 dBc

25°C 70 69 dBc

fIN = 10 MHz (3.2 V p-p Input) 25°C 92 92 dBc
fIN = 30 MHz (3.2 V p-p Input) 25°C 88 91 dBc
fIN = 170 MHz (3.2 V p-p Input) 25°C 86 86 dBc
fIN = 225 MHz (3.2 V p-p Input)
fIN = 300 MHz (3.2 V p-p Input)

WORST SPUR EXCLUDING SECOND OR

1

2

25°C 81 80 dBc

25°C 77 76 dBc

THIRD HARMONICS
fIN = 10 MHz 25°C −97 −97 dBc
fIN = 30 MHz 25°C −99 −90 −98 −89 dBc
Full −90 −88 dBc
fIN = 170 MHz 25°C −99 −92 −93 −85 dBc
fIN = 225 MHz

1

25°C −94 −88 −94 −84 dBc
Full −86 −80 dBc
fIN = 300 MHz
fIN = 400 MHz
fIN = 450 MHz

2

2

2

25°C −97 −90 −92 −82 dBc

25°C −93 −93 dBc

25°C −82 −87 dBc

fIN = 10 MHz (3.2 V p-p Input) 25°C −97 −95 dBc
fIN = 30 MHz (3.2 V p-p Input) 25°C −97 −95 dBc
fIN = 170 MHz (3.2 V p-p Input) 25°C −97 −95 dBc
fIN = 225 MHz (3.2 V p-p Input)
fIN = 300 MHz (3.2 V p-p Input)

1

2

25°C −95 −94 dBc

25°C −93 −91 dBc

TWO-TONE SFDR

fIN = 30.3 MHz @ −7 dBFS,

25°C 102 102 dBFS

31.3 MHz @ −7 dBFS

fIN = 170.3 MHz @ −7 dBFS,

25°C 92 91 dBFS

171.3 MHz @ −7 dBFS

ANALOG BANDWIDTH Full 615 615 MHz

1

RF ENABLE = low (AGND ) for AD9445-105; RF ENABLE = high (AVDD1) for AD9445-125.

2

RF ENABLE = high (AVDD1).

Min Typ Max Min Typ Max Unit

dBc

Rev. 0 | Page 5 of 40

AD9445

DIGITAL SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, R

Table 3.

AD9445BSVZ-105 AD9445BSVZ-125
Parameter Te mp Min Typ Max Min Typ Max Unit

CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)

High Level Input Voltage Full 2.0 2.0 V
Low Level Input Voltage Full 0.8 0.8 V
High Level Input Current Full
Low Level Input Current Full −10
Input Capacitance Full

DIGITAL OUTPUT BITS—CMOS MODE (D0 to D13, OTR)

DRVDD = 3.3 V

High Level Output Voltage Full 3.25
Low Level Output Voltage Full

DIGITAL OUTPUT BITS—LVDS MODE (D0 to D13, OTR)

VOD Differential Output Voltage

2

VOS Output Offset Voltage Full 1.125

CLOCK INPUTS (CLK+, CLK−)

Differential Input Voltage Full 0.2
Common-Mode Voltage Full 1.3 1.5 1.6 1.3 1.5 1.6 V
Differential Input Resistance Full 1.1 1.4 1.7 1.1 1.4 1.7 kΩ
Differential Input Capacitance Full

1

Output voltage levels measured with 5 pF load on each output.

2

LVDS R

= 100 Ω.

TERM

= 3.74 kΩ, unless otherwise noted.

LVD S_ BI AS

1

Full 247

200 200 µA
+10 −10 +10 µA

2

0.2 0.2 V

545 247 545 mV

1.375 1.125 1.375 V

2

2 pF

3.25 V

0.2 V

2 pF

SWITCHING SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.

Table 4.

AD9445BSVZ-105 AD9445BSVZ-125
Parameter Te mp Min Typ Max Min Typ Max Unit

CLOCK INPUT PARAMETERS

Maximum Conversion Rate Full 105 125 MSPS
Minimum Conversion Rate Full 10 10 MSPS
CLK Period Full 9.5 8.0 ns
CLK Pulse Width High1 (t
CLK Pulse Width Low1 (t

DATA OUTPUT PARAMETERS

Output Propagation Delay—CMOS (tPD)2 (Dx, DCO+) Full 3.35 3.35 ns
Output Propagation Delay—LVDS (tPD)3 (Dx+), (t
Pipeline Delay (Latency) Full 13 13 Cycles
Aperture Delay (tA) Full
Aperture Uncertainty (Jitter, tJ) Full 60 60

1

With duty cycle stabilizer (DCS) enabled.

2

Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.

3

LVDS R

= 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.

TERM

) Full 3.8 3.2 ns

CLKH

) Full 3.8

CLKL

)3 (DCO+) Full 2.1 3.6 4.8 2.3 3.6 4.8 ns

CPD

3.2 ns

ns

fsec
rms

Rev. 0 | Page 6 of 40

AD9445

TIMING DIAGRAMS

A

CLK+

CLK–

N–1

IN

t

CLKH

t

CLKL

N

N + 1

1/

f

S

t

PD

DATA OUT

DCO+

DCO–

VIN

CLK–

CLK+

DX

DCO+

DCO–

N–1

t

CLKH

N + 1

05489-002

t

CPD

N – 13

13 CLOCK CYCLES

N–12

N

Figure 2. LVDS Mode Timing Diagram

N

N + 1

t

CLKL

t

PD

N – 13 N – 12 N – 1 N

N + 2

13 CLOCK CYCLES

05489-003

Figure 3. CMOS Timing Diagram

Rev. 0 | Page 7 of 40

AD9445

ABSOLUTE MAXIMUM RATINGS

Table 5.

With
Respect

Parameter

ELECTRICAL

AVDD1 AGND −0.3 V to +4 V
AVDD2 AGND −0.3 V to +6 V
DRVDD DGND −0.3 V to +4 V
AGND DGND −0.3 V to +0.3 V
AVDD1 DRVDD −4 V to +4 V
AVDD2 DRVDD −4 V to +6 V
AVDD2 AVDD1 −4 V to +6 V
D0± to D13± DGND –0.3 V to DRVDD + 0.3 V
CLK+/CLK− AGND –0.3 V to AVDD1 + 0.3 V
OUTPUT MODE, DCS

MODE, DFS, SFDR,

RF ENABLE
VIN+, VIN− AGND –0.3 V to AVDD2 + 0.3 V
VREF AGND –0.3 V to AVDD1 + 0.3 V
SENSE AGND –0.3 V to AVDD1 + 0.3 V
REFT, REFB AGND –0.3 V to AVDD1 + 0.3 V

ENVIRONMENTAL

Storage Temperature

Range
Operating Temperature

Range
Lead Temperature

(Soldering 10 sec)
Junction Temperature 150°C

To

AGND –0.3 V to AVDD1 + 0.3 V

–65°C to +125°C

–40°C to +85°C

300°C

Rating

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

The heat sink of the AD9445 package must be soldered to ground.

Table 6.

Package Type θJA θ

100-lead TQFP/EP 19.8 8.3 2 °C/W

Typical θJA = 19.8°C/W (heat sink soldered) for multilayer
board in still air.

Typical θ

= 8.3°C/W (heat sink soldered) for multilayer board

JB

in still air.

Typical θ

= 2°C/W (junction to exposed heat sink) represents

JC

the thermal resistance through heat sink path.

Airflow increases heat dissipation, effectively reducing θ
more metal directly in contact with the package leads from
metal traces through holes, ground, and power planes reduces
the θ

. It is required that the exposed heat sink be soldered to

JA

the ground plane.

θJC Unit

JB

. Also,

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 8 of 40

AD9445

TERMINOLOGY

Analog Bandwidth (Full Power Bandwidth) Minimum Conversion Rate

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.

Aperture Delay (t

) Offset Error

A

The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter, t

)

J

The sample-to-sample variation in aperture delay.

Clock Pulse Width and Duty Cycle

Pulse width high is the minimum amount of time that the
clock pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16,384
codes must be present over all operating ranges.

Effective Number of Bits (ENOB)

The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured
SINAD using the following formula:

ENOB

()

SINAD

=

6.02

1.76−

Gain Error

The first code transition should occur at an analog value of
½ LSB above negative full scale. The last transition should occur
at an analog value of 1½ LSB below the positive full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.

Integral Nonlinearity (INL)

The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.

Maximum Conversion Rate

The clock rate at which parametric testing is performed.

The major carry transition should occur for an analog value of
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.

Output Propagation Delay (tPD)

The delay between the clock rising edge and the time when all
bits are within valid logic levels.

Power-Supply Rejection Ratio

The change in full scale from the value with the supply at the
minimum limit to the value with the supply at the maximum
limit.

Signal-to-Noise and Distortion (SINAD)

The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.

Signal-to-Noise Ratio (SNR)

The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component
may be a harmonic. SFDR can be reported in dBc (that is, degrades
as signal level is lowered) or dBFS (always related back to converter
full scale).

Tem p er at u re Dr i ft

The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at T

MIN

or T

MAX

.

Total Harmonic Distortion (THD)

The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.

Two -Tone SFDR

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.

Rev. 0 | Page 9 of 40

AD9445

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

RF ENABLE99AGND98AGND97AVDD196AVDD195AVDD194AVDD193AVDD192AVDD191AGND90OR+89OR–88DRVDD87DRGND86D13+ (MSB)85D13–84D12+83D12–82D11+81D11–80D10+79D10–78D9+77D9–76DRVDD

100

DNC

DFS

AVDD1
SENSE

VREF

AGND

REFT

REFB
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1

AGND

VIN+
VIN–

AGND

AVDD2

1
2
3
4
5
6
7
8
9

10

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

DCS MODE

OUTPUT MODE

LVDS_BIAS

DNC = DO NOT CONNECT

PIN 1

AD9445

LVDS MODE

TOP VIEW

(Not to Scale)

26

AVDD227AVDD228AVDD229AVDD230AVDD231AVDD232AVDD133AVDD134AVDD135AVDD236AVDD137AVDD238AVDD1

39

40

AGND

41

CLK+

42

CLK–

AGND

Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode

43

AVDD144AVDD145AVDD1

46

47

AGND

48

DRVDD

DRGND

49

DNC50DNC

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DRGND
D8+
D8–
D7+
D7–
D6+
D6–
DCO+
DCO–
D5+
D5–
DRVDD
DRGND
D4+
D4–
D3+
D3–
D2+
D2–
D1+
D1–
D0+
D0– (LSB)
DNC
DNC

05489-004

Rev. 0 | Page 10 of 40

AD9445

Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode

Pin No. Mnemonic Description

1 DCS MODE

2, 49 to 52 DNC Do Not Connect. These pins should float.
3 OUTPUT MODE

4 DFS

5 LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.
6, 18 to 20, 32 to 34, 36, 38,

43 to 45, 92 to 97
7 SENSE

8 VREF

9, 21, 24, 39, 42, 46, 91, 98, 99,
Exposed Heat Sink

10 REFT

11 REFB

12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (±5%).
22 VIN+ Analog Input—True.
23 VIN− Analog Input—Complement.
40 CLK+ Clock Input—True.
41 CLK− Clock Input—Complement.
47, 63, 75, 87 DRGND Digital Output Ground.
48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).
53 D0− (LSB) D0 Complement Output Bit (LVDS Levels).
54 D0+ D0 True Output Bit.
55 D1− D1 Complement Output Bit.
56 D1+ D1 True Output Bit.
57 D2− D2 Complement Output Bit.
58 D2+ D2 True Output Bit.
59 D3− D3 Complement Output Bit.
60 D3+ D3 True Output Bit.
61 D4− D4 Complement Output Bit.
62 D4+ D4 True Output Bit.
65 D5− D5 Complement Output Bit.
66 D5+ D5 True Output Bit.
67 DCO− Data Clock Output—Complement.
68 DCO+ Data Clock Output—True.
69 D6− D6 Complement Output Bit.
70 D6+ D6 True Output Bit.
71 D7− D7 Complement Output Bit.
72 D7+ D7 True Output Bit.
73 D8− D8 Complement Output Bit.
74 D8+ D8 True Output Bit.
77 D9− D9 Complement Output Bit.
78 D9+ D9 True Output Bit.
79 D10− D10 Complement Output Bit.
80 D10+ D10 True Output Bit.
81 D11− D11 Complement Output Bit.
82 D11+ D11 True Output Bit.

AVDD1 3.3 V (±5%) Analog Supply.

AGND

Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to
enable DCS (recommended); DCS = high (AVDD1) to disable DCS.

CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode;
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.

Data Format Select Pin. CMOS control pin that determines the format of the output data.
DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.

Reference Mode Selection. Connect to AGND for internal 1 V reference; connect to
AVDD1 for external reference.

1.0 V Reference I/O. Function dependent on SENSE and external programming resistors.
Decouple to ground with 0.1 µF and 10 µF capacitors.

Analog Ground. The exposed heat sink on the bottom of the package must be
connected to AGND.

Differential Reference Output. Decoupled to ground with 0.1 µF capacitor and to REFB
(Pin 14) with 0.1 µF and 10 µF capacitors.

Differential Reference Output. Decoupled to ground with a 0.1 µF capacitor and to REFT
(Pin 13) with 0.1 µF and 10 µF capacitors.

Rev. 0 | Page 11 of 40

AD9445

Pin No. Mnemonic Description

83 D12− D12 Complement Output Bit.
84 D12+ D12 True Output Bit.
85 D13− D13 Complement Output Bit.
86 D13+ (MSB) D13 True Output Bit.
89 OR− Out-of-Range Complement Output Bit.
90 OR+ Out-of-Range True Output Bit.
100 RF ENABLE

RF ENABLE Control Pin. CMOS-compatible control pin to optimize the configuration of
the AD9445 analog front end. Connecting RF ENABLE to AGND optimizes SFDR
performance for applications with analog input frequencies <210 MHz for 125 MSPS
speed grade and <230 MHz for the 105 MSPS speed grade. For applications with analog
inputs >225 MHz for the 125 MSPS speed grade and >230 MHz for the 105 MSPS speed
grade, this pin should be connected to AVDD1 for optimum SFDR performance. Power
dissipation from AVDD2 increases by 150 mW to 200 mW.

Rev. 0 | Page 12 of 40

AD9445

RF ENABLE99AGND98AGND97AVDD196AVDD195AVDD194AVDD193AVDD192AVDD191AGND90OR89D13 (MSB)88DRVDD87DRGND86D1285D1184D1083D982D881D780D679D578D477D376DRVDD

100

DNC

DFS

AVDD1
SENSE

VREF

AGND

REFT

REFB
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1

AGND

VIN+
VIN–

AGND

AVDD2

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

DCS MODE

OUTPUT MODE

LVDS_BIAS

DNC = DO NOT CONNECT

PIN 1

AD9445

CMOS MODE

TOP VIEW

(Not to Scale)

26

AVDD227AVDD228AVDD229AVDD230AVDD231AVDD232AVDD133AVDD134AVDD135AVDD236AVDD137AVDD238AVDD1

39

40

AGND

41

CLK+

42

CLK–

43

AGND

Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode

AVDD144AVDD145AVDD1

46

47

AGND

48

DRVDD

DRGND

49

DNC50DNC

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DRGND
D2
D1
D0 (LSB)
DNC
DNC
DNC
DCO+
DCO–
DNC
DNC
DRVDD
DRGND
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC

05489-005

Rev. 0 | Page 13 of 40

AD9445

Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode

Pin No. Mnemonic Description

1 DCS MODE

2, 49 to 62, 65 to 66, 69 to 71 DNC Do Not Connect. These pins should float.
3

4 DFS

5 LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.
6, 18 to 20, 32 to 34, 36, 38,

43 to 45, 92 to 97
7 SENSE

8 VREF

9, 21, 24, 39, 42, 46, 91, 98,
99, Exposed Heat Sink

10 REFT

11 REFB

12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (±5%).
22 VIN+ Analog Input—True.
23 VIN− Analog Input—Complement.
40 CLK+ Clock Input—True.
41 CLK− Clock Input—Complement.
47, 63, 75, 87 DRGND Digital Output Ground.
48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).
67 DCO− Data Clock Output—Complement.
68 DCO+ Data Clock Output—True.
72 D0 (LSB) D0 True Output Bit (CMOS levels).
73 D1 D1 True Output Bit.
74 D2 D2 True Output Bit.
77 D3 D3 True Output Bit.
78 D4 D4 True Output Bit.
79 D5 D5 True Output Bit.
80 D6 D6 True Output Bit.
81 D7 D7 True Output Bit.
82 D8 D8 True Output Bit.
83 D9 D9 True Output Bit.
84 D10 D10 True Output Bit.
85 D11 D11 True Output Bit.
86 D12 D12 True Output Bit.
89 D13 (MSB) D13 True Output Bit.
90 OR Out-of-Range True Output Bit.
100 RF ENABLE

OUTPUT
MODE

AVDD1 3.3 V (±5%) Analog Supply.

AGND

Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable
DCS (recommended); DCS = high (AVDD1) to disable DCS.

CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode;
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.

Data Format Select Pin. CMOS control pin that determines the format of the output data.
DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.

Reference Mode Selection. Connect to AGND for internal 1 V reference; connect to AVDD1 for
external reference.

1.0 V Reference I/O. Function dependent on SENSE and external programming resistors.
Decouple to ground with 0.1 µF and 10 µF capacitors.

Analog Ground. The exposed heat sink on the bottom of the package must be connected to
AGND.

Differential Reference Output. Decoupled to ground with 0.1 µF capacitor and to REFB
(Pin 14) with 0.1 µF and 10 µF capacitors.

Differential Reference Output. Decoupled to ground with a 0.1 µF capacitor and to REFT
(Pin 13) with 0.1 µF and 10 µF capacitors.

RF ENABLE CMOS-compatible Control Pin. Optimizes the configuration of the analog front end.
Connecting RF ENABLE to AGND optimizes SFDR performance for applications with analog input
frequencies <210 MHz for 125 MSPS speed grade and <230 MHz for the 105 MSPS speed grade.
For applications with analog inputs >225 MHz for the 125 MSPS speed grade and >230 MHz
for the 105 MSPS speed grade, this pin should be connected to AVDD1 for optimum SFDR.
Power dissipation from AVDD2 increases by 150 mW to 200 mW.

Rev. 0 | Page 14 of 40

AD9445

EQUIVALENT CIRCUITS

AVDD2

VIN+

VIN–

3.5V

6pF

6pF

X1

AVDD2

1k

Ω

1k

Ω

Figure 6. Equivalent Analog Input Circuit

DRVDD DRVDD

1.2V

LVDS_BIAS

3.74k

Ω

I

LVDSOUT

Figure 7. Equivalent LVDS_BIAS Circuit

T/H

DRVDD

DX

05489-006

05489-009

Figure 9. Equivalent CMOS Digital Output Circuit

VDD

K

05489-007

RF ENABLE, DCS

MODE, OUTPUT

MODE, DFS

30kΩ

05489-010

Figure 10. Equivalent Digital Input Circuit,

DFS, DCS MODE, OUTPUT MODE

AVDD2

DRVDD

3k

V

DX– DX+

V

V

V

05489-008

Figure 8. Equivalent LVDS Digital Output Circuit

CLK+

Ω

2.5k

Ω

Figure 11. Equivalent Sample Clock Input Circuit

3k

Ω

CLK–

2.5k

Ω

05489-011

Rev. 0 | Page 15 of 40

AD9445

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, rated sample rate, LVDS mode, DCS enabled, TA = 25°C, 2.0 V p-p differential
input, AIN = −1.0 dBFS, internal trimmed reference (nominal VREF = 1.0 V), unless otherwise noted.

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0 62.500

15.625 31.250 46.875
FREQUENCY (MHz)

125MSPS

30.3MHz @ –1.0dBFS
SNR = 73.4dB
ENOB = 12.1BITS
SFDR = 94dBc

05489-012

Figure 12. AD9445-125 64k Point Single-Tone FFT/125 MSPS/30.3 MHz Figure 15. AD9445-125 64k Point Single-Tone FFT/125 MSPS/225.3 MHz

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0 62.500

15.625 31.250 46.875
FREQUENCY (MHz)

125MSPS

225.3MHz @ –1.0dBFS
SNR = 72.9dB
ENOB = 12.1BITS
SFDR = 88dBc

05489-015

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0 62.500

15.625 31.250 46.875
FREQUENCY (MHz)

125MSPS

100.3MHz @ –1.0dBFS
SNR = 0dB
ENOB = 12.1BITS
SFDR = 96dBc

05489-013

0

125MSPS

–10

300.3MHz @ –1.0dBFS
SNR = 72.0dB

–20

ENOB = 11.8BITS
SFDR = 87dBc

–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90
–100
–110
–120
–130

0 62.500

15.625 31.250 46.875
FREQUENCY (MHz)

05489-016

Figure 13. AD9445-125 64k Point Single-Tone FFT/125 MSPS/100.3 MHz Figure 16. AD9445-125 64k Point Single-Tone FFT/125 MSPS/300.3 MHz

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0 62.500

15.625 31.250 46.875
FREQUENCY (MHz)

125MSPS

170.3MHz @ –1.0dBFS
SNR = 73.2dB
ENOB = 12.0BITS
SFDR = 91dBc

05489-014

0

125MSPS

–10

450.3MHz @ –1.0dBFS
SNR = 70.5dB

–20

ENOB = 11.6BITS
SFDR = 69dBc

–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90
–100
–110
–120
–130

0 62.500

15.625 31.250 46.875
FREQUENCY (MHz)

05489-017

Figure 14. AD9445-125 64k Point Single-Tone FFT/125 MSPS/170.3 MHz Figure 17. AD9445-125 64k Point Single-Tone FFT/125 MSPS/450.3 MHz

Rev. 0 | Page 16 of 40

AD9445

100

95

90

85

SNR +25°C

80

(dB)

75

70

65

60

55

0 50 100 150 200 250 300 350 400 450

SNR +85°C

ANALOG INPUT FREQUENCY (MHz)

SFDR +85°C

SFDR +25°C

SFDR –40°C

SNR –40°C

Figure 18. AD9445-125 SNR/SFDR vs. Analog Input Frequency,

125 MSPS, 2.0 V p-p Input Range

05489-018

100

95

90

85

80

(dB)

75

70

65

60

55

0 50 100 150 200 250 300 350 400 450

SFDR –40°C

SNR +25°C

ANALOG INPUT FREQUENCY (MHz)

SFDR +85°C

SFDR +25°C

SNR –40°C

SNR +85°C

Figure 21. AD9445-125 SNR/SFDR vs. Analog Input Frequency,

125 MSPS, 3.2 V p-p Input Range

05489-021

100

95

90

85

SNR +25°C

80

(dB)

75

70

65

60

55

0 100

SFDR +25°C

SNR –40°C

SNR +85°C

20 30 40 50 60 70 80 90

10

ANALOG INPUT FREQUENCY (MHz)

SFDR +85°C

SFDR –40°C

Figure 19. AD9445-125 SNR/SFDR vs. Analog Input Frequency,

3.2 V p-p Input Range, 125 MSPS, CMOS Output Mode

(dB)

120

100

80

60

SFDR dBFS

SNR dBFS

105

125M SFDR dBc

100

95

90

(dB)

85

80

75

05489-019

70

0

105M SFDR dBc

125M SNR dB

105M SNR dB

20 40 60 80 100 120 140

SAMPLE RATE (MSPS)

Figure 22. AD9445 Single-Tone SNR/SFDR vs. Sample Rate 2.3 MHz

120

SFDR dBFS

100

80

SNR dBFS

60

(dB)

05489-022

40

SFDR dBc

20

0

–90 –80 –70 –60 –50 –40 –30 –20 –10

–100 0

SNR dB

ANALOG INPUT AMPLITUDE (dB)

Figure 20. AD9445-125 SNR/SFDR vs. Analog Input Level,

125 MSPS/225.3 MHz

40

20

05489-020

0
–100 0

SFDR dBc

SNR dB

–90 –80 –70 –60 –50 –40 –30 –20 –10

ANALOG INPUT AMPLITUDE (dB)

Figure 23. AD9445-125 SNR/SFDR vs. Analog Input Level,

125 MSPS/225.3 MHz, CMOS Output Mode

Rev. 0 | Page 17 of 40

05489-023

AD9445

0

105MSPS

–10

30.3MHz @ –1.0dBFS
SNR = 74.3dB

–20

ENOB = 12.2BITS
SFDR = 92dBc

–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90
–100
–110
–120
–130

0 52.500

13.125 26.250 39.375
FREQUENCY (MHz)

05489-024

Figure 24. AD9445-105 64k Point Single-Tone FFT/105 MSPS/30.3 MHz Figure 27. AD9445-105 64k Point Single-Tone FFT/105 MSPS/225.3 MHz

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0 52.500

13.125 26.250 39.375
FREQUENCY (MHz)

105MSPS

225.3MHz @ –1.0dBFS
SNR = 73.0dB
ENOB = 12.0BITS
SFDR = 87dBc

05489-027

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0 52.500

13.125 26.250 39.375
FREQUENCY (MHz)

105MSPS

100.3MHz @ –1.0dBFS
SNR = 73.5dB
ENOB = 11.8BITS
SFDR = 93dBc

05489-025

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0 52.500

13.125 26.250 39.375
FREQUENCY (MHz)

105MSPS

300.3MHz @ –1.0dBFS
SNR = 72.1dB
ENOB = 11.8BITS
SFDR = 87dBc

05489-028

Figure 25. AD9445-105 64k Point Single-Tone FFT/105 MSPS/100.3 MHz Figure 28. AD9445-105 64k Point Single-Tone FFT/105 MSPS/300.3 MHz

0

105MSPS

–10

170.3MHz @ –1.0dBFS
SNR = 73.6dB

–20

ENOB = 12.1BITS
SFDR = 94dBc

–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90
–100
–110
–120
–130

0 52.500

13.125 26.250 39.375
FREQUENCY (MHz)

05489-026

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0 52.500

13.125 26.250 39.375
FREQUENCY (MHz)

105MSPS

450.3MHz @ –1.0dBFS
SNR = 70.5dB
ENOB = 11.6BITS
SFDR = 70dBc

05489-029

Figure 26. AD9445-105 64k Point Single-Tone FFT/105 MSPS/170.3 MHz Figure 29. AD9445-105 64k Point Single-Tone FFT/105 MSPS/450.3 MHz

Rev. 0 | Page 18 of 40

AD9445

(dB)

100

95

90

85

80

75

70

65

60

55

SFDR +25°C

SNR +85°C

0 50 100 150 200 250 300 350 400 450

ANALOG INPUT FREQUENCY (MHz)

SFDR –40°C

SFDR +85°C

SNR –40°C

SNR +25°C

Figure 30. AD9445-105 SNR/SFDR vs. Analog Input Frequency,

105 MSPS, 2.0 V p-p

05489-030

100

95

SFDR +25°C

SFDR –40°C

SNR –40°C

SNR +85°C

(dB)

90

85

80

75

70

65

60

55

SFDR +85°C

SNR +25°C

0 50 100 150 200 250 300 350 400 450

ANALOG INPUT FREQUENCY (MHz)

Figure 33. AD9445-105 SNR/SFDR vs. Analog Input Frequency,

105 MSPS, 3.2 V p-p

05489-033

100

95

90

85

80

SNR –40°C

(dB)

75

70

SNR +25°C

65

60

55

20 40 60 80 100 120 140 160

0 180

ANALOG INPUT FREQUENCY (MHz)

SFDR +25°C

SNR +85°C

SFDR +85°C

SFDR –40°C

Figure 31. AD9445-105 SNR/SFDR vs. Analog Input Frequency,

3.2 V p-p Input Range, 105 MSPS, CMOS Output Mode

120

SFDR dBFS

100

80

SNR dBFS

60

(dB)

05489-031

100

95

90

85

80

(dB)

75

70

65

60

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3
ANALOG INPUT COMMON-MODE VOLTAGE

SFDR dBc

SNR dB

Figure 34. AD9445-105 SNR/SFDR vs. Analog Input Common Mode,

105 MSPS/10.3 MHz

120

SFDR dBFS

100

80

SNR dBFS

60

(dB)

05489-034

40

20

SFDR dBc

0

–90 –80 –70 –60 –50 –40 –30 –20 –10

–100 0

SNR dB

ANALOG INPUT AMPLITUDE (dB)

Figure 32. AD9445-105 SNR/SFDR vs. Analog Input Level,

105 MSPS/225.3 MHz

05489-032

Rev. 0 | Page 19 of 40

40

SFDR dBc

20

0

–90 –80 –70 –60 –50 –40 –30 –20 –10

–100 0

SNR dB

ANALOG INPUT AMPLITUDE (dB)

Figure 35. AD9445-105 SNR/SFDR vs. Analog Input Level,

105 MSPS/225.3 MHz, CMOS Output Mode

05489-035

AD9445

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

AMPLITUDE (dBFS)

–100
–110
–120
–130
–140

0 54.500

125MSPS

30.3MHz @ –7.0dBFS

31.3MHz @ –7.0dBFS
SFDR = 102dBFS

13.625 27.250 40.875
FREQUENCY (MHz)

Figure 36. AD9445-125 64k Point Two-Tone FFT/

125 MSPS/30.3 MHz, 31.3 MHz

0
–10
–20
–30
–40

WORST IMD3 dBc

–50
–60
–70
–80

SPUR AND IMD3 (dB)

05489-037

–90

–100
–110
–120

SFDR dBFS

WORST IMD3 dBFS

–90 –80 –70 –60 –50 –40 –30 –20 –10

–100 0

SFDR dBc

FUNDAMENTAL LEVEL (dB)

Figure 39. AD9445-125 Two-Tone SFDR vs. Analog Input Level

125 MSPS/170.3 MHz, 171.3 MHz

05489-041

0
–10
–20
–30
–40
–50
–60
–70
–80

SPUR AND IMD3 (dB)

–90

–100
–110
–120

–100 0

WORST IMD3 dBc

SFDR dBFS

–90 –80 –70 –60 –50 –40 –30 –20 –10

SFDR dBc

WORST IMD3 dBFS

FUNDAMENTAL LEVEL (dB)

Figure 37. AD9445-125 Two-Tone SFDR vs. Analog Input Level

125 MSPS/30.3 MHz, 31.3 MHz

0

125MSPS

–10

170.3MHz @ –7.0dBFS

171.3MHz @ –7.0dBFS

–20

SFDR = 91dBFS

–30
–40
–50
–60
–70
–80
–90

AMPLITUDE (dBFS)

–100
–110
–120
–130
–140

0 54.500

13.625 27.250 40.875
FREQUENCY (MHz)

Figure 38. AD9445-125 64k Point Two-Tone FFT/

125 MSPS/170.3 MHz, 171.3 MHz

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

AMPLITUDE (dBFS)

–100
–110
–120

05489-038

–130
–140

0 52.50013.125 26.250 39.375

0

FREQUENCY (MHz)

105MSPS

30.3MHz @ –7.0dBFS

31.3MHz @ –7.0dBFS
SFDR = 102dBFS

Figure 40. AD9445-105 64k Point Two-Tone FFT/105 MSPS/30.3 MHz, 31.3 MHz

0
–10
–20
–30
–40
–50
–60
–70
–80

SPUR AND IMD3 (dB)

–90

–100

05489-040

–110
–120

–100 0

WORST IMD3 dBc

SFDR dBFS

WORST IMD3 dBFS

–90 –80 –70 –60 –50 –40 –30 –20 –10

FUNDAMENTAL LEVEL (dB)

SFDR dBc

Figure 41. AD9445-105 Two-Tone SFDR vs. Analog Input Level

105 MSPS/30.3 MHz, 31.3 MHz

05489-042

05489-043

Rev. 0 | Page 20 of 40

AD9445

25000

20000

23754

22190

30000

25000

26294

SAMPLE SIZE = 65538

15000

10000

FREQUENCY

5000

62

0

N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3

7968

1127

OUTPUT CODE

9003

1355

75

2

05489-044

N + 4

Figure 42. AD9445-125 Grounded Input Histogram Figure 45. AD9445-105 Grounded Input Histogram

0

105MSPS

–10

170.3MHz @ –7.0dBFS

171.3MHz @ –7.0dBFS

–20

SFDR = 92dBFS

–30
–40
–50
–60
–70
–80
–90

AMPLITUDE (dBFS)

–100
–110
–120
–130
–140

0 52.50013.125 26.250 39.375

0

FREQUENCY (MHz)

05489-045

Figure 43. AD9445-105 64k Point Two-Tone FFT/105 MSPS/170.3 MHz, 171.3 MHz

20000

15000

FREQUENCY

10000

5000

307

3

0

N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3

0

–0.1

–0.2

–0.3

–0.4

–0.5

GAIN ERROR (%FSR)

–0.6

–0.7

–0.8

–40

–20 0 20 40 60 80

15743

3350

OUTPUT CODE

TEMPERATURE (°C)

Figure 46. AD9445-125 Gain vs. Temperature

16117

3493

227

2

N + 4

05489-047

05489-048

0
–10
–20
–30
–40
–50

WORST IMD3 dBc

–60
–70
–80

SPUR AND IMD3 (dB)

–90

–100
–110
–120

–100 0

SFDR dBFS

WORST IMD3 dBFS

–90 –80 –70 –60 –50 –40 –30 –20 –10

SFDR dBc

FUNDAMENTAL LEVEL (dB)

Figure 44. AD9445-105 Two-Tone SFDR vs. Analog Input Level

105 MSPS/170.3 MHz, 171.3 MHz

05489-046

Rev. 0 | Page 21 of 40

0.4

0.3

0.2

0.1

0

–0.1

DNL ERROR (LSB)

–0.2

–0.3

–0.4

0

0 16384

4096 8192 12288

OUTPUT CODE

Figure 47. AD9445-105 DNL Error vs. Output Code, 105 MSPS, 10.3 MHz

05489-049

AD9445

0.4

0.3

0.2

0.1

0

–0.1

DNL ERROR (LSB)

–0.2

–0.3

–0.4

0

0 16384

4096 8192 12288

OUTPUT CODE

05489-050

Figure 48. AD9445-125 DNL Error vs. Output Code, 125 MSPS, 10.3 MHz Figure 51. AD9445-125 INL Error vs. Output Code, 125 MSPS, 10.3 MHz

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0

0 163844096 8192 12288

OUTPUT CODE

05489-053

1.014

1.012

1.010

1.008

VREF

1.006

1.004

1.002
–40

–20 0 20 40 60 80

TEMPERATURE (°C)

Figure 49. AD9445-125 VREF vs. Temperature

0.5

0.4

0.3

0.2

0.1

0

–0.1

INL ERROR (LSB)

–0.2

–0.3

–0.4

–0.5

0

0 163844096 8192 12288

OUTPUT CODE

Figure 50. AD9445-105 INL Error vs. Output Code, 105 MSPS, 10.3 MHz

05489-051

05489-052

400

350

(mA)

SUPPLY

I

300

250

200

150

100

AVDD1

AVDD2

DRVDD

50

0

20 40 60 80 100 120 140

0

SAMPLE RATE (MSPS)

160

05489-066

Figure 52. AD9445-105 Power Supply Current vs. Sample Rate

10.3 MHz @ −1 dBFS

78

(dB)

77

76

75

74

73

72

71

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

1.8
ANALOG INPUT RANGE (V p-p)

170.3MHz SNR dB

225.3MHz SNR dB

300.3MHz SNR dB

4.2

05489-067

Figure 53. AD9445-125 SNR vs. Analog Input Range, 125 MSPS/170.3 MHz,

225.3 MHz, 300.3 MHz

Rev. 0 | Page 22 of 40

AD9445

78

95

(dB)

77

76

75

74

73

72

71

1.8
ANALOG INPUT RANGE (V p-p)

170.3MHz SFDR dBc

225.3MHz SFDR dBc

300.3MHz SFDR dBc

Figure 54. AD9445-105 SNR vs. Analog Input Range,

105 MSPS/170.3 MHz, 225.3 MHz, 300.3 MHz

400

350

(mA)

SUPPLY

I

300

250

200

150

100

AVDD1

AVDD2

DRVDD

50

0

20 40 60 80 100 120 140

0

SAMPLE RATE (MSPS)

Figure 55. AD9445-125 Power Supply Current vs. Sample Rate

10.3 MHz @ −1 dBFS

90

170.3MHz SFDR dBc

85

(dB)

80

75

05489-068

4.22.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

70

1.8
ANALOG INPUT RANGE (V p-p)

225.3MHz SFDR dBc

300.3MHz SFDR dBc

Figure 57. AD9445-105 SFDR vs. Analog Input Range,

105 MSPS/170.3 MHz, 225.3 MHz, 300.3 MHz

81

80

79

78

(dB)

77

76

75

160

05489-069

74

105M SNR dBFS

125M SNR dBFS

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

1.8 4.2
ANALOG INPUT RANGE (V p-p)

Figure 58. SNR vs. Analog Input Range, 2.3 MHz @ −30 dBFS

05489-071

4.22.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

05489-039

95

(dB)

90

85

80

75

70

1.8
ANALOG INPUT RANGE (V p-p)

170.3MHz SFDR dBc

225.3MHz SFDR dBc

300.3MHz SFDR dBc

05489-070

4.22.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

Figure 56. AD9445-125 SFDR vs. Analog Input Range, 125 MSPS/170.3 MHz,

225.3 MHz, 300.3 MHz

Rev. 0 | Page 23 of 40

AD9445

THEORY OF OPERATION

The AD9445 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated, high bandwidth
track-and-hold circuit that samples the signal prior to quantization
by the 14-bit pipeline ADC core. The device includes an on-board
reference and input logic that accepts TTL, CMOS, or LVPECL
levels. The digital output logic levels are user selectable as standard
3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT
MODE pin.

ANALOG INPUT AND REFERENCE OVERVIEW

A stable and accurate 0.5 V band gap voltage reference is built
into the AD9445. The input range can be adjusted by varying
the reference voltage applied to the AD9445, using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly.

Internal Reference Connection

A comparator within the AD9445 detects the potential at the
SENSE pin and configures the reference into three possible states,
which are summarized in
reference amplifier switch is connected to the internal resistor
divider (see

Figure 59), setting VREF to ~1.0 V. Connecting the
SENSE pin to VREF switches the reference amplifier output to
the SENSE pin, completing the loop and providing a ~1.0 V
reference output. If a resistor divider is connected as shown in
Figure 60, the switch again sets to the SENSE pin. This puts the
reference amplifier in a noninverting mode with the VREF
output defined as

VVREF 15.0

In all reference configurations, REFT and REFB drive the
analog-to-digital conversion core and establish its input span.
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.

Internal Reference Trim

The internal reference voltage is trimmed during the production
test to adjust the gain (analog input voltage range) of the AD9445.
Therefore, there is little advantage to the user supplying an external
voltage reference to the AD9445. The gain trim is performed
with the AD9445 input range set to 2.0 V p-p nominal (SENSE

Table 9. Reference Configuration Summary

Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p)

External Reference AVDD1 N/A 2 × external reference
Programmable Reference 0.2 V to VREF

Internal Fixed Reference AGND to 0.2 V 1.0 2.0

Tabl e 9 . If SENSE is grounded, the

R2

⎞

⎛

+×=

⎟

⎜

R1

⎠

⎝

R2

⎛

+×

10.5

⎜

R1

⎝

connected to AGND). Because of this trim and the maximum ac
performance provided by the 2.0 V p-p analog input range, there
is little benefit to using analog input ranges <2 V p-p. Users are
cautioned that the differential nonlinearity of the ADC varies
with the reference voltage. Configurations that use <2.0 V p-p
may exhibit missing codes and, therefore, degraded noise and
distortion performance.

VIN+

10μF+0.1μF

10μF+0.1μF

⎞

(See Figure 60)

⎟
⎠

VIN–

ADC

CORE

VREF

SELECT

LOGIC

SENSE

0.5V

AD9445

Figure 59. Internal Reference Configuration

VIN+

VIN–

VREF

R2

SENSE

R1

Figure 60. Programmable Reference Configuration

SELECT

LOGIC

0.5V

AD9445

2 × VREF

ADC

CORE

REFT

0.1μF

0.1μF 10μF

REFB

0.1μF

REFT

0.1μF

0.1μF 10μF

REFB

0.1μF

+

05489-054

+

05489-055

Rev. 0 | Page 24 of 40

AD9445

External Reference Operation

The AD9445’s internal reference is trimmed to enhance the gain
accuracy of the ADC. An external reference may be more stable
over temperature, but the gain of the ADC is not likely to improve.
Figure 49 shows the typical drift characteristics of the internal
reference in both 1 V and 0.5 V modes.

1V p-p

VIN+

3.5V

When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1.6 V.

Analog Inputs

As with most new high speed, high dynamic range ADCs, the
analog input to the AD9445 is differential. Differential inputs
improve on-chip performance because signals are processed
through attenuation and gain stages. Most of the improvement
is a result of differential analog stages having high rejection of
even-order harmonics. There are also benefits at the PCB level.
First, differential inputs have high common-mode rejection of
stray signals, such as ground and power noise. Second, they
provide good rejection of common-mode signals, such as local
oscillator feedthrough. The specified noise and distortion of the
AD9445 cannot be realized with a single-ended analog input, so
such configurations are discouraged. Contact sales for
recommendations of other 14-bit ADCs that support single­ended analog input configurations.

With the 1 V reference, which is the nominal value (see the
Internal Reference Trim section), the differential input range of
the AD9445 analog input is nominally 2.0 V p-p or 1.0 V p-p on
each input (VIN+ or VIN−).

The AD9445 analog input voltage range is offset from ground
by 3.5 V. Each analog input connects through a 1 kΩ resistor to
the 3.5 V bias voltage and to the input of a differential buffer.
The internal bias network on the input properly biases the
buffer for maximum linearity and range (see the
Circuits

section).

Equivalent

VIN–

DIGITAL OUT = ALL 1s DIGITAL OUT = ALL 0s

Figure 61. Differential Analog Input Range for VREF = 1.0 V

Therefore, the analog source driving the AD9445 should be ac­coupled to the input pins. The recommended method for driving
the analog input of the AD9445 is to use an RF transformer to
convert single-ended signals to differential (see

Figure 62).
Series resistors between the output of the transformer and the
AD9445 analog inputs help isolate the analog input source from
switching transients caused by the internal sample-and-hold
circuit. The series resistors, along with the 1 kΩ resisters connected
to the internal 3.5 V bias, must be considered in impedance
matching the transformer input. For example, if R
51 Ω, R

is set to 33 Ω, and there is a 1:1 impedance ratio trans-

S

is set to

T

former, the input will match a 50 Ω source with a full-scale drive
of 10.0 dBm. The 50 Ω impedance matching can also be incor­porated on the secondary side of the transformer, as shown in

0.1

μF

Figure 67).

R

S

VIN+

AD9445

R

S

VIN–

05489-057

the evaluation board schematic (see

R

T

ADT1–1WT

ANALOG

INPUT

SIGNAL

Figure 62. Transformer-Coupled Analog Input Circuit

High IF Applications

In applications where the analog input frequency range is
>100 MHz, the phase and amplitude matching at the analog
inputs becomes critical to optimize performance of the ADC.
The circuit in

Figure 63 can be used to optimize the matching of
these parameters. This configuration uses a double balun config­uration that has low parasitics, high bandwidth, and parasitic
cancellation.

ETC1–1–13ETC1–1–13

33

Ω

VIN+

AD9445

33

Ω

μF

VIN–

50

SOURCE

25

Ω

CT

Ω

Figure 63. Double Balun-Coupled Analog Input Circuit

0.1μF
25

0.1

Ω

05489-056

05489-058

Rev. 0 | Page 25 of 40

AD9445

CLOCK INPUT CONSIDERATIONS

Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the analog-to­digital output. For that reason, considerable care was taken in
the design of the clock inputs of the AD9445, and the user is
advised to give careful thought to the clock source.

Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be
sensitive to the clock duty cycle. Commonly a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics. The AD9445 contains a clock duty
cycle stabilizer (DCS) that retimes the nonsampling edge,
providing an internal clock signal with a nominal 50% duty
cycle. Noise and distortion performance are nearly flat for a
30% to 70% duty cycle with the DCS enabled. The DCS circuit
locks to the rising edge of CLK+ and optimizes timing
internally. This allows for a wide range of input duty cycles at
the input without degrading performance. Jitter in the rising
edge of the input is still of paramount concern and is not
reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates of less than
30 MHz nominally. The loop is associated with a time constant
that should be considered in applications where the clock rate
can change dynamically, requiring a wait time of 1.5 μs to 5 μs
after a dynamic clock frequency increase or decrease before the
DCS loop is relocked to the input signal. During the time that
the loop is not locked, the DCS loop is bypassed, and the internal
device timing is dependent on the duty cycle of the input clock
signal. In such an application, it may be appropriate to disable
the duty cycle stabilizer. In all other applications, enabling the
DCS circuit is recommended to maximize ac performance.

The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the duty cycle
stabilizer, and logic high (AVDD1 = 3.3 V) disables the
controller.

The AD9445 input sample clock signal must be a high quality,
extremely low phase noise source to prevent degradation of
performance. Maintaining 14-bit accuracy places a premium on
the encode clock phase noise. SNR performance can easily
degrade by 3 dB to 4 dB with 70 MHz analog input signals
when using a high jitter clock source. (See the

Application Note

Performance

, Aperture Uncertainty and ADC System

.) For optimum performance, the AD9445 must be
clocked differentially. The sample clock inputs are internally
biased to ~2.2 V, and the input signal is usually ac-coupled into
the CLK+ and CLK− pins via a transformer or capacitors.
Figure 64 shows one preferred method for clocking the
AD9445. The clock source (low jitter) is converted from single­ended to differential using an RF transformer. The back-to-back

AN-501

Schottky diodes across the secondary of the transformer limit
clock excursions into the AD9445 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9445
and limits the noise presented to the sample clock inputs.

If a low jitter clock is available, it may help to band-pass filter
the clock reference before driving the ADC clock inputs.
Another option is to ac couple a differential ECL/PECL signal
to the encode input pins, as shown in Figure 65.

CLOCK

SOURCE

Figure 64. Crystal Clock Oscillator, Differential Encode

ECL/

PECL

ADT1–1WT

0.1

μF

HSMS2812

DIODES

VT

0.1

μF

0.1μF

VT

Figure 65. Differential ECL for Encode

CLK+

AD9445

CLK–

ENCODE

AD9445

ENCODE

05489-060

05489-059

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input

f

frequency (

t

) can be calculated using the following equation:

(

J

SNR = 20 log[2πf

) and rms amplitude due only to aperture jitter

INPUT

× tJ]

INPUT

In the equation, the rms aperture jitter represents the root­mean-square of all jitter sources, which includes the clock
input, analog input signal, and ADC aperture jitter
specification. IF undersampling applications are particularly
sensitive to jitter, see

Figure 66.

The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9445. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or another
method), it should be synchronized by the original clock during
the last step.

Rev. 0 | Page 26 of 40

AD9445

75

70

65

60

55

SNR (dBc)

50

45

40

1

Figure 66. SNR vs. Input Frequency and Jitter

INPUT FREQUENCY (MHz)

0.2ps

0.5ps

1.0ps

1.5ps

2.0ps

2.5ps

3.0ps

100010010

05489-061

POWER CONSIDERATIONS

Care should be taken when selecting a power source. The use of
linear dc supplies is highly recommended. Switching supplies
tend to have radiated components that may be received by the
AD9445. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1 μF chip capacitors.

The AD9445 has separate digital and analog power supply pins.
The analog supplies are denoted AVDD1 (3.3 V) and AVDD2
(5 V), and the digital supply pins are denoted DRVDD. Although
the AVDD1 and DRVDD supplies can be tied together, best
performance is achieved when the supplies are separate. This is
because the fast digital output swings can couple switching
current back into the analog supplies. Note that both AVDD1
and AVDD2 must be held within 5% of the specified voltage.

The DRVDD supply of the AD9445 is a dedicated supply for the
digital outputs in either LVDS or CMOS output mode. When in
LVDS mode, the DRVDD should be set to 3.3 V. In CMOS
mode, the DRVDD supply can be connected from 2.5 V to

3.6 V for compatibility with the receiving logic.

DIGITAL OUTPUTS

LVDS Mode

The off-chip drivers on the chip can be configured to provide
LVDS-compatible output levels via Pin 3 (OUTPUT MODE).
LVDS outputs are available when OUTPUT MODE is CMOS
logic high (or AVDD1 for convenience) and a 3.74 kΩ R

SET

resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic
performance, including both SFDR and SNR, is maximized
when the AD9445 is used in LVDS mode; designers are
encouraged to take advantage of this mode. The AD9445
outputs include complimentary LVDS outputs for each data bit
(Dx+/Dx−), the overrange output (OR+/OR−), and the output
data clock output (DCO+/DCO−). The R

resistor current is

SET

multiplied on-chip, setting the output current at each output
equal to a nominal 3.5 mA (11 × I

). A 100 Ω differential

R

SET

termination resistor placed at the LVDS receiver inputs results
in a nominal 350 mV swing at the receiver. LVDS mode
facilitates interfacing with LVDS receivers in custom ASICs and
FPGAs that have LVDS capability for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended, with a 100 Ω termination resistor
placed as close to the receiver as possible. It is recommended to
keep the trace length less than 2 inches and to keep differential
output trace lengths as equal as possible.

CMOS Mode

In applications that can tolerate a slight degradation in dynamic
performance, the AD9445 output drivers can be configured to
interface with 2.5 V or 3.3 V logic families by matching
DRVDD to the digital supply of the interfaced logic. CMOS
outputs are available when OUTPUT MODE is CMOS logic
low (or AGND for convenience). In this mode, the output data
bits, Dx, are single-ended CMOS, as is the overrange output,
OR. The output clock is provided as a differential CMOS signal,
DCO+/DCO−. Lower supply voltages are recommended to
avoid coupling switching transients back to the sensitive analog
sections of the ADC. The capacitive load to the CMOS outputs
should be minimized, and each output should be connected to a
single gate through a series resistor (220 Ω) to minimize
switching transients caused by the capacitive loading.

TIMING

The AD9445 provides latched data outputs with a pipeline delay
of 13 clock cycles. Data outputs are available one propagation
delay (t

) after the rising edge of CLK+. Refer to

PD

Figure 3 for detailed timing diagrams.

Figure 2 and

Rev. 0 | Page 27 of 40

AD9445

OPERATIONAL MODE SELECTION

Data Format Select

The data format select (DFS) pin of the AD9445 determines
the coding format of the output data. This pin is 3.3 V CMOS­compatible, with logic high (or AVDD1, 3.3 V) selecting twos
complement and DFS logic low (AGND) selecting offset binary

Tabl e 1 0 summarizes the output coding.

format.

Output Mode Select

The OUPUT MODE pin controls the logic compatibility, as well
as the pinout of the digital outputs. This pin is a CMOS-compatible
input. With OUTPUT MODE = 0 (AGND), the AD9445 outputs
are CMOS compatible, and the pin assignment for the device is
as defined in
V), the AD9445 outputs are LVDS compatible, and the pin
assignment for the device is as defined in

Duty Cycle Stabilizer

The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the DCS, and logic
high (AVDD1, 3.3 V) disables the controller.

Table 10. Digital Output Coding

Code

16,383 +1.600 +1.000 11 1111 1111 1111 01 1111 1111 1111
8192 0 0 10 0000 0000 0000 00 0000 0000 0000
8191 −0.000195 −0.000122 01 1111 1111 1111 11 1111 1111 1111
0 −1.60 −1.00 00 0000 0000 0000 10 0000 0000 0000

Tabl e 8 . With OUTPUT MODE = 1 (AVDD1, 3.3

Tabl e 7.

VIN+ − VIN−
Input Span = 3.2 V p-p (V)

VIN+ − VIN−
Input Span = 2 V p-p (V)

RF ENABLE

The RF ENABLE pin is a CMOS-compatible control pin that
optimizes the configuration of the AD9445 analog front end.
The crossover analog input frequency for determining the
RF ENABLE connection differs for the 105 MSPS and 125 MSPS
speed grades. For the 125 MSPS speed grade, connecting the
RF ENABLE to AGND optimizes SFDR performance for appli­cations with analog input frequencies <210 MHz. For applications
with analog inputs >210 MHz, this pin should be connected to
AVDD1 for optimum SFDR performance. Connecting this pin to
AVDD1 reconfigures the ADC, thereby improving high IF and RF
spurious performance. Operating in this mode increases power dis­sipation from AVDD2 by 150 mW to 200 mW. For the 105 MSPS
speed grade, connecting RF ENABLE to AGND optimizes SFDR
performance for applications with analog input frequencies
<230 MHz. For applications with analog inputs >230 MHz, this
pin should be connected to AVDD1 to optimize performance.

Digital Output
Offset Binary (D13••••••D0)

Digital Output
Twos Complement (D13••••••D0)

Rev. 0 | Page 28 of 40

AD9445

EVALUATION BOARD

Evaluation boards are offered to configure the AD9445 in
either CMOS or LVDS mode only. This design represents a
recommended configuration for using the device over a wide
range of sampling rates and analog input frequencies. These
evaluation boards provide all the support circuitry required to
operate the ADC in its various modes and configurations.
Complete schematics are shown in
Gerber files are available from engineering applications demon­strating the proper routing and grounding techniques that should
be applied at the system level.

Figure 67 through Figure 70.

The LVDS mode evaluation boards include an LVDS-to-CMOS
translator, making them compatible with the high speed ADC
FIFO evaluation kit (HSC-ADC-EVALA-SC). The kit includes a
high speed data capture board that provides a hardware solution
for capturing up to 32 kB samples of high speed ADC output
data in a FIFO memory chip (user upgradeable to 256 kB
samples). Software is provided to enable the user to download
the captured data to a PC via the USB port. This software also
includes a behavioral model of the AD9445 and many other
high speed ADCs.

It is critical that signal sources with very low phase noise
(<60 fsec rms jitter) be used to realize the ultimate performance
of the converter. Proper filtering of the input signal to remove
harmonics and lower the integrated noise at the input is also
necessary to achieve the specified noise performance.

The evaluation boards are shipped with a 115 V ac to 6 V dc
power supply. The evaluation boards include low dropout
regulators to generate the various dc supplies required by the
AD9445 and its support circuitry. Separate power supplies are
provided to isolate the DUT from the support circuitry. Each
input configuration can be selected by proper connection of
various jumpers (see

Figure 67).

Behavioral modeling of the AD9445 is also available at
www.analog.com/ADIsimADC. The ADIsimADC™ software
supports virtual ADC evaluation using ADI proprietary behavioral
modeling technology. This allows rapid comparison between
the AD9445 and other high speed ADCs with or without
hardware evaluation boards.

The user can choose to remove the translator and terminations
to access the LVDS outputs directly.

Rev. 0 | Page 29 of 40

AD9445

P21

P22

GND

DRGND

1

P1

2

P2

3

P3

4

P4

PTMICRO4

1

P1

2

P2

3

P3

4

P4

PTMICRO4

DRGND

GND

GND

H4
MTHOLE6

H3
MTHOLE6

H1
MTHOLE6

H2
MTHOLE6

XTALPWR
EXTREF

DRVDD

VCC

5V

(MSB) D15_T/D15_Y

DRVDD
D11_C/D6_Y
D11_T/D7_Y
D12_C/D8_Y
D12_T/D9_Y

D13_C/D10_Y
D13_T/D11_Y
D14_C/D12_Y
D14_T/D13_Y
D15_C/D14_Y

DRGND

DRVDD

DOR_C

DOR_T/DOR_Y

GND

VCC
VCC
VCC

VCC
VCC
VCC
GND

100

101

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

DRVDD
D11_C
D11_T
D12_C
D12_T
D13_C
D13_T
D14_C
D14_T
D15_C
D15_T
DRGND
DRVDD
OR_C
OR_T
AGND
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND
AGND

EPAD

DRGND

D10_T/D5_Y

74

75

D10_T

DRGND

D9_C/D2_Y

D9_T/D3_Y

D10_C/D4_Y

72

73

71

D9_T

D9_C

D10_C

D8_C/D0_Y

D8_T/D1_Y

68

69

70

D8_T

D8_C

DR

67

DCO

DRB

66

DCOB

D7_T

65

D7_T

D7_C

DRVDD

64

D7_C

DRVDD

U1

AD9445/AD9446

DRGND

62

63

DRGND

D6_T

D6_T

D6_C

61

D6_C

60

D5_T

D5_T

59

D5_C

58

D5_C

D4_T

57

D4_T

D4_C

56

D4_C

D3_T

55

D3_T

D3_C

54

D3_C

D2_T

53

D2_T

D2_C

52

D1_T

D2_C

DRVDD
DRGND

AGND
AVDD1
AVDD1
AVDD1

AGND

ENCB

AGND
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2

D1_T

51

D0_T

D0_C

ENC

D1_C

D1_C

50

D0_T

49

D0_C (LSB)

48

DRVDD

47

DRGND

46

GND

45

VCC

44

VCC

43

VCC

42

GND

41

ENCB

40

ENC

39

GND

38

VCC

37

5V

36

VCC

35

5V

34

VCC

33

VCC

32

VCC

31
30
29
28
27
26

5V

E19

VCC

E66

E18

GND

E4

VCC

DCS MODE

DNC

OUTPUT MODE

DFS

LVDSBIAS

AVDD1

SENSE

VREF

AGND

REFT

REFB

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD1

AVDD1

AVDD1

AGND

VIN+

VIN–

AGND

6

VCC

GND

GND

7

C86

E26

VCC

8

0.1μF

E25

9

E27

E41

GND

R1

11

10

GND

E24

EXTREF

DNP

R3

3.74kΩ

C3

12

0.1μF

+

GND

5V

13

C2

C51

C40

GND

R2

5V

0.1μF

10μF

0.1μF

GND

14

C9

C39

DNP

15

16

5V

5V

0.1μF

GND

10μF

20

21

19

18

17

5V

5V

C98

GND

DNP

VCC

VCC

GND

GND

VCC

T1

ETC1-1-13

R5

234

E14

R11

E2

GND

5

GND

1kΩ

VCC

1

GND

E10

E5

E6

GND

VCC

E1

GND

SCLK

E3

E9

VCC

23

22

24

GND

R28

33Ω

C7

0.1μF

GND

GND

TOUT

C12

CT

2

15

GND

L1

10nH

DNP

J4

SMBMST

AVDD2

25

5V

C13

OPTIONAL

R9

R4

36Ω

ETC1-1-13

125

T2

3

PRI SEC

TOUTB

0.1μF

34

PRI SEC

TINB

C5

0.1μF

ANALOG

DNP

DNP

4

C91

0.1μF

R6

E15

36Ω

T5

ADT1-1WT

GND

GND

TOUT

624

153

GND

R35

33Ω

C8

0.1μF

CT

PRI SEC

NC

TINB TOUTB

05489-062

Figure 67. AD9445 Evaluation Board Schematic

Rev. 0 | Page 30 of 40

AD9445

X

VIN

U6

GND

5

NC

ECLOSC

C42

4

XTALINPUT

8

OUTVCC

14

VXTAL

ENCB

3

1
2

GND

0.1μF

SEC

PRI

C41

0.1μF

C1

10μF

+

5V

E31

0Ω

GND

XTALPWR

C44

10μF

+

E30

E20

VXTAL

ENC

CR1

2

1

3

CR2

DNP

6

T3

123

ADT1-1WT

C36

DNP

VXTAL

OPTIONAL ENCODE CIRCUITS

LOADING SYMMETRICAL

CR2 TO MAKE LAYOUT AND PARASITIC

ENCODE

GND

R39

1

VEE ~OUT

7

GND

L5

FERRITE

DRVDDXDRVDD

VCCXVCC

L4

FERRITE

L2

DNP

L3

FERRITE

DRGNDGND

5VX5V

U3

3.3V

ADP3338

U7

3.3V

ADP3338

5V

U14

ADP3338

DRGND

1

GND

GND

1

GND

GND

1

GND

DRVDD

OUT1

OUT

DRVDDX

VCCX

OUT1

OUT

VCCX

5VX

OUT1

OUT

C4

10μF

+

342

IN

VIN

C6

10μF

+

342

IN

VIN

C34

10μF

+

342

IN

DRGND

C88

10μF

+

C87

10μF

+

C89

10μF

+

DRGND

GND

GND

GND

GND

GND

R7

DNP

J5

SMBMST

C26

0.1μF

GND

R8

50Ω

J1

SMBMST

XTALINPUT

POWER OPTIONS

P4

2

PJ-102A

GND

2

5VX

VIN

C33

10μF

+

1

3

1

3

GND

05489-063

Figure 68. AD9445 Evaluation Board Schematic (Continued)

Rev. 0 | Page 31 of 40

AD9445

BYPASS CAPACITORS

VCC

+

C64
10μF

GND

C43

0.1μF

C35

0.1μF

C32

0.1μF

C30

0.01μF

C28

0.1μF

C27

0.1μF

C90

0.1μF

C50

0.1μF

C60

0.1μF

C10

0.1μF

C61

0.1μF

C75

0.1μF

VCC

GND

DRVDD

DRGND

GND

GND

GND

C11XXC14

+

C65

C47

0.1μF

C85

0.1μF

C23

0.1μF

10μF

5V

+

C56
10μF

5V

5V

C17XXC16XXC15

XX

C53

C52

0.1μF

0.1μF

C72XXC73

XX

C94

C95

0.1μF

0.1μF

C21

0.1μF

C58

0.01μF

C22

0.1μF

C20

0.1μF

C31
XX

XX

C108XXC109

XX

C59

C93

0.1μF

0.1μF

DRVDD

DRGND

C38XXC29XXC19

C69XXC70

C37

0.1μF

C110
XX

C96

C97

0.1μF

0.1μF

XX

C48

0.1μF

C84

0.1μF

XX

C45XXC49

EXTREF

C18

0.1μF
GND

C46

0.1μF

XX

+

C55
10μF

05489-064

Figure 69. AD9445 Evaluation Board Schematic (Continued)

Rev. 0 | Page 32 of 40

AD9445

DRVDD

DRO

R190ΩR10

DRVDD

0Ω

DRGND

ORO

DRVDD

DRO

GNDN

DRGND

35

37

39

P35

P37

P39

P36

P38

P40

36

38

40

ORO

DRGND

D14O

D15O

16151413121110

220

R3R1R2

RSO16ISO

RZ5

DRVDD

DRGND

DRVDD

DRGND

DRVDD

312

33

34

D13O

D15O

P33

P34

7

8

D2O

6

DRVDD

D2O

P7

P8

R7

DRGND

D0O

D1O

DRGND

1

3

5

P1

P3

P5

P7

C40MS

P2

P4

P6

2

4

6

DRGND

D1O

D0O

9

R8

RZ4

8

7

DRVDD

DRVDD

DRGND

D13O

D11O

D9O

D8O

D10O

D12O

D14O

23

25

27

29

31

P23

P25

P27

P29

P31

P24

P26

P28

P30

P32

24

26

28

30

32

D8O

D9O

D10O

D11O

D12O

9

R8

R7

R6

R5

R4

8

7

6

5

4

DRVDD

DRGND

DRVDD

D7O

17

19

21

P17

P19

P21

P18

P20

P22

18

20

22

D7O

16151413121110

220

RSO16ISO

DRVDD

DRGND

15

16

D6O

P15

D6O

P16

D4O

D3O

D5O

9

11

13

P9

P11

P13

P10

P12

P14

10

12

14

D4O

D5O

D3O

R6

R5

R4

R3R1R2

5

4

312

DRVDD

91011

12

13

14

15

16

4Y

3Y

2Y

1Y

VCC

GND

EN_1_2

U15

2A

1B

1A

SN75LVDT390

1

DR

DRB

EN_3_4

4B

4A

3B

3A

2B

8765432

DOR_C

DOR_T/DOR_Y

64

D4Y

D3Y

D2Y

D1Y

C4Y

C3Y

C2Y

VCC3

B4B

16

D8_C/D0_Y

D9_C/D2_Y

23

P23

P24

24

D9_T/D3_Y

C1Y

VCC4

GND3

C2A

C1B

C1A

19

18

17

D7_T

D6_T

D7_C

D8_C/DO_Y

DRB

19

21

P19

P21

P20

P22

20

22

DR

D8_T/D1_Y

ENC

C4B

C4A

C3B

C3A

C2B

24

23

22

21

20

D5_T

D4_T

D6_C

D5_C

D4_C

D7_C

D5_C

D6_C

13

15

17

P13

P15

P17

P14

P16

P18

14

16

18

D7_T

D5_T

D6_T

END

VCC6

VCC5

GND5

GND4

D4B

D4A

D3B

D3A

D2B

D2A

D1B

D1A

32

31

30

29

28

27

26

25

D3_T

D2_T

D1_T

D2_C

7

8

D2_C

P7

P8

D2_T

D0_T

D1_C

D0_C

D0_C

D1_C

DRGND

1

3

5

P1

P3

P5

P2

P4

P6

2

4

6

D0_T

D1_T

DRGND

11

12

D4_C

P11

P12

D4_T

D3_C

D3_C

9

P9

P10

10

D3_T

C78

0.1μF

C77

0.1μF

C82

0.1μF

C76

0.1μF

DRVDD

DRGND

P6

C40MS

05489-065

A1Y

VCC1

A1B

D15_C/D14_Y

39

40

VCC2

GND1

A2B

A2A

D14_T/D13_Y

D14_C/D12_Y

DOR_C

DRGND

37

P37

P39

P38

P40

38

DRGND

DOR_T/DOR_Y

ENA

A3A

D13_T/D11_Y

35

36

A3B

D13_C/D10_Y

GND

U8

A1A

SN75LVDS386

D15_T/D15_Y

D15_C/D14_Y

P35

P36

D15_T/D15_Y

A4A

D12_T/D9_Y

33

34

A4B

D12_C/D8_Y

D14_C/D12_Y

P33

P34

D14_T/D13_Y

987654321

B1A

D11_T/D7_Y

D13_C/D10_Y

31

P31

32

D13_T/D11_Y

10

P32

ENB

B1B

D11_C/D6_Y

GND2

B4A

B3B

B3A

B2B

B2A

15

14

13

12

11

D9_T/D3_Y

D8_T/D1_Y

D9_C/D2_Y

D10_T/D5_Y

D10_C/D4_Y

D12_C/D8_Y

D10_C/D4_Y

D11_C/D6_Y

25

27

29

P25

P27

P29

P26

P28

P30

26

28

30

D12_T/D9_Y

D10_T/D5_Y

D11_T/D7_Y

B4Y

B3Y

B2Y

B1Y

A4Y

A3Y

A2Y

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Figure 70. AD9445 Evaluation Board Schematic (Continued)

Rev. 0 | Page 33 of 40

AD9445

Table 11. AD9445-125 Baseband Customer Evaluation Board Bill of Materials

Item Qty. Reference Designator Description Package Value Manufacturer Mfg. Part No.

1 7

C4, C6, C33, C34, C87,
C88, C89

2 44

C2, C3, C5, C7, C8,
C9, C10, C11, C12,
C15, C20, C21, C22,
C23, C26, C27, C28,
C32, C35, C38, C40,
C42, C43, C46, C47,
C48, C50, C52, C53,
C59, C60, C76, C77,
C78, C82, C84, C85,
C86, C90, C91, C94,

C95, C96, C97
3 2 C30, C58 Capacitor 201 0.01 F Digi-Key Corporation 445-1796-1-ND
4 4 C39, C56, C64, C65 Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2
5 1 C51 Capacitor 805 10 F Digi-Key Corporation 490-1717-1-ND
6 1 CR1 Diode SOT23M5 Digi-Key Corporation MA3X71600LCT-ND
7 1 CR2 Diode SOT23M5 Digi-Key Corporation MA3X71600LCT-ND
8 20

E1, E2, E3, E4, E5, E6,

E9, E10, E14, E18, E19,

E20, E24, E25, E26, E27,

E30, E31, E36, E41
9 2 J1, J4 SMA SMA Digi-Key Corporation ARFX1231-ND
10 1 L1 Inductor 0603A 10 nH Coilcraft, Inc. 0603CS-10NXGBU
11 3 L3, L4, L5

12 1 P4 PJ-002A PJ-002A Digi-Key Corporation CP-002A-ND
13 1 P7 Header C40MS Samtec, Inc. TSW-120-08-L-D-RA
14 1 R3 Resistor 402 3.74 kΩ Digi-Key Corporation P3.74KLCT-ND
15 1 R8 Resistor 402 50 Ω Digi-Key Corporation P49.9LCT-ND
16 4 R10, R19, R39, L2 Resistor 402 0 Ω Digi-Key Corporation P0.0JCT-ND
17 1 R11 BRES402 402 1 kΩ Digi-Key Corporation P1.0KLCT-ND
18 2 R28, R35 Resistor 402 33 Ω Digi-Key Corporation P33JCT-ND
19 2 RZ4, RZ5 Resistor array 16PIN 22 Ω Digi-Key Corporation 742C163220JCT-ND
20 2 T3, T5 Transformer ADT1-1WT Mini-Circuits ADT1-1WT
21 1 U1 AD9445BSVZ-125 SV-100-3 Analog Devices, Inc. AD9445BSVZ-125
22 1 U14 ADP3338-5 SOT-223HS Analog Devices, Inc. ADP3338-5
23 2 U3, U7 ADP3338-3.3 SOT-223HS Analog Devices, Inc. ADP3338-33
24 1 U8 SN75LVDT386 TSSOP64 Arrow Electronics, Inc. SN75LVDT386DGG
25 1 U15 SN75LVDT390 SOIC16PW Arrow Electronics, Inc. SN75LVDT390PW
26 2 R4, R6 Resistor 402 36 Ω Digi-Key Corporation P36JCT-ND
27 2 C1, C44, C55
28 23

C13, C14, C16, C17,

1

C18, C19, C29, C31,

C36, C37, C41, C45,

C49, C61, C69, C70,

C72, C73, C75, C93,

C108, C109, C110
29 1 C98
30 E15
31 J5
32 P6
33 2 R1, R2

1

1

1

1

1

34 3 R5, R7, R9
35 1 U2

1

1

1

Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2

Capacitor 402 0.1 F Digi-Key Corporation PCC2146CT-ND

Header EHOLE Mouser Electronics 517-6111TG

EMIFIL®

1206MIL Mouser Electronics 81-BLM31P500S

BLM31PG500SN1L

Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2
CAP402 402 XX

Capacitor 805 10 F Digi-Key Corporation 490-1717-1-ND
Header EHOLE Mouser Electronics 517-6111TG
SMA SMA Digi-Key Corporation ARFX1231-ND
Header C40MS Samtec, Inc. TSW-120-08-L-D-RA
BRES402 402 XX
BRES402 402 XX
ECLOSC DIP4(14)

Rev. 0 | Page 34 of 40

AD9445

Item Qty. Reference Designator Description Package Value Manufacturer Mfg. Part No.

36 4 H1, H2, H3, H4
37 2 T1, T2

1

38 2 P21, P22

1

Parts not populated.

Table 12. AD9445-125 IF Customer Evaluation Board Bill of Materials

Item Qty. Reference Designator Description Package Value Manufacturer MFG_PART_NO

1 7

C4, C6, C33, C34, C87,
C88, C89

2 44

C2, C3, C5, C7, C8,
C9, C10, C11, C12,
C15, C20, C21, C22,
C23, C26, C27, C28,
C32, C35, C38, C40,
C42, C43, C46, C47,
C48, C50, C52, C53,
C59, C60, C76, C77,
C78, C82, C84, C85,
C86, C90, C91, C94,

C95, C96, C97
3 2 C30, C58 Capacitor 201 0.01 F Digi-Key Corporation 445-1796-1-ND
4 4 C39, C56, C64, C65 Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2
5 1 C51 Capacitor 805 10 F Digi-Key Corporation 490-1717-1-ND
6 1 CR1 Diode SOT23M5 Digi-Key Corporation MA3X71600LCT-ND
7 1 CR2 Diode SOT23M5 Digi-Key Corporation MA3X71600LCT-ND
8 20

E1, E2, E3, E4, E5, E6,

E9, E10, E14, E18, E19,

E20, E24, E25, E26, E27,

E30, E31, E36, E41
9 2 J1, J4 SMA SMA Digi-Key Corporation ARFX1231-ND
10 1 L1 Inductor 0603A 10 nH Coilcraft, Inc. 0603CS-10NXGBU
11 3 L3, L4, L5 EMIFIL® BLM31PG500SN1L 1206MIL Mouser Electronics 81-BLM31P500S
12 1 P4 PJ-002A PJ-002A Digi-Key Corporation CP-002A-ND
13 1 P7 Header C40MS Samtec, Inc. TSW-120-08-L-D-RA
14 1 R3 Resistor 402 3.74 kΩ Digi-Key Corporation P3.74KLCT-ND
15 1 R8 Resistor 402 50 Ω Digi-Key Corporation P49.9LCT-ND
16 4 R10, R19, R39, L2 Resistor 402 0 Ω Digi-Key Corporation P0.0JCT-ND
17 1 R11 BRES402 402 1 kΩ Digi-Key Corporation P1.0KLCT-ND
18 2 R28, R35 Resistor 402 33 Ω Digi-Key Corporation P33JCT-ND
19 2 RZ4, RZ5 Resistor array 16PIN 22 Ω Digi-Key Corporation 742C163220JCT-ND
20 1 U1 AD9445BSVZ-125 SV-100-3 Analog Devices, Inc. AD9445BSVZ-125
21 1 U14 ADP3338-5

22 2 U3, U7 ADP3338-3.3 SOT-223HS Analog Devices, Inc. ADP3338-3.3
23 1 U8 SN75LVDT386 TSSOP64 Arrow Electronics, Inc. SN75LVDT386DGG
24 1 U15 SN75LVDT390 SOIC16PW Arrow Electronics, Inc. SN75LVDT390PW
25 2 T1, T2 Balun transformer SM-22 M/A-COM ETC-1-1-13
26 1 R5 Resistor 402 36 Ω Digi-Key Corporation P49.9LCT-ND
27 1 T3 Transformer ADT1-1WT Mini-Circuits ADT1-1WT
28 2 C1, C44, C55

1

MTHOLE6 MTHOLE6
Balun transformer SM-22 M/A-COM ETC1-1-13

1

Term strip PTMICRO4 Newark Electronics

Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2

Capacitor 402 0.1 F Digi-Key Corporation PCC2146CT-ND

Header EHOLE Mouser Electronics 517-6111TG

SOT-

Analog Devices, Inc. ADP3338-5

223HS

1

Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2

Rev. 0 | Page 35 of 40

AD9445

Item Qty. Reference Designator Description Package Value Manufacturer MFG_PART_NO

29 23

C13, C14, C16, C17,
C18, C19, C29, C31,
C36, C37, C41, C45,
C49, C61, C69, C70,
C72, C73, C75, C93,

C108, C109, C110
30 1 C98
31 E15
32 J5
33 P6
34 2 R1, R2
35 3 R5, R7, R9
36 1 U2

1

1

1

1

1

1

1

37 4 H1, H2, H3, H4
38 2 R4, R6
39 1 T5
40 2 P21, P22

1

Parts not populated.

1

1

1

1

1

CAP402 402 XX

Capacitor 805 10 F Digi-Key Corporation 409-1717-1-ND
Header EHOLE Mouser Electronics 517-6111TG
SMA SMA Digi-Key Corporation ARFX1231-ND
Header C40MS Samtec, Inc. TSW-120-08-L-D-RA
BRES402 402 XX
BRES402 402 XX
ECLOSC DIP4(14)
MTHOLE6 MTHOLE6
Resistor 402 36 Digi-Key Corporation P36JCT-ND
Transformer ADT1-1WT Mini-Circuits ADT1-1WT
Term strip PTMICRO4 Newark Electronics

Rev. 0 | Page 36 of 40

AD9445

OUTLINE DIMENSIONS

0.75

0.60

0.45

1.20

MAX

16.00 BSC SQ

1

PIN 1

14.00 BSC SQ

76100

76 100

75

75

1

1.05

1.00

0.95

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

BOTTO M V IEW

0.50 BSC

LEAD PITCH

EXPOSED

PAD

(PINS UP)

0.27

0.22

0.17

TOP VIEW

(PINS DOWN)

0° MIN

0.20

0.09
7°

3.5°
0°

0.08 MAX
COPLANARITY

NOTES

1. CENTER FIGURES ARE TY P ICAL UNLESS O THERWISE NOTED.

2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEATAND ENSURE RELIABLE OPE RATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EX P OSED ON THE BO TTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT I S RE COMMENDED THAT NO PCB SIGNAL
TRACES OR VI AS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHI CH MAY BE BENEFICIAL IN HIGH TEMPE RATURE ENVIRONM E NTS.

25

26 49

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-AE D- HD

50

51

9.50 SQ

25

2650

Figure 71. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-100-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9445BSVZ-125 –40°C to +85°C 100-Lead TQFP_EP SV-100-3
AD9445BSVZ-105 –40°C to +85°C 100-Lead TQFP_EP SV-100-3
AD9445-IF-LVDS/PCB AD9445-125 IF (>100 MHz) LVDS Mode Evaluation Board
AD9445-BB-LVDS/PCB AD9445-125 Baseband (<100 MHz) LVDS Mode Evaluation Board

1

Z = Pb-free part.

1

1

Rev. 0 | Page 37 of 40

AD9445

NOTES

Rev. 0 | Page 38 of 40

AD9445

NOTES

Rev. 0 | Page 39 of 40

AD9445

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05489–0–10/05(0)

Rev. 0 | Page 40 of 40