Analog Devices AD9444 Service Manual

14-Bit, 80 MSPS, A/D Converter

FEATURES

80 MSPS guaranteed sampling rate 100 dB two-tone SFDR with 69.3 MHz and 70.3 MHz

73.1 dB SNR with 70 MHz input 97 dBc SFDR with 70 MHz input Excellent linearity

DNL = ±0.4 LSB typical INL = ±0.6 LSB typical

1.2 W power dissipation

3.3 V and 5 V supply operation

2.0 V p-p differential full-scale input LVDS outputs (ANSI-644 compatible) Data format select Output clock available

APPLICATIONS

Multicarrier, multimode cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar, infared imaging Communications instrumentation

GENERAL DESCRIPTION

The AD9444 is a 14-bit monolithic, sampling analog-to-digital converter (ADC) with an on-chip, track-and-hold circuit and is optimized for power, small size, and ease of use. The product operates at up to an 80 MSPS conversion rate and is optimized for multicarrier, multimode receivers, such as those found in cellular infrastructure equipment.

The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS-compatible (ANSI-

644) or CMOS-compatible and include the means to reduce the overall current needed for short trace distances.

AD9444

FUNCTIONAL BLOCK DIAGRAM

AGND DRGND DRVDD

AVDD1 AVDD2

2

28

2

DFS DCS MODE OUTPUT MODE OR

D13–D0

DCO

AD9444

VIN+ VIN–

CLK+ CLK–

BUFFER

CLOCK

AND TIMING

MANAGEMENT

T/H

VREF

PIPELINE

ADC

REF

Figure 1.

14

CMOS

OR

LVDS

OUTPUT

STAGING

REFBSENSE REFT

Optional features allow users to implement various selectable operating conditions, including data format select and output data mode.

The AD9444 is available in a 100-lead surface-mount plastic package (100-lead TQFP/EP) specified over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. High performance: Outstanding SFDR performance for mul-

ticarrier, multimode 3G and 4G cellular base station receivers.

2. Ease of use: On-chip reference and track-and-hold. An

output clock simplifies data capture.

3. Packaged in a Pb-free, 100-lead TQFP/EP.

4. Clock DCS maintains overall ADC performance over a wide

range of clock pulse widths.

5. OR (out-of-range) outputs indicate when the signal is beyond

the selected input range.

05089-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

AD9444

DC SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed reference (1.0 V mode), A

Table 1.

Parameter Temp Test Level

RESOLUTION Full VI 14 Bits ACCURACY

No Missing Codes Full VI Guaranteed Offset Error Full VI 6 ±0.3 6 mV Gain Error

1

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)2 25°C I −1.3 ±0.6 +1.3 LSB Full VI −1.7 +1.7 LSB TEMPERATURE DRIFT

Offset Error Full V 12 µV/°C

Gain Error Full V 0.002 %FS/°C VOLTAGE REFERENCE

Output Voltage1 Full VI 0.87 1.0 1.13 V

Load Regulation @ 1.0 mA Full V ±2 mV

Reference Input Current (External 1.0 V Reference) Full VI 80 125 µA INPUT REFERRED NOISE 25°C V 1.0 LSB rms ANALOG INPUT

Input Span Full V 2 V p-p

Input Common-Mode Voltage Full V 3.5 V

Input Resistance

3

Input Capacitance3 Full V 2.5 pF POWER SUPPLIES

Supply Voltage

AVDD1 Full IV 3.14 3.3 3.46 V AVDD2 Full IV 4.75 5.0 5.25 V DRVDD—LVDS Outputs Full IV 3.0 3.6 V DRVDD—CMOS Outputs Full IV 3.0 3.3 3.6 V

Supply Current

AVDD1 Full VI 217 240 mA AVDD22 Full VI 71 80 mA IDRVDD2—LVDS Outputs Full VI 55 62 mA IDRVDD2—CMOS Outputs Full V 12 mA

PSRR

Offset Full V 1 mV/V Gain Full V 0.2 %/V

POWER CONSUMPTION

DC Input—LVDS Outputs Full VI 1.21 1.4 W

DC Input—CMOS Outputs Full V 1.07 W

Sine Wave Input2—LVDS Outputs Full VI 1.25 W

Sine Wave Input2—CMOS Outputs Full V 1.11 W

1

The internal voltage reference is trimmed at final test to minimize the gain error of the AD9444.

2

Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and

approximately 5 pF loading on each output bit for CMOS output mode.

3

Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to for the equivalent analog input

structure.

= −0.5 dBFS, DCS on, unless other wise note d.

IN

Full VI −3.0 ±0.4 +3.0 % FSR

2

Full VI −0.8 ±0.4 +0.8 LSB

Full V 1 kΩ

AD9444BSVZ-80

Min Typ Max

Figure 6

Unit

Rev. 0 | Page 3 of 40

AD9444

AC SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed reference (1.0 V mode), A

Table 2.

Parameter Temp Test Level

SIGNAL-TO-NOISE-RATIO (SNR)

fIN = 10 MHz 25°C IV 73.0 74.0 dB

Full IV 72.7 dB

fIN = 35 MHz 25°C I 72.4 73.7 dB Full IV 72.3 dB fIN = 70 MHz 25°C IV 72.3 73.1 dB

Full IV 72.0 dB

fIN = 100 MHz 25°C V 72.3 dB

SIGNAL-TO-NOISE-AND DISTORTION (SINAD)

fIN = 10 MHz 25°C IV 73.0 74.0 dB

Full IV 72.7 dB

fIN = 35 MHz 25°C I 72.4 73.7 dB Full IV 72.2 dB fIN = 70 MHz 25°C IV 72.2 73.1 dB

Full IV 72.0 dB

fIN = 100 MHz 25°C V 72.3 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 10 MHz 25°C V 12.1 Bits fIN = 35 MHz 25°C V 12.0 Bits fIN = 70 MHz 25°C V 11.9 Bits fIN = 100 MHz 25°C V 11.8 Bits

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 10 MHz 25°C IV 91 97 dBc

Full IV 87 dBc

fIN = 35 MHz 25°C I 91 97 dBc Full IV 87 dBc fIN = 70 MHz 25°C IV 90 97 dBc

Full IV 87 dBc

fIN = 100 MHz 25°C V 96 dBc

WORST HARMONIC, SECOND OR THIRD

fIN = 10 MHz 25°C IV −97 −91 dBc

Full IV −87 dBc

fIN = 35 MHz 25°C I −97 −91 dBc Full IV −87 dBc fIN = 70 MHz 25°C IV −97 −90 dBc

Full IV −87 dBc

fIN = 100 MHz 25°C V −96 dBc

WORST SPUR EXCLUDING SECOND OR HARMONICS

fIN = 10 MHz 25°C IV −102 −93 dBc

Full IV −93 dBc

fIN = 35 MHz 25°C I −103 −93 dBc Full IV −93 dBc fIN = 70 MHz 25°C IV −102 −93 dBc

Full IV −93 dBc

fIN = 100 MHz 25°C V −99 dBc

TWO-TONE SFDR

fIN = 10.8 MHz @ −7 dBFS, 9.8 MHz @ −7 dBFS 25°C V −102 dBFS fIN = 70.3 MHz @ −7 dBFS, 69.3 MHz @ −7 dBFS 25°C V −100 dBFS

ANALOG BANDWIDTH Full V 650 MHz

= −0.5 dBFS, DCS on, unless other wise note d.

IN

AD9444BSVZ-80

Min Typ Max

Unit

Rev. 0 | Page 4 of 40

AD9444

DIGITAL SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, R

Table 3.

Parameter Temp Test Level

CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)

High Level Input Voltage Full IV 2.0 V

Low Level Input Voltage Full IV 0.8 V

High Level Input Current Full VI +200 µA

Low Level Input Current Full VI −10 +10 µA

Input Capacitance Full V 2 pF DIGITAL OUTPUT BITS—CMOS Mode (D0 to D13, OTR)

DRVDD = 3.3 V

High Level Output Voltage Full IV 3.25 V Low Level Output Voltage Full IV 0.2 V

DIGITAL OUTPUT BITS LVDS Mode (D0 to D13, OTR)

VOD Differential Output Voltage

2

VOS Output Offset Voltage Full VI 1.125 1.375 V CLOCK INPUTS (CLK+, CLK−)

Differential Input Voltage Full IV 0.2 V

Common-Mode Voltage Full VI 1.3 1.5 1.6 V

Differential Input Resistance Full V 8 10 12 kΩ

Differential Input Capacitance Full V 4 pF

1

Output voltage levels measured with 5 pF load on each output.

2

LVDS R

= 100 Ω.

TERM

= 3.74 kΩ, unless otherwise noted.

LVD SB IA S

1

Full VI 247 545 mV

AD9444BSVZ-80

Min Typ Max

Unit

Rev. 0 | Page 5 of 40

AD9444

SWITCHING SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.

Table 4.

AD9444BSVZ-80

Parameter Temp Test Level

Min Typ Max

CLOCK INPUT PARAMETERS

Maximum Conversion Rate Full VI 80 MSPS Minimum Conversion Rate Full V 10 MSPS CLK Period Full V 12.5 ns CLK Pulse Width High1 (t CLK Pulse Width Low1 (t

) Full V 4 ns

CLKH

) Full V 4 ns

CLKL

DATA OUTPUT PARAMETERS

Output Propagation Delay—CMOS (tPD)2 (DX, DCO+) Full IV 3 5.25 8 ns Output Propagation Delay—LVDS (tPD)3 (DX+, DCO+) Full VI 3 5 7.5 ns Pipeline Delay (Latency) Full V 12 Cycles Aperture Delay (tA) Full V ns Aperture Uncertainty (Jitter, tJ) Full V 0.2 ps rms

1

With duty cycle stabilizer (DCS) enabled.

2

Output propagation delay is measured from clock 50% transition to data 50% transition, with 5 pF load.

3

LVDS R

= 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.

TERM

Unit

A

CLK+

CLK–

DATA OUT

DCO+

DCO–

N–1

IN

t

CLKH

t

CLKL

t

CPD

N

N+1

1/f

S

t

PD

N–12

12 CLOCK CYCLES

N–11

N

N+1

05089-002

Figure 2. LVDS Mode Timing Diagram

Rev. 0 | Page 6 of 40

AD9444

N

N+1

t

CLKL

t

PD

N+2

12 CYCLES

VIN

CLK–

CLK+

N–1

t

CLKH

DX

DCO+

DCO–

N-12 N-11 N-1 N

t

DCOPD

Figure 3. CMOS Timing Diagram

EXPLANATION OF TEST LEVELS

Test Level Definitions

I 100% production tested. II 100% production tested at 25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.

05089-003

Rev. 0 | Page 7 of 40

AD9444

ABSOLUTE MAXIMUM RATINGS

Table 5.

With

Parameter ELECTRICAL

AVDD1 AGND −0.3 +4 V AVDD2 AGND −0.3 +6 V DRVDD DGND −0.3 +4 V AGND DGND −0.3 +0.3 V AVDD1 DRVDD −4 +4 V AVDD2 DRVDD −4 +6 V AVDD2 AVDD1 −4 +6 V D0 to D13 DGND –0.3 DRVDD + 0.3 V CLK, MODE AGND –0.3 AVDD1 + 0.3 V VIN+, VIN− AGND –0.3 AVDD2 + 0.3 V VREF AGND –0.3 AVDD1 + 0.3 V SENSE AGND –0.3 AVDD1 + 0.3 V REFT, REFB AGND –0.3 AVDD1 + 0.3 V

ENVIRONMENTAL

Storage Temperature –65 +125 °C Operating Temperature Range –40 +85 °C Lead Temperature Range

(Soldering 10 sec)

Junction Temperature 150 °C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Respect to

Min Max Unit

300 °C

Thermal Resistance

The heat sink of the AD9444 package must be soldered to ground.

Table 6.

Package Type θ

100-Lead TQFP/EP 19.8 8.3 2 °C/W

JA

θ

JB

θ

JC

Unit

Typical θ

= 19.8°C/W (heat-sink soldered) for multilayer

JA

board in still air.

Typical θ

= 8.3°C/W (heat-sink soldered) for multilayer board

JB

in still air.

Typical θ

= 2°C/W (junction to exposed heat sink) represents

JC

the thermal resistance through heat-sink path.

Airflow increases heat dissipation effectively reducing θ

. Also,

JA

more metal directly in contact with the package leads, from metal traces, through holes, ground, and power planes, reduces

. It is required that the exposed heat sink be soldered to

the θ

JA

the ground plane.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 8 of 40

AD9444

DEFINITIONS OF SPECIFICATIONS

Analog Bandwidth (Full Power Bandwidth)

The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.

Minimum Conversion Rate

The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.

Aperture Delay (t

)

A

The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter, t

)

J

The sample-to-sample variation in aperture delay.

Clock Pulse Width and Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16384 codes must be present over all operating ranges.

Effective Number of Bits (ENOB)

The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula

()

SINAD

=

ENOB

1.76−

6.02

Gain Error

The first code transition should occur at an analog value ½ LSB above negative full scale. The last transition should occur at an analog value 1 ½ LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.

Offset Error

The major carry transition should occur for an analog value ½ LSB below VIN+ = VIN−. Offset error is defined as the deviation of the actual transition from that point.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.

Output Propagation Delay (tPD)

The delay between the clock rising edge and the time when all bits are within valid logic levels.

Power-Supply Rejection Ratio

The change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit.

Signal-to-Noise and Distortion (SINAD)

The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc.

Signal-to-Noise Ratio (SNR)

The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered) or dBFS (always related back to converter full scale).

Integral Nonlinearity (INL)

The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1 ½ LSBs beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.

Maximum Conversion Rate

The clock rate at which parametric testing is performed.

Rev. 0 | Page 9 of 40

Temperature Drift

The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at T

MIN

or T

MAX

.

Total Harmonic Distortion (THD)

The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components.

Two -Ton e SFDR

The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product.

AD9444

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DCS MODE

AGND

AVDD1

AGND

AVDD1

AGND

AVDD1

AGND

OR+

OR–

AVDD1

DNC DNC DNC

OUTPUT MODE

DFS

LVDSBIAS

AVDD1 AVDD1 SENSE

VREF

AGND

REFT REFB

AGND AVDD1 AVDD1

AVDD1 AVDD2

AGND

VIN+ VIN–

AGND AVDD1

AVDD1

99989796959493

100

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

929190

89

88

AD9444

TOP VIEW

(Not to Scale)

8786858483

DRVDD

DRGND 82

D13+ (MSB)

D13–79D12+78D12–77D11+76D11–

81

80

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

DRVDD DRGND D10+

D10– D9+

D9– D8+ D8–

DRGND D7+

D7– DCO+ DCO– DRVDD DRGND D6+ D6– D5+

D5– D4+

D4– DRVDD DRGND

D3+ D3–

2627282930

AVDD1

DNC = DO NOT CONNECT

AVDD2

31

AVDD2

32

C1

AGND

33

343536

AVDD1

CLK+

37

39

40

38

414243

4445464748

D1–

D0+

CLK–

AVDD1

AVDD2

AVDD1

D1+

(LSB) D0–

DRVDD

49

D2–

DRGND

50

D2+

05089-004

Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode

Rev. 0 | Page 10 of 40

AD9444

Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode

Pin No. Mnemonic Description

1, 8 to 9, 16 to 18, 24 to 27, 34 to 35, 38, 41 to 42, 87, 89 to 95, 98

2 to 4 DNC

5

6 DFS

7 LVDSBIAS

10 SENSE

11 VREF

12, 15, 20, 23, 32, 86, 88, 96 to 97, 99, Exposed Heat Sink

13 REFT

14 REFB

19, 28 to 31, 39 to 40

21 VIN+ Analog Input—True. 22 VIN− Analog Input—Complement. 33 C1

36 CLK+ Clock Input—True. 37 CLK− Clock Input—Complement. 43 D0− (LSB)

AVDD1 3.3 V (±5%) Analog Supply.

Do Not Connect. These pins should float.

OUTPUT MODE

AGND

AVDD2 5.0 V Analog Supply (±5%).

CMOS Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode, and OUTPUT MODE = 1 (AVDD1) for LVDS outputs.

Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos complement, DFS = low (ground) for offset binary format.

Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.

Reference Mode Selection. Connect to AGND for internal 1 V reference, and connect to AVDD2 for external reference.

1.0 V Reference I/O—Function Dependent on SENSE. Decouple to ground with 0.1 µF and 10 µF capacitors.

Analog Ground. The exposed heat sink on the bottom of the package must be connected to AGND.

Differential Reference Output. Decoupled to ground with 0.1 µF capacitor and to REFB (Pin 14) with

0.1 µF and 10 µF capacitors. Differential Reference Output.

Decoupled to ground with a 0.1 µF capacitor and to REFT (Pin 13) with

0.1 µF and 10 µF capacitors.

Internal Bypass Node. Connect a

0.1 µF capacitor from this pin to AGND.

D0 Complement Output Bit (LVDS Levels).

Pin No. Mnemonic Description

44 D0+ D0 True Output Bit. 45 D1− D1 Complement Output Bit. 46 D1+ D1 True Output Bit. 47, 54, 62,

75, 83 48, 53, 61,

67, 74, 82 49 D2− D2 Complement Output Bit. 50 D2+ D2 True Output Bit. 51 D3− D3 Complement Output Bit. 52 D3+ D3 True Output Bit. 55 D4− D4 Complement Output Bit. 56 D4+ D4 True Output Bit. 57 D5− D5 Complement Output Bit. 58 D5+ D5 True Output Bit. 59 D6− D6 Complement Output Bit. 60 D6+ D6 True Output Bit. 63 DCO− Data Clock Output—Complement. 64 DCO+ Data Clock Output—True. 65 D7− D7 Complement Output Bit. 66 D7+ D7 True Output Bit. 68 D8− D8 Complement Output Bit. 69 D8+ D8 True Output Bit. 70 D9− D9 Complement Output Bit. 71 D9+ D9 True Output Bit. 72 D10− D10 Complement Output Bit. 73 D10+ D10 True Output Bit. 76 D11− D11 Complement Output Bit. 77 D11+ D11 True Output Bit. 78 D12− D12 Complement Output Bit. 79 D12+ D12 True Output Bit. 80 D13− D13 Complement Output. 81 D13+ (MSB) D13 True Output Bit. 84 OR−

85 OR+ Out-of-Range True Output Bit. 100 DCS MODE

DRVDD

DRGND Digital Ground.

3.3 V Digital Output Supply (3.0 V to 3.6 V).

Out-of-Range Complement Output Bit.

Clock Duty Cycle Stabilizer (DCS) Control Pin, CMOS-Compatible. DCS = low (AGND) to enable DCS (recommended). DCS = high (AVDD1) to disable DCS.

Rev. 0 | Page 11 of 40

AD9444

AVDD1

DNC DNC DNC

OUTPUT MODE

DFS

DNC

AVDD1 AVDD1 SENSE

VREF

AGND

REFT

REFB

AGND AVDD1 AVDD1 AVDD1 AVDD2

AGND

VIN+ VIN–

AGND AVDD1 AVDD1

DCS MODE

AGND

AVDD1

AGND

99989796959493

100

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

AVDD1

929190

AVDD1

AGND

89

88

AD9444

TOP VIEW

(Not to Scale)

AVDD1

AGNDORD13 (MSB)

8786858483

DRVDD

DRGND

D12

81

82

D11 80

D10D9D8 797877

D7 76

75

DRVDD

74

DRGND

73

D6

72

D5

71

D4

70

D3

69

D2

68

D1

67

DRGND

66

D0 (LSB)

65

DNC

64

DCO+

63

DCO–

62

DRVDD

61

DRGND

60

DNC

59

DNC

58

DNC

57

DNC

56

DNC DNC

55 54

DRVDD

53

DRGND

52

DNC

51

DNC

2627282930

AVDD1

DNC = DO NOT CONNECT

Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode

AVDD2

31

AVDD2

32

AGND

33 C1

343536

AVDD1

CLK+

37

CLK–

38

AVDD1

39

AVDD2

40

AVDD2

414243

AVDD1

4445464748

DNC

DRVDD

49

DNC

DRGND

50

DNC

05089-005

Rev. 0 | Page 12 of 40

Analog Devices AD9444 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

EXPLANATION OF TEST LEVELS

ABSOLUTE MAXIMUM RATINGS

Thermal Resistance

ESD CAUTION

DEFINITIONS OF SPECIFICATIONS

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS