The AD9444 is a 14-bit monolithic, sampling analog-to-digital
converter (ADC) with an on-chip, track-and-hold circuit and is
optimized for power, small size, and ease of use. The product
operates at up to an 80 MSPS conversion rate and is optimized
for multicarrier, multimode receivers, such as those found in
cellular infrastructure equipment.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are LVDS-compatible (ANSI-
644) or CMOS-compatible and include the means to reduce
the overall current needed for short trace distances.
AD9444
FUNCTIONAL BLOCK DIAGRAM
AGNDDRGND DRVDD
AVDD1 AVDD2
2
28
2
DFS
DCS MODE
OUTPUT MODE
OR
D13–D0
DCO
AD9444
VIN+
VIN–
CLK+
CLK–
BUFFER
CLOCK
AND TIMING
MANAGEMENT
T/H
VREF
PIPELINE
ADC
REF
Figure 1.
14
CMOS
OR
LVDS
OUTPUT
STAGING
REFBSENSE REFT
Optional features allow users to implement various selectable
operating conditions, including data format select and output
data mode.
The AD9444 is available in a 100-lead surface-mount plastic
package (100-lead TQFP/EP) specified over the industrial
temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. High performance: Outstanding SFDR performance for mul-
ticarrier, multimode 3G and 4G cellular base station
receivers.
2. Ease of use: On-chip reference and track-and-hold. An
output clock simplifies data capture.
3. Packaged in a Pb-free, 100-lead TQFP/EP.
4. Clock DCS maintains overall ADC performance over a wide
range of clock pulse widths.
5. OR (out-of-range) outputs indicate when the signal is beyond
the selected input range.
05089-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
No Missing Codes Full VI Guaranteed
Offset Error Full VI 6 ±0.3 6 mV
Gain Error
1
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)2 25°C I −1.3 ±0.6 +1.3 LSB
Full VI −1.7 +1.7 LSB
TEMPERATURE DRIFT
Offset Error Full V 12 µV/°C
Gain Error Full V 0.002 %FS/°C
VOLTAGE REFERENCE
Output Voltage1 Full VI 0.87 1.0 1.13 V
Load Regulation @ 1.0 mA Full V ±2 mV
Reference Input Current (External 1.0 V Reference) Full VI 80 125 µA
INPUT REFERRED NOISE 25°C V 1.0 LSB rms
ANALOG INPUT
Input Span Full V 2 V p-p
Input Common-Mode Voltage Full V 3.5 V
Input Resistance
3
Input Capacitance3 Full V 2.5 pF
POWER SUPPLIES
Supply Voltage
AVDD1 Full IV 3.14 3.3 3.46 V
AVDD2 Full IV 4.75 5.0 5.25 V
DRVDD—LVDS Outputs Full IV 3.0 3.6 V
DRVDD—CMOS Outputs Full IV 3.0 3.3 3.6 V
Supply Current
AVDD1 Full VI 217 240 mA
AVDD22 Full VI 71 80 mA
IDRVDD2—LVDS Outputs Full VI 55 62 mA
IDRVDD2—CMOS Outputs Full V 12 mA
PSRR
Offset Full V 1 mV/V
Gain Full V 0.2 %/V
POWER CONSUMPTION
DC Input—LVDS Outputs Full VI 1.21 1.4 W
DC Input—CMOS Outputs Full V 1.07 W
Sine Wave Input2—LVDS Outputs Full VI 1.25 W
Sine Wave Input2—CMOS Outputs Full V 1.11 W
1
The internal voltage reference is trimmed at final test to minimize the gain error of the AD9444.
2
Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
3
Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to for the equivalent analog input
Maximum Conversion Rate Full VI 80 MSPS
Minimum Conversion Rate Full V 10 MSPS
CLK Period Full V 12.5 ns
CLK Pulse Width High1 (t
CLK Pulse Width Low1 (t
) Full V 4 ns
CLKH
) Full V 4 ns
CLKL
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (tPD)2 (DX, DCO+) Full IV 3 5.25 8 ns
Output Propagation Delay—LVDS (tPD)3 (DX+, DCO+) Full VI 3 5 7.5 ns
Pipeline Delay (Latency) Full V 12 Cycles
Aperture Delay (tA) Full V ns
Aperture Uncertainty (Jitter, tJ) Full V 0.2 ps rms
1
With duty cycle stabilizer (DCS) enabled.
2
Output propagation delay is measured from clock 50% transition to data 50% transition, with 5 pF load.
3
LVDS R
= 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
TERM
Unit
A
CLK+
CLK–
DATA OUT
DCO+
DCO–
N–1
IN
t
CLKH
t
CLKL
t
CPD
N
N+1
1/f
S
t
PD
N–12
12 CLOCK CYCLES
N–11
N
N+1
05089-002
Figure 2. LVDS Mode Timing Diagram
Rev. 0 | Page 6 of 40
Page 7
AD9444
N
N+1
t
CLKL
t
PD
N+2
12 CYCLES
VIN
CLK–
CLK+
N–1
t
CLKH
DX
DCO+
DCO–
N-12N-11N-1N
t
DCOPD
Figure 3. CMOS Timing Diagram
EXPLANATION OF TEST LEVELS
Test Level Definitions
I 100% production tested.
II 100% production tested at 25°C and sample tested at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
05089-003
Rev. 0 | Page 7 of 40
Page 8
AD9444
ABSOLUTE MAXIMUM RATINGS
Table 5.
With
Parameter
ELECTRICAL
AVDD1 AGND −0.3 +4 V
AVDD2 AGND −0.3 +6 V
DRVDD DGND −0.3 +4 V
AGND DGND −0.3 +0.3 V
AVDD1 DRVDD −4 +4 V
AVDD2 DRVDD −4 +6 V
AVDD2 AVDD1 −4 +6 V
D0 to D13 DGND –0.3 DRVDD + 0.3 V
CLK, MODE AGND –0.3 AVDD1 + 0.3 V
VIN+, VIN− AGND –0.3 AVDD2 + 0.3 V
VREF AGND –0.3 AVDD1 + 0.3 V
SENSE AGND –0.3 AVDD1 + 0.3 V
REFT, REFB AGND –0.3 AVDD1 + 0.3 V
ENVIRONMENTAL
Storage Temperature –65 +125 °C
Operating Temperature Range –40 +85 °C
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature 150 °C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Respect to
Min Max Unit
300 °C
Thermal Resistance
The heat sink of the AD9444 package must be soldered to
ground.
Table 6.
Package Type θ
100-Lead TQFP/EP 19.8 8.3 2 °C/W
JA
θ
JB
θ
JC
Unit
Typical θ
= 19.8°C/W (heat-sink soldered) for multilayer
JA
board in still air.
Typical θ
= 8.3°C/W (heat-sink soldered) for multilayer board
JB
in still air.
Typical θ
= 2°C/W (junction to exposed heat sink) represents
more metal directly in contact with the package leads, from
metal traces, through holes, ground, and power planes, reduces
. It is required that the exposed heat sink be soldered to
the θ
JA
the ground plane.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
Rev. 0 | Page 8 of 40
Page 9
AD9444
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Aperture Delay (t
)
A
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter, t
)
J
The sample-to-sample variation in aperture delay.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the
clock pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed no
missing codes to 14-bit resolution indicates that all 16384 codes
must be present over all operating ranges.
Effective Number of Bits (ENOB)
The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured
SINAD using the following formula
()
SINAD
=
ENOB
1.76−
6.02
Gain Error
The first code transition should occur at an analog value ½ LSB
above negative full scale. The last transition should occur at an
analog value 1 ½ LSB below the positive full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
Offset Error
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Output Propagation Delay (tPD)
The delay between the clock rising edge and the time when all
bits are within valid logic levels.
Power-Supply Rejection Ratio
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at its maximum limit.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered) or dBFS (always related
back to converter full scale).
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1 ½ LSBs beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Rev. 0 | Page 9 of 40
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at T
MIN
or T
MAX
.
Total Harmonic Distortion (THD)
The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.
Two -Ton e SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
CMOS Compatible Output Logic
Mode Control Pin. OUTPUT MODE
= 0 for CMOS mode, and OUTPUT
MODE = 1 (AVDD1) for LVDS
outputs.
Data Format Select Pin. CMOS
control pin that determines the
format of the output data. DFS =
high (AVDD1) for twos complement, DFS = low (ground) for
offset binary format.
Set Pin for LVDS Output Current.
Place 3.7 kΩ resistor terminated to
DRGND.
Reference Mode Selection.
Connect to AGND for internal 1 V
reference, and connect to AVDD2
for external reference.
1.0 V Reference I/O—Function
Dependent on SENSE. Decouple
to ground with 0.1 µF and 10 µF
capacitors.
Analog Ground. The exposed
heat sink on the bottom of the
package must be connected to
AGND.
Differential Reference Output.
Decoupled to ground with 0.1 µF
capacitor and to REFB (Pin 14) with
0.1 µF and 10 µF capacitors.
Differential Reference Output.
Decoupled to ground with a 0.1 µF
capacitor and to REFT (Pin 13) with
21 VIN+ Analog Input—True.
22 VIN− Analog Input—Complement.
AVDD1 3.3 V (±5%) Analog Supply.
DNC
OUTPUT
MODE
AGND
AVDD2 5.0 V Analog Supply (±5%).
Do Not Connect. These
pins should float.
CMOS Compatible Output
Logic Mode Control Pin.
OUTPUT MODE = 0 for CMOS
mode, and OUTPUT MODE =
1 (AVDD1) for LVDS outputs.
Data Format Select Pin.
CMOS control pin that determines the format of the
output data. DFS = high
(AVDD1) for twos complement, DFS = low (ground) for
offset binary format.
Reference Mode Selection.
Connect to AGND for internal
1 V reference, and connect to
AVDD2 for external reference.
1.0 V Reference I/O—
Function Dependent on
SENSE. Decouple to ground
with 0.1 µF and 10 µF
capacitors.
Analog Ground. The exposed
heat sink on the bottom of
the package must be
connected to AGND.
Differential Reference Output. Decoupled to ground
with 0.1 µF capacitor and to
REFB (Pin 14) with 0.1 µF and
10 µF capacitors.
Differential Reference Output. Decoupled to ground
with a 0.1 µF capacitor and to
REFT (Pin 13) with 0.1 µF and
10 µF capacitors.
Figure 32. Single-Tone SNR/SFDR vs. Clock Duty Cycle,
= 80 MSPS, 10.3 MHz @ −0.5 dBFS
F
SAMPLE
05089-032
Rev. 0 | Page 18 of 40
100
95
90
85
80
(dB)
75
70
65
60
2.52.72.93.13.33.53.73.9
SFDR (dBc)
SNR (dB)
V
COMMON-MODE (V)
IN
Figure 35. Single-Tone SNR/SFDR vs.
Common-Mode Voltage 80 MSPS/10.3 MHz
V
IN
05089-035
Page 19
AD9444
0.961
0.960
0.959
0.958
0.957
0.956
0.955
0.954
REFERENCE VOLTAGE (V)
0.953
0.952
0.951
–20020406080
–40
TEMPERATURE (°C)
Figure 36. VREF vs. Temperature
05089-036
GAIN (%FS)
0.2
0.1
–0.1
–0.2
–0.3
–0.4
–0.5
0
–20020406080
–40
TEMPERATURE (°C)
Figure 38. Gain vs. Temperature
05089-038
1.00
0.75
0.50
0.25
0
–0.25
DNL ERROR (LSB)
–0.50
–0.75
–1.00
02048 4096 6144 8192 10240 12288 14336 16384
OUTPUT CODE
Figure 37. DNL Error vs. Output Code, 80 MSPS, A
= 15 MHz
IN
05089-037
1.00
0.75
0.50
0.25
0
–0.25
INL ERROR (LSB)
–0.50
–0.75
–1.00
02048 4096 6144 8192 10240 12288 14336 16384
OUTPUT CODE
Figure 39. INL Error vs. Output Code, 80 MSPS, A
= 15 MHz
IN
05089-039
Rev. 0 | Page 19 of 40
Page 20
AD9444
THEORY OF OPERATION
The AD9444 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated, high bandwidth,
track-and-hold circuit that samples the signal prior to quantization by the 14-bit pipeline ADC core. The device includes an
on-board reference and input logic that accepts TTL, CMOS, or
LVPECL levels. The digital output logic levels are user selectable
as standard 3 V CMOS or LVDS (ANSI-644 compatible) via the
OUTPUT MODE pin.
ANALOG INPUT AND REFERENCE OVERVIEW
A stable and accurate 0.5 V voltage reference is built into the
AD9444. The input range can be adjusted by varying the reference voltage applied to the AD9444, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly. The
various reference modes are described in the next few sections.
Internal Reference Connection
A comparator within the AD9444 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table 9. If SENSE is grounded,
the reference amplifier switch is connected to the internal resistor divider (see Figure 40), setting VREF to ~1 V. Connecting
the SENSE pin to VREF switches the reference amplifier output
to the SENSE pin, completing the loop and providing a ~0.5 V
reference output. If a resistor divider is connected, as shown in
Figure 41, the switch again sets to the SENSE pin. This puts the
reference amplifier in a noninverting mode with the VREF
output defined as
R2
VREF10.5
⎛
⎜
⎝
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
⎞
+×=
⎟
R1
⎠
Internal Reference Trim
The internal reference voltage is trimmed during the production test to adjust the gain (analog input voltage range) of the
AD9444. Therefore, there is little advantage to the user supplying an external voltage reference to the AD9444. The gain trim
is performed with the AD9444’s input range set to 2 V p-p
nominal (SENSE connected to AGND). Because of this trim,
and because the 2 V p-p analog input range provides maximum
ac performance, there is little benefit to using analog input
ranges < 2 V p-p. Users are cautioned that the differential
nonlinearity of the ADC varies with the reference voltage.
Configurations that use < 2 V p-p may exhibit missing codes
and, therefore, degraded noise and distortion performance.
VIN+
10µF+0.1µF
10µF+0.1µF
VIN–
ADC
CORE
VREF
SELECT
LOGIC
SENSE
0.5V
AD9444
Figure 40. Internal Reference Configuration
VIN+
VIN–
VREF
R2
SENSE
SELECT
LOGIC
ADC
CORE
REFT
0.1µF
0.1µF10µF
REFB
0.1µF
REFT
0.1µF
0.1µF10µF
REFB
0.1µF
+
+
05089-043
Rev. 0 | Page 20 of 40
R1
Figure 41. Programmable Reference Configuration
0.5V
AD9444
05089-042
Page 21
AD9444
Table 9. Reference Configuration Summary
Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p)
External Reference AVDD N/A 2 × External Reference
Internal Fixed Reference VREF 0.5 1.0
Programmable Reference 0.2 V to VREF
R2
⎛
⎜
⎝
⎞
(See Figure 41)
+×
10.5
⎟
R1
⎠
Internal Fixed Reference AGND to 0.2 V 1.0 2.0
External Reference Operation
The AD9444’s internal reference is trimmed to enhance the gain
accuracy of the ADC. An external reference may be more stable
over temperature, but the gain of the ADC is not likely to be
VIN+
improved. Figure 36 shows the typical drift characteristics of the
internal reference in both 1 V and 0.5 V modes.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
1Vp-p
VIN–
DIGITAL OUT = ALL 1sDIGITAL OUT = ALL 0s
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1 V.
Analog Inputs
As with most new high speed, high dynamic range ADCs, the
analog input to the AD9444 is differential. Differential inputs
improve on-chip performance as signals are processed through
attenuation and gain stages. Most of the improvement is a result
of differential analog stages having high rejection of even-order
harmonics. There are also benefits at the PCB level. First,
differential inputs have high common-mode rejection of stray
signals, such as ground and power noise. Second, they provide
good rejection of common-mode signals, such as local oscillator
feedthrough. The specified noise and distortion of the AD9444
cannot be realized with a single-ended analog input, so such
configurations are discouraged. Contact ADI for recommendations of other 14-bit ADCs that support single-ended analog
input configurations.
With the 1 V reference (nominal value, see the Internal Reference Trim section), the differential input range of the AD9444’s
analog input is nominally 2 V p-p or 1 V p-p on each input
(VIN+ or VIN−).
The AD9444 analog input voltage range is offset from ground
by 3.5 V. Each analog input connects through a 1 kΩ resistor to
the 3.5 V bias voltage and to the input of a differential buffer.
The internal bias network on the input properly biases the
buffer for maximum linearity and range (see the Equivalent
Circuits section). Therefore, the analog source driving the
AD9444 should be ac-coupled to the input pins. The recommended method for driving the analog input of the AD9444 is
to use an RF transformer to convert single-ended signals to
differential (see Figure 44). Series resistors between the output
of the transformer and the AD9444 analog inputs help isolate
the analog input source from switching transients caused by the
internal sample-and-hold circuit. The series resistors, along with
the 1 kΩ resisters connected to the internal 3.5 V bias, must be
considered in impedance matching the transformers input. For
example, if R
with a 1:1 impedance ratio transformer, the input would match
a 50 Ω source with a full-scale drive of 10.0 dBm. The 50 Ω
impedance matching can also be incorporated on the secondary
side of the transformer, as shown in the evaluation board schematic (see Figure 47 and Figure 59).
Figure 42. Differential Analog Input Range for VREF = 1 V
ANALOG
INPUT
SIGNAL
Figure 43. Transformer-Coupled Analog Input Circuit
2 × VREF
3.5V
were set to 51 Ω and RS were set to 33 Ω, along
T
0.1
R
S
AIN
AD9444
R
S
µF
AIN
05089-046
R
T
ADT1–1WT
05089-045
Rev. 0 | Page 21 of 40
Page 22
AD9444
CLOCK INPUT CONSIDERATIONS
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the A/D output.
For that reason, considerable care was taken in the design of the
clock inputs of the AD9444, and the user is advised to give
careful thought to the clock source.
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be
sensitive to the clock duty cycle. Commonly a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance characteristics. The AD9444 contains a clock duty cycle
stabilizer (DCS) that retimes the nonsampling edge, providing
an internal clock signal with a nominal 50% duty cycle. As
shown in Figure 32, noise and distortion performance are nearly
flat for a 30% to 70% duty cycle with the DCS enabled. The DCS
circuit locks to the rising edge of CLK+ and optimizes timing
internally. This allows for a wide range of input duty cycles at
the input without degrading performance. Jitter in the rising
edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 30 MHz
nominally. The loop has a time constant associated with it that
needs to be considered in applications where the clock rate can
change dynamically, which requires a wait time of 1.5 µs to 5 µs
after a dynamic clock frequency increase (or decrease) before
the DCS loop is relocked to the input signal. During the time
period the loop is not locked, the DCS loop is bypassed, and the
internal device timing is dependant on the duty cycle of the
input clock signal. In such an application, it may appropriate to
disable the duty cycle stabilizer. In all other applications,
enabling the DCS circuit is recommended to maximize ac
performance.
the CLK+ and CLK− pins via a transformer or capacitors.
Figure 44 shows one preferred method for clocking the AD9444.
The clock source (low jitter) is converted from single-ended-todifferential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD9444 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9444 and limits the noise
presented to the sample clock inputs.
If a low jitter clock is available, another option is to ac couple a
differential ECL/PECL signal to the encode input pins, as shown
in Figure 46.
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (
(
t
) can be calculated using the following equation.
J
f
) and rms amplitude due only to aperture jitter
INPUT
SNR = 20 log[2πf
INPUT
× tJ]
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the duty cycle stabilizer, and logic high (AVDD1 = 3.3 V) disables the controller.
The AD9444 input sample clock signal must be a high quality,
extremely low phase noise source to prevent degradation of
performance. Maintaining 14-bit accuracy places a premium on
the encode clock phase noise. SNR performance can easily
degrade by 3 dB to 4 dB with 70 MHz analog input signals
when using a high jitter clock source. (See
AN-501, Aperture
Uncertainty and ADC System Performance, for complete
details.) For optimum performance, the AD9444 must be
clocked differentially. The sample clock inputs are internally
biased to ~2.2 V, and the input signal is usually ac-coupled into
Rev. 0 | Page 22 of 40
In the equation, the rms aperture jitter represents the root-mean
square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification. IF
undersampling applications are particularly sensitive to jitter,
see Figure 46.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9444. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.
Page 23
AD9444
75
70
65
60
55
SNR (dBc)
50
45
40
1
Figure 46. SNR vs. Input Frequency and Jitter
INPUT FREQUENCY (MHz)
0.2ps
0.5ps
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
100010010
05089-049
POWER CONSIDERATIONS
Care should be taken when selecting a power source. The use of
linear dc supplies is highly recommended. Switching supplies
tend to have radiated components that may be received by the
AD9444. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1 µF chip capacitors.
The AD9444 has separate digital and analog power supply
pins. The analog supplies are denoted AVDD1 (3.3 V) and
AVDD2 (5 V) and the digital supply pins are denoted DRVDD.
Although the AVDD1 and DRVDD supplies may be tied
together, best performance is achieved when the supplies are
separate. This is because the fast digital output swings can
couple switching current back into the analog supplies. Note
that both AVDD1 and AVDD2 must be held within 5% of the
specified voltage.
The DRVDD supply of the AD9444 is a dedicated supply for the
digital outputs, in either LVDS or CMOS output modes. When
in LVDS mode, the DRVDD should be set to 3.3 V. In CMOS
mode, the DRVDD supply may be connected from 2.5 V to
3.6 V to be compatible with the receiving logic.
DIGITAL OUTPUTS
LVDS Mode
The off-chip drivers on the chip can be configured to provide
LVDS-compatible output levels via Pin 5 (OUTPUT MODE).
LVDS outputs are available when OUTPUT MODE is CMOS
logic high (or AVDD1 for convenience) and a 3.74 kΩ R
resistor is placed at Pin 7 (LVDSBIAS) to ground. Dynamic
performance, including both SFDR and SNR, is maximized
when the AD9444 is used in LVDS mode, and designers are
encouraged to take advantage of this mode. The AD9444 outputs include complimentary LVDS outputs for each data bit
(DX+/DX−), the overrange output (OR+/OR−), and the output
data clock output (DCO+/DCO−). The R
resistor current is
SET
ratioed on-chip, setting the output current at each output equal
). A 100 Ω differential termina-
to a nominal 3.5 mA (11 ×
I
R
SET
SET
tion resistor placed at the LVDS receiver inputs results in a
nominal 350 mV swing at the receiver. LVDS mode facilitates
interfacing with LVDS receivers in custom ASICs and FPGAs
that have LVDS capability for superior switching performance
in noisy environments. Single point-to-point net topologies are
recommended with a 100 Ω termination resistor as close to the
receiver as possible. It is recommended to keep the trace length
less than 1 inch to 2 inches and to keep differential output trace
lengths as equal as possible.
CMOS Mode
In applications that can tolerate a slight degradation in dynamic
performance, the AD9444 output drivers can be configured to
interface with 2.5 V or 3.3 V logic families by matching DRVDD
to the digital supply of the interfaced logic. CMOS outputs are
available when OUTPUT MODE is CMOS logic low (or AGND
for convenience). In this mode, the output data bits are singleended CMOS, DX, as is the overrange output, OR. The output
clock is provided as a differential CMOS signal, DCO+/DCO−.
Lower supply voltages are recommended to avoid coupling
switching transients back to the sensitive analog sections of the
ADC. The capacitive load to the CMOS outputs should be
minimized, and each output should be connected to a single
gate through a series resistor (220 Ω) to minimize switching
transients caused by the capacitive loading.
TIMING
The AD9444 provides latched data outputs with a pipeline delay
of 12 clock cycles. Data outputs are available one propagation
delay (t
) after the rising edge of CLK+. Refer to Figure 2 and
PD
Figure 3 for detailed timing diagrams.
OPERATIONAL MODE SELECTION
Data Format Select
The data format select (DFS) pin of the AD9444 determines
the coding format of the output data. This pin is 3.3 V CMOS
compatible, with logic high (or AVDD1, 3.3 V) selecting twos
complement, and DFS logic low (AGND) selecting offset binary
format. Table 10 summarizes the output coding.
Output Mode Select
The OUPUT MODE pin controls the logic compatibility,
as well as the pinout of the digital outputs. This pin is a CMOS
compatible input. With OUTPUT MODE = 0 (AGND), the
AD9444 outputs are CMOS-compatible and the pin assignment
for the device is defined in Table 8. With OUTPUT MODE = 1
(AVDD1, 3.3 V), the AD9444 outputs are LVDS-compatible and
the pin assignment for the device is defined in Table 7.
Duty Cycle Stabilizer
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the DCS, and logic
high (AVDD1, 3.3 V) disables the controller.
Evaluation boards are offered to configure the AD9444 in
either CMOS or LVDS mode. Each represents a recommended
configuration for using the device over a wide range of sample
rates and analog input frequencies. These evaluation boards
provide all the support circuitry required to operate the ADC in
its various modes and configurations. Complete schematics and
layout plots follow and demonstrate the proper routing and
grounding techniques that should be applied at the system level.
It is critical that signal sources with very low phase noise
(< 1 ps rms jitter) be used to realize the ultimate performance
of the converter. Proper filtering of the input signal, to remove
harmonics and lower the integrated noise at the input, is also
necessary to achieve the specified noise performance.
The evaluation boards are shipped with an ac to 6 V dc power
supply. The evaluation boards include low dropout regulators to
generate the various dc supplies required by the AD9444 and its
support circuitry. Separate power supplies are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers
(see Figure 47 to Figure 50 and Figure 59 to Figure 61).
Both the LVDS and CMOS versions of the evaluation board are
compatible with the high speed ADC FIFO evaluation kit (part
number HSC-ADC-EVALA-SC). The kit includes a high speed
data capture board that provides a hardware solution for capturing up to 32Ksamples of high speed ADC output data in a FIFO
memory chip (user upgradeable to 256K samples). Software is
provided to enable the user to download the captured data to a
PC via the USB port. This software also includes a behavioral
model of the AD9444 and many other high speed ADCs.
Behavioral modeling of the AD9444 is also available at
www.analog.com/ADIsimADC. The ADIsimA DC™ software
supports virtual ADC evaluation using ADI proprietary
behavioral modeling technology. This allows rapid comparison
between the AD9444 and other high speed ADCs, with or
without hardware evaluation boards.
The AD9444 LVDS evaluation board includes an on-board,
LVDS-to-CMOS translator, but the user may choose to remove
the translator and terminations to access the LVDS outputs
directly.
The CMOS evaluation board includes a buffer for the output
data and the DCO output clock of the AD9444.
Capacitors, Select 10 V Ceramic X5R 0402 Panasonic
1
Resistors, Select 1/16 W 1% 0402 SMD Panasonic
Rev. 0 | Page 38 of 40
Page 39
AD9444
2
F
L
E
OUTLINE DIMENSIONS
1.20
0.75
MAX
0.60
0.45
SEATING
PLANE
0.20
0.09
NOTES
1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION O
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNA
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIV
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
3. THE EXPOSED HEAT SINK SOLDERED TO THE GROUND PLANE IS REQUIRED FOR THE 100-LEAD TQFP/EP.
1
25
2650
7°
3.5°
0°
Figure 70. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
16.00 SQ
14.00 SQ
76100
75
TOP VIEW
(PINS DOWN)
51
0.50 BSC
COMPLIANT TO JEDEC STANDARDS MS-026AED-HD
0.27
0.22
0.17
0.15
0.05
75
51
1.05
1.00
0.95
COPLANARITY
0.08
(SV-100-1)
Dimensions shown in millimeters
76100
BOTTOM VIEW
(PINS UP)
CONDUCTIVE
HEAT SINK
6.50
NOM
1
25
2650
ORDERING GUIDE
Model Temperature Range Package Description Package Outline