ANALOG DEVICES AD9434 Service Manual

12-Bit, 370 MSPS/500 MSPS,

V

A

FEATURES

SNR = 65 dBFS at fIN up to 250 MHz at 500 MSPS ENOB of 10.5 bits at f SFDR = 78 dBc at f Integrated input buffer Excellent linearity

DNL = ±0.5 LSB typical

INL = ±0.6 LSB typical LVDS at 500 MSPS (ANSI-644 levels) 1 GHz full power analog bandwidth On-chip reference, no external decoupling required Low power dissipation

690 mW at 500 MSPS—LVDS SDR mode

660 mW at 500 MSPS—LVDS DDR mode Programmable (nominal) input voltage range

1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal

1.8 V analog and digital supply operation Selectable output data format (offset binary, twos

complement, Gray code) Clock duty cycle stabilizer Integrated data clock output with programmable clock and

data alignment

APPLICATIONS

Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

GENERAL DESCRIPTION

The AD9434 is a 12-bit monolithic sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The part operates at up to a 500 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution. The VREF pin can be used to monitor the internal reference or provide an external voltage reference (external reference mode must be enabled through the SPI port).

The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

up to 250 MHz at 500 MSPS (−1.0 dBFS)

IN

up to 250 MHz at 500 MSPS (−1.0 dBFS)

IN

1.8 V Analog-to-Digital Converter AD9434

FUNCTIONAL BLOCK DIAGRAM

REF

REFERENCE

CML

VIN+

VIN–

CLK+

CLK–

TRACK-AND-HOLD

CLOCK

MANAGEME NT

SCLK/DFS

Fabricated on an advanced BiCMOS process, the AD9434 is available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C). This part is protected under a U.S. patent.

PRODUCT HIGHLIGHTS

1. High Performance.

Maintains 65 dBFS SNR at 500 MSPS with a 250 MHz input.

2. Low Power.

Consumes only 660 mW at 500 MSPS.

3. Ease of Use.

LVDS output data and output clock signal allow interface to FPGA technology. The on-chip reference and sampleand-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design.

4. Serial Port Control.

Standard serial port interface supports various product functions, such as data formatting, power-down, gain adjust, and output test pattern generation.

5. The AD9434 is pin compatible with the AD9230, and can

be substituted in many applications with minimal design changes.

AGNDPWDN

12 12

ADC

CORE

SERIAL PORT

SDIO CSB

Figure 1.

VDD

AD9434

OUTPUT

STAGING

LVDS

DRVDD

DRGND

D11± TO D0±

OR+

OR–

DCO+

DCO–

09383-001

AD9434

REVISION HISTORY

5/11—Rev. 0 to Rev. A

Changes to General Description .................................................... 1

Changes to Table 4, Aperture Time Values ................................... 6

Changes to Figure 32 ...................................................................... 17

Changes to Figure 42 ...................................................................... 19

Changes to Table 13, Register 10, Bits[7:0] Value, Register 14 Default Value, Register 15 Default Value, Register 17, Bit 7 Value

and Register 18, Bit[4:0] Values .................................................... 26

3/11—Revision 0: Initial Version

Rev. A | Page 2 of 28

AD9434

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 1.

Parameter1 Temp Min Typ Max Min Typ Max Unit

RESOLUTION 12 12 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Offset Error 25°C ±0.25 ±0.25 mV Full −3.0 +1.0 −3.0 +1.0 mV Gain Error 25°C 1.0 1.0 % FS Full −5.0 +7.0 −5.0 +7.0 % FS Differential Nonlinearity (DNL) 25°C ±0.4 ±0.5 LSB Full −0.9 +0.9 −0.95 +1.0 LSB Integral Nonlinearity (INL) 25°C ±0.4 ±0.6 LSB Full −0.92 +0.92 −1.3 +1.3 LSB

INTERNAL REFERENCE

VREF Full 0.71 0.75 0.78 0.71 0.75 0.78 V

TEMPERATURE DRIFT

Offset Error Full 18 18 μV/°C Gain Error Full 0.07 0.07 %/°C

ANALOG INPUTS (VIN+, VIN−)

Differential Input Voltage Range2 Full 1.18 1.5 1.6 1.18 1.5 1.6 V p-p Input Common-Mode Voltage Full 1.7 1.7 V Input Resistance (Differential) Full 1 1 kΩ Input Capacitance (Differential) 25°C 1.3 1.3 pF

POWER SUPPLY

AVDD Full 1.75 1.8 1.9 1.75 1.8 1.9 V DRVDD Full 1.75 1.8 1.9 1.75 1.8 1.9 V Supply Currents

3

I

Full 260 280 283 301 mA

AVDD

3

I

/SDR Mode4 Full 88 100 100 114 mA

DRVDD

3

I

/DDR Mode5 Full 70 80 82 96 mA

DRVDD

Power Dissipation

SDR Mode4 Full 625 685 690 747 mW DDR Mode5 Full 595 648 657 715 mW Standby Mode Full 40 50 40 50 mW Power-Down Mode Full 2.5 7 2.5 7 mW

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section.

3

I

and I

AVDD

4

Single data rate mode; this is the default mode of the AD9434.

5

Double data rate mode; user-programmable feature. See the Memory Map section.

are measured with a −1 dBFS, 30.3 MHz sine input at rated sample rate.

DRVDD

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.

MAX

AD9434-370 AD9434-500

Rev. A | Page 3 of 28

AD9434

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 2.

Parameter

SNR

SINAD

EFFECTIVE NUMBER OF BITS (ENOB)

WORST HARMONIC (SECOND or THIRD)

SFDR

WORST OTHER HARMONIC (SFDR EXCLUDING SECOND and THIRD)

TWO-TONE IMD

ANALOG INPUT BANDWIDTH

1

All ac specifications tested by driving CLK+ and CLK− differentially.

2

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

1, 2

Temp Min Typ Max Min Typ Max Unit

fIN = 30.3 MHz 25°C 66.3 65.9 dBFS fIN = 70.3 MHz 25°C 66.2 65.9 dBFS fIN = 100.3 MHz 25°C 66.1 65.8 dBFS Full 65.3 64.5 dBFS fIN = 250.3 MHz 25°C 65.5 65.2 dBFS fIN = 450.3 MHz 25°C 64.0 63.5 dBFS

fIN = 30.3 MHz 25°C 66.1 65.9 dBFS fIN = 70.3 MHz 25°C 66.1 65.8 dBFS fIN = 100.3 MHz 25°C 66.0 65.8 dBFS Full 65.2 64.4 dBFS fIN = 250.3 MHz 25°C 65.3 64.8 dBFS fIN = 450.3 MHz 25°C 63.7 62.9 dBFS

fIN = 30.3 MHz 25°C 10.7 10.7 Bits fIN = 70.3 MHz 25°C 10.7 10.6 Bits fIN = 100.3 MHz 25°C 10.7 10.6 Bits fIN = 250.3 MHz 25°C 10.6 10.5 Bits fIN = 450.3 MHz 25°C 10.3 10.2 Bits

fIN = 30.3 MHz 25°C −93 −93 dBc fIN = 70.3 MHz 25°C −89 −91 dBc fIN = 100.3 MHz 25°C −83 −87 dBc Full −75 −74 dBc fIN = 250.3 MHz 25°C −80 −78 dBc fIN = 450.3 MHz 25°C −78 −69 dBc

fIN = 30.3 MHz 25°C 89 84 dBc fIN = 70.3 MHz 25°C 88 82 dBc fIN = 100.3 MHz 25°C 83 83 dBc Full 75 74 dBc fIN = 250.3 MHz 25°C 79 78 dBc fIN = 450.3 MHz 25°C 78 68 dBc

fIN = 30.3 MHz 25°C −90 −85 dBc fIN = 70.3 MHz 25°C −90 −82 dBc fIN = 100.3 MHz 25°C −91 −84 dBc Full −75 −74 dBc fIN = 250.3 MHz 25°C −83 −85 dBc fIN = 450.3 MHz 25°C −82 −78 dBc

f

= 119.5 MHz, f

IN1

= 122.5 MHz 25°C −85 −85 dBc

IN2

Full Power 25°C 1 1 GHz

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.

MAX

AD9434-370 AD9434-500

Rev. A | Page 4 of 28

AD9434

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 3.

AD9434-370 AD9434-500

Parameter1 Temp Min Typ Max Min Typ Max Unit

CLOCK INPUTS

Logic Compliance Full CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 0.9 V Differential Input Voltage

High Level Input (VIH) Full 0.2 1.8 0.2 1.8 V p-p

Low Level Input (VIL) Full −1.8 −0.2 −1.8 −0.2 V p-p High Level Input Current (IIH) Full −10 +10 −10 +10 μA Low Level Input Current (IIL) Full −10 +10 −10 +10 μA Input Resistance (Differential) Full 8 10 12 8 10 12 kΩ Input Capacitance Full 4 4 pF

LOGIC INPUTS

Logic 1 Voltage Full 0.8 × DRVDD 0.8 × DRVDD V Logic 0 Voltage Full 0.2 × DRVDD 0.2 × DRVDD V Logic 1 Input Current (SDIO, CSB) Full 0 0 μA Logic 0 Input Current (SDIO, CSB) Full −60 −60 μA Logic 1 Input Current (SCLK, PDWN) Full 50 50 μA Logic 0 Input Current (SCLK, PDWN) Full 0 0 μA Input Capacitance 25°C 4 4 pF

LOGIC OUTPUTS2

VOD Differential Output Voltage Full 247 454 247 454 mV VOS Output Offset Voltage Full 1.125 1.375 1.125 1.375 V Output Coding Twos complement, Gray code, or offset binary (default)

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

LVDS R

TERMINATION

= 100 Ω.

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.

MAX

Rev. A | Page 5 of 28

AD9434

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 4.

AD9434-370 AD9434-500 Parameter Temp Min Typ Max Min Typ Max Unit

Maximum Conversion Rate Full 370 Minimum Conversion Rate Full

1, 2

CLK+ Pulse Width High (tCH) CLK+ Pulse Width Low (tCL) Full 1.1 11 0.9 11 ns Output (LVDS—SDR Mode)1

Data Propagation Delay (tPD) Full 0.85 0.85 ns Rise Time (tR) (20% to 80%) 25°C 0.15 0.15 ns Fall Time (tF) (20% to 80%) 25°C 0.15 0.15 ns DCO Propagation Delay (t Data to DCO Skew (t

CPD

) Full 0.15 0.38 0.15 0.38 ns

SKEW

Latency Full 15 15 Cycles

Output (LVDS—DDR Mode)2

Data Propagation Delay (tPD) Full 0.6 0.6 ns Rise Time (tR) (20% to 80%) 25°C 0.15 0.15 ns Fall Time (tF) (20% to 80%) 25°C 0.15 0.15 ns DCO Propagation Delay (t Data to DCO Skew (t

CPD

) Full −0.07 +0.07 −0.07 +0.07 ns

SKEW

Latency Full 15 15 Cycles Aperture Time (tA) 25°C 0.85 0.85 ns Aperture Uncertainty (Jitter, tJ) 25°C 80 80 fs rms

1

See Figure 2.

2

See Figure 3.

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.

MAX

500 50

MSPS

50 MSPS

Full 1.1 11 0.9 11 ns

) Full 0.6 0.6 ns

Rev. A | Page 6 of 28

AD9434

V

Timing Diagrams

VIN+, VIN–

N – 1

t

A

N

N + 3

N + 1

N + 2

N + 4

N + 5

CLK+

CLK–

DCO+

DCO–

Dx+

Dx–

IN+, VIN–

CLK+

CLK–

DCO+

DCO–

D0/D6+

D0/D6–

t

CH

N – 1

t

CPD

CL

1/

f

S

t

SKEW

t

PD

N – 15 N – 14 N – 13 N – 12 N – 11

09383-002

Figure 2. Single Data Rate Mode

t

A

N

N + 3

N + 1

t

CH

CL

t

CPD

1/

f

S

t

SKEW

t

PD

D6

N – 15D0N – 14D6N – 14D0N – 13D6N – 13D0N – 12D6N – 12D0N – 11D6N – 11D0N – 10

N + 2

N + 4

N + 5

D5/D11+

D5/D11–

D11

N – 15D5N – 14

6 LSBs

D11

N – 14D5N – 13

6 MSBs

D11

N – 13D5N – 12

D11

N – 12D5N – 11

D11

N – 11D5N – 10

09383-003

Figure 3. Double Data Rate Mode

Rev. A | Page 7 of 28

AD9434

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Electrical

AVDD to AGND −0.3 V to +2.0 V

DRVDD to DRGND −0.3 V to +2.0 V

AGND to DRGND −0.3 V to +0.3 V

AVDD to DRVDD −2.0 V to +2.0 V

D0+/D0− Through D11+/D11−

to DRGND DCO+, DCO− to DRGND −0.3 V to DRVDD + 0.2 V OR+, OR− to DRGND −0.3 V to DRVDD + 0.2 V CLK+ to AGND −0.3 V to AVDD + 0.2 V CLK− to AGND −0.3 V to AVDD + 0.2 V VIN+ to AGND −0.3 V to AVDD + 0.2 V VIN− to AGND −0.3 V to AVDD + 0.2 V CML to AGND −0.3 V to AVDD + 0.2 V VREF to AGND −0.3 V to AVDD + 0.2 V SDIO to DRGND −0.3 V to DRVDD + 0.2 V PDWN to AGND −0.3 V to DRVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.2 V SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V

Environmental

Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature

(Soldering, 10 sec)

Junction Temperature 150°C

−0.3 V to DRVDD + 0.2 V

300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the PCB increases the reliability of the solder joints, maximizing the thermal capability of the package.

Table 6.

Package Type θJA θ

56-Lead LFCSP_VQ (CP-56-5) 23.7 1.7 °C/W

Unit

JC

Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θ

JA

. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the θ

.

JA

ESD CAUTION

Rev. A | Page 8 of 28

AD9434

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

CO–

D0–

DCO+

D0+

D

D1–

D1+

D2–

D2+

52

53

54

55

56

PIN 1

1D3–

INDICATOR

2D3+ 3D4– 4D4+ 5D5– 6D5+ 7DRVDD 8DRGND

9D6– 10D6+ 11D7– 12D7+

PIN 0 (EXPOSED PADDLE ) = AGND

13D8– 14D8+

51

AD9434

TOP VIEW

(Not to Scale)

DRGND

50

49

48

AVDD

DRVDD

AVDD

CLK–

CLK+

44

43

47

46

45

42 AVDD 41 AVDD 40 CML 39 AVDD 38 AVDD 37 AVDD 36 VIN– 35 VIN+ 34 AVDD 33 AVDD 32 AVDD 31 VREF 30 AVDD 29 PWDN

16

15

D9–

D9+

NOTES

1. DNC = DO NOT CONNECT. DO NOT CO NNECT TO THIS PIN.

2. AGND AND DRGND SHOULD BE T IED TO A COMMON QUIET G ROUND PLANE.

3. THE EXPOSED PADDLE MUST BE SOLDERED T O A GROUND PLANE .

21

17

18

19

20

23

22

OR–

D10–

OR+

D11–

D10+

D11+

DRGND

28

27

26

25

24

CSB

DNC

SDIO

DRVDD

SCLK/DFS

09383-004

Figure 4. Pin Configuration—Single Data Rate Mode

Table 7. Pin Function Descriptions—Single Data Rate Mode

Pin No. Mnemonic Description

0 AGND1 Analog Ground. The exposed paddle must be soldered to a ground plane. 30, 32 to 34, 37 to 39,

AVDD 1.8 V Analog Supply.

41 to 43, 46 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 8, 23, 48 DRGND1 Digital Output Ground. 35 VIN+ Analog Input—True. 36 VIN− Analog Input—Complement. 40 CML

Common-Mode Output. Enabled through the SPI, this pin provides a reference for the

optimized internal bias voltage for VIN+/VIN−. 44 CLK+ Clock Input—True. 45 CLK− Clock Input—Complement. 31 VREF Voltage Reference Internal/Input/Output. Nominally 0.75 V. 28 DNC Do Not Connect. Do not connect to this pin. This pin should be left floating. 25 SDIO Serial Port Interface (SPI) Data Input/Output (Serial Port Mode). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 29 PWDN Chip Power-Down. 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 51 D0− D0 Complement Output (LSB). 52 D0+ D0 True Output (LSB). 53 D1− D1 Complement Output. 54 D1+ D1 True Output. 55 D2− D2 Complement Output. 56 D2+ D2 True Output. 1 D3− D3 Complement Output. 2 D3+ D3 True Output. 3 D4− D4 Complement Output.

Rev. A | Page 9 of 28

ANALOG DEVICES AD9434 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS