Analog Devices AD9433 Service Manual

12-Bit, 105 MSPS/125 MSPS

V

CC

AIN

AIN

ENCODE

ENCODE

REF
OUT

REF

IN

GND

V

DD

D11–D0

DFS

SFDR

12

12

PIPELINE

ADC

T/H

ENCODE

TIMING

REF

OUTPUT

STAGING

AD9433

a

FEATURES
IF Sampling up to 350 MHz
SNR = 67.5 dB, f
SFDR = 83 dBc, f
SFDR = 72 dBc, f
2 V p-p Analog Input Range Option
On-Chip Clock Duty Cycle Stabilization
On-Chip Reference and Track/Hold
SFDR Optimization Circuit
Excellent Linearity:

DNL = 0.25 LSB (Typ)

INL = 0.5 LSB (Typ)
750 MHz Full Power Analog Bandwidth
Power Dissipation = 1.35 W Typical @ 125 MSPS
Two’s Complement or Offset Binary Data Format

5.0 V Analog Supply Operation

2.5 V to 3.3 V TTL/CMOS Outputs

APPLICATIONS
Cellular Infrastructure Communication Systems

3G Single and Multicarrier Receivers

IF Sampling Schemes
Wideband Carrier Frequency Systems

Point to Point Radios

LMDS, Wireless Broadband

MMDS Base Station Units

Cable Reverse Path
Communications Test Equipment
Radar and Satellite Ground Systems

GENERAL INTRODUCTION

The AD9433 is a 12-bit monolithic sampling analog-to-digital
converter with an on-chip track-and-hold circuit and
for ease of use. The product operates up to
sion rate and is optimized for outstanding dynamic performance
in wideband and high IF carrier systems.

The ADC requires a 5 V analog power supply and a differential
encode clock for full performance operation. No external refer­ence or driver components are required for many applications.
The digital outputs are TTL/CMOS compatible and a separate
output power supply pin supports interfacing with 3.3 V or

2.5 V logic.

A user-selectable, on-chip proprietary circuit optimizes spurious­free dynamic range (SFDR) versus signal-to-noise-and-distortion
(SINAD) ratio performance for different input signal frequencies,
providing as much as 83 dBc SFDR performance over the dc
to 70 MHz band.

up to Nyquist @ 105 MSPS

IN

70 MHz @ 105 MSPS

IN

150 MHz @ 105 MSPS

IN

125 MSPS conver-

is designed

IF Sampling A/D Converter

AD9433

FUNCTIONAL BLOCK DIAGRAM

The encode clock supports either differential or single-ended
input and is PECL-compatible. The output format is user­selectable for binary or two’s complement and provides an
overrange (OR) signal.

Fabricated on an advanced BiCMOS process, the AD9433 is
available in a thermally enhanced 52-lead plastic quad flatpack
specified over the industrial temperature
+85°C) and is pin-compatible with the AD9432.

PRODUCT HIGHLIGHTS

1. IF Sampling

The AD9433 maintains outstanding ac performance up to
input frequencies of 350 MHz. Suitable for 3G Wideband
Cellular IF sampling receivers.

2. Pin-Compatibility
This ADC has the same footprint and pin layout as the
AD9432, 12-Bit 80/105 MSPS ADC.

3. SFDR Performance
A user-selectable on-chip circuit optimizes SFDR performance
as much at 85 dBc from dc to 70 MHz.

4. Sampling Rate
At 125 MSPS, this ADC is ideally suited for current wireless
and wired broadband applications such as LMDS/MMDS
and cable reverse path.

range (–40°C to

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD9433–SPECIFICATIONS

DC SPECIFICATIONS

(VDD = 3.3 V, VCC = 5 V; internal reference; differential encode input, unless otherwise noted.)

◊

Test AD9433BSQ-105 AD9433BSQ-125

Parameter Temp Level Min Typ Max Min Typ Max Unit

RESOLUTION 12 12 Bits

ACCURACY

No Missing Codes Full VI Guaranteed Guaranteed
Offset Error Full VI –5 0 +5 –5 0 +5 mV
Gain Error
Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

1

2

2

25⬚CI –7 ⫾1+3 –7⫾1+3 % FS
25⬚C I –0.75 ⫾0.25 +0.75 –0.75 ⫾0.3 +0.75 LSB
Full VI –1 +1 –1 +1 LSB
25⬚C I –1.0 ⫾0.5 +1.0 –1.0 ⫾0.5 +1.0 LSB
Full VI –1.3 +1.3 –1.3 +1.3 LSB

THERMAL DRIFT

Offset Error Full V –50 –50 ppm/⬚C
Gain Error

1

Full V –125 –125 ppm/⬚C

Reference Full V ± 80 ±80 ppm/⬚C

REFERENCE

Internal Reference Volatge (VREFOUT) Full I 2.4 2.5 2.6 2.4 2.5 2.6 V
Output Current (VREFOUT) Full V 100 100 µA
Input Current (VREFIN) Full IV 50 50 µA

ANALOG INPUTS

Differential Input Voltage Range Full V 2.0 2.0 V
(AIN, AIN)
Common-Mode Voltage Full V 4.0 4.0 V
Input Resistance Full VI 2 3 4 2 3 4 kΩ
Input Capacitance Full V 4 4 pF
Analog Bandwidth, Full Power Full V 750 750 MHz

POWER SUPPLY

V

CC

V

DD

Power Dissipation
Power Supply Rejection Ratio (PSRR) 25⬚CI ⫾3 ⫾3 mV/V

2

IV

CC

2

IV

DD

3

Full IV 4.75 5.0 5.25 4.75 5.0 5.25 V
Full IV 2.7 3.3 2.7 3.3 V
Full VI 1275 1425 1350 1500 mW

Full VI 255 285 270 300 mA
Full VI 12.5 14 16 18 mA

ENCODE INPUTS

Internal Common-Mode Bias Full V 3.75 3.75 V
Differential Input (ENC – ENC) Full V 500 500 mV
Input Voltage Range Full IV –0.5 V

+ 0.05 –0.5 V

CC

+ 0.05 V

CC

Input Common-Mode Range Full IV 2.0 4.25 2.0 4.25 V
Input Resistance Full VI 6 6 kΩ
Input Capacitance 25⬚CV 3 3 pF

DIGITAL INPUTS

Input High Voltage Full I 2.0 2.0 V
Input Low Voltage Full I 0.8 0.8 V
Input High Current (VIN = 5 V) Full V 50 50 µA
Input Low Current (VIN = 0 V) Full V 50 50 µA

DIGITAL OUTPUTS

Logic “1” Voltage Full VI VDD – 0.05 VDD – 0.05 V
Logic “0” Voltage Full VI 0.05 0.05 V
Output Coding Two’s Complement or Offset Binary

NOTES

1

Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p differential analog input).

2

SFDR disabled (SFDR = GND) for DNL and INL specifications.

3

Power dissipation measured with rated encode and a dc analog input (Outputs Static, I

Specifications subject to change without notice.

VDD

= 0). I

VCC

and I

measured with 10.3 MHz analog input @ –0.5 dBFS.

VDD

–2–

REV. 0

AD9433

AC SPECIFICATIONS

(VDD = 3.3 V, VCC = 5 V; differential encode input, unless otherwise noted.)

Test AD9433BSQ-105 AD9433BSQ-125

Parameter Temp Level Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE*

Signal-to-Noise Ratio (SNR)
(Without Harmonics)

= 10.3 MHz 25⬚C I 66.5 68.0 66.0 67.7 dB

f

IN

= 49 MHz 25⬚C I 65.5 67.5 64.0 66.0 dB

f

IN

= 70 MHz 25⬚C V 67.0 65.4 dB

f

IN

= 150 MHz 25⬚C V 65.4 62.0 dB

f

IN

= 250 MHz 25⬚C V 63.7 60.0 dB

f

IN

Signal-to-Noise Ratio and Distortion (SINAD)
(With Harmonics)
f

= 10.3 MHz 25⬚C I 66.0 68.0 65.0 67.0 dB

IN

= 49 MHz 25⬚C I 64.0 67.5 63.5 65.5 dB

f

IN

= 70 MHz 25⬚C V 66.9 64.5 dB

f

IN

= 150 MHz 25⬚C V 64.0 61.5 dB

f

IN

f

= 250 MHz 25⬚C V 61.2 57.7 dB

IN

Effective Number of Bits
f

= 10.3 MHz 25⬚C I 11.1 10.9 Bits

IN

= 49 MHz 25⬚C I 11.0 10.7 Bits

f

IN

= 70 MHz 25⬚C V 10.9 10.6 Bits

f

IN

= 150 MHz 25⬚C V 10.4 10.0 Bits

f

IN

f

= 250 MHz 25⬚C V 9.9 9.4 Bits

IN

2nd and 3rd Harmonic Distortion

= 10.3 MHz 25⬚C I –78 –85 –76 –85 dBc

f

IN

= 49 MHz 25⬚C I –73 –80 –72 –76 dBc

f

IN

= 70 MHz 25⬚C V –83 –78 dBc

f

IN

= 150 MHz 25⬚C V –72 –67 dBc

f

IN

f

= 250 MHz 25⬚C V –67 –65 dBc

IN

Worst Other Harmonic or Spur
(Excluding Second and Third)

= 10.3 MHz 25⬚C I –88 –92 –84 –90 dBc

f

IN

= 49 MHz 25⬚C I –82 –89 –82 –87 dBc

f

IN

= 70 MHz 25⬚C V –87 –85 dBc

f

IN

= 150 MHz 25⬚C V –87 –84 dBc

f

IN

f

= 250 MHz 25⬚C V –85 –76 dBc

IN

Two-Tone Intermod Distortion (IMD3)

= 49.3 MHz, f

f

IN1

f

= 150 MHz, f

IN1

*SNR/Harmonics based on an analog input voltage of –0.5 dBFS referenced to a 2 V full-scale input range. Harmonics are specified with the SFDR active

(SFDR = +5 V). SNR/SINAD specified with SFDR disabled (SFDR = Ground).

Specifications subject to change without notice.

= 50.3 MHz 25⬚C V –92 –90 dBc

IN2

= 151 MHz 25⬚C V –80 –76 dBc

IN2

SWITCHING SPECIFICATIONS

(VDD = 3.3 V, VCC = 5 V; differential encode input, unless otherwise noted.)

Test AD9433BSQ-105 AD9433BSQ-125

Parameter Temp Level Min Typ Max Min Typ Max Unit

Encode Rate Full IV 10 105 10 125 MSPS
Encode Pulsewidth High (t
Encode Pulsewidth Low (t
Aperture Delay (t

)25⬚C V 2.1 2.1 ns

A

Aperture Uncertainty (Jitter)
Output Valid Time (t
Output Propagation Delay (t
Output Rise Time (t
Output Fall Time (t

R

F

) Full IV 2.9 2.4 ns

EH

) Full IV 2.9 2.4 ns

EL

1

2

)

V

PD

2

)

25⬚C V 0.25 0.25 ps rms
Full VI 2.5 4.0 2.5 4.0 ns
Full VI 4.0 5.5 4.0 5.5 ns

) Full V 2.1 2.1 ns

) Full V 1.9 1.9 ns

Out of Range Recovery Time 25⬚CV 2 2 ns
Transient Response Time 25⬚CV 2 2 ns
Latency Full IV 10 10 Cycles

NOTES

1

Aperture uncertainty includes contribution of the AD9433, crystal clock reference, and encode drive circuit.

2

tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital output swing. The digital output load during testing is

not to exceed an ac load of 10 pF or a dc current of 50 µA. Rise and fall times measured from 10% to 90%.

Specifications subject to change without notice.

REV. 0

–3–

AD9433

ABSOLUTE MAXIMUM RATINGS*

Parameter Min Max Unit

ELECTRICAL

VDD Voltage –0.5 +6.0 V

Voltage –0.5 +6.0 V

V

CC

Analog Input Voltage –0.5 V
Digital Input Voltage –0.5 V

+ 0.5 V

CC

+ 0.5 V

CC

Digital Output Current 20 mA

ENVIRONMENTAL

Operating Temperature
Range (Ambient) –40 +85 ⬚C
Maximum Junction
Temperature +150 ⬚C
Storage Temperature
Range (Ambient) –65 +125 ⬚C

*Stresses greater than those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

THERMAL CHARCTERISTICS

Thermal Resitance

52-Lead PowerQuad® 4 LQFP_ED

= 25°C/W, Soldered Heat Sink, No Airflow

␪

JA

␪

= 33°C/W, Unsoldered Heat Sink, No Airflow

JA

␪

= 2°C/W, Bottom of Package (Heat Sink)

JC

Simulated typical performance for 4-layer JEDEC board, horizontal orientation.

EXPLANATION OF TEST LEVELS

Test Level

I 100% production tested.
II 100% production tested at 25⬚C and guaranteed by design

and characterization at specified temperatures.

III Sample Tested Only

Parameter is guaranteed by design and characterization testing.

IV
V Parameter is a typical value only.
VI 100% production tested at 25⬚C and guaranteed by design

and characterization for industrial temperature range.

Model Temperature Range Package Description Package Option

AD9433BSQ-105 –40°C to +85°C (Ambient) 52-Lead Plastic Thermally Enhanced Quad Flatpack SQ-52
AD9433BSQ-125 –40°C to +85°C (Ambient) 52-Lead Plastic Thermally Enhanced Quad Flatpack SQ-52
AD9433/PCB 25°C Evaluation Board with AD9433BSQ-125

(Supports – 105 Evaluation)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9433 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

PowerQuad is a registered trademark of AMkor Technology, Inc.

–4–

REV. 0

AD9433

PIN FUNCTION DESCRIPTIONS

Pin Number Mnemonic Function

1, 3, 4, 9, 11, 33, 34, 35, 38, 39, 40, GND Analog Ground
43, 48, 51
2, 5, 6, 10, 36, 37, 44, 47, 52 V

CC

7 ENCODE Encode Clock for ADC-Complementary
8 ENCODE Encode Clock for ADC-True (ADC samples on rising edge of

14 OR Out of Range Output
15–20, 25–30 D11–D0 Digital Output
13, 22, 23, 32 V

DD

12, 21, 24, 31 DGND Digital Output Ground
41 DFS Data Format Select. Low = Two’s Complement, High = Binary;

42 SFDR MODE CMOS control pin that enables (SFDR MODE = 1), a proprietary

45 VREFIN Reference Input for ADC (2.5 V typical)
46 VREFOUT Internal Reference Output (2.5 V typical); bypass with 0.1 µF to

49 AIN Analog Input-True
50 AIN Analog Input-Complement

Analog Supply (5 V)

ENCODE)

Digital Output Power Supply (3 V)

Floats Low

circuit that may improve the spurious free dynamic range (SFDR)
performance of the AD9433. It is useful in applications where the
dynamic range of the system is limited by discrete spurious
frequency content caused by nonlinearities in the ADC transfer
function. SFDR MODE = 0 for normal operation; Floats Low.

Ground

GND

V

GND

GND

V

V

ENCODE

ENCODE

GND

V

GND

DGND

V

PIN CONFIGURATION

CC

V

GND

52 51 50 49 48 43 42 41 4047 46 45 44

1

PIN 1

2

CC

CC

CC

CC

DD

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13

14 15 16 17 18 19 20 21 22 23 24 25 26

OR

(MSB) D11

V

AIN

AIN

GND

AD9433BSQ

TOP VIEW

(Not to Scale)

D9D8D7

D10

CC

CC

V

VREFOUT

VREFIN

DD VDD

D6

V

DGND

GND

SFDR MODE

DFS

D5

DGND

GND

D4

39

38

37

36

35

34

33

32

31

30

29

28

27

GND

GND

V

CC

V

CC

GND

GND

GND

V

DD

DGND

D0 (LSB)

D1

D2

D3

REV. 0

–5–

AD9433

DEFINITIONS OF SPECIFICATIONS

Analog Bandwidth

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

Aperture Delay

The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog
input is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance

The real and complex impedances measured at each analog

Integral Nonlinearity

The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best fit straight line
determined by a least square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The maximum encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.

Noise (for Any Range within the ADC)

input port. The resistance is measured statically and the capaci­tance and differential input impedances are measured with a
network analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to
the converter to generate a fullscale response. Peak differen­tial voltage is computed by observing the voltage on a single
pin and subtracting the voltage from the other pin, which is
180 degrees out of phase. Peak to peak differential is computed
by rotating the inputs phase 180 degrees and taking the peak
measurement again. Then the difference is computed between
both peak measurements.

Differential Nonlinearity

The deviation of any code width from an ideal 1 LSB step.

Effective Number of Bits

The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:

SNR dB

MEASURED

ENOB

=

Encode Pulsewidth/Duty Cycle

–. +

176 20

.

602

log



Full - Scale




Input Amplitude

Amplitude

Pulsewidth high is the minimum amount of time that the
ENCODE

pulse should be left in logic “1” state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. See timing impli­cations of changing t

in text. At a given clock rate, these

ENCH

specs define an acceptable Encode duty cycle.

Full-Scale Input Power

Expressed in dBm. Computed using the following equation:




rms



Z




Gain

Power

Full Scale



2

V







FullScale

0 001

.

10

=

log

Gain error is the difference between the measured and ideal
full-scale input voltage range of the ADC.

Harmonic Distortion

Where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value for the particular
input level, and SIGNAL is the signal level within the ADC
reported in dB below full scale. This value includes both thermal
and quantization noise.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in
power supply voltage.

Signal-to-Noise and Distortion (SINAD)

The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.

Signal-to-Noise Ratio (without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-



nents, excluding the first five harmonics and dc.




Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak
spurious spectral component. The peak spurious component
may or may not be a harmonic. May be reported in dBc (i.e.,
degrades as signal level is lowered), or dBFS (always related back
to converter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone (f1, f2) to the rms
value of the worst third order intermodulation product; reported
in dBc. Products are located at 2f

Two-Tone SFDR

The ratio of the rms value of either input tone (f1, f2) to the rms
value of the peak spurious component. The peak spurious com­ponent may or may not be an IMD product. May be reported in
dBc (i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).

Worst Other Spur

The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.

The ratio of the rms signal amplitude fundamental frequency to
the rms signal amplitude of a single harmonic component (second,
third, etc.), reported in dBc.

V = Z 0.001 10

NOISE

××



FS – SNR – Signal

dBm dBc dBFS




– f2 and 2f2 – f1.

1

10






–6–

REV. 0

AD9433

V

CC

VREFIN

SAMPLE N–1

A

IN

ENCODE

ENCODE

D11–D0

DATA N–11

EQUIVALENT CIRCUITS

V

DD

SAMPLE N

t

A

t

EH

SAMPLE N+1 SAMPLE N+8

t

EL

DATA N–10

DATA
N–9

DATA
N–2

Figure 1. AD9433 Timing Diagram

V

CC

DATA N–1

SAMPLE N+9

t

PD

SAMPLE N+10

1/f

S

t

V

DATA N DATA N+1

V

CC

3.75k

D

X

Figure 2. Digital Output

8k

ENCODE

24k

Figure 5. Encode Inputs

AIN

AIN

15k

Figure 3. Analog Input

V

CC

8k

ENCODE

24k

3.75k

VREFOUT

15k

Figure 4. Reference Output

Figure 6. Reference Input

REV. 0

–7–

AD9433

AIN – Hz

60

050

SNR/SINAD – dB

100 150 200 250

61

62

63

64

65

66

67

SINAD

SNR

68

300

11.1

10.9

10.8

10.6

10.4

10.3

10.1

9.9

9.8

ENOBs – Bits

–Typical Performance Characteristics

0

SNR = 67.5dB

–10

SFDR = 85.0dBFS

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

0

13.1

26.3 39.4

FREQUENCY – MHz

52.5

TPC 1. FFT: fS = 105 MSPS, fIN = 49.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled

0

SNR = 68.0dB

–10

SFDR = 80.0dBFS

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

0

13.1

26.3 39.4

FREQUENCY – MHz

52.5

–95

–90

–85

–80

dBc

–75

–70

–65

–60

0

50

100 150 200 250

AIN – MHz

WORST OTHER

3RD HARMONIC

2ND HARMONIC

TPC 4. Harmonics (Second, Third, Worst Other) vs. AIN
Frequency. AIN @ –0.5 dBFS, f

= 105 MSPS, SFDR Enabled

S

TPC 2. FFT: fS = 105 MSPS, fIN = 49.3 MHz, Differential

AIN @ –0.5 dBFS, SFDR Disabled

0

SNR = 67.7dB

–10

SFDR = 76.0dBFS

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

0

TPC 3. FFT: fS = 125 MSPS, fIN = 49.3 MHz, Differential

FREQUENCY – MHz

AIN @ –0.5 dBFS, SFDR Enabled

46.831.215.6

62.5

–8–

TPC 5. SNR vs. AIN Frequency. Differential AIN @
–0.5 dBFS, 105 MSPS, SFDR Disabled

100

95

90

85

80

75

SNR/SINAD – dB

70

65

60

10 30

2ND

–dBc

50 70 90 110

ENCODE – MSPS

3RD
–dBc

SNR

SINAD

140

TPC 6. SNR/SINAD and Harmonic Distortion vs.
Encode Frequency. Differential AIN @ –0.5 dBFS

REV. 0

AD9433

AIN – MHz

55

SNR/SINAD – dB

SNR

10.3

SINAD

49.3 80.3 170.3 250.3

57

59

61

63

65

67

69

8.9

ENOB – Bits

9.3

9.6

9.9

10.3

10.6

10.9

11.3

0

IMD3 = 92dBFS

–10

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

0

22.5 30.0 45.0

FREQUENCY – MHz

37.515.07.5

52.5

TPC 7. FFT: fS = 105 MSPS, fIN = 49.3 MHz and 50.3 MHz,
Differential AIN @ –7 dBFS for Each Tone, SFDR Enabled

TPC 10. SNR and SINAD vs. AIN Frequency.
Differential AIN @ –0.50 dBFS, f

= 125 MSPS,

S

SFDR Enabled

110

SFDR – dB

100

90

80

70

60

50

40

30

20

10

0

–90

SFDR dBFS

–80 –70 –60 –50 –40 –30 –20 –10 0

SFDR dBc

90dBFS
REFERENCE

AIN LEVEL – dBFS

SNR dBFS

fS = 105MSPS
f

= 49.3MHz

IN

DIFFERENTIAL AIN
SFDR ENABLED

TPC 8. SNR and SFDR vs. AIN Level, fS = 105 MSPS,
f

= 49.3 MHz, Differential AIN, SFDR Enabled

IN

110

100

90

80

TPC 9. Third Order IMD vs. AIN Level, fS = 105 MSPS,
f

IN

Enabled

70

THIRD ORDER IMD – dB

60

50

–90

–80 –70 –60 –50 –40 –30 –20 –10 0

AIN LEVEL – dBFS

= 49.3 MHz and 50.3 MHz, Differential AIN, SFDR

100

90

80

70

60

50

dB

40

30

20

10

0

3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5

3.5

3RD HARMONIC

2ND HARMONIC

SNR

AIN COMMON-MODE VOLTAGE – V

TPC 11. Dynamic Performance vs. AIN Common-Mode
Voltage. Differential AIN @ –0.5 dBFS, f

= 105 MSPS

f

S

69

68

67

66

65

64

SNR – dB

63

62

61

60

10.3 49.3 80.3 170.3 250.3
AIN – MHz

= 49.3 MHz,

IN

–40C

+25C

+85C

TPC 12. SNR vs. AIN Frequency/Temperature,

= 105 MSPS, Differential AIN, SFDR Disabled

f

S

REV. 0

–9–

AD9433

–95

–90

–85

–80

–75

–70

DYNAMIC PERFORMANCE – dB

–65

–60

WORST OTHER (dBc)

2ND HARMONIC (dBc)

020

30 40 50 60 70 80 9010
DUTY CYCLE HIGH – %

3RD HARMONIC (dBc)

SNR (dB)

TPC 13. Dynamic Performance vs. Encode Duty Cycle

fS = 105 MSPS, fIN = 49.3 MHz, Differential AIN @ –0.5 dBFS,

SFDR Enabled

0.75

0.50

0.25

300

280

260

ICC (mA)

240

– mA

CC

I

220

200

180

0

25 50 75 100 125

ENCODE FREQUENCY – MHz

I

(mA)

DD

TPC 16. IDD and ICC vs. Encode Rate. fIN = 10.3 MHz,
Differential AIN @ –0.5 dBFS

0.75

0.50

0.25

18

15

12

9

– mA

DD

I

6

3

0

0

INL – LSBs

–0.25

–0.50

–0.75

512 1024 1536 2048 2560 3072 3584 4095

0

OUTPUT CODE

TPC 14. Integral Nonlinearity vs. Output Code
with SFDR Disabled

0.5

0.4

0.3

0.2

0.1

0

–0.1

DNL – LSBs

–0.2

–0.3

–0.4

–0.5

512 1024 1536 2048 2560 3072 3584 4095

0

OUTPUT CODE

TPC 15. Differential Nonlinearity vs. Output Code

0

INL – LSBs

–0.25

–0.50

–0.75

512 1024 1536 2048 2560 3072 3584 4095

0

OUTPUT CODE

TPC 17. Integral Nonlinearity vs. Output Code with
SFDR Enabled

0

–10

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

0

7.68 15.36 23.04 30.72
FREQUENCY – MHz

TPC 18. FFT: fS = 61.44 MSPS, fIN = 46.08 MHz, 4 WCDMA

Carriers, Differential AIN, SFDR Enabled

–10–

REV. 0

TYPICAL IF SAMPLING PERFORMANCE

AIN LEVEL – dBFS

0

–90

SNR/SFDR – dB

10

20

30

40

50

60

70

80dBFS REFERENCE LINE

SNR – dBFS

fS = 105MSPS
f

IN

= 70.3MHz

DIFFERENTIAL AIN
SFDR ENABLED

SFDR – dBc

SFDR – dBFS

80

90

100

110

–80 –70 –60 –50 –40 –30 –20 –10 0

dBFS

–90

dBFS

f

S

= 105MSPS

f

IN

= 70.3MHz AND 69.3MHz

DIFFERENTIAL AIN
SFDR ENABLED

–110

–80 –70 –60 –50 –40 –30 –20 –10 0

–100

–90

–80

–70

–60

–50

0

SNR = 66.8dB

–10

SFDR = 83.0dBFS

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

7.5

0

22.5 30.0 37.5 45.0 52.5

15.0
FREQUENCY – MHz

TPC 19. FFT: fS = 105 MSPS, fIN = 70.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled

0

SNR = 65.5dB

–10

SFDR = 78.0dBFS

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

6.2

0

18.7 25.0 31.2 37.5 43.7 50.0 56.2 62.5

12.5
FREQUENCY – MHz

AD9433

0

SNR = 67.0dB

–10

SFDR = 80.0dBFS

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

TPC 22. FFT: fS = 105 MSPS, fIN = 70.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Disabled

7.5

15.0

0

22.5 30.0 37.5 45.0 52.5

FREQUENCY – MHz

TPC 20. FFT: fS = 125 MSPS, fIN = 70.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled

0

IMD3 – 85dBc

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0 7.5dB15.0

TPC 21. FFT: fS = 105 MSPS, fIN = 69.3 and 70.3 MHz,

22.5 30.0 37.5 45.0 52.5

FREQUENCY – MHz

Differential AIN @ –7 dBFS for Each Tone, SFDR Enabled

REV. 0

–11–

TPC 23. SNR/SFDR vs. AIN Level

TPC 24. Third Order IMD vs. AIN Level,

= 105 MSPS, fIN = 70.3 MHz and 69.3 MHz,

f

S

Differential AIN, SFDR Enabled

AD9433

0

SNR = 64.0dB

–10

SFDR = 78.0dBFS

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

7.5

0

22.5 30.0 37.5 45.0 52.5

15.0
FREQUENCY – MHz

TPC 25. FFT: fS = 105 MSPS, fIN = 150.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled

0

SNR = 61.2dB

–10

SFDR = 67.0dBFS

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

7.5dB15.0

22.5 30.0 37.5 45.0 52.5

FREQUENCY – MHz

TPC 26. FFT: fS = 105 MSPS, fIN = 250.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled

0

SNR = 62.0dB

–10

SFDR = 70.0dBFS

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

0 6.25

12.5

18.7 25.0 31.2 37.5 43.7 50.0 56.2 62.5
FREQUENCY – MHz

TPC 28. FFT: fS = 125 MSPS, fIN = 150.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled

0

SNR = 54.6dB

–10

SFDR = 58.0dBFS

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

0 6.2

18.7 25.0 31.2 37.5 43.7 50.0 56.2 62.5

12.5
FREQUENCY – MHz

TPC 29. FFT: fS = 125 MSPS, fIN = 350.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled

0

SNR = 55.3dB

–10

SFDR = 61.0dBFS

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

0

7.5

15.0

22.5 30.0 37.5 45.0 52.5

FREQUENCY – MHz

TPC 27. FFT: fS = 105 MSPS, fIN = 350.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled

–110

–100

–90

–80

–70

–60

–50

dBFS

–40

–30

–20

–10

0

–90

–80 –70 –60 –50 –40 –30 –20 –10 0

IMD3

dBFS

TPC 30. Third Order IMD vs. AIN Level, fS = 105 MSPS,

= 150.3 and 151.3 MHz, Differential AIN, SFDR Enabled

f

IN

–12–

REV. 0

AD9433

ENCODE

ENCODE

PECL
GATE

510

510

AD9433

0

–10

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

0 9.6

19.2 28.8 38.4

FREQUENCY – MHz

TPC 31. FFT: fS = 76.8 MSPS, fIN = 59.6 MHz, 2 WCDMA
Carriers, Differential AIN, SFDR Enabled

APPLICATION NOTES
Theory of Operation

The AD9433 is a multibit pipeline converter that uses a switched
capacitor architecture. Optimized for high speed, this

converter

provides flat dynamic performance up to and beyond the Nyquist

DNL transitional errors are calibrated at final test to a

limit.
typical accuracy of 0.25 LSB or less.

0

–10

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

0 11.52

23.04 34.56 46.08

FREQUENCY – MHz

TPC 32. FFT: fS = 92.16 MSPS, fIN = 70.3 MHz, WCDMA @

70.0 MHz, SFDR Enabled

USING THE AD9433
ENCODE Input

Any high-speed A/D converter is extremely sensitive to the quality
of the sampling clock provided by the user. A track/hold circuit
is essentially a mixer, and any noise, distortion, or timing jitter
on the clock will be combined with the desired signal at the A/D
output. For that reason, considerable care has been taken in the
design of the ENCODE input of the AD9433, and the

user is

advised to give commensurate thought to the clock source.

The AD9433 has an internal clock duty cycle stabilization
circuit that locks to the rising edge of ENCODE (falling edge
of ENCODE if driven differentially), and optimizes timing
internally. This allows for a wide range of input duty cycles at
the input without degrading performance. Jitter in the rising
edge of the input is still of paramount concern, and is not
reduced by the internal stabilization circuit. This circuit is
always on, and cannot be disabled by the user.

The ENCODE and ENCODE inputs are internally biased to

3.75 V (nominal), and support either differential or single­ended signals. For best dynamic performance, a differential
signal is recommended. Good performance is obtained using
an MC10EL16 in the circuit to directly drive the encode
inputs, as illustrated in Figure 7.

Figure 7. Using PECL to Drive the

ENCODE

Inputs

Often, the cleanest clock source is a crystal oscillator producing
a pure, single-ended sine wave. In this configuration, or with
any roughly symmetrical, single-ended clock source, the signal
can be ac-coupled to the ENCODE input. To minimize jitter,
the signal amplitude should be maximized within the input
range described in Table I below. The 12 kΩ resistors to
ground at each of the inputs, in parallel with the internal bias
resistors, set the common-mode voltage to approximately 2.5 V,
allowing the maximum swing at the input. The ENCODE input
should be bypassed with a capacitor to ground to reduce noise.
This ensures that the internal bias voltage is centered on the
encode signal. For best dynamic performance, impedances at
ENCODE and ENCODE should match.

50

SINE

SOURCE

50

0.1F

0.1F

25

12k

12k

ENCODE

AD9433

ENCODE

Figure 8. Single-Ended Sine Source Encode Circuit

REV. 0

–13–

AD9433

Shown in Figure 9 is another preferred method for clocking the
AD9433. The clock source (low jitter) is converted from single­ended to differential using an RF transformer. The back-to-back
Schottky diodes across the transformer secondary limit clock
excursions into the AD9433 to approximately 0.8 V p-p differ­ential. This helps prevent the large voltage swings of the clock
from feeding through to the other portions of the AD9433, and
limits the noise presented to the ENCODE inputs. A crystal
clock oscillator can also be used to drive the RF transformer if
an appropriate limiting resistor (typically 100 Ω) is placed in the
series with the primary.

0.1F
100

CLOCK

SOURCE

T1–4T

HMS2812

DIODES

ENCODE

AD9433

ENCODE

Figure 9. Transformer-Coupled Encode Circuit

ENCODE Voltage Level Definition

The voltage level definitions for driving ENCODE and
ENCODE in single-ended and differential mode are shown
in Figure 10.

Table I. ENCODE Inputs

Description Minimum Nominal Maximum

Differential Signal Amplitude 200 mV 750 mV 5.5 V

)

(V

ID

Input Voltage Range –0.5 V VCC + 0.5 V

(V

, V

, V

, V

IHD

ILD

IHS

ILS

)

Internal Common-Mode Bias 3.750 V

)

(V

ICM

External Common-Mode Bias 2.0 V 4.25 V
(V

ECM

)

ENCODE

ENCODE

ENCODE

ENCODE

0.1F

V

IHD

V

, V

ICM

ECM

V

ILD

V

IHS

V

, V

ICM

ECM

V

ILS

Figure 10. Differential and Single-Ended Input Levels

Analog Input

The analog input to the AD9433 is a differential buffer.
The input buffer is self-biased by an on-chip resistor divider
that nominally sets the dc common-mode voltage to 4 V (see
Equivalent Circuits section). Rated performance is achieved
by driving the input differentially. Minimum input offset voltage

obtained

is

when driving from a source with a low differential

source impedance, such as a transformer, in ac applica-

(See Figure 11)

tions

. Capacitive coupling at the inputs will

increase the input offset voltage by as much as 50 mV.

50

ANALOG

SIGNAL

SOURCE

1:1

25

25

0.1F

AIN

AIN

Figure 11. Transformer-Coupled Analog Input Circuit

In the highest frequency applications, two transformers con­nected in series may be necessary to minimize even-order
harmonic distortion. The first transformer will isolate and con­vert the signal to a differential signal, but the grounded input on
the primary side will degrade amplitude balance on the second­ary winding. Capacitive coupling between the windings causes
this imbalance. Since one input to the first transformer is
grounded, there is little or no capacitive coupling, resulting in an
amplitude mismatch at the first transformers output. A second
transformer will improve the amplitude balance, and thus
improve the harmonic distortion. A wideband transformer, such
as the ADT1-1WT from Mini Circuits, is recommended for
these applications, as the bandwidth through the two transformers
will be reduced by the √2.

50

ANALOG

SIGNAL

SOURCE

1:1

1:1

25

25

0.1F

AIN

AD9433

AIN

Figure 12. Driving the Analog Input with Two Transformers
for Improved Even-Order Harmonics

Driving the ADC single-endedly will degrade performance,
particularly even-order harmonics. For best dynamic performance,
impedances at AIN and AIN should match.

Special care was taken in the design of the analog input section
of the AD9433 to prevent damage and corruption of data when
the input is overdriven.

SFDR Optimization

The SFDR MODE pin enables (SFDR MODE = 1) a propri­etary circuit that may improve the spurious free dynamic range
(SFDR) performance of the AD9433. It is useful in applications
where the dynamic range of the system is limited by discrete
spurious frequency content caused by nonlinearities in the ADC
transfer function.

Enabling this circuit will give the circuit a dynamic transfer
function, meaning that the voltage threshold between two
adjacent output codes may change from clock cycle to clock
cycle. While improving spurious frequency content, this
dynamic aspect of the transfer function may be inappropriate
for some time domain applications of the converter. Connecting
the SFDR MODE pin to ground will disable this function. The
typical performance curves section of the data sheet illustrates
the improvement in the linearity of the converter and its effect
on spurious free dynamic range (TPC 1, 2, 15, 18).

–14–

REV. 0

AD9433

Digital Outputs

The digital outputs are 3 V (2.7 V to 3.3 V) TTL/CMOS­compatible for lower power consumption. The output data
format is selectable through the data format select (DFS)
CMOS input. DFS = 1 selects offset binary; DFS = 0 selects
two’s complement coding.

Table II. Offset Binary Output Coding (DFS = 1, V

= 2.5 V)

REF

AIN – AIN (V) Digital

Code Range = 2 V p-p Output

4095 +1.000 1111 1111 1111

●● ●

●● ●

2048 0 1000 0000 0000
2047 –0.00049 0111 1111 1111

●● ●

●● ●

0 –1.000 0000 0000 0000

Table III. Two’s Complement Output Coding (DFS = 0, V

= 2.5 V)

REF

AIN – AIN (V) Digital

Code Range = 2 V p-p Output

+2047 +1.000 0111 1111 1111

●● ●

●● ●

0 0 0000 0000 0000
–1 –0.00049 1111 1111 1111

●● ●

●● ●

–2048 –1.000 1000 0000 0000

Voltage Reference

A stable and accurate 2.5 V voltage reference is built into the
AD9433 (VREFOUT). In normal operation the internal reference
is used by strapping Pin 45 to Pin 46 and placing a 0.1 ␮F
decoupling capacitor at VREFIN. The input range can be
adjusted by varying the reference voltage applied to the
AD9433. No appreciable degradation in performance occurs
when the reference is adjusted to 50. The full-scale range of the
ADC tracks reference voltage changes linearly.

Timing

The AD9433 provides latched data outputs, with 10 pipeline
delays. Data outputs are available one propagation delay (t

PD

)
after the rising edge of the encode command (see Timing Dia­gram). The length of the output data lines and loads placed on
them should be minimized to reduce transients within the AD9433

;
these transients can detract from the converter’s dynamic per­formance. The minimum guaranteed conversion rate of the
AD9433 is 10 MSPS. At internal clock rates below 10 MSPS,
dynamic performance may degrade.

Layout Information

The schematic and layout of the evaluation board (Figures 13–21)
represents a typical implementation of the AD9433. A multi­layer board is recommended to achieve best results. It is highly
recommended that high quality, ceramic chip capacitors be used
to decouple each supply pin to ground directly at the device.
The pinout of the AD9433 facilitates ease of use in the implemen­tation of high frequency, high resolution design practices. All of the
digital outputs and their supply and ground pin connections are
segregated to one side of the package, with the inputs on the
opposite side for isolation purposes.

Care should be taken when routing the digital output traces. To
prevent coupling through the digital outputs into the analog portion of
the AD9433 (V

, AIN, and VREF), minimal capacitive loading

CC

should be placed on these outputs.

It is recommended that a fan-out of only one gate should be used
for all AD9433 digital outputs.

The layout of the encode circuit is equally critical, and should
be treated as an analog input. Any noise received on this circuitry
will result in corruption in the digitization process and lower
overall performance. The Encode clock must be isolated from
the digital outputs and the analog inputs.

Replacing the AD9432 with the AD9433

The AD9433 is pin-compatible with the AD9432, although
there are two control pins on the AD9433 that do not connect
(DNC) and supply (V

) connections on the AD9432. They are

CC

summarized in the table below.

Table IV. AD9432/AD9433 Pin Differences

Pin AD9432 AD9433

41 DNC DFS
42 V

CC

SFDR MODE

Using the AD9433 in an AD9432 pin assignment will configure
the AD9433 as follows:

• The SFDR improvement circuit will be enabled.

• The DFS pin will float LOW, selecting two’s complement

coding for the digital outputs, which is the same as the AD9432.

Table V summarizes differences between the AD9432 and
AD9433 analog and encode input common-mode voltages.
These inputs may be ac-coupled so that the devices can be used
interchangeably.

Table V. Other AD9432/AD9433 Differences

Attribute AD9432 AD9433

ENCODE/ENCODE V
AIN/AIN V

COMMON MODE

COMMON MODE

1.6 V 3.75 V

3.0 V 4.0 V

REV. 0

–15–

AD9433

Table VI. Power Supply Connections for the AD9433 Evaluation Board

Connector Pin Designator External Supply Required Approximate Current Level

P42 P1, P3 GND Ground

P2 –5 V (Optional U10 Supply) –5 V 30 mA
P4 V

DL

P43 P1, P3 GND Ground

P2 V
P4 V

O

CC

+3 V 144 mA

+3 V 10 mA
+5 V 325 mA Without U10

355 mA With U10

Evaluation Board

The AD9433 evaluation board offers designers an easy way to
evaluate device performance. The user must supply an analog
input signal, encode clock reference, and power supplies. The
digital outputs of the AD9433 are latched on the evaluation
board, and are available with a data ready signal at a 40-pin
edge connector. Please refer to the evaluation board schematic,
layout, and bill of materials that follow.

Power Connections

Power to the board is supplied via two detachable, four-pin
power strips (P42 and P43). These eight pins should be driven
as outlined in Table VI. Please note that the –5 V supply is
optional, and only required if the user adds differential op amp
U10 to the board.

Jumper Options

The table below describes the jumper options on the AD9433
Evaluation board.

Table VII. AD9433 Evaluation Board Jumper Options

Jumper
Designation Connection Configuration

SFDR 5 V SFDR Enhancement

Circuit Enabled

GND SFDR Enhancement

Circuit Disabled

DFS 5 V Offset Binary Output

Data Format

GND Two’s Complement

Output Data Storage

LATCH E10 to E6

Output Register (U7–U8)
Clock is Buffered

E10 to E5

Output Register (U7–U8)
Clock is Inverted

DATA READY E7 to E8 Data Ready Signal is

Buffered

E7 to E9 Data Ready Signal is

Inverted

Encode Signal and Distribution

The encode input signal should drive SMB connector P38,
which has an on-board 50 Ω termination. This signal is ac-coupled,
and may be either a low jitter pulse or a sine wave reference,
with up to 4 V p-p amplitude. U2 (MC10EP16) converts this
single-ended input signal to a differential PECL signal to drive

the AD9433. U1 (DS90LV048A) also converts the signal at P38
to a CMOS level signal to drive the clock inputs of the two out­put data registers U7–U8, (74LVT574WM), the reconstruction
DAC U3 (AD9772AAST), and the output data connector.

Analog Input

The analog input signal is ac-coupled to the evaluation board by
SMB connector P39. Transformers T1 and T2 (ADT1-1WT)
convert this signal to a differential signal to drive AIN and AIN
of the AD9433. These RF transformers are specified as 1:1, but
their turns ratio is actually 6:7. T1 is rotated 180° and mounted
on the board such that its secondary and primary are reversed,
making its ratio 7:6. The second transformer in series now form
a combined 1:1 turns ration for the analog signal, and provide a
50 Ω termination for connector J1 via 25 Ω resistors R3 and R4.
Resistor R3, normally omitted, can be used to terminate P39 if
the transformers are removed for single ended drive. In this
configuration, the user will need to short the input signal from
Pin 3 of T1 to Pin 6 of T2, and remove resistor R4. Resistor R3
should remain in place to match the impedance of AIN and AIN.

Using the AD8350

An optional driver circuit for the analog input, based on the
AD8350 differential amplifier, is included in the layout of the
AD9433 evaluation board. This portion of the evaluation circuit
is not populated when the board is manufactured, but can be
easily added by the user. Removing resistors R29 and R30 will
disconnect the normal analog input signal path, and populating
R17 and R31 will connect the AD8350 output network.

DAC Reconstruction Circuit

The data available at output connector U2 is also reconstructed
by DAC U3, the AD772A. This 14-bit, high-speed

digital-to­analog converter is included as a tool in setting up and debugging the
evaluation board. It should not be used to measure the performance
of the AD9433, as its performance will not accurately reflect the
performance of the ADC. As configured on the AD9433 evaluation
board, the AD9772A divides the input clock frequency by a factor
of two, and ignores every other sample from the AD9433. The
AD9772 internally interpolates the missing samples so that the
DAC output will reflect the input of the AD9433 only when the
analog input frequency is less than or equal to 1/4 the ADC
encode rate. The AD9772 requires offset binary format so the
DFS jumper should be connected to 5 V. The DAC’s output,
available at J1, will drive 50 Ω. The user may move the jumper
wire between E43 and E42 to connect E43 to E44, thus activating
the SLEEP function of the DAC.

–16–

REV. 0

AD9433

Evaluation Board Bill of Materials

Item Qty Reference Designator Device Package Value

1 1 AD9433/PCB PCB
2 1 U4 ADC QFP52 AD9433BST-XXX
3 1 U3 DAC LQFP48 AD9772AAST
4 1 U1 Quad LVDS/CMOS SO16 DS90LV048A
5 1 U2 Diff. ECL Receiver SO8NB MC10EP16
62U7–U8 D Flip-Flop 74LVT574WM
72T1–T2 1:1 Transformer CD542 ADT1-1WT
835C1,C2,C4–C8, C10, C12–C18, Capacitor 0603A 0.1 µF

C20–C24, C27–C28, C30–C38, C42–
C43, C45, C48

9 3 C9, C40–C41 Capacitor BCAPTAJD 10 µF
10 1 C11 Capacitor 0603A 10 µF
11 2 R10, R23 BRES603 0603A 50 Ω
12 2 R29–R30 BRES603 0603A 33 Ω
13 4 R1–R2, R24–R25 BRES603 0603A 510 Ω
14 3 R3–R4, R7 BRES603 0603A 25 Ω
15 3 R6, R8, R14 BRES603 0603A 2 kΩ
16 2 R9, R13 BRES603 0603A 1.2 kΩ
17 2 R11, R16 BRES603 0603A 1 kΩ
18 1 R12 BRES603 0603A 220 Ω
19 2 RZ1–RZ2 Resistor Pack SO16RES 742C163221 (220 Ω)
20 2 RZ4–RZ5 Resistor Pack SO16RES 742C163220 (22 Ω)
21 3 J1, P38–P39 SMBPN SMB PC-Mount SMB
22 1 P44 40 Pin Header C40MS Samtec Tsw-120-07-G-D
23 2 P42–P43 Power Connector PTMICRO4 Weiland

Z5.531.3425.0 Posts

25.602.5453.0 Top

24 15 E5–E7, E8–E10, E19–E21, E25–E27, “E” Holes Jumper Blocks TSW-120-07-G-S

E31–E33 SMT-100-BK-G

25 4 E28/E29, E36/E37, E39/E40, E42/E43 “E” Holes Wire Straps Short at Assembly
26* 1 T3 1:1 Transformer CD543 ADT1-1WT
27* 1 U10 Op Amp SO8 AD8350
28* 7C3,C46–C47, C50–C53 Capacitor 0603A 0.1 µF
29* 1 C44 Capacitor BCAPTAJD 10 µF
30* 2 R15, R27 BRES604 0603A 50 Ω
31* 2 R18–R19 BRES606 0603A 25 Ω
32* 2 R20, R33 BRES608 0603A 1.5 kΩ
33* 2 R21, R28 BRES605 0603A 100 Ω
34* 6L1–L2, R17, R22, R31, C29, C49 Select (R, L, C) 0603A Select
35* 1 P41 SMBPN SMB PC-Mount SMB
36* 6 E30, E34–E35, E38, E41, E44 “E” Holes Option Holes

*Items are included in the PCB design, but are omitted at assembly.

REV. 0

–17–

AD9433

R20

R33

1.5k

IN– OUT+

1.5k

IN+ OUT–

VCC

OPTIONAL

C52

R21

C18

E19

E20

E27

E26

E21

E25

VCC

GND

GND

R17

L1

ANALOG INPUT

C50

U10

CC

V

OUT+

CC

V

ENBL

GND

1234

IN+

100nF

100

R19

462

135

T3

ADT1-WT1

T18

CC

V

O

V

PAD UNDER PART

GND P5

CC

V

0.1F

U4

GND

GND

STRAPPED

TO GND

STRAPPED

TO GND

E30

E29

E33

E28

C29 C49

GND

R18

R31

L2

25

T1

VCC

8765

C53

R21

GND

E31

AIN

C51

OUT–

IN–

100nF

100

VCC

AIN

AD8350

25

D5D4D3D2D1

D6

D9

D8

D10

D10

GAIN

39

D7

D9

D8

D7

AD9433QFP52

VREFIN

VREFOUT

45

46

C6

0.1F

GND

R29

33

462

135

T2 ADT1-WT1

312

645

T1 ADT1-WT1

GND

OR

D11

14151617181920252627282930

CC

V

OR

CC

V

CC

V

CC

(MSB) D11

V

CC

V

CC

V

CC

V

CC

V

DD

V

DD

V

DD

V

DD

V

CC

V

GND

910 13322322 36 52 474437 6 5 2

GND

34

SCLK

DFS

SFDR

41

42

40

E32

GND

GND

GND

–5V

D5D4D3D2D1

D6

AIN

49

50

C10

0.1F

R4

25

GND

0.1F

C8

SEC

PRI

SEC

PRI

R15

50

OPTIONAL

AIN

8

GND

10pF

C11

GND

7:6 6:7

C4

P39

ENC

ENC

7

R30

R3

25

CC

V

C24

U2

0.1F

SMBMST

D0

D0

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

DGND

DGND

DGND

DGND

AIN

33

8

1

10EL16

C13

ANALOG

Figure 13. Evaluation Board Schematic

–18–

12 31 24 21 33 11 35 51 48 43 38 4 3 1

ENC

0.1F

CC

V

A

2

GND

C1

7

Q

CLK

3

C3

R22

OPTIONAL

ENC

0.1F

6

Q

EE

V

BB

V

CLKN

R25

R24

0.1F

GND

SELECT

DL

V

13

U1

1

DL

V

R8

2k

R9

C14

0.1F

1.2k

GND

R1

510

GND

R2

510

45

C2

0.1F

510

510

R12

C7

0.1F

P38

SMBMST

ENCODE

15

CC

V

IN1N

GND

220

R23

E5

OUT1

2

50

LATCH

E6

E10

14

OUT2

IN1P

IN2P

3

C15

0.1F

GND

4

DR

E8

E7

11

10

OUT3

IN2N

IN3N

IN3P

DS90LV04BATM

5

6

C16

0.1F

GND

E9

OUT4

IN4P

7

C17

0.1F

IN4N

8

ENN ENP

GND

V

1612 9

DL

R14

R13

GND

DL

V

GND

2k

1.2k

REV. 0

V

GND

GND

AD9433

R7

GND

DB2

R10
50

GND

DL

DD

AD9772A

DB1

DB0

25

GND

ACOM

IOUTA

U3

MOD1

MOD0

GND

ACOM

IOUTB

DCOM

DCOM

R6
2k

REFIO

FSADJ

DVDDDVDDNC

C5

0.1F

GND

ACOM

REFLO

SLEEP

PLLV

PLLCOM

CLKV

CLKCOM

CLK–

RESET

PLLLOCK

NC

LPF

CLK+

DIV0

DIV1

GND

E44

V

E42

E43

GND
V

GND

LATCH

GND

DL

DL

GND

GND

V

R11
1k

DL

R16
1k

STRAPPED TO

GROUND

C43

0.1F

GND

36

35

34

DD

33

32

DD

31

30

29

28

27

26

25

J1

DL

0.1F

C42

C38

0.1F

C34

0.1F

0.1F

C33

C12

0.1F
GND

VDLVDLVDLV

48 47 46 45 44 39 38 3743 42 41 40

GND
GND

B11

B10

1

2

3

4

B9

B8

B7

B6

B5

B4

B3

B2

5

6

7

8

9

10

11

12

DVDDDVDDAVDDAV
DCOM

DCOM

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

13 14 15 16 17 18 19 20 21 22 23 24

B0

B1

VDL

GND

VDL

E41

GND

E40

GND

GND

VDL

E37

E39

E38

E36

STRAPPED TO

Figure 14. Evaluation Board Schematic

NC = NO CONNECT

VDL

GROUND

REV. 0

–19–

AD9433

V

CC

GND

P42 PTMICRO4

P43 PTMICRO4

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

OR

P1

P2

P3

P4

P1

P2

P3

P4

RZ1

R5016I50

1

2

3

4

5

6

7

8

RZ1

R5016I50

1

2

3

4

5

6

7

8

OPTIONAL

C48

0.1F
GND

–5V

C44

10F

C47

+

0.1F
GND

V

DL

C45

C22

V

CC

+

C41

10F

DUT BYPASS – 0.1F

C28

C30

C27

C23

C32

C31

GND

OPTIONAL

1

GND

2

–5V

3

GND

4

V

1

GND

2

V

3

GND

4

V

221

R1

16

R2

15

R3

14

R4

13

R5

12

R6

11

R7

10

R8

9

DL

O

CC

(+3V)

(+3V)

(+5V)

GND

GND

V

DL

V

D

E34

E35

GND

U8

1

OUT EN

2

D0

3

D1

4

D2

5

A0

A1

A2

A3

A4

D3

6

D4

7

D5

8

D6

9

D7

10

GND

V

DL

10F

CLOCK

LATCHES – 0.1F

+

C9

20

V

CC

19

Q0

18

Q1

17

Q2

16

Q3

15

Q4

14

Q5

13

Q6

12

Q7

11

C20

V

DL

LATCH

C21

RZ1

R5016I50

1

2

3

4

5

6

7

8

R1

R2

R3

R4

R5

R6

R7

R8

220

V

D

GND

16

15

14

13

12

11

10

9

74AC574M

221

R1

R2

R3

R4

R5

R6

R7

R8

GND

16

15

14

13

12

11

10

9

GND

A5

A6

A7

A8

A9

A10

A11

ADR

1

2

3

4

5

6

7

8

9

10

OUT EN

D0

D1

D2

D3

D4

D5

D6

D7

GND

U7

V

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

CLOCK

20

CC

19

18

17

16

15

14

13

12

11

V

LATCH

RZ1

220

R5016I50

DL

R1

1

2

3

4

5

6

7

8

16

R2

15

R3

14

R4

13

R5

12

R6

11

R7

10

R8

9

74AC574M

DUT BYPASS – 0.1F

+

C40

10F

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B0R

C37 C36

GND

B0R

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

GND

DR

GND

C35

P44

C40M5

1

P1

3

P3

5

P5

7

P7

9

P9

11

P11

13

P13

15

P15

17

P17

19

P19

21

P21

23

P23

25

P25

27

P27

29

P29

31

P31

33

P33

35

P35

37

P37

39

P39

P2

P4

P6

P8

P10

P12

P14

P16

P18

P20

P22

P24

P26

P28

P30

P32

P34

P36

P38

P40

2

GND

4

GND

6

GND

8

GND

10

GND

12

GND

14

GND

16

GND

18

GND

20

GND

22

GND

24

GND

26

GND

28

GND

30

GND

32

GND

34

GND

36

GND

38

40

GND

GND

H1
MTHOLES

H2
MTHOLES

H3
MTHOLES

H4
MTHOLES

OPTIONAL

P41
5MBM5T

DR

R27
50

GND

Figure 15. Evaluation Board Schematic

–20–

REV. 0

AD9433 EVALUATION BOARD LAYOUT

AD9433

Figure 16. Top Silkscreen

Figure 18. Ground Plane

REV. 0

Figure 17. Top Level Routing

Figure 19. Power Plane

–21–

AD9433

Figure 20. Bottom Layer Routing

Figure 21. Bottom Silkscreen

–22–

REV. 0

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Thermally Enhanced

52-Lead Power Thin Plastic Quad Flatpack (LQFP_ED)

(SQ-52)

0.093 (2.35)

0.087 (2.20)

0.081 (2.05)

40 52

1

0.472 (12.00) SQ

0.307 (7.80)

0.104 (2.65)

0.098 (2.50)

4052

0.093 (2.35)

39

(4 PLCS)

39

AD9433

(4 PLCS)

1

TOP VIEW

(PINS DOWN)

13

14

SEATING
PLANE

0.015 (0.38)

0.013 (0.32)

0.009 (0.22)

VIEW A

0.026 (0.65)

0.063
(1.60)

MAX

0.030 (0.75)

0.024 (0.60)

0.018 (0.45)

NOTES

1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS. INCH DIMENSIONS ARE ROUNDED OFF MILLIMETER
EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

2. ALTHOUGH NOT REQUIRED IN ALL APPLICATIONS, THE AD9433 HAS AN EXPOSED METALLIC PAD ON THE
PACKAGE BOTTOM WHICH IS INTENDED TO ENHANCE THE HEAT REMOVAL PATH. TO MAXIMIZE THE REMOVAL
OF HEAT, A LAND PATTERN WITH CLOSELY SPACED THERMAL VIAS TO THE GROUND PLANE(S) SHOULD
BE INCORPORATED ON THE PCB WITHIN THE FOOTPRINT OF THE PACKAGE CORRESPONDING TO THE
EXPOSED METAL PAD DIMENSIONS OF THE PACKAGE. THE SOLDERABLE LAND AREA SHOULD BE SOLDER
MASK DEFINED AND BE AT LEAST THE SAME SIZE AND SHAPE AS THE EXPOSED PAD AREA ON THE
PACKAGE. AT LEAST 0.25 MM CLEARANCE BETWEEN THE OUTER EDGES OF THE LAND PATTERN AND THE
INNER EDGES OF THE PAD PATTERN SHOULD BE MAINTAINED TO AVOID ANY SHORTS.

0.402 (10.20)

0.394 (10.00) SQ

0.386 (9.80)

27

26

27

0.057 (1.45)

0.055 (1.40)

0.053 (1.35)

26

EXPOSED

HEATSINK

(CENTERED)

0.236 (6.00)

0.232 (5.90)

0.228 (5.80)

BOTTOM VIEW

(PINS UP)

0.004 (0.10)

COPLANARITY

VIEW A

13

14

0.006 (0.15)

0.002 (0.05)

0.236 (6.00)

0.232 (5.90)

0.228 (5.80)

REV. 0

–23–

C01977–.8–10/01(0)

–24–

PRINTED IN U.S.A.