Analog Devices AD9432 Service Manual

12-Bit, 80 MSPS/105 MSPS

12

AIN

ENCODE

12

AD9432

GND VREFOUT

D11–D0

VREFIN

AIN

ENCODE

V

CC

V

DD

TIMING

REF

OUTPUT

STAGING

PIPELINE

ADC

BUF

T/H

OR

a

FEATURES
On-Chip Reference and Track/Hold
On-Chip Input Buffer
850 mW Typical Power Dissipation at 105 MSPS
500 MHz Analog Bandwidth
SNR = 67 dB @ 49 MHz AIN at 105 MSPS
SFDR = 80 dB @ 49 MHz AIN at 105 MSPS

2.0 V p-p Differential Analog Input Range
Single 5.0 V Supply Operation

3.3 V CMOS/TTL Outputs
Two’s Complement Output Format

APPLICATIONS
Communications
Basestations and ‘Zero-IF’ Subsystems
Wireless Local Loop (WLL)
Local Multipoint Distribution Service (LMDS)
HDTV Broadcast Cameras and Film Scanners

GENERAL INTRODUCTION

The AD9432 is a 12-bit monolithic sampling analog-to-digital
converter with an on-chip track-and-hold circuit and is optimized
for high-speed conversion and ease of use. The product operates
at a 105 MSPS conversion rate with outstanding dynamic per­formance over its full operating range.

The ADC requires only a single 5.0 V power supply and a
105 MHz encode clock for full-performance operation. No

A/D Converter

AD9432

FUNCTIONAL BLOCK DIAGRAM

external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS compatible
and a separate output power supply pin supports interfacing
with 3.3 V logic. The encode input supports either differential
or single-ended and is TTL/CMOS-compatible.

Fabricated on an advanced BiCMOS process, the AD9432 is
available in a 52-lead plastic quad flatpack package (LQFP)
specified over the industrial temperature range (–40°C to +85°C).

REV. E

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

(VDD = 3.3 V, VCC = 5.0 V; external reference; differential encode input, unless

AD9432–SPECIFICATIONS

otherwise noted.)

Test AD9432BST/BSQ-80 AD9432BST/BSQ-105

Parameter Temp Level Min Typ Max Min Typ Max Unit

RESOLUTION 12 12 Bits

DC ACCURACY

Differential Nonlinearity 25°C I –0.75 ± 0.25 +0.75 –0.75 ± 0.25 +0.75 LSB

Full VI –1.0 ± 0.5 +1.0 –1.0 ±0.5 +1.0 LSB

Integral Nonlinearity 25°C I –1.0 ± 0.5 +1.0 –1.0 ± 0.5 +1.0 LSB

Full VI –1.5 ± 1.0 +1.5 –1.5 ± 1.0 +1.5 LSB
No Missing Codes Full VI Guaranteed Guaranteed
Gain Error
Gain Tempco

1

1

25°C I –5 +2 +7 –5 +2 +7 % FS

Full V 150 150 ppm/°C

ANALOG INPUT

Input Voltage Range (AIN–AIN) Full V ±1.0 ± 1.0 V
Common-Mode Voltage Full V 3.0 3.0 V
Input Offset Voltage Full VI –5 ± 0+5 –5 ± 0+5 mV
Input Resistance Full VI 2 3 4 2 3 4 kΩ
Input Capacitance 25°CV 4 4 pF
Analog Bandwidth, Full Power 25°C V 500 500 MHz

ANALOG REFERENCE

Output Voltage Full VI 2.4 2.5 2.6 2.4 2.5 2.6 V
Tempco Full V 50 50 ppm/°C
Input Bias Current Full VI 15 50 15 50 µΑ

SWITCHING PERFORMANCE

Maximum Conversion Rate Full VI 80 105 MSPS
Minimum Conversion Rate Full IV 1 1 MSPS
Encode Pulsewidth High (t
Encode Pulsewidth Low (t
Aperture Delay (t

)25°C V 2.0 2.0 ns

A

Aperture Uncertainty (Jitter) 25°C V 0.25 0.25 ps rms
Output Valid Time (t

V

Output Propagation Delay (t
Output Rise Time (t
Output Fall Time (t

)

R

) Full V 1.9 1.9 ns

F

)25°C IV 4.0 6.2 4.0 4.8 ns

EH

)25°C IV 4.0 6.2 4.0 4.8 ns

EL

2

)

2

PD

2

)

Full VI 3.0 5.3 3.0 5.3 ns

Full VI 5.5 8.0 5.5 8.0 ns

Full V 2.1 2.1 ns

Out-of-Range Recovery Time 25°CV 2 2 ns
Transient Response Time 25°CV 2 2 ns
Latency Full IV 10 10 Cycles

DIGITAL INPUTS

Encode Input Common Mode Full V 1.6 1.6 V
Differential Input (ENC–ENC) Full V 750 750 mV
Single-Ended

Logic “1” Voltage Full IV 2.0 2.0 V

Logic “0” Voltage Full IV 0.8 0.8 V
Input Resistance Full VI 3 5 8 3 5 8 kΩ
Input Capacitance 25°C V 4.5 4.5 pF

DIGITAL OUTPUTS

Logic “1” Voltage (VDD = 3.3 V) Full VI VDD – 0.05 VDD – 0.05 V
Logic “0” Voltage (V

= 3.3 V) Full VI 0.05 0.05 V

DD

Output Coding Two’s Complement Two’s Complement

POWER SUPPLY

Power Dissipation

3

Full VI 790 1000 850 1100 mW

Power Supply Rejection Ratio (PSRR) 25°C I –5 +0.5 +5 –5 +0.5 +5 mV/V

I

I

VCC

VDD

Full VI 158 200 170 220 mA
Full VI 9.5 12.2 12.5 16 mA

–2–

REV. E

AD9432

Test AD9432BST/BSQ-80 AD9432BST/BSQ-105

Parameter Temp Level Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR)

(Without Harmonics)
f

= 10.3 MHz 25°C I 65.5 67.5 65.5 67.5 dB

IN

= 40 MHz 25°C I 65 67.2 67.2 dB

f

IN

f

= 49 MHz 25°C I 67.0 64 67.0 dB

IN

f

= 70 MHz 25°C V 66.1 66.1 dB

IN

Signal-to-Noise Ratio (SINAD)

(With Harmonics)

= 10.3 MHz 25°C I 65 67.2 65 67.2 dB

f

IN

= 40 MHz 25°C I 64.5 66.9 66.9 dB

f

IN

f

= 49 MHz 25°C I 66.7 63 66.7 dB

IN

f

= 70 MHz 25°C V 65.8 65.8 dB

IN

Effective Number of Bits

= 10 MHz 25°C V 11.0 11.0 Bits

f

IN

f

= 40 MHz 25°C V 10.9 10.9 Bits

IN

= 49 MHz 25°C V 10.9 10.9 Bits

f

IN

f

= 70 MHz 25°C V 10.7 10.7 Bits

IN

Second and Third Harmonic Distortion

= 10 MHz 25°C I –75 –85 –75 –85 dBc

f

IN

f

= 40 MHz 25°C I –73 –85 –83 dBc

IN

f

= 49 MHz 25°C I –83 –72 –80 dBc

IN

= 70 MHz 25°C V –80 –78 dBc

f

IN

Worst Harmonic or Spur

(Excluding Second and Third)

= 10 MHz 25°C I –80 –90 –80 –90 dBc

f

IN

f

= 40 MHz 25°C I –80 –90 –90 dBc

IN

f

= 49 MHz 25°C I –90 –80 –90 dBc

IN

= 70 MHz 25°C V –90 –90 dBc

f

IN

Two-Tone Intermod Distortion (IMD)

f

= 29.3 MHz; f

IN1

f

= 70.3 MHz; f

IN1

NOTES

1

Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p differential analog input).

2

tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is
not to exceed an ac load of 10 pF or a dc current of ± 40 µA. Rise and fall times measured from 10% to 90%.

3

Power dissipation measured with encode at rated speed and a dc analog input. (Outputs Static, I

4

SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 2 V full-scale input range.

Specifications subject to change without notice.

IN2

IN2

4

= 30.3 MHz 25°C V –75 –75 dBc
= 71.3 MHz 25°C V –66 –66 dBc

= 0.)

VDD

REV. E –3–

AD9432

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

CC

Analog Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to V

Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to V

VREFIN . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V

+ 0.5 V

CC

+ 0.5 V

DD

+ 0.5 V

CC

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.

EXPLANATION OF TEST LEVELS
Test Level

I 100% production tested.

II 100% production tested at 25°C and sample tested at

specified temperatures.

III Sample tested only.

IV Parameter is guaranteed by design and characterization

testing.

V Parameter is a typical value only.

VI 100% production tested at 25°C; guaranteed by design and

characterization testing for industrial temperature range.

THERMAL CHARACTERISTICS

52-Lead Plastic LQFP (ST-52)

␪

= 50°C/W, No Airflow

JA

52-lead PowerQuad

= 25°C/W, Soldered Exposed Heat Sink, No Airflow

␪

JA

␪

= 33°C/W, Unsoldered Exposed Heat Sink, No Airflow

JA

␪

= 2°C/W, Bottom of package (Exposed Heat Sink)

JC

®

4 LQFP (SQ-52)

Simulated Typical performance for 4-layer JEDEC board,
horizontal orientation.

ORDERING GUIDE

Temperature Package Package

Model Ranges Descriptions Option

AD9432BSQ –40°C to +85°C 52-Lead Thermally SQ-52

-80, -105 Enhanced Plastic
Quad Flatpack

AD9432BST –40°C to +85° C 52-Lead Plastic Quad ST-52

-80, -105 Flatpack (LQFP)

AD9432/PCB 25°C Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9432 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

PowerQuad is a registered trademark of AMkor Technology, Inc.

–4–

REV. E

PIN CONFIGURATION

AD9432

CC

AIN

GND

V

52 51 50 49 48 43 42 41 4047 46 45 44

1

GND GND

V

CC

GND

GND

V

CC

V

CC

ENCODE

ENCODE

GND

V

CC

GND

DGND

V

DD

PIN 1
IDENTIFIER

2

3

4

5

6

7

8

9

10

11

12

13

14 15 16 17 18 19 20 21 22 23 24 25 26

OR

D10

(MSB) D11

VCCAIN

GND

AD9432

TOP VIEW

(Not to Scale)

D9D8D7

VREFOUT

D6

CC

VREFIN

V

DDVDD

V

DGND

GND

CC

DNC

V

D5

DGND

GND

D4

39

38

37

36

35

34

33

32

31

30

29

28

27

GND
V

CC

V

CC

GND

GND

GND
V

DD

DGND

D0 (LSB)

D1

D2

D3

PIN FUNCTION DESCRIPTIONS

Pin Number (AD9432BST) Mnemonic Function

1, 3, 4, 9, 11, 33, 34, 35, 38, 39, 40, 43, 48, 51 GND Analog Ground
2, 5, 6, 10, 36, 37, 42, 44, 47, 52 V

CC

Analog Supply (5 V)

7 ENCODE Encode Clock for ADC–Complementary
8 ENCODE Encode Clock for ADC–True (ADC samples on rising edge of ENCODE)
14 OR Out of Range Output
15–20, 25–30 D11–D6, D5–D0 Digital Output
12, 21, 24, 31 DGND Digital Output Ground
13, 22, 23, 32 V

DD

Digital Output Power Supply (2.7 V to 3.6 V)
41 DNC Do Not Connect

45 VREFIN Reference Input for ADC (2.5 V Typical); Bypass with 0.1 µF to Ground.
46 VREFOUT Internal Reference Output (2.5 V Typical)
49 AIN Analog Input–True
50 AIN Analog Input–Complementary

DEFINITION OF SPECIFICATIONS

Analog Bandwidth (Small Signal)

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

Aperture Delay

The delay between a differential crossing of ENCODE and
ENCODE and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Differential Nonlinearity

The deviation of any code from an ideal 1 LSB step.

Encode Pulsewidth/Duty Cycle

Pulsewidth high is the minimum amount of time that the ENCODE
pulse should be left in Logic “1” state to achieve rated performance;
pulsewidth low is the minimum time ENCODE pulse should be left
in low state. At a given clock rate, these specs define an acceptable
Encode duty cycle.

Integral Nonlinearity

The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.

REV. E

–5–

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in
power supply voltage.

Signal-to-Noise Plus Distortion (SINAD)

The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo­nents, including harmonics but excluding dc.

Signal-to-Noise Ratio (SNR)

The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo­nents, excluding the first five harmonics and dc.

AD9432

V

DD

DIGITAL
OUTPUT

DIGITAL OUTPUT

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo­nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.

SAMPLE N–1

AIN

ENCODE

ENCODE

D11–D0

SAMPLE N

t

A

t

EH

DATA N–11 DATA N–10 N–9 DATA N–1 DATA N DATA N + 1

SAMPLE N+1

t

EL

N–2

Figure 1. Timing Diagram

V

CC

Two-Tone SFDR

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).

Worst Harmonic

The ratio of the rms signal amplitude to the rms value of the
worst harmonic component, reported in dBc.

SAMPLE N+10 SAMPLE N+11

SAMPLE N+9

1/f

S

t

PD

t

V

V

CC

VREFIN

Figure 2. Equivalent Voltage Reference Input Circuit

V

CC

Q1

NPN

VREFOUT

OUTPUT

V

REF

Figure 3. Equivalent Voltage Reference Output Circuit

V

CC

AIN

AIN

5k⍀

7k⍀

17k⍀

ENCODE ENCODE

100⍀

8k⍀

17k⍀

100⍀

8k⍀

Figure 4. Equivalent Encode Input Circuit

Figure 5. Equivalent Digital Output Circuit

5k⍀

7k⍀

ANALOG INPUT

Figure 6. Equivalent Analog Input Circuit

–6–

REV. E

AIN INPUT FREQUENCY – MHz (–0.5dBFS)

70

0

SNR – dB

50 100 150 200

250

65

60

55

50

ANALOG INPUT FREQUENCY – MHz

0 100

dBc

20 12040 14060 16080

50

40

60

70

80

90

100

180

2nd or 3rd (–3.0dBFS)

2nd or 3rd (–6.0dBFS)

2nd or 3rd (–0.5dBFS)

200

ENCODE = 105MSPS

Typical Performance Characteristics–

AD9432

90

85

80

75

dB

70

AIN = 10.3MHz

SFDR

SNR

65

SINAD

60

020

40 60 80 100 120 140 160

ENCODE – MSPS

TPC 1. SNR/SINAD/SFDR vs. fS: fIN = 10.3 MHz

–50

–55

–60

–65

–70

–75

dBc

–80

–85

–90

–95

–100

020

3rd

2nd

40 60 80 100 120 140 160

ENCODE – MSPS

AIN = 10.3MHz

TPC 2. Harmonics vs. fS: fIN = 10.3 MHz

TPC 4. SNR vs. AIN Input Frequency,
Encode = 105 MSPS

TPC 5. Harmonics vs. fIN: fS = 105 MSPS

REV. E

70

65

60

SINAD (–3.0dBFS)

55

dB

50

45

40

020

SINAD (–6.0dBFS)

SINAD (–0.5dBFS)

40 60 80 100 120 140 160

ANALOG INPUT FREQUENCY – MHz

TPC 3. SINAD vs. fIN: fS = 105 MSPS

ENCODE = 105MSPS

180

200

–7–

100

ENCODE = 105MSPS

90

80

WORST OTHER (–6.0dBFS)

70

dBc

60

WORST OTHER (–0.5dBFS)

WORST OTHER (–3.0dBFS)

50

40

020

40 60 80 100 120 140 160

ANALOG INPUT FREQUENCY – MHz

180 200

TPC 6. Worst-Case Spur (Other than Second and
Third) vs. f

: fS = 105 MSPS

IN

AD9432

0

–10

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

ENCODE = 105MSPS
AIN = 10.3MHz (–0.53dBFS)
SNR = 67.32dB
SINAD = 67.07dB
SFDR = –85dBc

SAMPLES

TPC 7. Spectrum: fS = 105 MSPS, fIN = 10.3 MHz

0

ENCODE = 105MSPS

–10

AIN = 27.0MHz (–0.52dBFS)
SNR = 67.3dB

–20

SINAD = 67.0dB
SFDR = –83.1dBc

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

SAMPLES

TPC 8. Spectrum: fS = 105 MSPS, fIN = 27 MHz

0

ENCODE = 105MSPS

–10

AIN = 50.3MHz (–0.46dBFS)
SNR = 67.0dB

–20

SINAD = 66.7dB

–30

SFDR = –80dBc

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

SAMPLES

TPC 10. Spectrum: fS = 105 MSPS, fIN = 50.3 MHz

0

AIN1 = 29.3MHz (–7dBFS)

–10

AIN2 = 30.3MHz (–7dBFS)
ENCODE = 105MSPS

–20

–30

–40

–50

–60

dBc

–70

–80

–90

–100

–110

–120

SAMPLES

TPC 11. Two-Tone Spectrum, Wideband: fS =
105 MSPS, AIN1 = 29.3 MHz, AIN2 = 30.3 MHz

0

ENCODE = 105MSPS

–10

AIN = 40.9MHz (–0.56dBFS)
SNR = 67.2dB

–20

SINAD = 66.9dB
SFDR = –80dBc

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

SAMPLES

TPC 9. Spectrum: fS = 105 MSPS, fIN = 40.9 MHz

–8–

0

AIN1 = 70.3MHz (–7dBFS)

–10

AIN2 = 71.3MHz (–7dBFS)
ENCODE = 105MSPS

–20

–30

–40

–50

–60

dBc

–70

–80

–90

–100

–110

–120

SAMPLES

TPC 12. Two-Tone Spectrum, Wideband: fS =
105 MSPS, AIN1 = 70.3 MHz, AIN2 = 71.3 MHz

REV. E

110

LSB

INL

–0.50

–0.75

–0.25

0.00

0.25

0.50

0.75

1.00

–1.00

CURRENT – mA

02

VOLTAGE – V

4810

2.0

2.5

3.0

1.5
6

100

90

80

ENCODE = 105MSPS

70

AIN = 50.3MHz

60

50

40

30

20

10

WORST-CASE SPURIOUS – dBc AND dBFS

0

–80 –70

1.00

0.75

0.50

0.25

dBFS

dBc

–60 –40 –30 –20 –10

–50 0

ANALOG INPUT POWER LEVEL – dBFS

TPC 13. Single Tone SFDR

AD9432

TPC 15. Integral Nonlinearity: fS = 105 MSPS

0.00

LSB

–0.25

–0.50

–0.75

–1.00

DNL

TPC 14. Differential Nonlinearity: fS = 105 MSPS

TPC 16. Voltage Reference Output vs. Current Load

REV. E

–9–

AD9432

APPLICATION NOTES
Theory of Operation

The AD9432 is a multibit pipeline converter that uses a switched
capacitor architecture. Optimized for high speed, this converter
provides flat dynamic performance up to frequencies near Nyquist.
DNL transitional errors are calibrated at final test to a typical
accuracy of 0.25 LSB or less.

USING THE AD9432

Analog Input

The analog input to the AD9432 is a differential buffer. The input
buffer is self-biased by an on-chip resistor divider that sets the
dc common-mode voltage to a nominal 3 V (see Equivalent
Circuits section). Rated performance is achieved by driving the
input differentially. Minimum input offset voltage is obtained when
driving from a source with a low differential source impedance
such as a transformer in ac applications. Capacitive coupling at the
inputs will increase the input offset voltage by as much as ±25 mV.
Driving the ADC single-endedly will degrade performance.
For best dynamic performance, impedances at AIN and AIN
should match.

Special care was taken in the design of the analog input section
of the AD9432 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is 2 V p-p.
Each analog input will be 1 V p-p when driven differentially.

4.0

3.5

AIN

AD9432

ENCODE

ENCODE

PECL
GATE

510⍀

GND

510⍀

0.1␮F

0.1␮F

Figure 8. AC Coupling to ENCODE Inputs

ENCODE Voltage Level Definition

The voltage level definitions for driving ENCODE and ENCODE
in single-ended and differential mode are shown in Figure 9.

ENCODE Inputs
Differential Signal Amplitude (V

) . . . . . . . . . . . 500 mV min

ID

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 mV nom

High Differential Input Voltage (V
Low Differential Input Voltage (V
Common-Mode Input (V

) . . . . . . . 1.25 V min, 1.6 V nom

ICM

High Single-Ended Voltage (V
Low Single-Ended Voltage (V

ENCODE

ENCODE

ENCODE

0.1␮F

ILS

V

IHD

V

ICM

V

ILD

V

IHS

V

ILS

) . . . . . . . . . . 3.5 V max

IHD

) . . . . . . . . . . . . . 0 V min

ILD

) . . . . . 2 V min to 3.5 V max

IHS

) . . . . . 0 V min to 0.8 V max

V

ID

3.0

2.5

2.0

AIN

Figure 7. Full-Scale Analog Input Range

ENCODE Input

Any high speed A/D converter is extremely sensitive to the qual­ity of the sampling clock provided by the user. A track/hold
circuit is essentially a mixer, and any noise, distortion, or timing
jitter on the clock will be combined with the desired signal at the
A/D output. For that reason, considerable care has been taken
in the design of the ENCODE input of the AD9432, and the
user is advised to give commensurate thought to the clock source.
The ENCODE input supports either differential or single-ended
and is fully TTL/CMOS compatible.

Note that the ENCODE inputs cannot be driven directly from
PECL level signals (V

is 3.5 V max). PECL level signals can

IHD

easily be accommodated by ac coupling as shown in Figure 8.
Good performance is obtained using an MC10EL16 in the
circuit to drive the encode inputs.

Figure 9. Differential and Single-Ended Input Levels

Often, the cleanest clock source is a crystal oscillator producing
a pure sine wave. In this configuration, or with any roughly
symmetrical clock input, the input can be ac-coupled and biased
to a reference voltage that also provides the ENCODE. This
ensures that the reference voltage is centered on the encode signal.

Digital Outputs

The digital outputs are 3.3 V (2.7 V to 3.6 V) TTL/CMOS­compatible for lower power consumption. The output data
format is Two’s Complement, illustrated in Table I. The out of
range (OR) output (logic LOW for normal operation) will be
HIGH during any clock cycle when the ADC output data (Dx)
reach positive or negative full scale (–2048 or +2047). The OR
is internally generated each clock cycle, has the same pipe­line latency and propagation delay as the ADC output data, and
will remain HIGH until the output data reflect an in-range
condition. The ADC output bits (Dx) will not roll over, and
will therefore remain at positive or negative full scale (+2048 or
–2047) while the OR output is HIGH.

–10–

REV. E

AD9432

AIN – MHz

0

dB

20 60

64

40

63

62

61

60

SNR

SINAD

65

66

Table I. Output Coding (VREF = 2.5 V) (Two’s Complement)

Code AIN–AIN (V) Digital Output

+2047 1.000 0111 1111 1111

The dc common-mode voltage for the AD8138 outputs can be
adjusted via input V

to provide the 3 V common-mode voltage

OCM

the AD9432 inputs require.

500⍀

•• •

•• •

10pF

AD9432

0 0 0000 0000 0000

–1 –0.00049 1111 1111 1111

•• •

•• •

–2048 –1.000 1000 0000 0000

Voltage Reference

A stable and accurate 2.5 V voltage reference is built into the

VIN

50⍀

500⍀

AD8138

V

OCM

500⍀

50⍀

22pF

50⍀

AIN

AIN

5V

2k⍀

AD9432 (VREFOUT). In normal operation the internal refer­ence is used by strapping Pin 45 to Pin 46 and placing a 0.1 µF
decoupling capacitor at VREFIN.

25⍀

500⍀

10pF

3k⍀

0.1␮F

The input range can be adjusted by varying the reference voltage
applied to the AD9432. No appreciable degradation in perfor­mance occurs when the reference is adjusted ±5%. The full-scale

Figure 10. AD8138/AD9432 Schematic

range of the ADC tracks reference voltage changes linearly.

Timing

The AD9432 provides latched data outputs, with 10 pipeline
delays. Data outputs are included or available one propagation
delay (t

) after the rising edge of the encode command

PD

(see Figure 1). The length of the output data lines and loads
placed on them should be minimized to reduce transients within
the AD9432; these transients can detract from the converter’s
dynamic performance.

The minimum guaranteed conversion rate of the AD9432 is
1 MSPS. At internal clock rates below 1 MSPS, dynamic
performance may degrade. Therefore, input clock rates below
1 MHz should be avoided.

During initial power-up, or whenever the clock to the AD9432
is interrupted, the output data will not be accurate data for 200 ns
or 10 clock cycles, whichever is longer.

Figure 11. Measured SNR and SINAD (Encode = 105 MSPS)

Using the AD8138 to Drive the AD9432

A new differential output op amp from Analog Devices, Inc.,

–70

the AD8138, can be used to drive the AD9432 in dc-coupled
applications. The AD8138 was specifically designed for ADC
driver applications. Superior SNR performance is maintained up
to analog frequencies of 30 MHz. The AD8138 op amp provides

–80

H2

single-ended-to-differential conversion, providing for a low-cost
option to transformer coupling for ac applications as well.

dB

H3

The circuit in Figure 10 was breadboarded and the measured
performance is shown in Figures 11 and 12. The figures shown

–90

are for ± 5 V supplies at the AD8138—performance dropped by
about 1 dB–2 dB with a single 5 V supply at the AD8138.

Figure 11 shows SNR and SINAD for a –1 dBFS analog input
frequency varied from 2 MHz to 40 MHz with an encode rate of
105 MSPS. The measurements are for nominal conditions at
room temperature. Figure 12 shows the second and third har­monic distortion performance under the same conditions.

–100

0204060

AIN – MHz

Figure 12. Measured Second and Third Order Harmonic
Distortion (Encode = 105 MSPS)

REV. E

–11–

AD9432

[T]

86 ACQS

STOP:

TEK 5.00GS/s

T

2

CH2

CH1 1.00V 1.00V M 5.00ns CH1 1.20V

C1 MAX

2.33V

C1 MIN
810mV

C1 FREQ

106.3167MHz
LOW
SIGNAL
AMPLITUDE

EVALUATION BOARD

The AD9432 evaluation board offers an easy way to test the
AD9432. It requires an analog signal, encode clock, and power
supplies as inputs. The clock is buffered on the board to provide
the clocks for an on-board DAC and latches. The digital outputs
and output clock are available at a standard 37-pin connector P7.

Power Connector

Power is supplied to the board via two detachable 4-pin power
strips P30, P40.

P40

P1 VCC2 5 V/165 mA DAC Supply
P2 GND
P3 VCC 5 V/200 mA ADC Analog Supply
P4 GND

P30

P5 No Connect
P6 No Connect
P7 VD 3.3 V /105 mA Latch, ADC Digital Output Supply
P8 GND

Analog Inputs

The evaluation board accepts a 2 V p-p analog input signal at
SMB connector P2. This single-ended signal is ac-coupled by
capacitor C11 and drives a wideband RF transformer T1 (Mini­Circuits ADT1-1WT) that converts the single-ended signal to a
differential signal. (The AD9432 should be driven differentially to
provide optimum performance.) The evaluation board is shipped
with termination resistors R4, R5, which provide the effective
50 Ω termination impedance; input termination resistor R10 is
optional. Note: The second harmonic distortion that some RF
transformers tend to introduce at high frequencies can be reduced
by coupling two transformers in series as shown in Figure 13.
(Improvements on the order of 3 dB–4 dB can be realized.)

C1

0.1␮F

TO AIN+

TO AIN–

C2

0.1␮F

IN

T2T1

R1
25⍀

R2
25⍀

Figure 13. Improving Second Harmonic Distortion
Performance

TEK 5.00GS/s

STOP:

2

CH1

500mV

CH3

2.00V

14 ACQS

[T]

T

500mV M 5.00ns CH1 3.00V

CH2

C1 MAX

3.4V

C1 MIN

2.5mV

C1 FREQ

49.995MHz
LOW SIGNAL
AMPLITUDE

Figure 14. Analog Input Levels

The full-scale analog inputs to the ADC should be two 1 V p-p
signals 180 degrees out of phase with each other, as shown in
Figure 14. The analog inputs are dc biased by two on-chip
resistor dividers that set the common-mode voltage to approxi­mately 0.6 × VCC (0.6 × 5 = 3 V). AIN+ and AIN– each vary
between 2.5 V and 3.5 V as shown in the two upper traces in Fig­ure 14. The lower trace is the input at SMB P2 (on a 2 V/div scale).

Encode

The encode input to the board is at SMB connector P3. The
(>1 V p-p) input is ac-coupled and drives two high-speed differ­ential line receivers (MC10EL16). These receivers provide
subnanosecond rise times at their outputs—a requirement for
the ADC clock inputs for optimum performance. The EL16
outputs are PECL levels and must be ac-coupled to meet the
common-mode dc levels required at the AD9432 encode inputs.
A PECL/TTL translator (MC100ELT23), provides the clocks
required at the output latches, DAC, and 37-pin connector.

Note: Jitter performance on the clock source is critical at this
performance level; a stable, crystal-controlled signal generator is
used to generate all of the ADC performance plots. Figure 15
shows the Encode+ clock at the ADC. The 3 V latch clock
generated on the card is also shown in the plot.

–12–

Figure 15. Encode+ Clock and Latch Clock

REV. E

AD9432

DATA OUTPUTS

The ADC digital outputs are latched on the board by two 574s;
the latch outputs are available at the 37-pin connector at Pins
25–36. A latch output clock (data ready) is available at Pin 21,
with the complement at Pin 2. There are series termination
resistors on the data and clock outputs. These can be changed if
required to accommodate different loading situations. Figure
16 shows a data bit switching and output clock (DR) at the
connector.

CH2

265 ACQS

[T]

T

C1 MAX

3.06V

C1 MIN
–390mV

C1 FREQ

105.4562MHz

TEK 5.00GS/s

STOP:

2

CH1 1.00V 1.00V M 5.00ns CH1 1.20V

Figure 16. Data Bit and Clock at 37-Pin Connector

REFERENCE

The AD9432 has an on-chip reference of 2.5 V available at
VREFOUT (Pin 46). Most applications will simply tie this
output to the VREFIN input (Pin 45). This is accomplished
jumping E4 to E6 on the board. An external voltage reference
can drive the VREFIN pin if desired by strapping E4 to E3 and
placing an AD780 voltage reference on the board (not supplied).

DAC

The evaluation board has an on-board reconstruction DAC
(AD9752). This is placed only to facilitate testing and debug of
the board. It should not be used to measure the performance of
the ADC, as it will not accurately indicate the ADC performance.
The DAC output is available at SMB P1. It will drive a 50 Ω
load. Provision to power down the DAC is at Pin 15 at the DAC.

PCB LAYOUT

The PCB is designed on a four-layer (1 oz. Cu) board. Compo­nents and routing are on the top layer with a ground flood for
additional isolation. Test and ground points were judiciously
placed to facilitate high-speed probing. A common ground plane
exists on the second layer. The third layer has three split power
planes, two for the ADC and one for support logic. The DAC,
components, and routing are located on the bottom layer.

TROUBLESHOOTING

If the board does not seem to be working correctly, try the
following:

• Verify power at IC pins.

• Check that all jumpers are in the correct position for the

desired mode of operation.

• Verify VREF is at 2.5 V.

• Try running encode clock and analog inputs at low speeds

(10 MSPS/1 MHz) and monitor 574 outputs, DAC output,
and ADC outputs for toggling.

The AD9432 Evaluation Board is provided as a design example
for customers of Analog Devices, Inc. ADI makes no warranties,
express, statutory, or implied, regarding merchantability or fitness
for a particular purpose.

REV. E

–13–

AD9432

PCB Bill of Materials

# Quantity REFDES Device Package Value

1 30 C1–C8, C10–C13, C17, C19–C22, Capacitor 603 0.1 µF

C27–C29, C41, C42, C47, C48,

C53, C56, C58, C60, C61, C70
2 1 C9 Capacitor 603 0.01 µF
3 4 C14, C18, C31, C34 Capacitor CAPTAJD 10 µF
4 1 C15 Capacitor CAPTAJD 1 µF
5 18 E1–E13, E30, E32, E40, E42, E43 E-HOLE Test Point
6 3 P1, P2, P3 Connector SMB
7 1 P7 37-Pin Connector Female AMP 747462-2
8 2 P30, P40 Power Connector
9 6 R1, R2, R7, R8, R10, R18 Resistor 1206 50 Ω

(R1, R2, R10 Optional)
10 2 R3, R35 Resistor 1206 100 Ω
11 4 R25, R26, R31, R32 Resistor 1206 500 Ω
12 2 R6, R24 Resistor 1206 2 kΩ
13 4 RP1–RP4 RES PAK 100 Ω
14 1 T1 Transformer Mini-Circuits

ADT1-1WT
15 1 U1 DAC SOIC AD9752
16 1 U2 Reference (Not Supplied) SOIC AD780N
17 2 U3, U4 Inverter (U4 Not Supplied) SC70 NC7SZ04P5
18 1 U9 ADC 52QFP AD9432
19 2 U12–U13 Latch SOIC 74AC574M
20 1 Z1 PECL/TTL Translator SOIC MC100ELT23
21 2 Z2, Z3 Differential Receiver SOIC MC10EL16
22 3 R4, R5, R15 Resistor 1206 24.9 Ω

–14–

REV. E

AD9432

VCC

100⍀

RPAK_742

VD

E1

E2

U2

OR

D11

D10D9D8

9

10111213141516

9

10111213141516

8

7654321

8765432

VCC

2

5

6

37

44

47

52

13

36

VCC

22

23

32

10

9

34

AGND

U9

424140

C4

0.1␮F

AGND

EXTREF

876

NC

VOUT

2.5/3V

(NOT SUPPLIED)

+VIN

NC

TEMP

123

D7D6D5

9

RP2

100⍀

RPAK_742

1

14151617181920252627282930

D9D8D7D6D5D4D3D2D1

OR

D10

(MSB ) D11

8765432

AD9432

VREFIN

VREFOUT

AIN

46

0.1␮F

T1

ADT1-1WT

49

50

AIN

AGND

R4

24.9⍀R524.9⍀

6

2

1

AIN

4

3

VCC

5

TRIM

GND

4

AGND

C15

AGND

FLOAT

C14

10␮F

+

AD780N

1␮F

39

AGND

AGND

E3EXTREF

E4

45

E5

C2

D4D3D2D1D0

10111213141516

9

10111213141516

8

7654321

D0

1

3

4

38

43

48

51

12

35

11

33

21

24

31

ENC

ENC

7

8

AIN

AGND

AGND

C9

0.01␮F

C70

0.1␮F

PRI SEC

1

AGND

R31

C61

AGND

AGND

0.1␮F

Z2

C7

500⍀

RP1

AGND

AGND

0.1␮F

VCC

876

VCC

NCDDB

123

DR

0.1␮F

Y

Q0

D08

Q

AGND

Q1

D18

QB

DR

R7

50⍀R850⍀

AGND

NC7SZ04P5

U4 (NOT SUPPLIED)

AGND

5

GND

MC100ELT23

D1

4

R26

500⍀

AGND

5

VEE

MC10EL16

VBB

4

C6

0.1␮F

R3

100⍀

NC = NO CONNECT

AGND

AGND

CLOCK

R2

100⍀R1100⍀

VD

(R1, R2 ,

OPTIONAL)

AGND

C8

0.1␮F

AGND

R32

500⍀

AGND

AGND

AGND

5

Q

QB

VEE

MC10EL16

VBB

4

C58

0.1␮F

R35

100⍀

C1

C60

AGND

5

123

0.1␮F

Z1

0.1␮F

Z3

AGND

VD

C5

4

VCC

NCAGND

VCC2

876

VCC

D0

123

R25

500⍀

VCC2

876

VCC

NCDDB

123

REV. E

VCC

AGND

C11

0.1␮F

P2

SMBPN

ANALOG

R10

50⍀

(OPTIONAL)

AGND

C47

0.1␮F

P3

SMBPN

ENCODE

Figure 17a. PCB Schematic

–15–

AD9432

BOR

B11

B10B9B8B7B6B5B4B3B2B1B0

DR

VCC2

BYPASS

OUT

C18

C53

C56

C22

C21

C20

C19

3736353433323130292827262524232221

P37

P36

P35

P34

P33

P32

P31

P30

P29

P28

P27

P26

P7

P19

P18

P17

P16

P15

P14

P13

P12

AGND

RPAK_742

CLOCK

11

CLOCK

GND

10

GND

P11

AGND

AGND

AGND

74AC574M

191817161514131211

AGND

AGND

AGND

AGND

AGND

B0B1B2B3B4

16151413121110

16151413121110

RP3

100⍀

1234567

1234567

10␮F

AGND

0.1␮F

0.1␮F

0.1␮F

0.1␮F

C42

0.1␮F

C41

0.1␮F

VD

AGND

VD

201918171615141312

Q0Q1Q2Q3Q4Q5Q6

VCC

U13

OUT_END0D1D2D3D4D5D6D7

123456789

AGND

D0D1D2D3D4

9

9

8

8

Q7

P25

P10P9P8P7P6P5P4P3P2

9876543

10

AGND

AGND

AGND

AGND

AGND

B5B6B7B8B9

16151413121110

16151413121110

RP4

100⍀

1234567

1234567

VD

201918171615141312

Q0Q1Q2Q3Q4Q5Q6

VCC

U12

OUT_END0D1D2D3D4D5D6D7

123456789

D5D6D7

GND

P24

P23

AGND

D8D9D10

P22

AGND

P21

2

AGND

B10

20

DR

P20

P1

1

AGND

B11

9

9

8

8

BOR

11

Q7

10

D11ORGND

RPAK_742

CLOCK

CLOCK

74AC574M

GND

INV

MSB

VCC2

C12

P1

SMBPN

DACOUT

VCC2

C17

0.1␮F

AGND

CLOCK

28272625242322212019181716

CLK

DVDD

U1

GND

DCON

NC2

0.1␮F

C10

AVDD

AGND

ICOMP

IOUTA

IOUTB

0.1␮F

R18

R15

ACON

AGND

50⍀

AGNDAGND

24.9⍀

2k⍀

R24

AGNDAGNDAGNDVCC2

C13

0.1␮F

E1 E8

2k⍀

R6

AGND

NC3

REFIO

FSADJ

15

SLEEP

REFLO

AD9752

D11

0.1␮F

0.1␮F

C29

C27

0.1␮F

E-HOLES

0.1␮F
E30

E32

E12

E11

E10

E9

D10D9D8D7D6D5D4D3D2D1D0NCNC1

123456789

B10B9B8B7B6B5B4B3B2B1B0

MSB

1011121314

C48

0.1␮F

C34

10␮F

+

VCC

AGND

(+3V)

AGND

VD

NC

8765432

P30

NC

BYPASS LATCHES

OUT

(+5V)

AGND

VCC

P40

VD

C28

C31

+

AGND

0.1␮F

10␮F

(+5V)

VCC2

1

AGND

CONNECTING

PLANE

GROUND

E42

POINTS

TEST

SCOPE

D0

E43

D11

E40

DR

AGND

CLOCK

AGND

E7DRE6

Figure 17b. PCB Schematic (Continued)

–16–

C3

U3

0.1␮F

5

123

VCC2

4

Y

VCC

NCAGND

INV

AGND

NC7SZ04P5

NC = NO CONNECT

REV. E

AD9432

Figure 18. Top Silkscreen

Figure 19. Top Level Routing

Figure 21. Split Power Plane

Figure 22. Bottom Layer Route

REV. E

Figure 20. Ground Plane

Figure 23. Bottom Silkscreen

–17–

AD9432

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

52-Lead Plastic Quad Flatpack (LQFP)

(ST-52)

0.063 (1.60)

0.030 (0.75)

0.018 (0.45)

SEATING

PLANE

MAX

39

40

0.472 (12.00) SQ

TOP VIEW

(PINS DOWN)

27

26

0.394
(10.0)

SQ

52

0.006 (0.15)

0.002 (0.05)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.057 (1.45)

0.053 (1.35)

1

0.026 (0.65)
BSC

0.015 (0.38)

0.009 (0.22)

14

13

THERMALLY ENHANCED

52-Lead Power Thin Plastic Quad Flatpack (LQFP_ED)

(SQ-52)

0.093 (2.35)

0.472 (12.00) SQ

0.307 (7.80)

1

TOP VIEW

(PINS DOWN)

13

14

SEATING
PLANE

0.015 (0.38)

0.013 (0.32)

0.009 (0.22)

0.026 (0.65)

0.063

(1.60)

MAX

0.030 (0.75)

0.024 (0.60)

0.018 (0.45)

NOTES

1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER
EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

2. ALTHOUGH NOT REQUIRED IN ALL APPLICATIONS, THE AD9432 HAS AN EXPOSED METALLIC PAD ON THE
PACKAGE BOTTOM WHICH IS INTENDED TO ENHANCE THE HEAT REMOVAL PATH. TO MAXIMIZE THE REMOVAL
OF HEAT, A LAND PATTERN WITH CLOSELY SPACED THERMAL VIAS TO THE GROUND PLANE(S) SHOULD
BE INCORPORATED ON THE PCB WITHIN THE FOOTPRINT OF THE PACKAGE CORRESPONDING TO THE
EXPOSED METAL PAD DIMENSIONS OF THE PACKAGE. THE SOLDERABLE LAND AREA SHOULD BE SOLDER
MASK DEFINED AND BE AT LEAST THE SAME SIZE AND SHAPE AS THE EXPOSED PAD AREA ON THE
PACKAGE. AT LEAST 0.25 MM CLEARANCE BETWEEN THE OUTER EDGES OF THE LAND PATTERN AND THE
INNER EDGES OF THE PAD PATTERN SHOULD BE MAINTAINED TO AVOID ANY SHORTS.

4052

39

27

26

VIEW A

0.104 (2.65)

0.098 (2.50)

0.093 (2.35)

0.402 (10.20)

0.394 (10.00) SQ

0.386 (9.80)

(4 PLCS)

39

27

0.057 (1.45)

0.055 (1.40)

0.053 (1.35)

0.087 (2.20)

0.081 (2.05)

40 52

HEATSINK

(CENTERED)

26

0.236 (6.00)

0.232 (5.90)

0.228 (5.80)

BOTTOM VIEW

VIEW A

(4 PLCS)

EXPOSED

(PINS UP)

0.004 (0.10)

COPLANARITY

1

13

14

0.006 (0.15)

0.002 (0.05)

0.236 (6.00)

0.232 (5.90)

0.228 (5.80)

–18–

REV. E

AD9432

Revision History

Location Page

Data Sheet changed from REV. D to REV. E.

Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Addition of text to USING THE AD9432 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Edits to Figure 17a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Edits to Figure 17b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Addition of SQ-52 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

REV. E

–19–

C00587–0–1/02(E)

–20–

PRINTED IN U.S.A.