Analog Devices AD9430-PCB-CMOS, AD9430BSV-170 Datasheet

PRELIMINARY TECHNICAL DATA

range

REV. PrG 4/01/2002

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Fax:[phone] © Analog Devices, Inc., 2002

a

12-Bit, 170 MSPS

3.3V A/D Converter

Preliminary Technical Data AD9430

FEATURES
SNR = 65dB @ Fin up to 65MHz at 170Msps
ENOB of 10.3 @ Fin up to 65MHz at 170 Msps
SFDR = -80dBc @ Fin up to 65MHz at 170Msps

(-1dBFs)

(-1dBFs)

Excellent Linearity:

- DNL = +/- 1 lsb (typ)

- INL = +/- 1.5 lsb (typ)
Two Output Data options

- Demultiplexed 3.3V CMOS outputs each at 85 Msps

- LVDS at 170Msps
700 MHz Full Power Analog Bandwidth
On–chip reference and track/hold
Power dissipation = 1.25W typical at 170Msps

1.5V Input voltage range
+3.3V Supply Operation
Output data format option
Data Sync input and Data Clock output provided
Interleaved or parallel data output option (CMOS)
Clock Duty Cycle Stabilizer.

APPLICATIONS
Wireless and Wired Broadband Communications

- Wideband carrier frequency systems

- Cable Reverse Path
Communications Test Equipment
Radar and Satellite sub-systems
Power Amplifier Linearization

PRODUCT DESCRIPTION

The AD9430 is a 12-bit monolithic sampling analog–to–
digital converter with an on–chip track–and–hold circuit and
is optimized for low cost, low power, small size and ease of
use. The product operates up to 170 Msps conversion rate
and is optimized for outstanding dynamic performance in
wideband carrier systems.

The ADC requires a +3.3V power supply and a differential
encode clock for full performance operation. No external
reference or driver components are required for many
applications. The digital outputs are TTL/CMOS or LVDS
compatible. Separate output power supply pins support
interfacing with 3.3V CMOS logic.

An output data format select option of two’s complement or
offset binary is supported. In CMOS mode two output buses
support demultiplexed data up to 85 Msps rates. A data sync
input is supported for proper output data port alignment and
a data clock output is available for proper output data timing.

Fabricated on an advanced BiCMOS process, the AD9430 is
available in a 100 pin surface mount plastic package (100
TQFP ePAD) specified over the industrial temperature
(–40°C to +85°C).

AD9430

DS+

ENC+

ENC-

AIN+

AIN-

DS-

Management

Track &

Clock

S1 S5

AD9430 FUNCTIONAL BLOCK DIAGRAM

Hold

S2

SENSE

Scaleable
Reference

VREF

ADC

12-bit

Pipeline

Core

AGND

S4

DrGND

Outputs

12

Outputs

Select CMOS or LVDS

DrVDDAV

LVDS

CMOS

DD

A port

B port

Data(24), OR(2)

Data(12), OR(1)

Data(12), OR(1)

DCO+

DCO-

PRELIMINARY TECHNICAL DATA

AD9430

AIN

AIN

ENC

DC SPECIFICATIONS (AV

reference, LVDS Output Mode)

Parameter

= DrVDD = 3.3V; T

DD

Temp

Test

Level

= -40°C, T

MIN

= +85°C, Fin = -0.5dBFS, 1.235V External

MAX

AD9430BSV-170

Min Typ Max Units

RESOLUTION 12 Bits

ACCURACY

No Missing Codes

Offset Error

Gain Error

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

TEMPERATURE DRIFT

Offset Error

Gain Error

Full

25°C
25°C
25°C
25°C

Full
Full

POWER SUPPLY REJECTION Full V

REFERENCE OUT (V

ANALOG INPUTS (AIN,

Input Voltage Range (AIN–

Input Common Mode Voltage

Input Resistance

Input Capacitance

POWER SUPPLY

Supply Voltages

AV

DD

DrVDD

Supply Current

I

I

DIGITAL

(AVDD= 3.3V)

ANALOG

(DrVDD = 3.3V)2

) Full V 1.235 V

REF

)

)1

Full
Full
Full
Full

Full
Full

2

Full
Full

V
V

V
V
V
V

V
V

V
V

I
I
I
I
I

3.0 3.3 3.6

3.0 3.3 3.6

Guaranteed

tbd
tbd

+/- .3

+/- .5

tbd
tbd

± tbd

± .768

2.8
3
5

335

55

POWER CONSUMPTION3 Full V 1.29 W

NOTES

1

Nominal Differential Full Scale = .766 V * 2 = 1.53 V

2 I

and I

AVDD

Characteristics and Applications section for I

are measured with an analog input of 10.3MHz, -0.5dBFs, sine wave, rated Encode rate and in LVDS output mode. See Typical Performance

DrVDD

DrVDD

p-p differential

. 3 Power Consumption is measured with a DC input at rated Encode rate in LVDS output mode

DIGITAL SPECIFICATIONS (AV

Parameter (Conditions)

ENCODE AND DATA SYNC
INPUTS (ENC,

Differential Input Voltage

, DS, DS/ )

1

Encode Common Mode Voltage

Input Resistance
Input Capacitance
LOGIC INPUTS ( S1,S2,S4,S5 )
Logic ‘1’ Voltage
Logic ‘0’ Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUTS (Demux Mode)
Logic “1” Voltage
Logic “0” Voltage

2
2

LOGIC OUTPUTS (LVDS Mode)
V

Differential Output Voltage

OD

V

Output Offset Voltage

OS

Output Coding

NOTES

2

1

All AC specifications tested by driving ENCODE and ENCODE differentially | ENCODE - ENCODE | > 200mV

Digital Output Logic Levels: DrV

2,3

Temp

= 3.3V, C

DD

Full
Full

Full
Full

Full
Full
Full
Full

Full
Full

Full
Full
Full

for S5 = 0; Nominal Differential Full Scale = .766 V

= 3.3V, DrVDD = 3.3V; T

DD

Test

Level

IV
IV

IV
IV

IV

AD9430BSV-170

Min Typ Max Units

0.2

1.5

5.5

2.0

MIN

4

IV

DD

30

4

-0.05

0.05

IV
IV

IV
IV

DrV

IV

247 454

IV

1.125 1.375

IV

LOAD

Two’s Comp or Binary

= 5pF.

3

LVDS Rl=100 ohms, LVDS Output Swing Set Resistor = 3.7K

mV

% FS

LSB
LSB

ppm/°C
ppm/°C

mV/V

kΩ

pF

mA
mA

= -40°°C, T

V
V

kΩ

pF

V

.8

V

kΩ

pF

V
V

mV

V

V
V

V
V

MAX

p-p differential

for S5 = 1 (see Fig. X)

= +85°°C)

-2- 4/01/2002 REV. PrG

PRELIMINARY TECHNICAL DATA

AC SPECIFICATIONS

= +85°C, Internal voltage reference, LVDS Output Mode )

Parameter (Conditions)

SNR
Analog Input 10 MHz
@ -0.5dBFS 65 MHz
100 MHz
240 MHz

SINAD
Analog Input 10 MHz
@ -0.5dBFS 65 MHz
100 MHz
240 MHz

Worst Harmonic (2nd or 3rd)
Analog Input 10 MHz
@ -0.5dBFS 65 MHz
100 MHz
240 MHz

Worst Harmonic (4th or higher)
Analog Input 10 MHz
@ -0.5dBFS 65 MHz
100 MHz
240 MHz

Two-tone IMD2
F1, F2 @ -7 dBFS

Analog Input Bandwidth

NOTES

1

All AC specifications tested by driving ENCODE and ENCODE differentially.

2 F1 = 31.5 MHz, F2 = 32.5 MHz

SWITCHING SPECIFICATIONS (AVDD= 3.3 V, DrVDD = 3.3V; ENCODE = Maximum Conversion Rate ;

Parameter (Conditions)

Maximum Conversion Rate1
Minimum Conversion Rate
Encode Pulse Width High (t
Encode Pulse Width Low (t
DS Input Setup Time (t
DS Input Hold Time (t

NOTES

1

All AC specifications tested by driving ENCODE and ENCODE differentially, LVDS Mode.

2 DS inputs used in CMOS Mode only.

SDS

HDS

1

) 2

) 2

1

(AVDD= 3.3 V, DrVDD = 3.3V; ENCODE = Maximum Conversion Rate ; T

Test

Temp

25°C
25°C
25°C
25°C

25°C
25°C
25°C
25°C

25°C
25°C
25°C
25°C

25°C
25°C
25°C
25°C

Full

25°C

Temp

Full

)1

EH

1

)

EL

Full
Full
Full
Full
Full

Level

I

I
V
V

I

I
V
V

I

I
V
V

I

I
V
V

V
V 700 MHz

= -40°C, T

T

MIN

Test

Level

I
V
V
V

IV
IV

AD9430BSV-170

Min Typ Max Units

65
65
65
64

65
65

64.5
60

-85

-80

-77

-63

-87

-87

-77

-63

-75

= +85°C )

MAX

dB
dB
dB
dB

dB
dB
dB
dB

dBc
dBc
dBc
dBc

dBc
dBc
dBc
dBc

dBc

AD9430BSV-170

Min Typ Max Units

170
40

2
2

.5

1.5

MSPS
MSPS

nS
nS
nS
nS

AD9430

= -40°C, T

MIN

MAX

REV. PrG 4/01/2002 -3-

PRELIMINARY TECHNICAL DATA

AD9430

SWITCHING SPECIFICATIONS (cont’d)

Parameter

OUTPUT Parameters in Demux Mode
Valid Time (t
Propagation Delay (t
Rise Time (t
Fall Time (t
DCO Propagation Delay (t
Data to DCO Skew (t

)

V

) (20% to 80%)

R

) (20% to 80%)

F

PD

PD

– t

)

CPD

CPD

)

)
Interleaved Mode (A, B Latency)
Parallel Mode (A, B Latency)

OUTPUT Parameters in LVDS Mode
Valid Time (t
Propagation Delay (t
Rise Time (t
Fall Time (t
DCO Propagation Delay (t
Data to DCO Skew (t

)

V

) (20% to 80%)

R

) (20% to 80%)

F

PD

PD

– t

)

CPD

CPD

)

)
Pipeline Latency

Aperture Delay (tA)
Aperture Uncertainty (Jitter, t

)

J

Temp

Full
Full

25°C
25°C

Full
Full
Full
Full

Full
Full

25°C
25°C

Full
Full
Full

25°C
25°C

Test

Level

IV
IV

V

V
VI
IV
VI
VI

IV

I
V
V

VI
IV
VI

V
V

Min Typ Max Units

2.0

1.8 2.7 3.8

Measured Preliminary Performance : FFT 65MHz Ain at 170MSPS

AD9430BSV-170

tbd

3.8
1
1

3.8
0

14/14
14/15

3.2 4.3

.5
.5

.5

14

1.2

0.25

ns
ns
ns
ns
ns

ns
Cycles
Cycles

ns

ns

ns

ns

ns

ns
Cycles

ps
ps rms

-4- 4/01/2002 REV. PrG

PRELIMINARY TECHNICAL DATA

AD9430 Timing Diagram

AD9430

REV. PrG 4/01/2002 -5-

PRELIMINARY TECHNICAL DATA

AD9430

ABSOLUTE MAXIMUM RATINGS

AVDD, DRVDD.. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V

Analog Inputs . . . . . . . . . . .. . .. . . –0.5 V to AVDD + 0.5 V

Digital Inputs . . .. . . . . . . . .. . . .. –0.5 V to DRVDD + 0.5 V

REFIN Inputs . . . . . . . . . . . . . . . . –0.5 V to AVDD + 0.5 V

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating Temperature . . . . . . . . . . ... . . . . . –55C to +125C

Storage Temperature . . . . . . . . . . . . . ... . . . . –65C to +150C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C

Maximum Case Temperature . . . . . . . . . . . . . . . . . . . ..150C

2



θ

. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . 25C/W, 32C/W

JA

NOTES

EXPLANATION OF TEST LEVELS
Test Level

I 100% production tested.
II 100% production tested at 25C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI 100% production tested at 25C; guaranteed by design
and characterization testing for industrial temperature
range; 100% production tested at temperature extremes
for military devices.

1 Stresses above those listed under Absolute Maximum Ratings may

cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions outside of those
indicated in the operation sections of this specification is not implied.
Exposure to absolute maximum ratings for extended periods may affect
device reliability.

2 Typical
25C/W (heat slug soldered), for multilayer board in still air.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9430 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality

θJA = 32C/W (heat slug not soldered), Typical θ

=

JA

.

ORDERING GUIDE

Model Temperature Range Package Option

AD9430BSV-170 –40°C to +85°C TQFP–100

AD9430/PCB-CMOS +25°C Evaluation Board

(CMOS Mode)

Table 1. AD9430 Output Select Coding

S1

(Data
Format
Select)

S2

(LVDS/CMOS
Output Mode
Select )

1

S4

(Select
Interleaved or
Parallel Mode)

(Full Scale
Adjust)

2

S5

1 X X X 2’s Complement

0 X X X Offset Binary
X 0 1 X Dual Mode CMOS Interleaved
X 0 0 X Dual Mode CMOS Parallel
X 1 X X LVDS Mode
X X X 1 Full Scale -> .766 V

1.533 V

X X X 0 Full Scale -> 1.533 V

Notes:

1

X = Don’t Care

S1-S5 all have 30K resistive pulldowns on chip

2

In interleaved mode output data on port A is offset from output data changes on port B by ½ output clock cycle.

Interleaved mode

Parallel Mode

Mode

pp differential

Single- Ended

pp

pp differential

-6- 4/01/2002 REV. PrG