Analog Devices AD9430-PCB-CMOS, AD9430BSV-170 Datasheet

PRELIMINARY TECHNICAL DATA

range

REV. PrG 4/01/2002

Information furnished by Analog Devices is believed to be accurate and
reliable.However,no responsibility is assumed by Analog Devices for its use,nor
for any infringements of patents or other rights of third parties that may result from
its use.No license is granted by implication or otherwise under any patent or
patent rights of Analog Devices.

One Technology Way,P.O.Box 9106,Norwood,MA 02062-9106,U.S.A.
Tel:[phone] www.analog.com
Fax:[phone] © Analog Devices, Inc., 2002

a

12-Bit, 170 MSPS

3.3V A/D Converter

Preliminary Technical Data AD9430

FEATURES
SNR = 65dB @ Fin up to 65MHz at 170Msps
ENOB of 10.3 @ Fin up to 65MHz at 170 Msps
SFDR = -80dBc @ Fin up to 65MHz at 170Msps

(-1dBFs)

(-1dBFs)

Excellent Linearity:

- DNL = +/- 1 lsb (typ)

- INL = +/- 1.5 lsb (typ)
Two Output Data options

- Demultiplexed 3.3V CMOS outputs each at 85 Msps

- LVDS at 170Msps
700 MHz Full Power Analog Bandwidth
On–chip reference and track/hold
Power dissipation = 1.25W typical at 170Msps

1.5V Input voltage range
+3.3V Supply Operation
Output data format option
Data Sync input and Data Clock output provided
Interleaved or parallel data output option (CMOS)
Clock Duty Cycle Stabilizer.

APPLICATIONS
Wireless and Wired Broadband Communications

- Wideband carrier frequency systems

- Cable Reverse Path
Communications Test Equipment
Radar and Satellite sub-systems
Power Amplifier Linearization

PRODUCT DESCRIPTION

The AD9430 is a 12-bit monolithic sampling analog–to–
digital converter with an on–chip track–and–hold circuit and
is optimized for low cost, low power, small size and ease of
use. The product operates up to 170 Msps conversion rate
and is optimized for outstanding dynamic performance in
wideband carrier systems.

The ADC requires a +3.3V power supply and a differential
encode clock for full performance operation. No external
reference or driver components are required for many
applications. The digital outputs are TTL/CMOS or LVDS
compatible. Separate output power supply pins support
interfacing with 3.3V CMOS logic.

An output data format select option of two’s complement or
offset binary is supported. In CMOS mode two output buses
support demultiplexed data up to 85 Msps rates. A data sync
input is supported for proper output data port alignment and
a data clock output is available for proper output data timing.

Fabricated on an advanced BiCMOS process, the AD9430 is
available in a 100 pin surface mount plastic package (100
TQFP ePAD) specified over the industrial temperature
(–40°C to +85°C).

AD9430

DS+

ENC+

ENC-

AIN+

AIN-

DS-

Management

Track &

Clock

S1 S5

AD9430 FUNCTIONAL BLOCK DIAGRAM

Hold

S2

SENSE

Scaleable
Reference

VREF

ADC

12-bit

Pipeline

Core

AGND

S4

DrGND

Outputs

12

Outputs

Select CMOS or LVDS

DrVDDAV

LVDS

CMOS

DD

A port

B port

Data(24), OR(2)

Data(12), OR(1)

Data(12), OR(1)

DCO+

DCO-

PRELIMINARY TECHNICAL DATA

AD9430

AIN

AIN

ENC

DC SPECIFICATIONS (AV

reference, LVDS Output Mode)

Parameter

= DrVDD = 3.3V; T

DD

Temp

Test

Level

= -40°C, T

MIN

= +85°C, Fin = -0.5dBFS, 1.235V External

MAX

AD9430BSV-170

Min Typ Max Units

RESOLUTION 12 Bits

ACCURACY

No Missing Codes

Offset Error

Gain Error

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

TEMPERATURE DRIFT

Offset Error

Gain Error

Full

25°C
25°C
25°C
25°C

Full
Full

POWER SUPPLY REJECTION Full V

REFERENCE OUT (V

ANALOG INPUTS (AIN,

Input Voltage Range (AIN–

Input Common Mode Voltage

Input Resistance

Input Capacitance

POWER SUPPLY

Supply Voltages

AV

DD

DrVDD

Supply Current

I

I

DIGITAL

(AVDD= 3.3V)

ANALOG

(DrVDD = 3.3V)2

) Full V 1.235 V

REF

)

)1

Full
Full
Full
Full

Full
Full

2

Full
Full

V
V

V
V
V
V

V
V

V
V

I
I
I
I
I

3.0 3.3 3.6

3.0 3.3 3.6

Guaranteed

tbd
tbd

+/- .3

+/- .5

tbd
tbd

± tbd

± .768

2.8
3
5

335

55

POWER CONSUMPTION3 Full V 1.29 W

NOTES

1

Nominal Differential Full Scale = .766 V * 2 = 1.53 V

2 I

and I

AVDD

Characteristics and Applications section for I

are measured with an analog input of 10.3MHz, -0.5dBFs, sine wave, rated Encode rate and in LVDS output mode. See Typical Performance

DrVDD

DrVDD

p-p differential

. 3 Power Consumption is measured with a DC input at rated Encode rate in LVDS output mode

DIGITAL SPECIFICATIONS (AV

Parameter (Conditions)

ENCODE AND DATA SYNC
INPUTS (ENC,

Differential Input Voltage

, DS, DS/ )

1

Encode Common Mode Voltage

Input Resistance
Input Capacitance
LOGIC INPUTS ( S1,S2,S4,S5 )
Logic ‘1’ Voltage
Logic ‘0’ Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUTS (Demux Mode)
Logic “1” Voltage
Logic “0” Voltage

2
2

LOGIC OUTPUTS (LVDS Mode)
V

Differential Output Voltage

OD

V

Output Offset Voltage

OS

Output Coding

NOTES

2

1

All AC specifications tested by driving ENCODE and ENCODE differentially | ENCODE - ENCODE | > 200mV

Digital Output Logic Levels: DrV

2,3

Temp

= 3.3V, C

DD

Full
Full

Full
Full

Full
Full
Full
Full

Full
Full

Full
Full
Full

for S5 = 0; Nominal Differential Full Scale = .766 V

= 3.3V, DrVDD = 3.3V; T

DD

Test

Level

IV
IV

IV
IV

IV

AD9430BSV-170

Min Typ Max Units

0.2

1.5

5.5

2.0

MIN

4

IV

DD

30

4

-0.05

0.05

IV
IV

IV
IV

DrV

IV

247 454

IV

1.125 1.375

IV

LOAD

Two’s Comp or Binary

= 5pF.

3

LVDS Rl=100 ohms, LVDS Output Swing Set Resistor = 3.7K

mV

% FS

LSB
LSB

ppm/°C
ppm/°C

mV/V

kΩ

pF

mA
mA

= -40°°C, T

V
V

kΩ

pF

V

.8

V

kΩ

pF

V
V

mV

V

V
V

V
V

MAX

p-p differential

for S5 = 1 (see Fig. X)

= +85°°C)

-2- 4/01/2002 REV. PrG

PRELIMINARY TECHNICAL DATA

AC SPECIFICATIONS

= +85°C, Internal voltage reference, LVDS Output Mode )

Parameter (Conditions)

SNR
Analog Input 10 MHz
@ -0.5dBFS 65 MHz
100 MHz
240 MHz

SINAD
Analog Input 10 MHz
@ -0.5dBFS 65 MHz
100 MHz
240 MHz

Worst Harmonic (2nd or 3rd)
Analog Input 10 MHz
@ -0.5dBFS 65 MHz
100 MHz
240 MHz

Worst Harmonic (4th or higher)
Analog Input 10 MHz
@ -0.5dBFS 65 MHz
100 MHz
240 MHz

Two-tone IMD2
F1, F2 @ -7 dBFS

Analog Input Bandwidth

NOTES

1

All AC specifications tested by driving ENCODE and ENCODE differentially.

2 F1 = 31.5 MHz, F2 = 32.5 MHz

SWITCHING SPECIFICATIONS (AVDD= 3.3 V, DrVDD = 3.3V; ENCODE = Maximum Conversion Rate ;

Parameter (Conditions)

Maximum Conversion Rate1
Minimum Conversion Rate
Encode Pulse Width High (t
Encode Pulse Width Low (t
DS Input Setup Time (t
DS Input Hold Time (t

NOTES

1

All AC specifications tested by driving ENCODE and ENCODE differentially, LVDS Mode.

2 DS inputs used in CMOS Mode only.

SDS

HDS

1

) 2

) 2

1

(AVDD= 3.3 V, DrVDD = 3.3V; ENCODE = Maximum Conversion Rate ; T

Test

Temp

25°C
25°C
25°C
25°C

25°C
25°C
25°C
25°C

25°C
25°C
25°C
25°C

25°C
25°C
25°C
25°C

Full

25°C

Temp

Full

)1

EH

1

)

EL

Full
Full
Full
Full
Full

Level

I

I
V
V

I

I
V
V

I

I
V
V

I

I
V
V

V
V 700 MHz

= -40°C, T

T

MIN

Test

Level

I
V
V
V

IV
IV

AD9430BSV-170

Min Typ Max Units

65
65
65
64

65
65

64.5
60

-85

-80

-77

-63

-87

-87

-77

-63

-75

= +85°C )

MAX

dB
dB
dB
dB

dB
dB
dB
dB

dBc
dBc
dBc
dBc

dBc
dBc
dBc
dBc

dBc

AD9430BSV-170

Min Typ Max Units

170
40

2
2

.5

1.5

MSPS
MSPS

nS
nS
nS
nS

AD9430

= -40°C, T

MIN

MAX

REV. PrG 4/01/2002 -3-

PRELIMINARY TECHNICAL DATA

AD9430

SWITCHING SPECIFICATIONS (cont’d)

Parameter

OUTPUT Parameters in Demux Mode
Valid Time (t
Propagation Delay (t
Rise Time (t
Fall Time (t
DCO Propagation Delay (t
Data to DCO Skew (t

)

V

) (20% to 80%)

R

) (20% to 80%)

F

PD

PD

– t

)

CPD

CPD

)

)
Interleaved Mode (A, B Latency)
Parallel Mode (A, B Latency)

OUTPUT Parameters in LVDS Mode
Valid Time (t
Propagation Delay (t
Rise Time (t
Fall Time (t
DCO Propagation Delay (t
Data to DCO Skew (t

)

V

) (20% to 80%)

R

) (20% to 80%)

F

PD

PD

– t

)

CPD

CPD

)

)
Pipeline Latency

Aperture Delay (tA)
Aperture Uncertainty (Jitter, t

)

J

Temp

Full
Full

25°C
25°C

Full
Full
Full
Full

Full
Full

25°C
25°C

Full
Full
Full

25°C
25°C

Test

Level

IV
IV

V

V
VI
IV
VI
VI

IV

I
V
V

VI
IV
VI

V
V

Min Typ Max Units

2.0

1.8 2.7 3.8

Measured Preliminary Performance : FFT 65MHz Ain at 170MSPS

AD9430BSV-170

tbd

3.8
1
1

3.8
0

14/14
14/15

3.2 4.3

.5
.5

.5

14

1.2

0.25

ns
ns
ns
ns
ns

ns
Cycles
Cycles

ns

ns

ns

ns

ns

ns
Cycles

ps
ps rms

-4- 4/01/2002 REV. PrG

PRELIMINARY TECHNICAL DATA

AD9430 Timing Diagram

AD9430

REV. PrG 4/01/2002 -5-

PRELIMINARY TECHNICAL DATA

AD9430

ABSOLUTE MAXIMUM RATINGS

AVDD, DRVDD.. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V

Analog Inputs . . . . . . . . . . .. . .. . . –0.5 V to AVDD + 0.5 V

Digital Inputs . . .. . . . . . . . .. . . .. –0.5 V to DRVDD + 0.5 V

REFIN Inputs . . . . . . . . . . . . . . . . –0.5 V to AVDD + 0.5 V

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating Temperature . . . . . . . . . . ... . . . . . –55C to +125C

Storage Temperature . . . . . . . . . . . . . ... . . . . –65C to +150C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C

Maximum Case Temperature . . . . . . . . . . . . . . . . . . . ..150C

2



θ

. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . 25C/W, 32C/W

JA

NOTES

EXPLANATION OF TEST LEVELS
Test Level

I 100% production tested.
II 100% production tested at 25C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI 100% production tested at 25C; guaranteed by design
and characterization testing for industrial temperature
range; 100% production tested at temperature extremes
for military devices.

1 Stresses above those listed under Absolute Maximum Ratings may

cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions outside of those
indicated in the operation sections of this specification is not implied.
Exposure to absolute maximum ratings for extended periods may affect
device reliability.

2 Typical
25C/W (heat slug soldered), for multilayer board in still air.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9430 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality

θJA = 32C/W (heat slug not soldered), Typical θ

=

JA

.

ORDERING GUIDE

Model Temperature Range Package Option

AD9430BSV-170 –40°C to +85°C TQFP–100

AD9430/PCB-CMOS +25°C Evaluation Board

(CMOS Mode)

Table 1. AD9430 Output Select Coding

S1

(Data
Format
Select)

S2

(LVDS/CMOS
Output Mode
Select )

1

S4

(Select
Interleaved or
Parallel Mode)

(Full Scale
Adjust)

2

S5

1 X X X 2’s Complement

0 X X X Offset Binary
X 0 1 X Dual Mode CMOS Interleaved
X 0 0 X Dual Mode CMOS Parallel
X 1 X X LVDS Mode
X X X 1 Full Scale -> .766 V

1.533 V

X X X 0 Full Scale -> 1.533 V

Notes:

1

X = Don’t Care

S1-S5 all have 30K resistive pulldowns on chip

2

In interleaved mode output data on port A is offset from output data changes on port B by ½ output clock cycle.

Interleaved mode

Parallel Mode

Mode

pp differential

Single- Ended

pp

pp differential

-6- 4/01/2002 REV. PrG

PRELIMINARY TECHNICAL DATA

(MSB)

AGND

AVDD

AGND

AGND

AVDD

AVDD

AGND

323733

AGND

AVDD

AGND

90

91

92

LVDS PINOUT

TOP VIEW

(Not to Scale)

36

34

AVDD

AVDD

888786

89

AD9430

38

AGND

OR_T

OR_C

AGND

DRVDD

858084

83

424344454647484950

393540

41

DRGND

D11_T
81

D11_C

D10_T

79

D9_T

D10_C

788277

D9_C

76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52 D1_T
51

DNC

AGND

LVDSBIAS

AVDD

AGND

SENSE

VREF
AGND
AGND

AVDD

AVDD
AGND
AGND

AVDD

AVDD

AGND

AGND

AVDD
AGND

AIN
AIN

AVDD

9796959493

99

98

100

1

S5

2
3

S4

4
5

S2

6

S1

7
8

9
10
11
12
13
14
15
16

17
18
19
20
21
22
23
24
25

293031

27

28

26

DRVDD

DRGND

D8_T
D8_C
D7_T
D7_C
D6_T
D6_C
DRGND
D5_T
D5_C
DCO
DCO
DRVDD
DRGND

D4_T

D4_C
D3_T
D3_C
D2_T

D2_C
DRVDD
DRGND

D1_C

AD9430

ENC

AGND

AVDD

AVDD

AVDD

AGND

AGND

GND

AVDD

AVDD

AGND

ENC

AVDD

AGND

AVDD

AGND

DNC

DNC

DNC

DNC

DNC

DRVDD

DRGND

D0_C

D0_T

AD9430 LVDS Mode Pinout

AGND

AVDD

AVDD

AGND

AGND

DA11 (MSB)

DRVDD

DRGND

DA10

DA9

DA8

DA7

DB2

79

788277

DRVDD

DRGND

DA6

DB3

DA5

76

DB4

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60

59
58
57
56
55
54
53
52
51

DRVDD

DRGND

DA4
DA3
DA2
DA1
DA0
DNC
DRGND
DNC
DNC
DCO
DCO
DRVDD
DRGND

OR_B

DB11
DB10
DB9
DB8

DB7
DRVDD
DRGND
DB6
DB5

(MSB)

DNC

AGND

DNC

AVDD

AGND

SENSE

VREF
AGND
AGND

AVDD

AVDD
AGND
AGND

AVDD

AVDD

AGND

AIN
AIN

AGND

AVDD
AGND

AGND

AVDD

AGND

AGND

AVDD

AVDD

99

98

100

1

S5

2
3

S4

4
5

S2

6

S1

7
8

9
10
11
12
13
14
15
16

17
18
19
20
21
22
23
24
25

27

28

26

AVDD

AVDD

AGND

AVDD

9796959493

293031

323733

DS

AVDD

AGND

AGND

AGND

AGND

92

34

DS

AVDD

91

AVDD

90

89

AD9430

CMOS PINOUT

TOP VIEW

(Not to Scale)

36

ENC

ENC

AGND

888786

38

393540

AVDD

AGND

OR_A

858084

41

AVDD

AGND

81

83

424344454647484950

DB0

DB1

DNC

DNC

AD9430 CMOS Dual Mode Pinout

REV. PrG 4/01/2002 -7-

PRELIMINARY TECHNICAL DATA

AD9430

PIN FUNCTION DESCRIPTIONS (CMOS mode)
CMOS Mode

Name

Function in CMOS Mode

Pin Number

2,7,42,43,65,66,68 DNC Do not connect
1 S5

3 S4 Interlaced or parallel output mode. (only in Dual Port mode

5 S2 Output Mode select. Low = Dual Port, CMOS; High = LVDS
6 S1 Data format select. Low = Binary, High = Two’s compliment
8,14,15,18,19,24,27,28,29,34,
39,40,88,89,90,94,95,98,99
4,9,12,13,16,17,20,23,25,26,3
0,31,35,38,41,86,87,91,92,93,
96,97,100
10 SENSE Control Pin for Reference , Full Scale
11 VREF 1.235 Reference I/O - function dependent on REFSENSE
21 VIN+ Analog input – true.
22 VIN- Analog input – compliment.
32 DS+ Data sync (input) – true. Aligns output channels so that data from

33 DS- Data sync (input) – compliment. Tie HIGH if not used.
36 ENC+ Clock input – true.
37 ENC- Clock input – compliment.
44 DB0 B Port Output Data Bit (LSB)
45 DB1 B Port Output Data Bit
46 DB2 B Port Output Data Bit
49 DB3 B Port Output Data Bit
50 DB4 B Port Output Data Bit
51 DB5 B Port Output Data Bit
52 DB6 B Port Output Data Bit
55 DB7 B Port Output Data Bit
56 DB8 B Port Output Data Bit
57 DB9 B Port Output Data Bit
58 DB10 B Port Output Data Bit
59 DB11 B Port Output Data Bit (MSB)
60 OR_B B Port Overrange
48,53,61,67,74,82 DrGND Digital ground.
47,54,62,75,83 DrVDD 3.3V digital output supply. (3.0V to 3.6V)
63 DCO- Data Clock output – compliment.
64 DCO+ Data Clock output – true.
69 DA0 A port Output Data Bit (LSB)
70 DA1 A port Output Data Bit
71 DA2 A port Output Data Bit
72 DA3 A port Output Data Bit
73 DA4 A port Output Data Bit
76 DA5 A port Output Data Bit
77 DA6 A port Output Data Bit
78 DA7 A port Output Data Bit
79 DA8 A port Output Data Bit
80 DA9 A port Output Data Bit
81 DA10 A port Output Data Bit
84 DA11 A port Output Data Bit (MSB)
85 OR_A A port Overrange

AVDD 3.3V analog supply. (3.0V to 3.6V)

AGND Analog Ground

Full Scale Adjust pin : ‘1’ sets FS =

‘0’ sets FS =

operation) HIGH = data arrives in channel A at falling edge of clock
and data arrives in channel A at rising edge of clock. LOW = data
arrives in channels A and B at rising edge of clock.

channel A represents a sample that is prior from data in channel B,
taking into account the pipeline delay. (See timing diagram). Tie
LOW if not used.

1.533 V

pp differential

.766 V

pp differential,

-8- 4/01/2002 REV. PrG

PRELIMINARY TECHNICAL DATA

PIN FUNCTION DESCRIPTIONS (LVDS mode )
LVDS Mode

Name

Pin Number

2,42,43,44,45,46 DNC Do not connect
1 S5

3 S4 Interlaced or parallel output mode. (only in Dual Port mode

5 S2 Output Mode select. Low = Dual Port, CMOS; High = LVDS
6 S1 Data format select. Low = Binary, High = Two’s compliment
7 LVDSBIAS Sets LVDS Output Current = 3.5mA

8,14,15,18,19,24,27,28,29,34,
39,40,88,89,90,94,95,98,99
4,9,12,13,16,17,20,23,25,26,3
0,31,35,38,41,86,87,91,92,93,
96,97,100
10 SENSE Control Pin for Reference , Full Scale
11 VREF 1.235 Reference I/O - function dependent on REFSENSE
21 VIN+ Analog input – true.
22 VIN- Analog input – compliment.
32 DS+ Data sync (input) – Not used in LVDS mode.Tie LOW .
33 DS- Data sync (input) – compliment. Not used in LVDS mode.Tie HIGH.
36 ENC+ Clock input – true. (LVPECL levels)
37 ENC- Clock input – compliment. (LVPECL levels)
47,54,62,75,83 DrVDD 3.3V digital output supply.

AVDD 3.3V analog supply. (3.0V to 3.6V)

AGND Analog Ground

Function in LVDS Mode

Full Scale Adjust pin : ‘1’ sets FS =

‘0’ sets FS =

operation) HIGH = data arrives in channel A at falling edge of clock
and data arrives in channel A at rising edge of clock. LOW = data
arrives in channels A and B at rising edge of clock.

(Place 3.7K RSET resistor from LVDSBIAS to ground)

1.533 V

pp differential

.766 V

pp differential,

AD9430

48,53,61,67,74,82 DrGND Digital ground.
49 D0_C D0 complement output bit (LSB) (LVDS Levels)
50 D0_T D0 true output bit (LSB) (LVDS Levels)
51 D1_C D1 complement output bit (LVDS Levels)
52 D1_T D1 true output bit (LVDS Levels)
55 D2_C D2 complement output bit (LVDS Levels)
56 D2_T D2 true output bit (LVDS Levels)
57 D3_C D3 complement output bit (LVDS Levels)
58 D3_T D3 true output bit (LVDS Levels)
59 D4_C D4 complement output bit (LVDS Levels)
60 D4_T D4 true output bit (LVDS Levels)
63 DCO- Data Clock output – compliment. (LVDS Levels)
64 DCO+ Data Clock output – true. (LVDS Levels)
65 D5_C D5 complement output bit (LVDS Levels)
66 D5_T D5 true output bit (LVDS Levels)
68 D6_C D6 complement output bit (LVDS Levels)
69 D6_T D6 true output bit (LVDS Levels)
70 D7_C D7 complement output bit (LVDS Levels)
71 D7_T D7 true output bit (LVDS Levels)
72 D8_C D8 complement output bit (LVDS Levels)
73 D8_T D8 true output bit (LVDS Levels)
76 D9_C D9 complement output bit (LVDS Levels)
77 D9_T D9 true output bit (LVDS Levels)
78 D10_C D10 complement output bit (LVDS Levels)
79 D10_T D10 true output bit (LVDS Levels)
80 D11_C D11 complement output bit (LVDS Levels) MSB
81 D11_T D11 true output bit (LVDS Levels) MSB
84 OR_C Overrange complement output bit (LVDS Levels)
85 OR_T Overrange true output bit (LVDS Levels)

REV. PrG 4/01/2002 -9-

PRELIMINARY TECHNICAL DATA

AD9430

02.6

TERMINOLOGY
Analog Bandwidth

The analog input frequency at which the spectral power of
the fundamental frequency (as determined by the FFT
analysis) is reduced by 3 dB.

Aperture Delay

The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog
input is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Crosstalk

Coupling onto one channel being driven by a low level (–40
dBFS) signal when the adjacent interfering channel is driven
by a full-scale signal.

Differential Analog Input Resistance, Differential Analog
Input Capacitance and Differential Analog Input
Impedance

The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak
differential voltage is computed by observing the voltage on
a single pin and subtracting the voltage from the other pin,
which is 180 degrees out of phase. Peak-to-peak differential
is computed by rotating the inputs phase 180 degrees and
again taking the peak measurement. The difference is then
computed between both peak measurements.

Differential Nonlinearity

The deviation of any code width from an ideal 1 LSB step.

Effective Number of Bits

The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:

ENOB

ENCODE Pulsewidth / Duty Cycle

Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. See timing
implications of changing t
these specifica-tions define an acceptable ENCODE duty
cycle.

76.1 dBSNR

=

MEASURED

in text. At a given clock rate,

ENCH

−

Full-Scale Input Power

Expressed in dBm. Computed using the following equation:

2



V

Fullscale




Power

Fullscale

=

log10

Z



001.






Gain Error

Gain error is the difference between the measured and ideal
full scale input voltage range of the ADC.

Harmonic Distortion, Second

The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.

Harmonic Distortion, Third

The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.

Integral Nonlinearity

The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.

Noise (for Any Range within the ADC)




=

noise

Where Z is the input impedance, FS is the full scale of the
device for the frequency in question, SNR is the value for the
particular input level, and Signal is the signal level within
the ADC reported in dB below full scale. This value includes
both thermal and quantization noise.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in
power supply voltage.

Signal-to-Noise-and-Distortion (SINAD)

The ratio of the rms signal amplitude (set 1 dB below full
scale) to the rms value of the sum of all other spectral
components, including harmonics but excluding dc.

-10- 4/01/2002 REV. PrG

ZV



10*001.*

Input



rms









−−

SignalSNRFS

10



dBFSdBcdBm




PRELIMINARY TECHNICAL DATA

Signal-to-Noise Ratio (without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious
component may or may not be a harmonic. May be reported
in dBc (i.e., degrades as signal level is lowered), or dBFS
(always related back to converter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms
value of the worst third order intermodulation product;
reported in dBc.

Two-Tone SFDR

The ratio of the rms value of either input tone to the rms
value of the peak spurious component. The peak spurious
component may or may not be an IMD product. May be
reported in dBc (i.e., degrades as signal level is lowered), or
in dBFS (always related back to converter full scale).

Worst Other Spur

The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.

Transient Response Time

Transient response is defined as the time it takes for the
ADC to reacquire the analog input after a transient from
10% above negative full scale to 10% below positive full
scale.

Out-of-Range Recovery Time

Out of range recovery time is the time it takes for the ADC
to reacquire the analog input after a transient from 10%
above positive full scale to 10% above negative full scale, or
from 10% below negative full scale to 10% below positive
full scale.

EQUIVALENT CIRCUITS

AD9430

Figure X Analog Inputs

Figure X S1-S5 Inputs

Figure X VREF, SENSE I/O

Figure X Data Outputs (CMOS Mode)

Figure X Encode and DS Inputs

REV. PrG 4/01/2002 -11-

Figure X Data Outputs (LVDS Mode)

PRELIMINARY TECHNICAL DATA

AD9430

APPLICATION NOTES

THEORY OF OPERATION

The AD9430 architecture is optimized for high speed and
ease of use. The analog inputs drive an integrated high
bandwidth track-and-hold circuit that samples the signal
prior to quantization by the 12-bit core. For ease of use the
part includes an onboard reference and input logic that
accepts TTL, CMOS, or LVPECL levels. The digital outputs
logic levels are user selectable as standard 3V CMOS or
LVDS (ANSI-644 compatible) via pin S2.

USING THE AD9430
ENCODE Input

Any high speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A
track/hold circuit is essentially a mixer, and any noise,
distortion, or timing jitter on the clock will be combined
with the desired signal at the A/D output. For that reason,
considerable care has been taken in the design of the
ENCODE input of the AD9430, and the user is advised to
give commensurate thought to the clock source.

The AD9430 has an internal clock duty cycle stabilization
circuit that locks to the rising edge of ENCODE (falling
edge of ENCODE if driven differentially), and optimizes
timing internally. This allows for a wide range of input duty
cycles at the input without degrading performance. Jitter in
the rising edge of the input is still of paramount concern, and
is not reduced by the internal stabilization circuit. This
circuit is always on, and cannot be disabled by the user.
The ENCODE and ENCODE inputs are internally biased to

1.5V (nominal), and support either differential or single –
ended signals. For best dynamic performance, a differential
signal is recommended. Good performance is obtained
using an MC10EL16 in the circuit to drive the
encode inputs , as illustrated in figure below.

differential analog inputs for applications that require a
single-ended-to-differential conversion. Both analog inputs
are self-biased by an on-chip resistor divider to a nominal

2.8 V. (See Equivalent Circuits section TBD.)
Special care was taken in the design of the Analog Input
section of the AD9430 to prevent damage and corruption of
data when the input is overdriven. The nominal input range
is 1.5 V diff p-p. The nominal differential input range is 768
mV p-p × 2.

Differential Analog Input Range

Driving Encode with EL16

Analog Input

The analog input to the AD9430 is a differential buffer. For

____

best dynamic performance, impedances at
should match. The analog input has been optimized to
provide superior wideband performance and requires that the
analog inputs be driven differentially. SNR and SINAD
performance will degrade significantly (~6dB) if the analog
input is driven with a single-ended signal. A wideband
transformer such as Minicircuits ADT1-1WT can be used to
provide the

AIN and

AIN

-12- 4/01/2002 REV. PrG

Single Ended Analog Input Range

PRELIMINARY TECHNICAL DATA

Digital Outputs

The off chip drivers on the chip can be configured by the
user to provide CMOS or LVDS compatible output levels
via pin S2.

The CMOS digital outputs (S2=0) are TTL/CMOS­compatible for lower power consumption. The outputs are
biased from a separate supply (VDD), allowing easy
interface to external logic. The outputs are CMOS devices
which will swing from ground to VDD (with no dc load). It
is recommended to minimize the capacitive load the ADC
drives by keeping the output traces short (<1 inch, for a total
C

< 5 pF). When operating in cmos mode it is also

LOAD

recommended to place low value (220 ohm) series damping
resistors on the data lines to reduce switching transient
effects on performance.

LVDS outputs are available when S2=VDD and a 3.7K
RSET resistor is placed at pin 7 ( LVDSBIAS) to ground .
This resistor sets the output current at each output equal to a
nominal 3.5mA ( 10* I
termination resistor placed at the lvds receiver inputs results
in a nominal 350mV voltage swing at the receiver. Note that
when operating in LVDS mode the output supply must be at
a dc potential greater than or equal to the analog supply level
(AVDD). This can be accomplished simply by biasing the
two supplies from the same power plane or by tying the two
supplies on the pcb through an inductor. When operating in
CMOS mode this is not required and separate supplies are
recommended.

Clock Outputs (DCO+, DCO-)

The input ENCODE is divided by two (in CMOS mode) and
available off-chip at DCO+ and DCO-. These clocks can
facilitate latching off-chip, providing a low skew clocking
solution (see timing diagram). The on-chip clock buffers
should not drive more than 5 pF of capacitance to limit
switching transient effects on performance.
Note that the Outputs clocks are CMOS levels when CMOS
mode is selected(S2=0) and are LVDS levels when in LVDS
mode(S2=VDD). (Requiring a 100ohm differential
termination at receiver in LVDS mode). The output clock in
LVDS mode switches at the encode rate.

) . A 100 ohm differential

RSET

AD9430

Voltage Reference

A stable and accurate 1.25 V voltage reference is built into
the AD9430 (VREF). The analog input Full Scale Range is
linearly proportional to the voltage at VREF. VREF (and in
turn input full scale ) can be varied by adding an external
resistor network at VREF, SENSE and GROUND. (See
figure X ) . No appreciable degradation in performance
occurs when VREF is adjusted ±5%. Note that an external
reference can be used by connecting the SENSE pin to VDD
(disabling internal reference) and driving VREF with the
external reference source. A .1uF capacitor to ground is
recommended at VREF pin in internal and external reference
applications.

Simplified Voltage Reference Equivalent Circuit

REV. PrG 4/01/2002 -13-

AD9430

PRELIMINARY TECHNICAL DATA

AD9430 EVALUATION BOARD

The AD9430 evaluation board offers an easy way to test the
AD9430. It requires a clock source, an analog input signal, and
a 3.3 V power supply. The clock source is buffered on the board
to provide the clocks for the ADC, an on-board DAC, latches,
and a data ready signal. The digital outputs and output clocks
are available at two 40-pin connectors, P3 and P4. The board
has several different modes of operation, and is shipped in the
following configuration:

• Offset Binary

• Internal Voltage Reference

• CMOS Parallel Timing

• Full-Scale Adjust = Low

Power Connector

Power is supplied to the board via a detachable 12-lead power
strip (three 4-pin blocks).

> 0.5 V p-p. Power to the EL16 is set at jumper E47. E47–E45
powers the buffer from AVDD, E47–E46 powers the buffer from
VCLK/V_XTAL.

Voltage Reference

The AD9430 has an internal 1.23 V voltage reference. The
ADC uses the internal reference as the default when jumpers
E24–E27 and E25–E26 are left open. The full scale can be
increased by placing optional resistor R3. The required value
would vary with process and needs to be tuned for the specific
application. Full scale can similarly be reduced by placing R4;
tuning would be required here as well. An external reference can
be used by shorting the SENSE pin to 3.3 V (place jumper
E26–E25). E27–E24 jumper connects the ADC VREF pin to
EXT_VREF pin at the power connector.

Data Format Select

Data Format Select sets the output data format of the ADC. Set­ting DFS (E1–E2) low sets the output format to be offset binary;
setting DFS high (E1–E3) sets the output to two’s complement.

Table II. Power Connector

AVDD 3.3 V Analog Supply for ADC (~ 350 mA)
DRVDD 3.3 V Output Supply for ADC (~ 28 mA)
VDL 3.3 V

Supply for Support Logic and DAC (~350 mA)

EXT_VREF* Optional External Reference Input
VCLK/V_XTAL Supply for Clock Buffer/Optional XTAL
VAMP Supply for Optional Amp

*LVEL16 clock buffer can be powered from AVDD or VCLK at E47 jumper

(AVDD, DrVDD,VDL are the minimum required power connections).

Analog Inputs

The evaluation board accepts a 1.3 V p-p analog input signal
centered at ground at SMB connector J4. This signal is terminated
to ground through 50 Ω by R16. The input can be alternatively
terminated at T1 transformer secondary by R13, R14. T1 is a
wideband RF transformer providing the single-ended to differential
conversion allowing the ADC to be driven differentially, minimizing

I/P

Output timing is set at E11–E13. E12–E11 sets S4 low for
parallel output timing mode. E11–E13 sets S4 high for interleaved
timing mode.

Timing Controls

Flexibility in latch clocking and output timing is accomplished
by allowing for clock inversion at the timing controls section of
the PCB. Each buffered clock is buffered by an XOR and can be
inverted by moving the appropriate jumper for that clock.

Data Outputs

The ADC digital outputs are latched on the board by four LVT574s;
the latch outputs are available at the two 40-pin connectors at pins
11–33 on P23 (channel A) and pins 11–33 on P3 (channel B).
The latch output clocks (data ready) are available at Pin 37 on
P23 (channel A) and Pin 37 on P3 (channel B). The data ready
clocks can be inverted at the timing controls section if needed.

even order harmonics. An optional second transformer T2 can be
placed following T1 if desired. This would provide some

perfor­mance advantage (~1–2 dB) for high analog input frequencies
(>100 MHz). If T2 is placed, two shorting traces at the pads would
need to be cut. The analog signal is low pass filtered by R41,
C12

, and R42, C13 at the ADC input.

Gain

Full scale is set at E17–E19, E17–E18 sets S5 low, full scale =

1.5 V differential; E17–E19 sets S5 high, full scale = 0.75 V
differential.

Encode

The encode clock is terminated to ground through 50 Ω at SMB
connector J5. The input is ac-coupled to a high-speed differential
receiver (LVEL16) which provides the required low-jitter, fast
edge rates needed for optimum performance. J5 input should be

⌬: 4.6nS
C1 FREQ

84.65608MHz

1

2

2.00V⍀ 2.00V⍀

CH1 CH2CH2 M 5.00nS

Figure 13. Data Output and Clock @ 80-Pin Connector

-14- 4/01/2002 REV. PrG

PRELIMINARY TECHNICAL DATA

AD9430

DAC Outputs

Each channel is reconstructed by an on-board dual-channel DAC,
an AD9753. This DAC is intended to assist in debug—it should
not be used to measure the performance of the ADC. It is a current
output DAC with on-board 50 Ω termination resistors.
figure

below is representative of the DAC output with a full-scale
input. The scope setting is low bandwidth.

analog

The

Optional Amplifier

The footprint for transformer T2 can be modified to accept a
wideband differential amplifier (AD8350) for low frequency
applications where gain is required. Note that Pin 2 would need
to be lifted and left floating for operation. Input transformer T1
would need to be modified to a 4:1 for impedance matching and
ADC input filtering would enhance performance (see AD8350
data sheet). SNR/SINAD Performance of 61 dB/60 dB is pos­sible

1

2.00mV⍀

CH1 CH1M 25.0nS

C1 FREQ

10.33592MHz

C1 PK-PK
448mV

248mV

Figure 14. DAC Output

Encode Xtal

An optional xtal oscillator can be placed on the board to serve
as a clock source for the PCB. Power to the xtal is through the
VCLK/VXTAL pin at the power connector. If an oscillator is used,
ensure proper termination for best results. The board has been
tested with a Valpey Fisher VF561 and a Vectron JN00158-163.84.
Test results for the VF561 are shown below.

and would start to degrade at about 30 MHz.

CUT TRACE

AD9430

1

CUT TRACE

Figure 16. Using the AD8350 on the AD9430 PCB

0

ENCODE 163.84MHz

–10

ANALOG 65.02MHz
SNR 63.93dB
SINAD 63.87dB

–20

FUND –0.45dBFS
2ND –85.62dBc

–30

3RD –91.31dBc
4TH –90.54dBc

–40

5TH –90.56dBc
6TH –91.12dBc

–50

THD –82.21dBc

dB

SFDR 83.93dBc

–60

SAMPLES 8k
NOISEFLR –100.44dBFS
WORSTSP –83.93dBc

–70

–80

–90

–100

08020

40 60

MHz

Figure 15. FFT—Using VF561 XTAL as Clock Source

REV. PrG 4/01/2002 -15-

PRELIMINARY TECHNICAL DATA

AD9430

Table III. Evaluation Board Bill of Materials

No. Qty. Reference Designator Device Package Value Comments

1 45 C1, C3–C11, C15–C17, Capacitor 0603 0.1 µF C43, C47

C19–C29, C31–C48, Not Placed

C58–C62
2 0 C2 Capacitor 0603 10 pF Not Placed
3 0 C12, C13 Capacitor 0603 20 pF Not Placed
4 1 C14 Capacitor 0603 0.01 µF
5 0 C18 Capacitor 0603 1 µF
6 7 C30, C49, C63–C67 Capacitor CAPL 10 µF C30 Not Placed
7 9 E3–E1–E2 3-Pin Header/Jumper

E19–E17–E18 3-Pin Header/Jumper

E13–E11–E12 3-Pin Header/Jumper

E26–E25–E27–E24 4-Pin Header

E46–E47–E45 3-Pin Header/Jumper

E35–E33–E34 3-Pin Header/Jumper

E32–E30–E31 3-Pin Header/Jumper

E29–E23–E28 3-Pin Header/Jumper

E22–E16–E21 3-Pin Header/Jumper
8 5 J1, J2, J3, J4, J5, J6 SMB SMB J1 Not Placed
9 2 P3, P23 40-Pin Header
10 3 P4, P21, P22 4-Pin Power Connector Post 25.531.3425.0 Wieland

Detachable
Connector 25.602.5453.0 Wieland

11 8 R1, R5, R13, R14, R16, Resistor 0603 50 Ω R1, R13, R14

Not Placed

R25, R27, R28, R41, R42
12 1 R2, R3, R4 Resistor 0603 3.9 kΩ R3, R4 Not Placed

13 8 R6–R8, R10, R15, Resistor 0603 100 Ω R15, R21–R24, R38

Not Placed

R21–R24, R33–R36, R38
14 5 R12, R30, R37 Resistor 0603 0 Ω
15 4 R17, R18, R19, R20 Resistor 0603 510 Ω
16 1 R26 Resistor 0603 2 kΩ
17 1 R29 Resistor 0603 390 Ω
18 7 R31, R32, R39, R40, R43, Resistor 0603 1 kΩ

R44, R45
19 4 RZ1, RZ2, RZ3, RZ4 Resistor Pack 220 Ω SO16RES 742C163221JTR CTS
20 8 RZ5, RZ6, RZ7, RZ8, RZ9, Resistor Pack 22 Ω SO16RES 742C163220JTR CTS

RZ10, RZ11, RZ12
21 1 T1, T2 Transformer CD542 Minicircuits T2 Not Placed

ADT1–1WT
22 1 U1 AD9430BSV TQFP100 ADC
23 1 U2 MC100LVEL16D SO8NB Clock Buffer
24 1 U3 74LCX86 SO14NB Xor/Buffer
25 4 U4, U5, U6, U7 74LVT574 SO20 Latch
26 1 U9 AD9753AST LQFP48 DAC

-16- 4/01/2002 REV. PrG

GND

DRA

GND

DX11

DX10

PRELIMINARY TECHNICAL DATA

AD9430

GND

DRB

GND

DY1 1

DY1 0

DY9

DY8

DY7

DY6

DY5

DY4

DY3

DY2

DY1

DY0

DYA

DYB

DRY

DX9

DX8

DX7

DX6

DX5

DX4

DX3

DX2

DX1

DX0

DXA

DXB

DRX

GND

GND

P39

P37

P35

P33

P31

P40

P38

P36

P34

P32

GND

DRX

DX11

DX10

16151413121110

R1R2R3R4R5R6R7

RZ8 22

1234567

VDL

201918171615141312

Q0Q1Q2Q3Q4Q5Q6

VCC

U4

OUT_END0D1D2D3D4D5D6D7

123456789

GND

16151413121110

R1R2R3R4R5R6R7

RZ1 220

1234567

CLKLATA

R33

100⍀

3

U3

74LCX86

74LCX86

1

2

4

R10

100⍀

COUTA

E35

E34

E33

VCC

GND

E7

E20VDL

DRVDD

GND

VAM P

GND

VCLK/V_XTAL

4

P4

123

P4

P1P2P3

PTMICA04

EXT_VREF

4

P21

123

P1P2P3

P29

P27

P25

P23

P30

P28

P26

P24

DX9

DX8

DM8

DM7

DRA

R34

100⍀

6

U3

5

R8

100⍀

COUTA

E32

E31

E30

VCC

GND

COUTA

R9

COUT

H4

MTHOLESH3MTHOLESH2MTHOLESH2MTHOLES

VDL

GND

DRVDD

123

P4

P1P2P3

PTMICA04

P21

P19

P17

P22

P20

P18

DX7

DX6

DM6

74LCX86

9

GND

AVDD (VCC)

4

P4

PTMICA04

P22

P15

P16

DX5

9

R8

8

DM5

Q7

9

R8

8

CLKLATB

8

U3

10

COUTAB

E29

VCC

COUTAB

R11

COUTB

P13

P14

R35

E23

P9P7P5P3P1

P11

P12

P10P8P6P4P2

RZ7 22

VDL

CLKLATA

11

201918171615141312

VCC

CLOCK

U5

LVT574

GND

OUT_END0D1D2D3D4D5D6D7

123456789

10

GND

GND

RZ2 220

DRB

R36

100⍀

11

U3

74LCX86

12

13

R7

100⍀

COUTAB

E28

E22

E16

VCC

GND

GND

P23

C4OMS

DX4

DX3

DX2

DX1

DX0

16151413121110

R1R2R3R4R5R6R7

1234567

Q0Q1Q2Q3Q4Q5Q6

16151413121110

R1R2R3R4R5R6R7

1234567

100⍀

PLB GND

GROUND PAD UNDER PART

R6

100⍀

E21

GND

DXA

DXB

9

R8

8

CLKLATA

11

Q7

CLOCK

LVT574

GND

10

GND

9

R8

8

DRVDD

GND

75747372717069686766656463626160595857565554535251

76
77
78
79
80
81

GND

82

DRVDD

83
84
85

GND

86

GND

87

VCC

88

VCC

89

VCC

90

GND

91

GND

92

GND

93

VCC

94

VCC

95

GND

96

GND

97

VCC

98

VCC

99

GND

100

123456789

GND

GND

GND

E13VCC

E18GND

E14

E12GNDE8E10VCC

E11

E19VCC

E17

Figure 17a. Evaluation Board Schematic

REV. PrG 4/01/2002 -17-

P39

P37

P35

P33

P31

P29

P40

P38

P36

P34

P32

P30

GND

DRY

DY1 1

DY1 0

16151413121110

R1R2R3R4R5R6R7

RZ6 22

1234567

VDL

201918171615141312

Q0Q1Q2Q3Q4Q5Q6

VCC

U6

OUT_END0D1D2D3D4D5D6D7

123456789

GND

16151413121110

R1R2R3R4R5R6R7

RZ3 220

1234567

GND

COUT

COUTB

DRVDD

GND

U1

AD9430

101112131415161718192021222324

VCC

VCC

VCC

GND

25⍀

E26VCC

1k⍀

E29

R3

E9GND

GND

GND

C1

E24EXT_VREF

E27

R4

R39

1k⍀

GND

E6VCC

0.1␮F

VCC

E4

E5GND

GND

GND

GND

R3, R4

OPTIONAL

E3VCC

E1

E2GND

VCC

R41

R39

C12

P27

P28

DY9

GND

20pF

P25

P23

P21

P26

P24

P22

DY8

DY7

DRVDD

GND

GND

GND

C43

0.1␮F

T2

T2

OPTIONAL

P19

P17

P20

P18

DY6

R8

R8

25

VCC

GND

R41

25⍀

426

153

ADT1-1WT

C3

0.1␮F

R14

29⍀

426

T1

153

ADT1-1WT

P15

P16

9

8

9

8

DY5

Q7

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

P13

P14

11

10

C11 0.1␮F

GND

GND

P9P7P5P3P1

P11

P12

P10P8P6P4P2

RZ5 22

VDL

CLKLATA

201918171615141312

VCC

CLOCK

U7

LVT574

OUT_END0D1D2D3D4D5D6D7

GND

123456789

GND

GND

RZ4 220

GND

DRVDD

GND

VCC

GND

GND

VCC

GND
GND

VCC

R5

50⍀

VCC
VCC

GND

GND

C13

20pF

GND

R42

25⍀

C47

PRI SEC

C2

10pF

R13

25⍀

C6

0.1␮F

PRI SEC

C6

R16

50⍀

0.1␮F

J4

P3

C4OMS

DY4

DY3

DY2

DY1

16151413121110

R1R2R3R4R5R6R7

1234567

Q0Q1Q2Q3Q4Q5Q6

16151413121110

R1R2R3R4R5R6R7

1234567

CLK–

CLK+

R1

50⍀

J2

GND

GND

J1

GND

C36

0.1␮F

DATA SYNC

U2

E45

E46

0.1␮F

E47

VCC

VCLK

R13, R14 OPTIONAL

E19

ANALOG

DY0

DYA

9

R8

8

9

R8

8

R1 NOT PLACED

7

8

VCC

DQ

234

MC100LVEL 16

C5

0.15␮F

J5

DYB

CLKLATB

11

Q7

CLOCK

GND

10

GND

E36

6

DNQNVBB

R27

50⍀

ENCODE

LVT574

00

R19

510⍀

R20

510⍀

R10

R17

VEE

510⍀

510⍀

GND

R12

C30

10␮F

+

GND

GND

C4

0.1␮F

VCC

GND

5

GND

C8

0.1␮F

AD9430

V

CC

+

C64
10␮F

C16

0.1␮F

C17

0.1␮F

PRELIMINARY TECHNICAL DATA

C24

C27

C26

C19

0.1␮F

C21

0.1␮F

C20

0.1␮F

C23

0.1␮F

C22

0.1␮F

C25

0.1␮F

0.1␮F

0.1␮F

0.1␮F

C29

0.1␮F

C28

0.1␮F

C31

0.1␮F

C32

0.1␮F

C35

0.1␮F

GND

VDL

GND

DRV

DD

GND

+

C67
10␮F

+

C65
10␮F

R38 FOR
VF561 CRYSTAL

C40

0.1U

C61

0.1␮F

100⍀

VOL

GND

R38

R31
1k⍀

R32
1k⍀

C62

0.1␮F

R15

100⍀

GND

GND

GND

C45

0.1U

DX11

DX10

DX9

DX8

DX7

DX6

DX5

DX4

DX3

DX2

DX1

DX0

DXA

DXB

C60

0.1␮F

C59

C58

0.1␮F

0.1␮F

1

E/D

2

NC

3

GND

OUTPUT B

U8

OPTIONAL XTAL

R43

1k⍀

GND

VOL

GND

DRA

C48

0.1U

RZ9

R1

16

1

R2

15

2

R3

14

3

R4

13

4

R5

12

5

R6

11

6

R7

10

7

R8

9

8

220

RZ11

R1

16

1

R2

15

2

R3

14

3

R4

13

4

R5

12

5

R6

11

6

R7

10

7

R8

9

8

220

V

OUTPUT

GND

CC

VCLK

GND

R37

GND

0⍀

6
5

4

C38
.1U

VOL

1

2

3

4

5

6

7

8

9

10

11

12

VCLK

C66
10␮F

VCLK

R30

0⍀

GND

J6

48

13

R21
100⍀

R22
100⍀

GND

C18

0.1U

47

E40

E37

C42

0.1␮F

C41

0.1␮F

VAM P

GND

OPIN B

GND

IN–

87 65

12 34

IN+

GND

OPIN

VOL

GND

GND

VOL

GND

GND

GND

ENBL

GND

GND

CC

V

VAM P

10

11

12

13

14

15

16

10

11

12

13

14

15

16

+

OPIN B

OUT–

OUT+

OPIN

RZ12

R8

9

R7

R6

R5

R4

R3

R2

R1

220

RZ10

R8

9

R7

R6

R5

R4

R3

R2

R1

220

U10

C49
10␮F

OPTIONAL AMPAD9430

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

C15

0.1␮F

C48

0.1␮F

DYB

DYA

DY0

DY1

DY2

DY3

DY4

DY5

DY6

DY7

DY8

DY9

DY1 0

DY1 1

C37

0.1␮F

C44

0.1␮F

C14

0.01␮F

P1

VCLK

R23
100⍀

R24
100⍀

GND

R25
50⍀

GND

J3

R28
50⍀

GND

GND
R29
392⍀

44

45

46

VREF

GND

P2

C34

VOL

0.1U

GND

R26

2k⍀

41

42

43

+

C63
10␮F

GND

C33

0.1U

39

40

E4Z

E41

R44

1k⍀

E39

E38

R45
1k⍀

37

38

36

35

34

33

32

31

AD9430

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

GND

C35

0.1U

VOL

GND

Figure 17b. Evaluation Board Schematic

-18- 4/01/2002 REV. PrG

PRELIMINARY TECHNICAL DATA

AD9430

Figure 18. PCB Top Side Silkscreen

Figure 19. PCB Top Side Copper

Figure 21. PCB Split Power Plane

Figure 22. PCB Bottom Side Copper

Figure 20. PCB Ground Layer

REV. PrG 4/01/2002 -19-

Figure 23. PCB Bottom Side Silkscreen

AD9430

PRELIMINARY TECHNICAL DATA

Troubleshooting

If the board does not seem to be working correctly, try the following:

•

Verify power at IC pins.

•

Check that all jumpers are in the correct position for the
desired mode of operation.

•

Verify VREF is at 1.23 V.

•

Try running Encode Clock and Analog Inputs at low speeds
(10 MSPS/1 MHz) and monitor 574, DAC, and ADC outputs
for toggling.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

100-Lead TQFP (with Exposed Heat Sink)

(TQFP-100)

0.030 (0.75)

0.024 (0.60)

0.018 (0.45)

SEATING

PLANE

0.047 (1.20)
MAX

1

0.630 (16.00) SQ

0.551 (14.00) SQ

76100

75

The AD9430 Evaluation Board is provided as a design example
for customers of Analog Devices, Inc. ADI makes no warranties,
express, statutory, or implied, regarding merchantability or
fitness for a particular purpose.

76 100

75

BOTTOM VIEW

1

TOP VIEW

(PINS DOWN)

CONDUCTIVE

25

26 49

0.006 (0.15)

0.002 (0.05)

0.0197 (0.50)
BSC

NOTE:
THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE
WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.

0.011 (0.27)

0.009 (0.22)

0.007 (0.17)

50

0.041 (1.05)

0.039 (1.00)

0.037 (0.95)

7ⴗ
0ⴗ

50

CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
CENTER FIGURES ARE TYPICAL UNLESS
OTHERWISE NOTED.

HEAT SINK

0.260 (6.00) NOM

25

2649

-20- 4/01/2002 REV. PrG