Analog Devices AD9430 Service Manual
12-Bit, 170/210 MSPS
FEATURES
SNR = 65 dB @ fIN = 70 MHz @ 210 MSPS
ENOB of 10.6 @ f
SFDR = 80 dBc @ f
Excellent linearity:
DNL = ±0.3 LSB (typical)
INL = ±0.5 LSB (typical)
2 output data options:
Demultiplexed 3.3 V CMOS outputs each @ 105 MSPS
Interleaved or parallel data output option
LVDS at 210 MSPS
700 MHz full-power analog bandwidth
On-chip reference and track-and-hold
Power dissipation = 1.3 W typical @ 210 MSPS
1.5 V input voltage range
3.3 V supply operation
Output data format option
Data sync input and data clock output provided
Clock duty cycle stabilizer
GENERAL DESCRIPTION
The AD9430 is a 12-bit, monolithic, sampling analog-to-digital
converter (ADC) optimized for high performance, low power,
and ease of use. The product operates up to a 210 MSPS
conversion rate and is optimized for outstanding dynamic
performance in wideband carrier and broadband systems. All
necessary functions, including a track-and-hold (T/H) and
reference, are included on the chip to provide a complete
conversion solution.
The ADC requires a 3.3 V power supply and a differential
ENCODE clock for full performance operation. The digital
outputs are TTL/CMOS or LVDS compatible and support either
twos complement or offset binary format. Separate output
power supply pins support interfacing with 3.3 V or 2.5 V
CMOS logic.
Two output buses support demultiplexed data up to 105 MSPS
rates in CMOS mode. A data sync input is supported for proper
output data port alignment in CMOS mode, and a data clock
output is available for proper output data timing. In LVDS
mode, the chip provides data at the ENCODE clock rate.
Fabricated on an advanced BiCMOS process, the AD9430 is
available in a 100-lead, surface-mount plastic package
(100 e-PAD TQFP) specified over the industrial temperature
range (–40°C to +85°C).
= 70 MHz @ 210 MSPS (–0.5 dBFS)
IN
= 70 MHz @ 210 MSPS (–0.5 dBFS)
IN
3.3 V A/D Converter
AD9430
FUNCTIONAL BLOCK DIAGRAM
DRGND
12
OR LVDS
S5S4S2S1
DRVDD
LVDS
OUTPUTS
CMOS
OUTPUTS
AVDD
DATA,
OVERRANGE
IN LVDS OR
2-PORT CMOS
DCO+
DCO–
VIN+
VIN–
DS+
DS–
CLK+
CLK–
AD9430
TRACK-
AND-HOLD
CLOCK
MANAGEMENT
SENSE VREF
SCALABLE
REFERENCE
ADC
12-BIT
PIPELINE
CORE
AGND
SELECT CMOS
Figure 1.
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
PRODUCT HIGHLIGHTS
1. High performance.
Maintains 65 dB SNR @ 210 MSPS with a 65 MHz input.
2. Low power.
Consumes only 1.3 W @ 210 MSPS.
3. Ease of use.
LVDS output data and output clock signal allow interface
to current FPGA technology. The on-chip reference and
sample-and-hold provide flexibility in system design. Use
of a single 3.3 V supply simplifies system power supply
design.
4. Out of range (OR) feature.
The OR output bit indicates when the input signal is
beyond the selected input range.
5. Pin compatible with 10-bit AD9411 (LVDS only).
.
02607-001
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
AD9430
TABLE OF CONTENTS
DC Specifications ............................................................................. 4
AC Specifications.............................................................................. 6
Digital Specifications........................................................................ 7
Switching Specifications .................................................................. 8
Timing Diagrams.............................................................................. 9
Absolute Maximum Ratings.......................................................... 10
Explanation of Test Levels......................................................... 10
ESD Caution................................................................................ 10
Pin Configurations and Function Descriptions .........................11
Equivalent Circuits......................................................................... 15
Typical Performance Characteristics ........................................... 16
Te r mi n ol o g y .................................................................................... 23
Application Notes ........................................................................... 25
Theory of Operation ..................................................................25
Encode Input............................................................................... 25
Analog Inputs ............................................................................. 28
Gain.............................................................................................. 28
ENCODE..................................................................................... 28
Volt a ge R e fe r e nc e ....................................................................... 28
Data Format Select..................................................................... 28
I/P Timing Select........................................................................ 28
Timing Controls ......................................................................... 28
CMOS Data Outputs.................................................................. 29
Crystal Oscillator........................................................................ 29
Optional Amplifier..................................................................... 29
Troubleshooting.......................................................................... 30
Evaluation Board, LVDS Mode .................................................... 36
Power Connector........................................................................ 36
Analog Inputs ............................................................................. 36
Gain.............................................................................................. 36
Analog Input ............................................................................... 26
DS Inputs (DS+, DS–)................................................................ 26
CMOS Outputs........................................................................... 26
LVDS Output s .............................................................................27
Volt a ge R e fe r e nc e ....................................................................... 27
Noise Power Ratio Testing (NPR)............................................ 27
Evaluation Board, CMOS Mode ...................................................28
Power Connector........................................................................ 28
Clock ............................................................................................ 36
Volt a ge R e fe r e nc e ....................................................................... 36
Data Format Select..................................................................... 36
Data Outputs............................................................................... 36
Crystal Oscillator........................................................................ 36
Outline Dimensions ....................................................................... 42
Ordering Guide .......................................................................... 42
Rev. D | Page 2 of 44
AD9430
REVISION HISTORY
8/05—Rev. C to Rev. D
Change to I
Spec Units...............................................................4
VREF
Changes to Minimum ENOB Specification...................................6
Added Footnote for Pin 33 in LVDS Mode ...................................7
Change to LVDS Output Section ..................................................27
Added New Evaluation Board, CMOS Mode Section................32
Updated Outline Dimensions........................................................42
11/04—Rev. B to Rev. C
Changes to Specifications ................................................................4
Changes to Figure 60 .................................................................... 31
Changes to LVDS PCB BOM ....................................................... 35
Changes to Figure 68 (Evaluation Board—LVDS Mode) ......... 36
Updated Outline Dimensions ...................................................... 40
7/03—Rev. A to Rev. B
Changed order of Figure 1 and Figure 2 ...................................... 5
Updated TPC 13 .............................................................................14
Changes to LVDS OUTPUTS section..........................................20
Add New AD9430 EVALUATION BOARD, LVDS MODE
Section ......................................................................................... 27
Updated OUTLINE DIMENSIONS ........................................... 32
3/03—Rev. 0 to Rev. A
Upgraded for AD9430-210 .............................................. Universal
Changes to FEATURES ................................................................. 1
Changes to PRODUCT HIGHLIGHTS ...................................... 1
Changes to SPECIFICATIONS ..................................................... 2
Changes to Figure 2 ........................................................................ 5
Changes to ORDERING GUIDE .................................................. 6
Change to PIN FUNCTION DESCRIPTIONS .......................... 7
Edits to Output Propagation Delay section. .............................. 10
Added TPCs 5–8, 10–12, 14, 16, 18, 20, 22, 27, 31–32, 34 ...... 12
Changes to TPCs............................................. 17, 19, 26, 35–36, 38
Added text to ENCODE INPUT section ................................... 18
Added DS INPUTS section ..........................................................19
Change to Table I ..........................................................................19
Changes to LVDS Outputs section.............................................. 20
Changes to Voltage Reference section .........................................20
Replaced Figure 12......................................................................... 20
Change to Troubleshooting section .............................................22
Updated OUTLINE DIMENSIONS.............................................27
5/02—Revision 0: Initial Version
Rev. D | Page 3 of 44
AD9430
DC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, T
unless otherwise noted.
Table 1.
AD9430-170 AD9430-210
Parameter
RESOLUTION 12 Bits
ACCURACY
No Missing Codes Full VI Guaranteed Guaranteed
Offset Error 25°C I –3 +3 –3 +3 mV
Gain Error 25°C I –5 +5 –5 +5 % FS
Differential Nonlinearity (DNL) 25°C I –1 ± 0.3 +1 –1 ± 0.3 +1 LSB
Full VI –1 ± 0.3 +1.5 –1 ± 0.3 +1.5 LSB
Integral Nonlinearity (INL) 25°C I –1.5 ± 0.5 +1.5 –1.75 ± 0.3 +1.75 LSB
Full VI –2.25 ± 0.5 +2.25 –2.5 ± 0.3 +2.5 LSB
TEMPERATURE DRIFT
Offset Error Full V 58 58 μV/°C
Gain Error Full V 0.02 0.02 %/°C
Reference Out (VREF) Full V +0.12/–0.24 +0.12/–0.24 mV/°C
REFERENCE
Reference Out (VREF) 25°C I 1.15 1.235 1.3 1.15 1.235 1.3 V
Output Current
I
Input Current2 25°C I 20 20 μA
VREF
I
Input Current
SENSE
1
2
ANALOG INPUTS (VIN+, VIN–)3
Differential Input Voltage Range
(S5 = GND)
Differential Input Voltage Range
(S5 = AVDD)
Input Common-Mode Voltage Full VI 2.65 2.8 2.9 2.65 2.8 2.9 V
Input Resistance Full VI 2.2 3 3.8 2.2 3 3.8 kΩ
Input Capacitance 25°C V 5 5 pF
POWER SUPPLY (LVDS Mode)
AVDD Full IV 3.1 3.3 3.6 3.2 3.3 3.6 V
DRVDD Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V
Supply Currents
I
(AVDD = 3.3 V)
ANALOG
I
(DRVDD = 3.3 V)4 Full VI 55 62 55 62 mA
DIGITAL
4
Power Dissipation4 Full VI 1.29 1.43 1.5 1.7 W
Power Supply Rejection 25°C V –7.5 –7.5 mV/V
= –40°C, T
MIN
Temp
= +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, LVDS output mode,
MAX
Te st
Level Min Typ
Max
Min Typ
Max Unit
25°C IV 3.0 3.0 mA
25°C I 1.6 5.0 1.6 5.0 mA
Full V 1.536 1.536 V
Full V 0.766 0.766 V
Full VI 335 372 390 450 mA
Rev. D | Page 4 of 44
AD9430
AD9430-170 AD9430-210
Parameter
POWER SUPPLY (CMOS Mode)
AVDD Full IV 3.1 3.3 3.6 3.2 3.3 3.6 V
DRVDD Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V
Supply Currents
I
(AVDD = 3.3 V)
AVDD
I
(DRVDD = 3.3 V)5 Full IV 24 30 30 30 mA
DRVDD
Power Dissipation
5
5
Power Supply Rejection 25°C V –7.5 –7.5 mV/V
1
Internal reference mode; SENSE = Floats.
2
External reference mode; SENSE = DRVDD, VREF driven by external 1.23 V reference.
3
S5 (Pin 1) = GND. See the Analog Input section. S5 = GND in all dc and ac tests, unless otherwise noted.
4
I
and I
AVDD
Characteristics and Application Notes sections for I
5
I
AVDD
Characteristics and Application Notes sections for I
are measured with an analog input of 10.3 MHz, –0.5 dBFS, sine wave, rated ENCODE rate, and in LVDS output mode. See Typical Performance
DRVDD
and I
are measured with an analog input of 10.3 MHz, –0.5 dBFS, sine wave, rated ENCODE rate, and in CMOS output mode. See Typical Performance
DRVDD
Temp
Te st
Level Min Typ
Max Min Typ
Max Unit
Full IV 335 372 390 450 mA
Full IV 1.1 1.3 W
. Power consumption is measured with a dc input at rated ENCODE rate in LVDS output mode.
DRVDD
. Power consumption is measured with a dc input at rated ENCODE rate in CMOS output mode.
DRVDD
Rev. D | Page 5 of 44
AD9430
AC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, T
unless otherwise noted.
1
Table 2.
AD9430-170 AD9430-210
Parameter Temp Test Level Min Typ Max Min Typ Max Unit
SNR
Analog Input @ –0.5 dBFS 10 MHz 25°C I 63.5 65 62.5 64.5 dB
70 MHz 25°C I 63 65 62.5 64.5 dB
100 MHz 25°C V 65 64.5 dB
240 MHz 25°C V 61 61 dB
SINAD
Analog Input @ –0.5 dBFS 10 MHz 25°C I 63.5 65 62.5 64.5 dB
70 MHz 25°C I 63 65 62.5 64.5 dB
100 MHz 25°C V 65 64.5 dB
240 MHz 25°C V 60 60 dB
EFFECTIVE NUMBER OF BITS (ENOB)
10 MHz 25°C I 10.3 10.6 10.2 10.5 Bits
70 MHz 25°C I 10.3 10.6 10.2 10.5 Bits
100 MHz 25°C V 10.6 10.5 Bits
240 MHz 25°C V 9.8 9.8 Bits
WORST HARMONIC (2nd or 3rd)
Analog Input @ –0.5 dBFS, 10 MHz 10 MHz 25°C I –85 –75 –84 –74 dBc
70 MHz 25°C I –85 –75 –84 –74 dBc
100 MHz 25°C V –77 –77 dBc
240 MHz 25°C V –63 –63 dBc
WORST HARMONIC (4th or Higher)
Analog Input @ –0.5 dBFS, 10 MHz 10 MHz 25°C I –87 –78 –87 –77 dBc
70 MHz 25°C I –87 –78 –87 –77 dBc
100 MHz 25°C V –77 –77 dBc
240 MHz 25°C V –63 –63 dBc
TWO-TONE IMD
2
F1, F2 @ −7 dBFS 25°C V –75 –75 dBc
ANALOG INPUT BANDWIDTH 25°C V 700 700 MHz
1
All ac specifications tested by differentially driving CLK+ and CLK−.
2
F1 = 28.3 MHz, F2 = 29.3 MHz.
= –40°C, T
MIN
= +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, LVDS output mode,
MAX
Rev. D | Page 6 of 44
AD9430
DIGITAL SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, T
Table 3.
Test AD9430-170 AD9430-210
Parameter Temp Level Min Typ Max Min Typ Max Unit
ENCODE AND DS INPUTS
(CLK+, CLK–, DS+, DS–)1
Differential Input Voltage2 Full IV 0.2 0.2 V
Common-Mode Voltage3 Full VI 1.375 1.5 1.575 1.375 1.5 1.575 V
Input Resistance Full VI 3.2 5.5 6.5 3.2 5.5 6.5 kΩ
Input Capacitance 25°C V 4 4 pF
LOGIC INPUTS (S1, S2, S4, S5)
Logic 1 Voltage Full IV 2.0 2.0 V
Logic 0 Voltage Full IV 0.8 0.8 V
Logic 1 Input Current Full VI 190 190 μA
Logic 0 Input Current Full VI 10 10 μA
Input Resistance 25°C V 30 30 kΩ
Input Capacitance 25°C V 4 4 pF
LOGIC OUTPUTS (CMOS Mode)
Logic 1 Voltage4 Full IV DRVDD DRVDD V
–0.05 –0.05
Logic 0 Voltage4 Full IV 0.05 0.05 V
LOGIC OUTPUTS (LVDS Mode)
4, 5
VOD Differential Output Voltage Full VI 247 454 247 454 mV
VOS Output Offset Voltage Full VI 1.125 1.375 1.125 1.375 V
Output Coding Twos complement or binary Twos complement or binary
1
ENCODE (Clock) and DS inputs identical on the chip. See the Equivalent Circuits section.
2
All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 200 mV.
3
ENCODE (Clock) inputs’ common-mode can be externally set, such that 0.9 V < (CLK+ or CLK−) < 2.6 V.
4
Digital output logic levels: DRVDD = 3.3 V, C
5
LVDS R
= 100 Ω, LVDS output current set resistor (R
TERM
= –40°C, T
MIN
= +85°C, unless otherwise noted.
MAX
= 5 pF.
LOAD
) = 3.74 kΩ (1% tolerance).
SET
Rev. D | Page 7 of 44
AD9430
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, T
Table 4.
Test AD9430-170 AD9430-210
Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Unit
Maximum Conversion Rate1 Full VI 170
Minimum Conversion Rate
CLK+ Pulse Width High (tEH)
CLK+ Pulse Width Low (tEL)
DS Input Setup Time (t
DS Input Hold Time (t
1
1
Full IV 2
1
Full IV 2
)2 Full IV –0.5 –0.5 ns
SDS
)2 Full IV 1.75 1.75 ns
HDS
OUTPUT (CMOS Mode)
Valid Time (tV) Full IV 2 2 ns
Propagation Delay (tPD) Full IV 3.8 5 3.8 5 ns
Rise Time (tR) (20% to 80%) 25°C V 1 1 ns
Fall Time (tF) (20% to 80%) 25°C V 1 1 ns
DCO Propagation Delay (t
Data to DCO Skew (tPD to t
CPD
CPD
Interleaved Mode (A, B Latency) Full IV 14, 14 14, 14 Cycles
Parallel Mode (A, B Latency) Full IV 15, 14 15, 14 Cycles
OUTPUT (LVDS Mode)
Valid Time (tV) Full VI 2.0 2.0 ns
Propagation Delay (tPD) Full VI 3.2 4.3 3.2 4.3 ns
Rise Time (tR) (20% to 80%) 25°C V 0.5 0.5 ns
Fall Time (tF) (20% to 80%) 25°C V 0.5 0.5 ns
DCO Propagation Delay (t
Data to DCO Skew (tPD – t
CPD
CPD
Latency Full IV 14 14 Cycles
APERTURE DELAY (tA) 25°C V 1.2 1.2 ns
APERTURE UNCERTAINTY (Jitter, tJ) 25°C V 0.25 0.25 ps rms
OUT OF RANGE RECOVERY TIME (CMOS and LVDS) 25°C V 1 1 Cycles
1
All ac specifications tested by differentially driving CLK+ and CLK−.
2
DS inputs used in CMOS mode only.
= –40°C, T
MIN
= +85°C, unless otherwise noted.
MAX
Full V
40
12.5 2
12.5 2
210
MSPS
40 MSPS
12.5 ns
12.5 ns
) Full IV 3.8 5 3.8 5 ns
) Full IV –0.5 0 +0.5 –0.5 0 +0.5 ns
) Full VI 1.8 2.7 3.8 1.8 2.7 3.8 ns
) Full IV 0.2 0.5 0.8 0.2 0.5 0.8 ns
Rev. D | Page 8 of 44
AD9430
–
TIMING DIAGRAMS
CLK+
CLK–
DS+
DS–
PORT A
DA11–DA0
PORT B
DB11–DB0
PORT A
DA11–DA0
PORT B
DB11–DB0
DCO–
DCO+
t
HDS
INTERLEAVED DATA OUT
STATIC
STATIC
PARALLEL DATA OUT
STATIC
STATIC
STATIC
t
SDS
14 CYCLES
INVALID
INVALID
INVALID
INVALID
Figure 2. CMOS Timing Diagram
INVALID
INVALID
INVALID
t
PD
N N+2
N+1
N N+2
N+1 N+3
t
CPD
N+3
t
V
02607-002
1
N
A
IN
N
N+1
t
EL
t
EH
CLK+
CLK–
DATA OUT
DCO+
DCO–
t
CPD
1/f
S
t
PD
N–14
N–13
14 CYCLES
Figure 3. LVDS Timing Diagram
N
N+1
02607-003
Rev. D | Page 9 of 44
AD9430
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
AVDD, DRVDD 4 V
Analog Inputs –0.5 V to AVDD + 0.5 V
Digital Inputs –0.5 V to DRVDD + 0.5 V
REFIN Inputs –0.5 V to AVDD + 0.5 V
Digital Output Current 20 mA
Operating Temperature –55°C to +125°C
Storage Temperature –65°C to +150°C
Maximum Junction Temperature 150°C
Maximum Case Temperature 150°C
1
θ
JA
1
Typical θJA = 32°C/W (heat slug not soldered); typical θJA = 25°C/W (heat slug
soldered) for multilayer board in still air with solid ground plane.
25°C/W, 32°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational section
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
Table 6.
Level Description
I 100% production tested.
II
III Sample tested only.
IV
V Parameter is a typical value only.
VI
100% production tested at 25°C and sample tested at
specified temperatures.
Parameter is guaranteed by design and
characterization testing.
100% production tested at 25°C; guaranteed by
design and characterization testing for industrial
temperature range; 100% production tested at
temperature extremes for military devices.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 10 of 44
AD9430
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DRVDD
DRGND
DA10
81
82
4445464748
DB1
DB0
DNC
DA979DA878DA777DA676DA5
80
50
49
DB2
DB3
DB4
DRVDD
DRGND
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DRVDD
DRGND
DA4
DA3
DA2
DA1
DA0
DNC
DRGND
DNC
DNC
DCO+
DCO–
DRVDD
DRGND
OR_B
DB11
DB10
DB9
DB8
DB7
DRVDD
DRGND
DB6
DB5
02607-004
DNC
AGND
DNC
AVDD
AGND
SENSE
VREF
AGND
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
VIN+
VIN–
AGND
AVDD
AGND
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
AGND
AGND
AVDD
AVDD
AVDD
AGND
AGND
OR_A
DA11
99989796959493
100
S5
1
2
S4
3
4
S2
5
S1
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2627282930
AVDD
AVDD
AVDD
AGND
AGND
31
AGND
929190
89
88
8786858483
AD9430
CMOS PI NO UT
TOP VIEW
(Not to S cale)
33
32
343536
DS+
DS–
AVDD
AGND
CLK+
39
37
40
38
414243
AVDD
AVDD
DNC
AGND
CLK–
AGND
Figure 4. CMOS Dual-Mode Pin Configuration
Table 7. CMOS Mode Pin Function Descriptions
Pin Number Mnemonic Description
1 S5
Full-Scale Adjust Pin. AVDD sets f
GND sets f
= 1.536 V p-p differential.
S
= 0.768 V p-p differential,
S
2, 7, 42, 43, 65, 66, 68 DNC Do Not Connect.
3 S4 Interleaved, Parallel Select Pin. High = interleaved.
1
Analog Ground.
4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86,
AGND
87, 91, 92, 93, 96, 97, 100
5 S2 Output Mode Select. Low = dual-port CMOS, high = LVDS.
6 S1
Data Format Select. Low = binary, high = twos complement for
both CMOS and LVDS modes.
8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40, 88, 89, 90, 94,
AVDD 3.3 V Analog Supply.
95, 98, 99
10 SENSE Reference Mode Select Pin. Float for internal reference operation.
11 VREF 1.235 V Reference I/O—Function Dependent on SENSE.
21 VIN+ Analog Input—True.
22 VIN– Analog Input—Complement.
32 DS+ Data Sync (Input)—True. Tie low if not used.
33 DS–2 Data Sync (Input)—Complement. Tie high if not used.
36 CLK+ Clock Input—True.
37 CLK– Clock Input—Complement.
44 DB0 B Port Output Data Bit (LSB).
45 DB1 B Port Output Data Bit.
Rev. D | Page 11 of 44
AD9430
Pin Number Mnemonic Description
46 DB2 B Port Output Data Bit.
47, 54, 62, 75, 83 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).
48, 53, 61, 67, 74, 82 DRGND1 Digital Output Ground.
49 DB3 B Port Output Data Bit.
50 DB4 B Port Output Data Bit.
51 DB5 B Port Output Data Bit.
52 DB6 B Port Output Data Bit.
55 DB7 B Port Output Data Bit.
56 DB8 B Port Output Data Bit.
57 DB9 B Port Output Data Bit.
58 DB10 B Port Output Data Bit.
59 DB11 B Port Output Data Bit (MSB).
60 OR_B B Port Overrange.
63 DCO– Data Clock Output—Complement.
64 DCO+ Data Clock Output—True.
69 DA0 A Port Output Data Bit (LSB).
70 DA1 A Port Output Data Bit.
71 DA2 A Port Output Data Bit.
72 DA3 A Port Output Data Bit.
73 DA4 A Port Output Data Bit.
76 DA5 A Port Output Data Bit.
77 DA6 A Port Output Data Bit.
78 DA7 A Port Output Data Bit.
79 DA8 A Port Output Data Bit.
80 DA9 A Port Output Data Bit.
81 DA10 A Port Output Data Bit.
84 DA11 A Port Output Data Bit (MSB).
85 OR_A A Port Overrange.
1
AGND and DRGND should be tied together to a common ground plane.
2
DS Complement (DS−); can be tied to AVDD (as recommended) or left floating with no ill effects.
Rev. D | Page 12 of 44
AD9430
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
AGND
AGND
AVDD
AVDD
AVDD
AGND
AGND
OR+
OR–
DRVDD
DRGND
D11+
D11–79D10+78D10–77D9+76D9–
DNC
DNC
81
82
80
4445464748
DNC
DNC
DNC
DRVDD
49
D0–
DRGND
75
DRVDD
74
DRGND
73
D8+
72
D8–
71
D7+
70
D7–
69
D6+
68
D6–
67
DRGND
66
D5+
65
D5–
64
DCO+
63
DCO–
62
DRVDD
61
DRGND
60
D4+
59
D4–
58
D3+
57
D3–
56
D2+
D2–
55
54
DRVDD
53
DRGND
52
D1+
51
D1–
50
D0+
02607-005
DNC
AGND
LVDSBIAS
AVDD
AGND
SENSE
VREF
AGND
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
VIN+
VIN–
AGND
AVDD
AGND
99989796959493
100
S5
1
2
3
S4
4
5
S2
S1
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2627282930
AVDD
AVDD
AVDD
AGND
AGND
31
32
GND
AGND
929190
33
343536
AVDD
AVDD
89
AD9430
LVDS PINOUT
TOP VIEW
(Not to Scale)
37
CLK–
CLK+
AGND
8786858483
88
39
40
38
AVDD
AVDD
AGND
414243
AGND
Figure 5. LVDS Mode Pin Configuration
Table 8. LVDS Mode Pin Function Descriptions
Pin Number Mnemonic Description
1 S5 Full-Scale Adjust Pin. AVDD sets fS = 0.768 V p-p differential,
GND sets fS = 1.536 V p-p differential.
2, 42 to 46 DNC Do Not Connect.
3 S4
Control Pin for CMOS Mode. Tie low when operating in LVDS
mode.
1
Analog Ground.
4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86, 87, 91,
AGND
92, 93, 96, 97, 100
5 S2 Output Mode Select. GND = dual-port CMOS; AVDD = LVDS.
6 S1
7 LVDSBIAS
Data Format Select. GND = binary, AVDD = twos complement.
Set Pin for LVDS Output Current. Place 3.74 kW resistor
terminated to ground.
8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34, 39, 40, 88, 89, 90, 94, 95,
98, 99
10 SENSE
AVD D2 3.3 V Analog Supply.
Reference Mode Select Pin. Float for internal reference
operation.
11 VREF 1.235 V Reference I/O—Function Dependent on SENSE.
21 VIN+ Analog Input—True.
22 VIN– Analog Input—Complement.
32 GND Data Sync (Input)—Not Used in LVDS Mode. Tie to GND.
36 CLK+ Clock Input—True (LVPECL Levels).
37 CLK– Clock Input—Complement (LVPECL Levels).
Rev. D | Page 13 of 44
AD9430
Pin Number Mnemonic Description
47, 54, 62, 75, 83 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).
48, 53, 61, 67, 74, 82 DRGND1 Digital Output Ground.
49 D0– D0 Complement Output Bit (LSB).
50 D0+ D0 True Output Bit (LSB).
51 D1– D1 Complement Output Bit.
52 D1+ D1 True Output Bit.
55 D2– D2 Complement Output Bit.
56 D2+ D2 True Output Bit.
57 D3– D3 Complement Output Bit.
58 D3+ D3 True Output Bit.
59 D4– D4 Complement Output Bit.
60 D4+ D4 True Output Bit.
63 DCO– Data Clock Output—Complement.
64 DCO+ Data Clock Output—True.
65 D5– D5 Complement Output Bit.
66 D5+ D5 True Output Bit.
68 D6– D6 Complement Output Bit.
69 D6+ D6 True Output Bit.
70 D7– D7 Complement Output Bit.
71 D7+ D7 True Output Bit.
72 D8– D8 Complement Output Bit.
73 D8+ D8 True Output Bit.
76 D9– D9 Complement Output Bit.
77 D9+ D9 True Output Bit.
78 D10– D10 Complement Output Bit.
79 D10+ D10 True Output Bit.
80 D11– D11 Complement Output Bit.
81 D11+ D11 True Output Bit.
84 OR– Overrange Complement Output Bit.
85 OR+ Overrange True Output Bit.
1
AGND and DRGND should be tied together to a common ground plane.
2
Pin 33 can be tied to AVDD (as recommended) or left floating with no ill effects
Rev. D | Page 14 of 44
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