10-Bit, 170/200 MSPS
FEATURES
SNR = 60 dB @ fIN up to 70 MHz @ 200 MSPS
ENOB of 9.8 @ f
SFDR = 80 dBc @ f
Excellent linearity:
DNL = ±0.15 LSB (typical)
INL = ±0.25 LSB (typical)
LVDS output levels
700 MHz full-power analog bandwidth
On-chip reference and track-and-hold
Power dissipation = 1.25 W typical @ 200 MSPS
1.5 V input voltage range
3.3 V supply operation
Output data format option
Clock duty cycle stabilizer
Pin compatible to LVDS mode AD9430
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
up to 70 MHz @ 200 MSPS (–0.5 dBFS)
IN
up to 70 MHz @ 200 MSPS (–0.5 dBFS)
IN
VIN+
VIN–
CLK+
CLK–
3.3 V A/D Converter
FUNCTIONAL BLOCK DIAGRAM
SENSE VREF
SCALABLE
REFERENCE
TRACK
AND
HOLD
CLOCK
MANAGEMENT
S1 S5
AGND DRGND DRVDD AVDD
AD9411
ADC
10
10-BIT
PIPELINE
CORE
Figure 1.
LVDS TIMING
/
LVDS
OUTPUTS
AD9411
DATA,
OVERRANGE
IN LVDS
DCO+
DCO–
04530-0-001
GENERAL DESCRIPTION
The AD9411 is a 10-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates up to a 200 MSPS conversion rate
and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary
functions, including track-and-hold (T/H) and reference, are
included on the chip to provide a complete conversion solution.
The ADC requires a 3.3 V power supply and a differential
sample clock for full performance operation. The digital outputs
are LVDS compatible and support both twos complement and
offset binary format. A data clock output is available to ease
data capture.
Fabricated on an advanced BiCMOS process, the AD9411 is
available in a 100-lead surface-mount plastic package (e-PAD
TQFP-100) specified over the industrial temperature range
(–40°C to +85°C).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
PRODUCT HIGHLIGHTS
1. High performance.
Maintains 60 dB SNR @ 200 MSPS with a 70 MHz input.
2. Low power.
Consumes only 1.25 W @ 200 MSPS.
3. Ease of use.
LVDS output data and output clock signal allow interface
to current FPGA technology. The on-chip reference and
sample-and-hold function provide flexibility in system
design. Use of a single 3.3 V supply simplifies system
power supply design.
4. Out-of-range (OR).
The OR output bit indicates when the input signal is
beyond the selected input range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
AD9411
TABLE OF CONTENTS
DC Specifications ............................................................................. 3
Clock Outputs (DCO+, DCO–)............................................... 19
AC Specifications.............................................................................. 4
Digital Specifications........................................................................ 5
Switching Specifications .................................................................. 6
Explanation of Test Levels........................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Te r mi n ol o g y .................................................................................... 10
Equivalent Circuits......................................................................... 12
Typical Performance Characteristics........................................... 13
Application Notes ........................................................................... 18
Clock Input.................................................................................. 18
Analog Input ............................................................................... 18
LVDS Output s ............................................................................. 19
Volt a ge R e fe r e nc e ....................................................................... 19
Noise Power Ratio Testing (NPR)............................................ 19
Evaluation Board ............................................................................ 21
Power Connector ........................................................................ 21
Analog Inputs ............................................................................. 21
Gain.............................................................................................. 21
Clock ............................................................................................ 21
Volt a ge R e fe r e nc e ....................................................................... 21
Data Format Select..................................................................... 21
Data Outputs............................................................................... 21
Clock XTAL................................................................................. 21
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
7/04—Data Sheet Changed from Rev. 0 to Rev. A
Added 200 MSPS Grade ....................................................Universal
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide.......................................................... 27
Rev 0 : Initial Version
Rev. A | Page 2 of 28
AD9411
DC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, T
otherwise noted.
Table 1.
Parameter Temp
RESOLUTION 12 12 Bits
ACCURACY
No Missing Codes Full VI Guaranteed Guaranteed
Offset Error 25°C I –3 +3 –3 +3 mV
Gain Error 25°C I –5 +5 –5 +5 % FS
Differential Nonlinearity (DNL) 25°C I –0.5 ± 0.15 +0.5 –0.5 ± 0.15 +0.5 LSB
Full VI –0.6 ± 0.25 +0.6 –0.6 ± 0.25 +0.6 LSB
Integral Nonlinearity (INL) 25°C I –0.8 ± 0.5 +0.8 –0.8 ± 0.5 +0.8 LSB
Full VI –1 ± 0.5 +1 –1 ± 0.5 +1 LSB
TEMPERATURE DRIFT
Offset Error Full V 58 58 µV/°C
Gain Error Full V 0.02 0.02 %/°C
Reference Out (VREF) Full V
REFERENCE
Reference Out (VREF) 25°C I 1.15 1.235 1.3 1.15 1.235 1.3 V
Output Current
I
Input Current2 25°C I 20 20 mA
VREF
I
Input Current2 25°C I 1.6 5.0 1.6 5.0 mA
SENSE
1
ANALOG INPUTS (VIN+, VIN–)3
Differential Input Voltage Range
(S5 = GND)
Differential Input Voltage Range
(S5 = AVDD)
Input Common-Mode Voltage Full VI 2.65 2.8 2.9 2.65 2.8 2.9 V
Input Resistance Full VI 2.2 3 3.8 2.2 3 3.8 kΩ
Input Capacitance 25°C V 5 5 pF
POWER SUPPLY (LVDS Mode)
AVDD Full IV 3.1 3.3 3.6 3.2 3.3 3.6 V
DRVDD Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V
Supply Currents
I
I
(AVDD = 3.3 V)
ANALOG
(DRVDD = 3.3 V)4 Full VI 49 57 49 57 mA
DIGITAL
4
Power Dissipation4 Full VI 1.27 1.42 1.43 1.59 W
Power Supply Rejection 25°C V –7.5 –7.5 mV/V
1
Internal reference mode; SENSE = floats.
2
External reference mode; SENSE = DRVDD; VREF driven by external 1.23 V reference.
3
S5 (Pin 1) = GND. See the Analog Input section. S5 = GND in all dc, ac tests, unless otherwise specified
4
I
and I
AVDD
Characteristics
are measured with an analog input of 10.3 MHz, –0.5 dBFS, sine wave, rated clock rate, and in LVDS output mode. See the
DRVDD
Application Notes
and sections for I
= –40°C, T
MIN
= +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, unless
MAX
AD9411-170 AD9411-200
Test
Level
Min Typ Max Min Typ Max Unit
+0.12/
–0.24
+0.12/
–0.24
mV/°C
25°C IV 3.0 3.0 mA
Full V 1.536 1.536 V
Full V 0.766 0.766 V
Full VI 335 372 385 425 mA
. Power consumption is measured with a dc input at rated clock rate in LVDS output mode.
DRVDD
Typical Performance
Rev. A | Page 3 of 28
AD9411
AC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, T
otherwise noted.
Table 2.
AD9411-170 AD9411-200
Parameter Temp
SNR
Analog Input @ –0.5 dBFS
10 MHz 25°C I 59 60.2 59 60.2 dB
70 MHz 25°C I 59 60.1 59 60.1 dB
100 MHz 25°C V 60 60 dB
240 MHz 25°C V 59.1 59.1 dB
SINAD
Analog Input @ –0.5 dBFS
10 MHz 25°C I 58.5 60 58.5 60 dB
70 MHz 25°C I 58.5 60 58.5 60 dB
100 MHz 25°C V 59.5 59.5 dB
240 MHz 25°C V 57.5 57.5 dB
EFFECTIVE NUMBER OF BITS (ENOB)
10 MHz 25°C I 9.5 9.8 9.5 9.8 Bits
70 MHz 25°C I 9.5 9.8 9.5 9.8 Bits
100 MHz 25°C V 9.7 9.7 Bits
240 MHz 25°C V 9.3 9.3 Bits
WORST HARMONIC (Second or Third)
Analog Input @ –0.5 dBFS 10 MHz
10 MHz 25°C I –80 –73 –80 –70 dBc
70 MHz 25°C I –80 –73 –80 –70 dBc
100 MHz 25°C V −74 −74 dBc
240 MHz 25°C V −69 −69 dBc
WORST HARMONIC (Fourth or Higher)
Analog Input @ –0.5 dBFS 10 MHz
10 MHz 25°C I –82 –75 –82 –75 dBc
70 MHz 25°C I –82 –75 –82 –75 dBc
100 MHz 25°C V −76 −76 dBc
240 MHz 25°C V −70 −70 dBc
TWO-TONE IMD2
F1, F2 @ –7 dBFS 25°C V 70 70 dBc
ANALOG INPUT BANDWIDTH 25°C V 700 700 MHz
1
All ac specifications tested by driving CLK+ and CLK– differentially.
2
F1 = 30.5 MHz, F2 = 31 MHz.
1
MIN
= –40°C, T
= +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, unless
MAX
Test
Level
Min Typ Max Min Typ Max Unit
Rev. A | Page 4 of 28
AD9411
DIGITAL SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, T
Table 3.
Parameter Temp Test Level Min Typ Max Min Typ Max Unit
CLOCK INPUTS
(CLK+, CLK–)1
Differential Input Voltage2 Full IV 0.2 0.2 V
Common-Mode Voltage3 Full VI 1.375 1.5 1.575 1.375 1.5 1.575 V
Input Resistance Full VI 3.2 5.5 6.5 3.2 5.5 6.5 kΩ
Input Capacitance 25°C V 4 4 pF
LOGIC INPUTS (S1, S2, S4, S5)
Logic 1 Voltage Full IV 2.0 2.0 V
Logic 0 Voltage Full IV 0.8 0.8 V
Logic 1 Input Current Full VI 190 190 µA
Logic 0 Input Current Full VI 10 10 µA
Input Resistance 25°C V 30 30 kΩ
Input Capacitance 25°C V 4 4 pF
LVDS LOGIC OUTPUTS4
VOD Differential Output Voltage Full VI 247 454 247 454 mV
VOS Output Offset Voltage Full VI 1.125 1.375 1.125 1.375 V
Output Coding Twos Complement or Binary Twos Complement or Binary
1
See the section. Equivalent Circuits
2
All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 200 mV.
3
Clock inputs’ common mode can be externally set, such that 0.9 V < CLK± < 2.6 V.
4
LVDS R
= 100 Ω, LVDS output current set resistor (R
TERM
= –40°C, T
MIN
= +85°C, unless otherwise noted.
MAX
AD9411-170 AD9411-200
) = 3.74 kΩ (1% tolerance).
SET
Rev. A | Page 5 of 28
AD9411
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, T
Table 4.
Parameter (Conditions) Temp Test
Maximum Conversion Rate1 Full VI 170
Minimum Conversion Rate
1
Full V
CLK+ Pulse Width High (tEH)1 Full IV 2
CLK+ Pulse Width Low (tEL)1 Full IV 2
OUTPUT (LVDS Mode)
Valid Time (tV) Full VI 2.0 2.0 ns
Propagation Delay (tPD) Full VI 3.2 4.3 3.2 4.3 ns
Rise Time (tR) (20% to 80%) 25°C V 0.5 0.5 ns
Fall Time (tF) (20% to 80%) 25°C V 0.5 0.5 ns
DCO Propagation Delay (t
Data to DCO Skew (tPD–t
CPD
) Full IV 0.2 0.5 0.8 0.2 0.5 0.8 ns
CPD
Latency Full IV 14 14 Cycles
Aperture Delay (tA) 25°C V 1.2 1.2 ns
Aperture Uncertainty (Jitter, tJ) 25°C V 0.25 0.25
Out-of-Range Recovery Time 25°C V 1 1 Cycles
1
All ac specifications tested by driving CLK+ and CLK– differentially.
= –40°C, T
MIN
= +85°C, unless otherwise noted.
MAX
AD9411-170 AD9411-200
Min Typ Max Min Typ Max Unit
Level
200
40
12.5 2
12.5 2
40 MSPS
12.5 ns
12.5 ns
MSPS
) Full VI 1.8 2.7 3.8 1.8 2.7 3.8 ns
ps
rms
EXPLANATION OF TEST LEVELS
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100%
production tested at temperature extremes for military devices.
CLK+
CLK–
DATA OUT
DCO+
DCO–
N–1
A
IN
t
EH
N
N+1
t
EL
1/f
S
t
PD
N–14 N–13 N
14 CYCLES
N+1
t
CPD
Figure 2. LVDS Timing Diagram
Rev. A | Page 6 of 28
04530-0-002
AD9411
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
AVDD, DRVDD 4 V
Analog Inputs –0.5 V to AVDD +0.5 V
Digital Inputs –0.5 V to DRVDD +0.5 V
REFIN Inputs –0.5 V to AVDD +0.5 V
Digital Output Current 20 mA
Operating Temperature –55ºC to +125°C
Storage Temperature –65ºC to +150°C
Maximum Junction Temperature 150°C
Maximum Case Temperature 150°C
1
θ
JA
1
Typical θ
soldered) for multilayer board in still air with solid ground plane.
= 32°C/W (heat slug not soldered); typical θJA = 25°C/W (heat slug
JA
25°C/W, 32°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions outside of those indicated in the operation
section of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect
device reliability.
Rev. A | Page 7 of 28
AD9411
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
AGND
AGND
AVDD
AVDD
AVDD
AGND
AGND
OR+
OR–
9998979695949392919089888786858483828180797877
100
S5
1
2
DNC
AGND
3
AGND
4
5
AVDD
6
S1
AVDD
AGND
SENSE
VREF
AGND
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
VIN+
VIN–
AGND
AVDD
AGND
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
AD9411
TOP VIEW
(Not to Scale)
LVDSBIAS
DVRDD
DRGND
D9+
D9–
D8+
D8–
D7+
D7–
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DRVDD
DRGND
D6+
D6–
D5+
D5–
D4+
D4–
DRGND
D3+
D3–
DCO+
DCO–
DRVDD
DRGND
D2+
D2–
D1+
D1–
D0+
D0–
DRVDD
DRGND
DNC
DNC
26272829303132333435363738394041424344454647484950
AVDD
AGND
AVDD
AVDD
AGND
AGND
AGND
AVDD
AVDD
CLK+
AGND
CLK–
AVDD
AGND
AVDD
AGND
DNC
DNC
DNC
DNC
DNC
DRVDD
DRGND
DNC
Figure 3. TQFP/EP Pinout
Rev. A | Page 8 of 28
DNC
04530-0-003
AD9411
Table 6. Pin Function Descriptions
Pin No. Mnemonic Function
1 S5 Full-Scale Adjust Pin. AVDD sets FS = 0.768 V p-p differential;
GND sets FS = 1.536 V p-p differential.
2, 42–46,49–52 DNC Do Not Connect.
3, 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31,
32, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100
5, 8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34,
39, 40, 88, 89, 90, 94, 95, 98, 99
6 S1 Data Format Select. GND = binary; AVDD = twos complement.
7 LVDSBIAS
10 SENSE Reference Mode Select Pin. Float for internal reference operation.
11 VREF 1.235 V Reference Input/Output. Function depends on SENSE.
21 VIN+ Analog Input. True.
22 VIN– Analog Input. Complement.
36 CLK+ Clock Input. True (LVPECL levels).
37 CLK– Clock Input. Complement (LVPECL levels).
47, 54, 62, 75, 83 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).
48, 53, 61, 67, 74, 82 DRGND
56 D0+ D0 True Output Bit.
57 D1– D1 Complement Output Bit.
58 D1+ D1 True Output Bit.
59 D2– D2 Complement Output Bit.
60 D2+ D2 True Output Bit.
63 DCO– Data Clock Output. Complement.
64 DCO+ Data Clock Output. True.
65 D3– D3 Complement Output Bit.
66 D3+ D3 True Output Bit.
68 D4– D4 Complement Output Bit.
69 D4+ D4 True Output Bit.
70 D5– D5 Complement Output Bit.
71 D5+ D5 True Output Bit.
72 D6– D6 Complement Output Bit.
73 D6+ D6 True Output Bit.
76 D7– D7 Complement Output Bit.
77 D7+ D7 True Output Bit.
78 D8– D8 Complement Output Bit.
79 D8+ D8 True Output Bit.
80 D9– D9 Complement Output Bit.
81 D9+ D9 True Output Bit.
84 OR– Overrange Complement Output Bit.
85 OR+ Overrange True Output Bit.
AGND
AVDD 3.3 V Analog Supply.
Analog Ground. AGND and DRGND should be tied together to a common
ground plane.
Set Pin for LVDS Output Current. Place a 3.74 kΩ resistor terminated to
ground.
Digital Output Ground. AGND and DRGND should be tied together to a
common ground plane.
Rev. A | Page 9 of 28
AD9411
TERMINOLOGY
Analog Bandwidth
Clock Pulse Width/Duty Cycle
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the clock
command and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Crosstalk
Coupling onto one channel being driven by a low level (–40 dBFS)
signal when the adjacent interfering channel is driven by a fullscale signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
Pulse width high is the minimum amount of time the clock
pulse should be left in the Logic 1 state to achieve rated
performance; pulse width low is the minimum time the clock
pulse should be left in the low state. Refer to the timing
implications of changing t
Input section. At a given clock rate, these specifications define
an acceptable CLOCK duty cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
Power
Gain Error
The difference between the measured and ideal full-scale input
voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
FULLSCALE
in the Application Notes, Clock
ENCH
⎛
⎜
2
V
FULLSCALE
=
⎜
log10
Z
⎜
⎜
⎝
INPUT
001.0
RMS
⎞
⎟
⎟
⎟
⎟
⎠
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the input’s phase 180° and again taking the peak measurement.
The difference is then computed between both peak
measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB)
Calculated from the measured SNR based on the equation
ENOB
=
SNR
MEASURED
dB76.1−
02.6
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The CLOCK rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate
The CLOCK rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of CLK+ and CLK–
and the time when all output data bits are within valid logic
levels.
Rev. A | Page 10 of 28
AD9411
Noise (for Any Range within the ADC)
Calculated as follows:
⎛
××=
NOISE
ZV
10001.0
⎜
⎝
10
−−
SignalSNRFS
⎞
dBFSdBcdBM
⎟
⎠
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value of
the worst third-order intermodulation product, reported in dBc.
Two -Tone SFDR
where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value of the particular
input level, and Signal is the signal level within the ADC reported
in dB below full scale. This value includes both thermal and
quantization noise.
Power Supply Rejection Ratio (PSRR)
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered) or dBFS (always related
back to converter full scale).
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonics) reported in dBc.
Transi ent Res p onse T i m e
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above negative full scale to 10%
below positive full scale.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
Rev. A | Page 11 of 28
AD9411
EQUIVALENT CIRCUITS
AVDD
12kΩ
CLK+
150Ω 150Ω
10kΩ
12kΩ
10kΩ
CLK–
FULL
K
SCALE
0.1µF
VREF
1V
A1
200Ω
Figure 4. Clock Inputs
AVDD
3.5kΩ
VIN+ VIN–
20kΩ
3.5kΩ
20kΩ
Figure 5. Analog Inp uts
VDD
S1,S5
30kΩ
04530-0-006
Figure 6. S1 to S5 Inputs
04530-0-004
04530-0-005
DISABLE
A1
VDD
Figure 7. VREF, SENSE I/O
DRVDD
V+
DX–
V–
Figure 8. Data Outputs
1kΩ
V–
DX+
V+
SENSE
04530-0-008
04530-0-007
Rev. A | Page 12 of 28
AD9411
TYPICAL PERFORMANCE CHARACTERISTICS
dB
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
MHz
SNR = 59.7dB
SINAD = 59.5dB
H2 = –83.6dBc
H3 = –72.6dBc
SFDR = 72.5dBc
Figure 12. FFT: fS = 200 MSPS, AIN = 10.3 MHz @ −0.5 dBFS
10002010 4030 6050 80 9070
04530-A-001
0
dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
SNR = 60.1dB
SINAD = 59.9dB
H2 = –91.3dBc
H3 = –75.2dBc
SFDR = 75.3dBc
403010 200 50607080
MHz
Figure 9. FFT: fS = 170 MSPS, AIN = 10.3 MHz @ −0.5 dBFS
04530-0-009
0
dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
SNR = 59.8dB
SINAD = 59.8dB
H2 = –91.9dBc
H3 = –80.6dBc
SFDR = 73.2dBc
403010 200 50607080
MHz
Figure 10. FFT: fS = 170 MSPS, AIN = 65 MHz @ –0.5 dBFS
0
dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
SNR = 59.2dB
SINAD = 59.1dB
H2 = –70.1dBc
H3 = –87.0dBc
SFDR = 69.8dBc
403010 200 50607080
MHz
Figure 11. FFT: fS = 170 MSPS, AIN = 10.3, MHz @ –0.5 dBFS,
Single-Ended Input, 0.76 V Input Range
04530-0-010
04530-0-011
0
SINAD = 59.4dB
SFDR = 72.7dBc
dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
MHz
Figure 13. FFT: fS = 200 MSPS, AIN = 65 MHz @ −0.5 dBFS
0
SINAD = 43.8dB
SFDR = 43.6dBc
dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
MHz
Figure 14. FFT: fS = 200 MSPS, AIN = 70 MHz @ −0.5 dBFS,
Single-Ended Drive, 1.5 V Input Range
SNR = 59.5dB
H2 = –82.5dBc
H3 = –72.8dBc
SNR = 50.6dB
H2 = –44.8dBc
H3 = –67.4dBc
1000203010 40 50 60 70 80 90
04530-A-002
10002010 4030 6050 80 9070
04530-A-003
Rev. A | Page 13 of 28
AD9411
100
90
80
THIRD
70
dB
60
50
40
Figure 15. Harmonic Distortion (Second and Third) and SFDR vs. AIN
100
SFDR
20015050 1000 250 300 350 400
A
(MHz)
IN
Frequency @ 170 MSPS
SECOND
04530-0-015
dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
SFDR = 71.5dBc
403010 200 50607080
MHz
Figure 18. Two-Tone Intermodulation Distortion
(30.5 MHz and 31.0 MHz; fS = 170 MSPS)
0
04530-0-019
(dB)
90
80
70
60
50
40
SFDR
SECOND
THIRD
4000 50 100 150 200 250 300 350
(MHz)
Figure 16. Harmonic Distortion (Second and Third) and SFDR vs. AIN
Frequency @ 200 MSPS
(dB)
61
59
57
55
53
51
49
SNR_170
SNR_200
SINAD_170
SINAD_200
–20
–40
–60
(dB)
–80
–100
–120
04530-A-006
(MHz)
SFDR = 78.8dBc
1000 204060809010 30 50 70
04530-A-004
Figure 19. Two-Tone Intermodulation Distortion
(69.3 MHz and 70.3 MHz; fS = 200 MSPS)
80
SFDR_170
SINAD_170
(dB)
75
70
65
60
55
50
SFDR_200
SINAD_200
47
45
(MHz)
4500 50 100 150 200 250 300 350 400
Figure 17. SNR and SINAD vs. AIN Frequency; fS = 170/200 MSPS,
AIN @ –0.5 dBFS Full Scale = 1.536 V
04530-A-007
Rev. A | Page 14 of 28
45
40
(MSPS)
Figure 20. SINAD and SFDR vs. Clock Rate
(AIN = 10.3 MHz @ –0.5 dBFS) 170/200 grade
2500 50 100 150 200
04530-A-008
AD9411
450
400
350
300
250
200
150
ANALOG SUPPLY CURRENT (mA)
100
AVDD
I
50
0
100 120 140 160 180 200 220 240
ANALOG SUPPLY
CURRENT
OUTPUT SUPPLY
CURRENT
ENCODE (MSPS)
Figure 21. IAVDD and IDRVDD vs. Clock Rate, 170 MSPS Grade, CLOAD = 5 pF
(AIN = 10.3 MHz @ –0.5 dBFS)
450
400
350
300
250
200
150
100
ANALOG SUPPLY CURRENT (mA)
50
AVDD
I
0
ANALOG SUPPLY CURRENT
OUTPUT SUPPLY CURRENT
SAMPLE RATE (MSPS)
Figure 22. IAVDD and IDRVDD vs. Clock Rate, 200 MSPS Grade, CLOAD = 5 pF
(AIN = 10.3 MHz @ –0.5 dBFS)
75
73
71
69
67
65
dB
63
61
59
57
55
20 30 40 50 60 70 80 90
ENCODE POSITIVE DUTY CYCLE (%)
SFDR
SNR
SINAD
Figure 23. SINAD and SFDR vs. Clock Pulse Width High
(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS)
90
80
70
60
50
40
30
OUTPUT SUPPLY CURRENT (mA)
20
DRVDD
10
I
0
04530-2-023
(dB)
80
75
SFDR
70
65
SNR
60
55
50
SAMPLE CLOCK POSITIVE DUTY CYCLE
SINAD
8020 30 40 50 60 70
04530-A-010
Figure 24. SINAD and SFDR vs. Clock Pulse Width High
(AIN = 10.3 MHz @ –0.5 dBFS, 200 MSPS)
90
80
70
60
50
40
30
20
OUTPUT SUPPLY CURRENT (mA)
10
DRVDD
I
0
240100 120 140 180160 200 220
04530-A-009
1.4
1.2
1.0
0.8
(V)
REF
V
0.6
0.4
0.2
0
RO = 13Ω TYP
4312056
I
(mA)
LOAD
78
04530-A-016
Figure 25. VREFOUT vs. ILOAD (Both Speed Grades)
80
SFDR
SINAD
V
REF
(V)
1.50.5 0.7 0.9 1.1 1.3
04530-A-011
04530-0-025
(dB)
75
70
65
60
55
50
Figure 26. Sinad, SFDR vs. VREF in External Reference Mode
(AIN = 70 MHz @ –0.5 dBFS, 200 MSPS)
Rev. A | Page 15 of 28
AD9411
2.0
90
1.5
1.0
0.5
0
–0.5
GAIN ERROR (%)
–1.0
–1.5
–2.0
–50 –30 –10 10 30 50 70 90
% GAIN ERROR
USING EXT REF
TEMPERATURE (°C)
Figure 27. Full-Scale Gain Error vs. Temperature
(AIN = 10.3 MHz @ –0.5 dBFS, 170/200 MSPS)
(dB)
60
59
58
57
56
55
AVDD = 3.3V
TEMPERATURE (°C)
AVDD = 3.6V
AVDD = 3.0V
AVDD = 3.15V
80–40–200 204060
04530-0-028
04530-A-012
85
80
75
70
dB
65
60
55
50
–50 –30 –10 10 30 50 70 90
SFDR
SNR
SINAD
TEMPERATURE (°C)
Figure 30. SNR, SINAD, and SFDR vs. Temperature
(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS)
1.00
0.75
0.50
0.25
LSB
0
–0.25
–0.50
–0.75
–1.00
0 100 200 300 400 500 600 700 800 900 1000
CODE
04530-0-030
04530-0-032
Figure 28. SINAD vs. Temperature and AVDD
(AIN = 10.3 MHz @ –0.5 dBFS, 200 MSPS)
1.250
1.245
1.240
(V)
REFOUT
1.235
V
1.230
1.225
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9
AVDD (V)
Figure 29. VREF Output Voltage vs. AVDD (Both Speed Grades)
04530-0-029
Rev. A | Page 16 of 28
(AIN = 10.3 MHz @ –0.5 dBFS, 170/200 MSPS)
Figure 31. Typical INL Plot
1.0
0.8
0.6
0.4
0.2
0
LSB
–0.2
–0.4
–0.6
–0.8
–1.0
0 100 200 300 400 500 600 700 800 900 1000
CODE
Figure 32. Typical DNL Plot (AIN = 10.3 MHz @ –0.5 dBFS) 170/200 MSPS
04530-0-033
AD9411
dB
–20
–40
–60
–80
–100
–120
0
MHz
NPR = 51 dB
CLK = 200MSPS
NOTCH AT 18.5MHz
400 5 10 15 20 25 30 35
04530-A-005
110
100
90
80
70
60
dB
50
40
30
20
10
80dB
REFERENCE LINE
0
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
ANALOG INPUT LEVEL (dBFS)
SFDR –dBFS
SFDR –dBc
04530-0-034
Figure 33. SFDR vs. AIN Input Level 10.3 MHz, AIN @ 170 MSPS
90
80
70
dB
60
SFDR –dBFS
50
40
30
20
10
0
SFDR –dBc
70dB REFERENCE LINE
ANALOG INPUT LEVEL (dBFS)
Figure 34. SFDR vs. AIN Input Level 70 MHz, AIN @ 200 MSPS
0
–20
–40
–60
–80
NOISE LEVEL (dB)
–100
–120
–140
NPR = 51.2dB
ENCODE = 170MSPS
NOTCH @ 18.15MHz
100203040
MHz
Figure 35. Noise Power Ratio Plot (170 MSPS Grade)
Figure 36. Noise Power Ratio Plot (200 MSPS Grade)
4.5
4.0
3.5
ns
T
PD
3.0
T
CPD
0–70 –60 –50 –40 –30 –20 –10
04530-A-013
2.5
–40 –20 0 20 40 60 80 100
TEMPERATURE (°C)
04530-0-036
Figure 37. Propagation Delay vs. Temperature (Both Speed Grades)
900
800
700
600
500
(mV)
DIF
400
V
300
200
100
04530-0-035
0
02468101214
V
OS
V
OD
RSET (kΩ)
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
(V)
OS
V
04530-0-037
Figure 38. LVDS Output Swing, Common-Mode Voltage vs. RSET,
Placed at LVDSBIAS (Both Speed Grades)
Rev. A | Page 17 of 28
AD9411
APPLICATION NOTES
The AD9411 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated high bandwidth
track-and-hold circuit that samples the signal prior to quantization by the 10-bit core. For ease of use, the part includes an onboard reference and input logic that accepts TTL, CMOS, or
LVPECL levels. The digital output’s logic levels are LVDS
(ANSI-644) compatible.
CLOCK INPUT
Any high speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A track-andhold circuit is essentially a mixer, and any noise, distortion, or
timing jitter on the clock is combined with the desired signal at
the A/D output. For this reason, considerable care has been
taken in the design of the clock inputs of the AD9411, and the
user is advised to give careful thought to the clock source.
The AD9411 has an internal clock duty cycle stabilization
circuit that locks to the rising edge of CLK+ and optimizes
timing internally. This allows a wide range of input duty cycles
at the input without degrading performance. Jitter in the rising
edge of the input is still of paramount concern and is not
reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates less than 30 MHz
nominally. The time constant associated with the loop should
be considered in applications where the clock rate changes
dynamically, requiring a wait time of 1.5 µs to 5 µs after a
dynamic clock frequency increase before valid data is available.
This circuit is always on and cannot be disabled by the user.
Table 7. Output Select Coding
S1 (Data Format
Select)
S5 (Full-Scale
Select)
1
2
Mode
1 X Twos Complement
0 X Offset Binary
X 1 Full Scale = 0.768 V
X 0 Full Scale = 1.536 V
1
X = Don’t Care.
2
S5 full-scale adjust (refer to the Analog Input section).
ANALOG INPUT
The analog input to the AD9411 is a differential buffer. For best
dynamic performance, impedances at VIN+ and VIN– should
match. The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven
differentially. SNR and SINAD performance degrades significantly if the analog input is driven with a single-ended signal.
A wideband transformer, such as Mini-Circuits’ ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip resistor divider to a
nominal 2.8 V (refer to the Equivalent Circuits section). Note
that the input common-mode can be overdriven by
approximately +/−150 mV around the self-bias point, as shown
in Figure 42.
The clock inputs are internally biased to 1.5 V (nominal) and
support either differential or single-ended signals. For best
dynamic performance, a differential signal is recommended. An
MC100LVEL16 performs well in the circuit to drive the clock
inputs, as illustrated in Figure 39. Note that for this low voltage
PECL device, the ac coupling is optional.
0.1µF
PECL
GATE
0.1µF
510Ω510Ω
Figure 39. Driving Clock Inputs with LVEL16
AD9411
CLK+
CLK–
04530-A-017
Rev. A | Page 18 of 28
Special care was taken in the design of the analog input section
of the AD9411 to prevent damage and corruption of data when
the input is overdriven. The nominal differential input range is
approximately 1.5 V p-p ~ (768 mV × 2). Note that the best
performance is achieved with S5 = 0 (full-scale = 1.5). See
Figure 40 and Figure 41.
S5 = GND
VIN+
2.8V768mV 2.8V
VIN–
DIGITALOUT = ALL 1s DIGITALOUT = ALL 0s
Figure 40. Differential Analog Input Range
04530-0-041
AD9411
S5 = AVDD
VIN+
providing a low skew clocking solution (see Figure 2). The onchip clock buffers should not drive more than 5 pF of capacitance
to limit switching transient effects on performance. The output
clocks are LVDS signals requiring 100 Ω differential termination
at receiver.
2.8V768mV 2.8V
VIN– = 2.8V
Figure 41. Single-Ended Analog Input Range
61
60
59
dB
58
57
56
ANALOG INPUT COMMON MODE (V)
Figure 42. SINAD Sensitivity to Analog Input Common-Mode Voltage,
(Ain = −.5 dBfs Differential D rive, S5 = 0)
SINAD
3.22.0 2.2 2.4 2.6 2.8 3.0
LVDS OU TPUTS
The off-chip drivers provide LVDS compatible output levels. A
3.74 kΩ RSET resistor placed at Pin 7 (LVDSBIAS) to ground
sets the LVDS output current. The RSET resistor current is
ratioed on-chip, setting the output current at each output equal
to a nominal 3.5 mA (11 × IRSET). A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a
nominal 350 mV swing at the receiver. LVDS mode facilitates
interfacing with LVDS receivers in custom ASICs and FPGAs
that have LVDS capability for superior switching performance
in noisy environments. Single point-to-point network topologies
are recommended with a 100 Ω termination resistor as close to
the receiver as possible. It is recommended to keep the trace
lengths < 4 inches and to keep differential output trace lengths
as equal as possible.
CLOCK OUTPUTS (DCO+, DCO–)
The input clock is buffered on-chip and available off-chip at
DCO+ and DCO–. These clocks can facilitate latching off-chip,
04530-0-042
04530-A-014
VOLTAGE REFERENCE
A stable and accurate 1.23 V voltage reference is built into the
AD9411 (VREF). The analog input full-scale range is linearly
proportional to the voltage at VREF. Note that an external
reference can be used by connecting the SENSE pin to VDD
(disabling internal reference) and driving VREF with the
external reference source. No appreciable degradation in
performance occurs when VREF is adjusted ±5%. A 0.1 µF
capacitor to ground is recommended at the VREF pin in
internal and external reference applications. Float the SENSE
pin for internal reference operation.
FULL
K
SCALE
S5 = 0 K = 1.24
S5 = 1 K = 0.62
VREF
1V
DISABLE
A1
A1
EXTERNAL 1.23V
1kΩ
REFERENCE
SENSE
200Ω
VDD
Figure 43. Using an External Reference
NOISE POWER RATIO TESTING (NPR)
NPR is a test that is commonly used to characterize the return
path of cable systems where the signals are typically QAM signals with a “noise-like” frequency spectrum. NPR performance
of the AD9411 was characterized in the lab yielding an effective
NPR = 51.2 dB at an analog input of 18 MHz. This agrees with a
theoretical maximum NPR of 51.6 dB for a 10-bit ADC at 13 dB
backoff. The rms noise power of the signal inside the notch is
compared with the rms noise level outside the notch using an
FFT. This test requires sufficiently long record lengths to
guarantee a large number of samples inside the notch. A highorder band-stop filter that provides the required notch depth
for testing is also needed.
0.1µF
3.3V
04530-0-043
Rev. A | Page 19 of 28
AD9411
3.3V3.3V 3.3V
+++
SIGNAL
GENERATOR
REFIN
10MHz
REFOUT
SIGNAL
GENERATOR
BAND-PASS
FILTER
AVDD GND GND GNDVDLDRVDD
ANALOG
J4
AD9411 EVALUATION BOARD
CLOCK
J5
DATA
CAPTURE
AND
PROCESSING
04530-0-044
Figure 44. Evaluation Board Connections
Rev. A | Page 20 of 28
AD9411
EVALUATION BOARD
The AD9411 evaluation board offers an easy way to test the
AD9411 in LVDS mode. It requires a clock source, an analog
input signal, and a 3.3 V power supply. The clock source is
buffered on the board to provide the clocks for the ADC,
latches, and a data-ready signal. The digital outputs and output
clocks are available at a 40-pin connector, P23. The board has
several different modes of operation and is shipped in the
following configurations:
• Offset binary
• Internal voltage reference
• Full-scale adjust = low
GAIN
Full scale is set at E17–E19, E17–E18 sets S5 low, full scale =
1.5 V differential; E17–E19 sets S5 high, full scale = 0.75 V
differential. Best performance is obtained at 1.5 V full scale.
CLOCK
The clock input is terminated to ground through 50 Ω resistor
at SMB connector J5. The input is ac-coupled to a high speed
differential receiver (LVEL16) that provides the required low
jitter, fast edge rates needed for optimum performance. J5 input
should be > 0.5 V p-p. Power to the LVEL16 is set at Jumper
E47. E47–E45 powers the buffer from AVDD; E47–E46 powers
the buffer from VCLK/V_XTAL.
POWER CONNECTOR
Power is supplied to the board via a detachable 12-lead power
strip (three 4-pin blocks).
Table 8. Power Connector, LVDS Mode
AVDD1 3.3 V Analog Supply for ADC (350 mA)
DRVDD1 3.3 V Output Supply for ADC (50 mA)
VDL1 3.3 V Supply for Support Logic
VCLK/V_XTAL Supply for Clock Buffer/Optional XTAL
EXT_VREF
1
AVDD, DRVDD, and VDL are the minimum required power connections.
2
LVEL16 clock buffer can be powered from AVDD or VCLK at E47 jumper.
2
Optional External Reference Input
ANALOG INPUTS
The evaluation board accepts a 1.3 V p-p analog input signal
centered at ground at SMB connector J4. This signal is
terminated to ground through 50 Ω
alternatively terminated at the T1 transformer secondary by
R13 and R14. T1 is a wideband RF transformer that provides a
single-ended-to-differential conversion, allowing the ADC to be
driven differentially, which minimizes even-order harmonics.
An optional second transformer, T2, can be placed following T1
if desired. This provides some performance advantage (~1 dB to
2 dB) for high analog input frequencies (>100 MHz). If T2 is
placed, cut the two shorting traces at the pads. The analog
signal can be low-pass filtered by R41, C12 and R42, C13 at the
ADC input. The footprint for transformer T2 can be modified
to accept a wideband differential amplifier (AD8351) for low
frequency applications where gain is required. See the PCB
schematic for more information.
by R16. The input can be
VOLTAGE REFERENCE
The AD9411 has an internal 1.23 V voltage reference. The ADC
uses the internal reference as the default when Jumpers E24–E27
and E25–E26 are left open. The full scale can be increased by
placing an optional resistor (R3). The required value varies with
the process and needs to be tuned for the specific application.
Full scale can similarly be reduced by placing R4; tuning is
required here as well. An external reference can be used by
shorting the SENSE pin to 3.3 V (place Jumper E26–E25).
Jumper E27–E24 connects the ADC VREF pin to the
EXT_VREF pin at the power connector.
DATA FORMAT SELECT
Data format select (DFS) sets the output data format of the
ADC. Setting DFS (E1–E2) low sets the output format to be
offset binary; setting DFS high (E1–E3) sets the output to twos
complement.
DATA OUTPUTS
The ADC LVDS digital outputs are routed directly to the
connector at the card edge. Resistor pads placed at the output
connector allow for termination if the connector receiving logic
lack the differential termination for the data bits and DCO.
Each output trace pair should be terminated differentially at
the far end of the line with a single 100 ohm resistor.
CLOCK XTAL
An optional XTAL oscillator can be placed on the board to
serve as a clock source for the PCB. Power to the XTAL is
through the VCLK/VXTAL pin at the power connector. If an
oscillator is used, ensure proper termination for best results.
The board was tested with a Valpey Fisher VF561 and a Vectron
JN00158-163.84.
Rev. A | Page 21 of 28
AD9411
Table 9. Evaluation Board Bill of Material—AD9411 PCB
No. Quantity Reference Designator Device Package Value
1 33 C1, C3*, C4–C11, C15–C17, C18*,
C19–C32, C35, C36, C39*, C40*, C58-C62
2 4
3
4 C63–C66 Capacitor TAJD CAPL 10 µF
4 1
5 2
6 2 J4, J5 Jacks SMB
7 2 P21, P22 Power Connectors—Top 25.602.5453.0
8 2 P21, P22 Power Connectors—Posts Z5.531.3425.0
9 1 P23 40-Pin Right Angle Connector Digi-Key
10
16 R1, R6–R12*, R15*, R31–R37* Resistor 0402 100
11
1 R2
12
3 R5, R16, R27 Resistor
13
2 R17, R18 Resistor
14
2 R19, R20 Resistor
15
2 R29, R30
16
2 R41, R42 Resistor
17
2 R3, R4 Resistor
18
2 R13, R14 Resistor
19
6 R22*, R23*, R24*, R25*, R26*, R28* Resistor
20
5 R38*, R39*, R40*, R45*, R47* Resistor
21
2 R43*, R44* Resistor
22
1 R46* Resistor
23
2 R48*, R49* Resistor
24
2 R50*, R51* Resistor
25
C33*, C34*, C37*, C38*
C2* Capacitor 0603 10 pF
C12*, C13* Capacitor 0603 20 pF
Capacitor 0603 0.1 µF
Capacitor 0402 0.1 µF
Wieland
Wieland
S2131-20-ND
Resistor
0603
3.7 kΩ
0603 50
0603 510
0603 150
Resistor
0603
1 kΩ
0603 25
0603
3.8 kΩ
0603 25
0603 100
0402 25
0402
0402
10 kΩ
1.2 kΩ
0402 0
0402
Mini Circuits
1 kΩ
1 T1, T2* RF Transformer
26
1 U2 RF Amp AD8351
27
1 U9 Optional XTAL JN00158 or VF561
28
1 U1 AD9411 TQFP-100
29
1 U3 MC100LVEL16 SO8NB
* C2, C3, C12, C13, C18, C33, C34, C37, C38, C39, C40, R1, R6–R12, R15, R22–R26, R28, R31–R40, R43–R51 and T2 not placed.
Rev. A | Page 22 of 28
ADT1-1WT
AD9411
D
GNDDR
GNDD11
D10
D11
R6
100Ω
DOR
DORB
R1
100Ω
GND
GROUND PAD UNDER PART
P16
D11B
D10
R7
D9
D9B
R8
100Ω
D10B
100Ω
GND
DRVDD
GND
GND
VCC
VCC
VCC
GND
GND
GND
VCC
VCC
GND
GND
VCC
VCC
GND
H4
MTHOLE6H3MTHOLE6H2MTHOLE6H1MTHOLE6
GND
VREF
GND
VDL
1
2
3
P1
P2
P3
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GND
GND
DRVDD
4
1
P4
P1
PTM1CRO4
P21
D4
D8
D8B
R12
100Ω
D7
D7B
D5
D5B
R11
100Ω
D6
DRVDD
GND
75747372717069686766656463626160595857565554535251
D6–
D5–
D6+
D5+
D7–
D7+
DRVDD
DRGND
D4+
R10
R9
100Ω
D6B
DR
100Ω
GND
D4–
D3+
DRGND
DRB
R37
100Ω
DRVDD
D3–
DC0–
DC0+
DRVDD
D4B
R33
100Ω
D3
R32
100Ω
GND
D2–
D1–
D2+
D1+
D0+
DRGND
D8–
D8+
D9–
D9+
DRGND
DVRDD
OR–
OR+
AGND
AGND
AVDD
AVDD
AVDD
U1
AD9411
AGND
AGND
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
S5
DNCS4AGNDS2S1
123456789
E19
E18
R30
E17
VCC
GND
GND
VCC
2
3
4
P2
P3
P4
PTM1CRO4
P22
LVDSBIAS
AVDD
AGND
SENSE
VREF
AGND
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
101112131415161718192021222324
1kΩ
VCC
GND
GND
GND
R29
1kΩ
VCC
E3
VCC
E26
E24
E25
E27
VCC
E2
GND
E1
GND
R2
VREF
R3
R4
3.8kΩ
GND
3.8kΩ
GND
VCC
VCC
GND
C1
0.1µF
3.8kΩ
GND
GND
VCC
VCC
GND
GND
Figure 45. Evaluation Board Schematic
D3B
D2
C12
R31
D0–
AIN
20pF
39
P39
P40
40
GND
100Ω
T2 OPTIONAL
37
P37
P38
38
DRB
D2B
GND
DRVDD
DRVDD
DRGND
AINB
AGND
GND
R41
AMPINB
C15
GND
35
P35
P36
36
GND
25Ω
0.1µF
T2
ADT1-1WT
T1
ADT1-1WT
33
P33
P34
34
D11B
D1
DNC
AVDD
VCC
GND
31
P31
P32
32
D10B
R15
100Ω
DNC
AGND
25
GND
C3
R14
GND
4
1
GND
426
153
R16
ANALOG
D9D8D7D6D5
29
27
P29
P27
P30
P28
30
28
D9B
D8B
D1B
DNC
DNC
DRGND
DRVDD
DNC
DNC
DNC
DNC
DNC
AGND
AVDD
AVDD
AGND
CLK–
CLK+
AGND
AVDD
AVDD
AGND
AGND
AGND
AVDD
AVDD
AVDD
AGND
C13
20pF
C2
0.1µF
25Ω
C11
0.1µF
2
6
5
3
C7
0.1µF
SEC PRI SEC
PRI
NC NC
50Ω
J4
GND
10pF
C6
25
P25
P26
26
D7B
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
R13
0.1µF
23
P23
P24
24
D6B
GND
R42
25Ω
D4D3D2D1D0
21
19
P21
P19
P22
P20
22
20
D5B
D4B
D0
R36
100Ω
E46
VCC
25Ω
C30
AMPIN
AMP
GND
GND
GND
VCC
GND
GND
VCC
GND
GND
VCC
VCC
VCC
GND
0.1µF
17
P17
P18
18
D3B
D0B
15
P15
P16
16
D2B
D1F
R35
DRVDD
~ENC
R5
50Ω
GND
C36
0.1µF
E45
E47
VDL
10EL16
C5
13
P13
P14
14
D1B
100Ω
GND
C10
8
U3
J5
11
P11
P12
12
D0B
D1FB
ELOUT
VCC
0.1µF
0.1µF
7
D1F
D2F
DORGN
9
7
5
P9P7P5P3P1
P10P8P6P4P2
8
6
10
D1FB
D2FB
DORB
D2F
D2FB
R34
100Ω
C4
0.1µF
C9
0.1µF
ELOUTB
6
Q
QN
VEE
VBB
D
DN
234
R27
50Ω
GND
ENCODE
GND
5
R18
R17
3
4
CONNECTOR
R19
R20
1
2
GND
VCC
510Ω
GND
510Ω
C8
0.1µF
GND
510Ω
510Ω
GND
04530-A-015
Rev. A | Page 23 of 28
AD9411
VCC
C64
10µF
GND
+
C16
C17
0.1µF
0.1µF
C19
0.1µF
C21
0.1µF
C20
0.1µF
C23
0.1µF
C22
0.1µF
C25
0.1µF
C24
0.1µF
C27
0.1µF
C26
0.1µF
C29
0.1µF
C28
0.1µF
C31
0.1µF
C32
0.1µF
C35
0.1µF
TO USE VF561 CRYSTAL
GND
R28
100Ω
1
R22
100Ω
GND
2
3
E/D
NC
GND
JN00158
OUTPUTB
U9
VDL
VCC
6
5
OUTPUT
4
POWER DOWN
USE R43 OR R44
GND
DRVDD
VDL
GND
VDL
GND
C65
10µF
R23
100Ω
R25
100Ω
+
GND
VDL
C61
0.1µF
P4
R24
100Ω
R26
100Ω
C62
0.1µF
P5
C60
0.1µF
C59
0.1µF
Figure 46. Evaluation Board Schematic (continued)
R51
1kΩ
VDL GND
C38
0.1µF
R50
1kΩ
VDL
C58
0.1µF
C37
0.1µF
VDL
+
C66
C18
10µF
0.1µF
GND
GNDGND
VREF
GND
C63
10µF
+
04530-0-046
R38
25kΩ
AMP IN
AMP
GND
C33
0.1µF
C34
0.1µF
R43
10kΩ
R39
25kΩ
R40
25kΩ
R44
10kΩ
R45
25kΩ
1
2
3
4
5
PWUP
RGP1
INHI
INLO
RPG2
U2
AD8351
R46
1.2kΩ
VOCM
VPOS
OPHI
OPLO
COMM
R47
25kΩ
10
9
8
7
GND
6
R49
R48
C39
0.1µF
0Ω
0.1µF
0Ω
C40
AMPINB
AMPIN
04530-0-053
Figure 47. Evaluation Board Schematic (continued)
Rev. A | Page 24 of 28
AD9411
Figure 48. PCB Top Side Silkscreen
04530-0-049
Figure 50. PCB Ground Layer
Figure 49. PCB Top Side Copper Routing
04530-0-048
Rev. A | Page 25 of 28
Figure 51. PCB Split Power Plane
04530-0-050
AD9411
04530-0-051
Figure 52. PCB Bottom Side Copper Routing Figure 53. PCB Bottom Side Silkscreen
04530-0-052
Rev. A | Page 26 of 28
AD9411
OUTLINE DIMENSIONS
1.20
0.75
MAX
0.60
0.45
SEATING
PLANE
0.20
0.09
NOTES
1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
2. THE AD9411 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
1
25
26 50
7°
3.5°
0°
16.00 SQ
14.00 SQ
76100
75
TOP VIEW
(PINS DOWN)
51
0.50 BSC
COMPLIANT TO JEDEC STANDARDS MS-026AED-HD
0.27
0.22
0.17
0.15
0.05
75
51
1.05
1.00
0.95
COPLANARITY
0.08
76 100
CONDUCTIVE
HEAT SINK
6.50
NOM
1
25
2650
Figure 54. 100-Lead Thin Plastic Quad Flat Package, Exposed Pad [TQFP/EP]
(SV-100)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Model
AD9411BSV-170
AD9411BSV-200
Range
–40°C to +85°C
–40°C to +85°C
AD9411/PCB EVALUATION BOARD
Package Description
TQFP/EP
TQFP/EP
Rev. A | Page 27 of 28
Package Option
SV-100
SV-100
AD9411
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04530-0-7/04(A)
Rev. A | Page 28 of 28
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