Analog Devices AD9411 Service Manual

10-Bit, 170/200 MSPS

FEATURES

SNR = 60 dB @ fIN up to 70 MHz @ 200 MSPS
ENOB of 9.8 @ f
SFDR = 80 dBc @ f
Excellent linearity:
DNL = ±0.15 LSB (typical)
INL = ±0.25 LSB (typical)
LVDS output levels
700 MHz full-power analog bandwidth
On-chip reference and track-and-hold
Power dissipation = 1.25 W typical @ 200 MSPS

1.5 V input voltage range

3.3 V supply operation
Output data format option
Clock duty cycle stabilizer
Pin compatible to LVDS mode AD9430

APPLICATIONS

Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization

up to 70 MHz @ 200 MSPS (–0.5 dBFS)

IN

up to 70 MHz @ 200 MSPS (–0.5 dBFS)

IN

VIN+
VIN–

CLK+
CLK–

3.3 V A/D Converter

FUNCTIONAL BLOCK DIAGRAM

SENSE VREF

SCALABLE

REFERENCE

TRACK

AND

HOLD

CLOCK

MANAGEMENT

S1 S5

AGND DRGND DRVDD AVDD

AD9411

ADC

10

10-BIT

PIPELINE

CORE

Figure 1.

LVDS TIMING

/

LVDS

OUTPUTS

AD9411

DATA,
OVERRANGE
IN LVDS

DCO+
DCO–

04530-0-001

GENERAL DESCRIPTION

The AD9411 is a 10-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates up to a 200 MSPS conversion rate
and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary
functions, including track-and-hold (T/H) and reference, are
included on the chip to provide a complete conversion solution.

The ADC requires a 3.3 V power supply and a differential
sample clock for full performance operation. The digital outputs
are LVDS compatible and support both twos complement and
offset binary format. A data clock output is available to ease
data capture.

Fabricated on an advanced BiCMOS process, the AD9411 is
available in a 100-lead surface-mount plastic package (e-PAD
TQFP-100) specified over the industrial temperature range
(–40°C to +85°C).

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

PRODUCT HIGHLIGHTS

1. High performance.

Maintains 60 dB SNR @ 200 MSPS with a 70 MHz input.

2. Low power.

Consumes only 1.25 W @ 200 MSPS.

3. Ease of use.

LVDS output data and output clock signal allow interface
to current FPGA technology. The on-chip reference and
sample-and-hold function provide flexibility in system
design. Use of a single 3.3 V supply simplifies system
power supply design.

4. Out-of-range (OR).

The OR output bit indicates when the input signal is
beyond the selected input range.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD9411

TABLE OF CONTENTS

DC Specifications ............................................................................. 3

Clock Outputs (DCO+, DCO–)............................................... 19

AC Specifications.............................................................................. 4

Digital Specifications........................................................................ 5

Switching Specifications .................................................................. 6

Explanation of Test Levels........................................................... 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Te r mi n ol o g y .................................................................................... 10

Equivalent Circuits......................................................................... 12

Typical Performance Characteristics........................................... 13

Application Notes ........................................................................... 18

Clock Input.................................................................................. 18

Analog Input ............................................................................... 18

LVDS Output s ............................................................................. 19

Volt a ge R e fe r e nc e ....................................................................... 19

Noise Power Ratio Testing (NPR)............................................ 19

Evaluation Board ............................................................................ 21

Power Connector ........................................................................ 21

Analog Inputs ............................................................................. 21

Gain.............................................................................................. 21

Clock ............................................................................................ 21

Volt a ge R e fe r e nc e ....................................................................... 21

Data Format Select..................................................................... 21

Data Outputs............................................................................... 21

Clock XTAL................................................................................. 21

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 27

REVISION HISTORY

7/04—Data Sheet Changed from Rev. 0 to Rev. A

Added 200 MSPS Grade ....................................................Universal

Updated Outline Dimensions....................................................... 27

Changes to Ordering Guide.......................................................... 27

Rev 0 : Initial Version

Rev. A | Page 2 of 28

AD9411

DC SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, T
otherwise noted.

Table 1.

Parameter Temp
RESOLUTION 12 12 Bits
ACCURACY

No Missing Codes Full VI Guaranteed Guaranteed
Offset Error 25°C I –3 +3 –3 +3 mV
Gain Error 25°C I –5 +5 –5 +5 % FS
Differential Nonlinearity (DNL) 25°C I –0.5 ± 0.15 +0.5 –0.5 ± 0.15 +0.5 LSB
Full VI –0.6 ± 0.25 +0.6 –0.6 ± 0.25 +0.6 LSB

Integral Nonlinearity (INL) 25°C I –0.8 ± 0.5 +0.8 –0.8 ± 0.5 +0.8 LSB
Full VI –1 ± 0.5 +1 –1 ± 0.5 +1 LSB
TEMPERATURE DRIFT

Offset Error Full V 58 58 µV/°C

Gain Error Full V 0.02 0.02 %/°C

Reference Out (VREF) Full V

REFERENCE

Reference Out (VREF) 25°C I 1.15 1.235 1.3 1.15 1.235 1.3 V

Output Current

I

Input Current2 25°C I 20 20 mA

VREF

I

Input Current2 25°C I 1.6 5.0 1.6 5.0 mA

SENSE

1

ANALOG INPUTS (VIN+, VIN–)3

Differential Input Voltage Range

(S5 = GND)

Differential Input Voltage Range

(S5 = AVDD)

Input Common-Mode Voltage Full VI 2.65 2.8 2.9 2.65 2.8 2.9 V

Input Resistance Full VI 2.2 3 3.8 2.2 3 3.8 kΩ

Input Capacitance 25°C V 5 5 pF
POWER SUPPLY (LVDS Mode)

AVDD Full IV 3.1 3.3 3.6 3.2 3.3 3.6 V

DRVDD Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V

Supply Currents

I

I

(AVDD = 3.3 V)

ANALOG

(DRVDD = 3.3 V)4 Full VI 49 57 49 57 mA

DIGITAL

4

Power Dissipation4 Full VI 1.27 1.42 1.43 1.59 W

Power Supply Rejection 25°C V –7.5 –7.5 mV/V

1

Internal reference mode; SENSE = floats.

2

External reference mode; SENSE = DRVDD; VREF driven by external 1.23 V reference.

3

S5 (Pin 1) = GND. See the Analog Input section. S5 = GND in all dc, ac tests, unless otherwise specified

4

I

and I

AVDD

Characteristics

are measured with an analog input of 10.3 MHz, –0.5 dBFS, sine wave, rated clock rate, and in LVDS output mode. See the

DRVDD

Application Notes

and sections for I

= –40°C, T

MIN

= +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, unless

MAX

AD9411-170 AD9411-200

Test
Level

Min Typ Max Min Typ Max Unit

+0.12/
–0.24

+0.12/
–0.24

mV/°C

25°C IV 3.0 3.0 mA

Full V 1.536 1.536 V

Full V 0.766 0.766 V

Full VI 335 372 385 425 mA

. Power consumption is measured with a dc input at rated clock rate in LVDS output mode.

DRVDD

Typical Performance

Rev. A | Page 3 of 28

AD9411

AC SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, T
otherwise noted.

Table 2.

AD9411-170 AD9411-200

Parameter Temp

SNR
Analog Input @ –0.5 dBFS

10 MHz 25°C I 59 60.2 59 60.2 dB
70 MHz 25°C I 59 60.1 59 60.1 dB
100 MHz 25°C V 60 60 dB
240 MHz 25°C V 59.1 59.1 dB

SINAD
Analog Input @ –0.5 dBFS

10 MHz 25°C I 58.5 60 58.5 60 dB
70 MHz 25°C I 58.5 60 58.5 60 dB
100 MHz 25°C V 59.5 59.5 dB
240 MHz 25°C V 57.5 57.5 dB

EFFECTIVE NUMBER OF BITS (ENOB)

10 MHz 25°C I 9.5 9.8 9.5 9.8 Bits
70 MHz 25°C I 9.5 9.8 9.5 9.8 Bits
100 MHz 25°C V 9.7 9.7 Bits
240 MHz 25°C V 9.3 9.3 Bits

WORST HARMONIC (Second or Third)
Analog Input @ –0.5 dBFS 10 MHz

10 MHz 25°C I –80 –73 –80 –70 dBc
70 MHz 25°C I –80 –73 –80 –70 dBc
100 MHz 25°C V −74 −74 dBc
240 MHz 25°C V −69 −69 dBc

WORST HARMONIC (Fourth or Higher)
Analog Input @ –0.5 dBFS 10 MHz

10 MHz 25°C I –82 –75 –82 –75 dBc
70 MHz 25°C I –82 –75 –82 –75 dBc
100 MHz 25°C V −76 −76 dBc
240 MHz 25°C V −70 −70 dBc

TWO-TONE IMD2

F1, F2 @ –7 dBFS 25°C V 70 70 dBc

ANALOG INPUT BANDWIDTH 25°C V 700 700 MHz

1

All ac specifications tested by driving CLK+ and CLK– differentially.

2

F1 = 30.5 MHz, F2 = 31 MHz.

1

MIN

= –40°C, T

= +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, unless

MAX

Test
Level

Min Typ Max Min Typ Max Unit

Rev. A | Page 4 of 28

AD9411

DIGITAL SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, T

Table 3.

Parameter Temp Test Level Min Typ Max Min Typ Max Unit
CLOCK INPUTS
(CLK+, CLK–)1

Differential Input Voltage2 Full IV 0.2 0.2 V

Common-Mode Voltage3 Full VI 1.375 1.5 1.575 1.375 1.5 1.575 V

Input Resistance Full VI 3.2 5.5 6.5 3.2 5.5 6.5 kΩ

Input Capacitance 25°C V 4 4 pF
LOGIC INPUTS (S1, S2, S4, S5)

Logic 1 Voltage Full IV 2.0 2.0 V

Logic 0 Voltage Full IV 0.8 0.8 V

Logic 1 Input Current Full VI 190 190 µA

Logic 0 Input Current Full VI 10 10 µA

Input Resistance 25°C V 30 30 kΩ

Input Capacitance 25°C V 4 4 pF
LVDS LOGIC OUTPUTS4

VOD Differential Output Voltage Full VI 247 454 247 454 mV

VOS Output Offset Voltage Full VI 1.125 1.375 1.125 1.375 V

Output Coding Twos Complement or Binary Twos Complement or Binary

1

See the section. Equivalent Circuits

2

All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 200 mV.

3

Clock inputs’ common mode can be externally set, such that 0.9 V < CLK± < 2.6 V.

4

LVDS R

= 100 Ω, LVDS output current set resistor (R

TERM

= –40°C, T

MIN

= +85°C, unless otherwise noted.

MAX

AD9411-170 AD9411-200

) = 3.74 kΩ (1% tolerance).

SET

Rev. A | Page 5 of 28

AD9411

SWITCHING SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, T

Table 4.

Parameter (Conditions) Temp Test

Maximum Conversion Rate1 Full VI 170
Minimum Conversion Rate

1

Full V

CLK+ Pulse Width High (tEH)1 Full IV 2
CLK+ Pulse Width Low (tEL)1 Full IV 2
OUTPUT (LVDS Mode)

Valid Time (tV) Full VI 2.0 2.0 ns
Propagation Delay (tPD) Full VI 3.2 4.3 3.2 4.3 ns
Rise Time (tR) (20% to 80%) 25°C V 0.5 0.5 ns
Fall Time (tF) (20% to 80%) 25°C V 0.5 0.5 ns
DCO Propagation Delay (t
Data to DCO Skew (tPD–t

CPD

) Full IV 0.2 0.5 0.8 0.2 0.5 0.8 ns

CPD

Latency Full IV 14 14 Cycles
Aperture Delay (tA) 25°C V 1.2 1.2 ns
Aperture Uncertainty (Jitter, tJ) 25°C V 0.25 0.25

Out-of-Range Recovery Time 25°C V 1 1 Cycles

1

All ac specifications tested by driving CLK+ and CLK– differentially.

= –40°C, T

MIN

= +85°C, unless otherwise noted.

MAX

AD9411-170 AD9411-200

Min Typ Max Min Typ Max Unit

Level

200

40

12.5 2

12.5 2

40 MSPS

12.5 ns

12.5 ns

MSPS

) Full VI 1.8 2.7 3.8 1.8 2.7 3.8 ns

ps
rms

EXPLANATION OF TEST LEVELS

I. 100% production tested.

II. 100% production tested at 25°C and sample tested at specified temperatures.

III. Sample tested only.

IV. Parameter is guaranteed by design and characterization testing.

V. Parameter is a typical value only.

VI. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100%

production tested at temperature extremes for military devices.

CLK+

CLK–

DATA OUT

DCO+

DCO–

N–1

A

IN

t

EH

N

N+1

t

EL

1/f

S

t

PD

N–14 N–13 N

14 CYCLES

N+1

t

CPD

Figure 2. LVDS Timing Diagram

Rev. A | Page 6 of 28

04530-0-002

AD9411

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating
AVDD, DRVDD 4 V
Analog Inputs –0.5 V to AVDD +0.5 V
Digital Inputs –0.5 V to DRVDD +0.5 V
REFIN Inputs –0.5 V to AVDD +0.5 V
Digital Output Current 20 mA
Operating Temperature –55ºC to +125°C
Storage Temperature –65ºC to +150°C
Maximum Junction Temperature 150°C
Maximum Case Temperature 150°C

1

θ

JA

1

Typical θ

soldered) for multilayer board in still air with solid ground plane.

= 32°C/W (heat slug not soldered); typical θJA = 25°C/W (heat slug

JA

25°C/W, 32°C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions outside of those indicated in the operation
section of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect
device reliability.

Rev. A | Page 7 of 28

AD9411

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND

AVDD

AVDD

AGND

AGND

AVDD

AVDD

AGND

AGND

AGND

AVDD

AVDD

AVDD

AGND

AGND

OR+

OR–

9998979695949392919089888786858483828180797877

100

S5

1
2

DNC

AGND

3

AGND

4
5

AVDD

6

S1

AVDD

AGND

SENSE

VREF
AGND
AGND

AVDD

AVDD
AGND
AGND

AVDD

AVDD
AGND

VIN+
VIN–

AGND

AVDD
AGND

7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

AD9411

TOP VIEW

(Not to Scale)

LVDSBIAS

DVRDD

DRGND

D9+

D9–

D8+

D8–

D7+

D7–

76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DRVDD
DRGND
D6+
D6–
D5+
D5–
D4+
D4–
DRGND
D3+
D3–
DCO+
DCO–
DRVDD
DRGND
D2+
D2–
D1+

D1–
D0+

D0–
DRVDD
DRGND
DNC
DNC

26272829303132333435363738394041424344454647484950

AVDD

AGND

AVDD

AVDD

AGND

AGND

AGND

AVDD

AVDD

CLK+

AGND

CLK–

AVDD

AGND

AVDD

AGND

DNC

DNC

DNC

DNC

DNC

DRVDD

DRGND

DNC

Figure 3. TQFP/EP Pinout

Rev. A | Page 8 of 28

DNC

04530-0-003

AD9411

Table 6. Pin Function Descriptions

Pin No. Mnemonic Function

1 S5 Full-Scale Adjust Pin. AVDD sets FS = 0.768 V p-p differential;
GND sets FS = 1.536 V p-p differential.
2, 42–46,49–52 DNC Do Not Connect.
3, 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31,

32, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100
5, 8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34,

39, 40, 88, 89, 90, 94, 95, 98, 99
6 S1 Data Format Select. GND = binary; AVDD = twos complement.
7 LVDSBIAS

10 SENSE Reference Mode Select Pin. Float for internal reference operation.
11 VREF 1.235 V Reference Input/Output. Function depends on SENSE.
21 VIN+ Analog Input. True.
22 VIN– Analog Input. Complement.
36 CLK+ Clock Input. True (LVPECL levels).
37 CLK– Clock Input. Complement (LVPECL levels).
47, 54, 62, 75, 83 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).
48, 53, 61, 67, 74, 82 DRGND

56 D0+ D0 True Output Bit.
57 D1– D1 Complement Output Bit.
58 D1+ D1 True Output Bit.
59 D2– D2 Complement Output Bit.
60 D2+ D2 True Output Bit.
63 DCO– Data Clock Output. Complement.
64 DCO+ Data Clock Output. True.
65 D3– D3 Complement Output Bit.
66 D3+ D3 True Output Bit.
68 D4– D4 Complement Output Bit.
69 D4+ D4 True Output Bit.
70 D5– D5 Complement Output Bit.
71 D5+ D5 True Output Bit.
72 D6– D6 Complement Output Bit.
73 D6+ D6 True Output Bit.
76 D7– D7 Complement Output Bit.
77 D7+ D7 True Output Bit.
78 D8– D8 Complement Output Bit.
79 D8+ D8 True Output Bit.
80 D9– D9 Complement Output Bit.
81 D9+ D9 True Output Bit.
84 OR– Overrange Complement Output Bit.
85 OR+ Overrange True Output Bit.

AGND

AVDD 3.3 V Analog Supply.

Analog Ground. AGND and DRGND should be tied together to a common
ground plane.

Set Pin for LVDS Output Current. Place a 3.74 kΩ resistor terminated to
ground.

Digital Output Ground. AGND and DRGND should be tied together to a
common ground plane.

Rev. A | Page 9 of 28