Analog Devices AD9398 Service Manual

HDMI™ Display Interface

FEATURES

HDMI interface

Supports high bandwidth digital content protection RGB to YCbCr 2-way color conversion

1.8 V/3.3 V power supply 100-lead, Pb-free LQFP RGB and YCbCr output formats

Digital video interface

HDMI 1.1, DVI 1.0 150 MHz HDMI receiver Supports high bandwidth digital content protection

(HDCP 1.1)

Digital audio interface

HDMI 1.1-compatible audio interface SPDIF (IEC90658-compatible) digital audio output Multichannel I

APPLICATIONS

Advanced TVs HDTVs Projectors LCD monitors

S audio output (up to 8 channels)

SCL SDA

Rx0+ Rx0– Rx1+ Rx1– Rx2+

Rx2– RxC+ RxC–

RTERM

MCL MDA

DDCSCL DDCSD

AD9398

FUNCTIONAL BLOCK DIAGRAM

SERIAL REGISTER

AND

POWER MANAGEMENT

R/G/B 8 × 3 OR YCbCr

HDMI

RECEIVER

HDCP

DATACK

HSYNC VSYNC

Figure 1.

RGB ↔YCbCr

AD9398

R/G/B 8 × 3 YCbCr (4:2:2

OR 4:4:4) 2

DATACK HSOUT

VSOUT

COLORSPACE CONVERTER

DE S/PDIF OUT 8-CHANNEL

MCLK LRCLK

05678-001

GENERAL DESCRIPTION

The AD9398 offers a high definition multimedia interface (HDMI) receiver integrated on a single chip. Also included is support for high bandwidth digital content protection (HDCP).

The AD9398 contains a HDMI 1.0-compatible receiver and supports all HDTV formats (up to 1080p) and display resolutions up to SXGA (1280 × 1024 @ 75 Hz). The receiver features an intrapair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays can now receive encrypted video content. The AD9398 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP 1.1 protocol.

Fabricated in an advanced CMOS process, the AD9398 is provided in a space-saving 100-lead, surface-mount, Pb-free, plastic LQFP and is specified over the 0°C to 70°C temperature range.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9398

TABLE OF CONTENTS

Features .............................................................................................. 1

4:4:4 to 4:2:2 Filter...................................................................... 11

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Digital Interface Electrical Characteristics ............................... 3

Absolute Maximum Ratings............................................................ 5

Explanation of Test Levels........................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Design Guide..................................................................................... 9

General Description ..................................................................... 9

Digital Inputs ................................................................................ 9

Serial Control Port ....................................................................... 9

Output Signal Handling............................................................... 9

Audio PLL Setup......................................................................... 12

Audio Board Level Muting........................................................ 13

Output Data Formats................................................................. 13

2-Wire Serial Register Map ........................................................... 14

2-Wire Serial Control Register Details ........................................ 25

Chip Identification ..................................................................... 25

BT656 Generation...................................................................... 27

Macrovision................................................................................. 28

Color Space Conversion............................................................ 29

2-Wire Serial Control Port ............................................................ 36

Data Transfer via Serial Interface............................................. 36

Serial Interface Read/Write Examples..................................... 37

PCB Layout Recommendations.................................................... 38

Power Supply Bypassing ............................................................ 38

Outputs (Both Data and Clocks).............................................. 38

Power Management...................................................................... 9

Timing.......................................................................................... 10

VSYNC Filter and Odd/Even Fields ........................................ 10

HDMI Receiver........................................................................... 10

DE Generator ..............................................................................10

REVISION HISTORY

10/05—Revision 0: Initial Version

Digital Inputs .............................................................................. 38

Color Space Converter (CSC) Common Settings...................... 39

Outline Dimensions ....................................................................... 41

Ordering Guide .......................................................................... 41

Rev. 0 | Page 2 of 44

AD9398

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VDD, VD = 3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum.

Table 1.

AD9398KSTZ-100 AD9398KSTZ-150 Parameter Temp Test Level Min Typ Max Min Typ Max Unit

DIGITAL INPUTS (5 V TOLERANT)

Input Voltage, High (VIH) Full VI 2.6 2.6 V Input Voltage, Low (VIL) Full VI 0.8 0.8 V Input Current, High (IIH) Full V −82 −82 μA Input Current, Low (IIL) Full V 82 82 μA Input Capacitance 25°C V 3 3 pF

DIGITAL OUTPUTS

Output Voltage, High (VOH) Full VI VDD − 0.1 VDD − 0.1 V Output Voltage, Low (VOL) Full VI 0.4 0.4 V Duty Cycle, DATACK Full V 45 50 55 45 50 55 % Output Coding Binary Binary

THERMAL CHARACTERISTICS

θJA Junction-to-Ambient V 35 35 °C/W

DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS

VDD = VD =3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum.

Table 2.

AD9398KSTZ-100 AD9398KSTZ-150 Parameter Test Level Conditions Min Typ Max Min Typ Max Unit

RESOLUTION 8 8 Bit DC DIGITAL I/O SPECIFICATIONS

High-Level Input Voltage (VIH) VI 2.5 2.5 V Low-Level Input Voltage (VIL) VI 0.8 0.8 V High-Level Output Voltage (VOH) VI VDD − 0.1 V Low-Level Output Voltage (VOL) VI VDD − 0.1 0.1 0.1 V

DC SPECIFICATIONS

Output High Level IV Output drive = high 36 36 mA

) (V

OHD

Output Low Level IV Output drive = high 12 12 mA

OLD

DATACK High Level IV Output drive = high 40 40 mA

OHC

DATACK Low Level IV Output drive = high 30 30 mA

OLC

= VOH) IV Output drive = low 24 24 mA

OUT

, (V

= VOL) IV Output drive = low 8 8 mA

OUT

, (V

= VOH) IV Output drive = low 20 20 mA

OUT

, (V

= VOL) IV Output drive = low 15 15 mA

OUT

Differential Input Voltage, Single-

IV 75 700 75 700 mV

Ended Amplitude

Rev. 0 | Page 3 of 44

AD9398

AD9398KSTZ-100 AD9398KSTZ-150 Parameter Test Level Conditions Min Typ Max Min Typ Max Unit

POWER SUPPLY

VD Supply Voltage IV 3.15 3.3 3.47 3.15 3.3 3.47 V VDD Supply Voltage IV 1.7 3.3 347 1.7 3.3 347 V DVDD Supply Voltage IV 1.7 1.8 1.9 1.7 1.8 1.9 V PVDD Supply Voltage IV 1.7 1.8 1.9 1.7 1.8 1.9 V IVD Supply Current (Typical Pattern) I

Supply Current (Typical Pattern)

VDD

Supply Current (Typical Pattern)

DVDD

Supply Current (Typical Pattern) V 26 35 30 40 mA

PVDD

Power-Down Supply Current (IPD) VI 130 130 mA

AC SPECIFICATIONS

Intrapair (+ to −) Differential Input

DPS

)

Skew (T

Channel to Channel Differential Input

Skew (T

CCS

)

Low-to-High Transition Time for Data

and Controls (D

LHT

)

IV Output drive = low;

Low-to-High Transition Time for

DATACK (D

LHT

)

IV Output drive = low;

High-to-Low Transition Time for Data

and Controls (D

HLT

)

IV Output drive = low;

High-to-Low Transition Time for

DATACK (D

HLT

)

IV Output drive = low;

Clock-to-Data Skew5 (T

) IV −0.5 2.0 −0.5 2.0 ns

SKEW

Duty Cycle, DATACK IV 45 50 55 % DATACK Frequency (F

The typical pattern contains a gray scale area, output drive = high. Worst-case pattern is alternating black and white pixels.

The typical pattern contains a gray scale area, output drive = high.

Specified current and power values with a worst-case pattern (on/off).

DATACK load = 10 pF, data load = 5 pF.

Drive strength = high.

) VI 20 150 MHz

CIP

V 80 100 80 110 mA

V 40 100

V 88 110 110 145 mA

55 1751mA

IV 360 ps

IV 6 Clock

period

IV Output drive = high;

= 10 pF

900 ps

1300 ps

= 5 pF

IV Output drive = high;

= 10 pF

650 ps

1200 ps

= 5 pF

IV Output drive = high;

= 10 pF

850 ps

1250 ps

= 5 pF

IV Output drive = high;

= 10 pF

800 ps

1200 ps

= 5 pF

Rev. 0 | Page 4 of 44

AD9398

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VDD 3.6 V DV

Analog Inputs VD to 0.0 V Digital Inputs 5 V to 0.0 V Digital Output Current 20 mA Operating Temperature Range −25°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Maximum Case Temperature 150°C

3.6 V

1.98 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

EXPLANATION OF TEST LEVELS

Table 4.

Level Test

I 100% production tested. II

III Sample tested only. IV

V Parameter is a typical value only. VI

100% production tested at 25°C and sample tested at specified temperatures.

Parameter is guaranteed by design and characterization testing.

100% production tested at 25°C; guaranteed by design and characterization testing.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 5 of 44

AD9398

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND GREEN 7 GREEN 6 GREEN 5 GREEN 4 GREEN 3 GREEN 2 GREEN 1 GREEN 0

GND

BLUE 7 BLUE 6 BLUE 5 BLUE 4 BLUE 3 BLUE 2 BLUE 1 BLUE 0

MCLKIN

MCLKOUT

SCLK

LRCLK

I2S3 I2S2

VDDRED 0

RED 1

RED 2

RED 3

RED 4

RED 5

RED 6

RED 7

GND

VDDDATACKDEHSOUTNCVSOUT

100

1 2 3

5 6 7 8 9

11 12 13 14 15

17 18 19

24 25

PIN 1

898887

AD9398

TOP VIEW

(Not to Scale)

O/E FIELD

SDA

SCL

PWRDN

VDNC

GNDNCV

787776

GND

FILT

GND

MDA

MCL

NC = NO CONNECT

S/PDIF

GND

Rx2+

GND

RxC–

RxC+

Rx2–

GND

Rx0–

Rx1–

Rx0+

Rx1+

GND

DDCSCL

DDCSDA

05678-002

RTERM

Figure 2. Pin Configuration

Table 5. Complete Pinout List

Pin Type Pin No. Mnemonic Function Value

INPUTS 81 PWRDN Power-Down Control 3.3 V CMOS DIGITAL VIDEO DATA INPUTS 35 Rx0+ Digital Input Channel 0 True TMDS 34 Rx0− Digital Input Channel 0 Complement TMDS 38 Rx1+ Digital Input Channel 1 True TMDS 37 Rx1− Digital Input Channel 1 Complement TMDS 41 Rx2+ Digital Input Channel 2 True TMDS 40 Rx2− Digital Input Channel 2 Complement TMDS DIGITAL VIDEO CLOCK INPUTS 43 RxC+ Digital Data Clock True TMDS 44 RxC− Digital Data Clock Complement TMDS OUTPUTS 92 to 99 RED [7:0] Outputs of Red Converter, Bit 7 is MSB V 2 to 9 GREEN [7:0] Outputs of Green Converter, Bit 7 is MSB V 12 to 19 BLUE [7:0] Outputs of Blue Converter, Bit 7 is MSB V 89 DATACK Data Output Clock V 87 HSOUT HSYNC Output Clock (Phase-Aligned with DATACK) V 85 VSOUT VSYNC Output Clock (Phase-Aligned with DATACK) V 84 FIELD Odd/Even Field Output V REFERENCES 57 FILT

Connection for External Filter Components For audio

PLL

Rev. 0 | Page 6 of 44

AD9398

Pin Type Pin No. Mnemonic Function Value

POWER SUPPLY 80, 76, 72, 67, 45, 33 V 100, 90, 10 V 59, 56, 54 PV 48, 32, 30 DV

GND Ground 0 V CONTROL 83 SDA Serial Port Data I/O 3.3 V CMOS 82 SCL Serial Port Data Clock 3.3 V CMOS HDCP 49 DDCSCL HDCP Slave Serial Port Data Clock 3.3 V CMOS 50 DDCSDA HDCP Slave Serial Port Data I/O 3.3 V CMOS 51 MCL HDCP Master Serial Port Data Clock 3.3 V CMOS 52 MDA HDCP Master Serial Port Data I/O 3.3 V CMOS AUDIO DATA OUTPUTS 28 S/PDIF S/PDIF Digital Audio Output V 27 I2S0 I2S Audio (Channel 1, Channel 2) V 26 I2S1 I2S Audio (Channel 3, Channel 4) V 25 I2S2 I2S Audio (Channel 5, Channel 6) V 24 I2S3 I2S Audio (Channel 7, Channel 8) V 20 MCLKIN External Reference Audio Clock In V 21 MCLKOUT Audio Master Clock Output V 22 SCLK Audio Serial Clock Output V 23 LRCLK Data Output Clock for Left and Right Audio Channels V DATA ENABLE 88 DE Data Enable 3.3 V CMOS RTERM 46 RTERM Sets Internal Termination Resistance 500 Ω

Table 6. Pin Function Descriptions

Mnemonic Description

INPUTS

Rx0+ Digital Input Channel 0 True. Rx0− Digital Input Channel 0 Complement. Rx1+ Digital Input Channel 1 True. Rx1− Digital Input Channel 1 Complement. Rx2+ Digital Input Channel 2 True. Rx2− Digital input Channel 2 Complement.

These six pins receive three pairs of transition minimized differential signaling (TMDS) pixel data (at 10× the pixel

rate) from a digital graphics transmitter. RxC+ Digital Data Clock True. RxC− Digital Data Clock Complement.

This clock pair receives a TMDS clock at 1× pixel data rate. FILT External Filter Connection.

For proper operation, the audio-clock generator PLL requires an external filter. Connect the filter shown in

to this pin. For optimal performance, minimize noise and parasitics on this node. For more information see the

PCB Layout Recommendations section . PWRDN

Power-Down Control/Three-State Control.

The function of this pin is programmable via Register 0x26 [2:1].

OUTPUTS

HSOUT Horizontal Sync Output.

A reconstructed and phase-aligned version of the HSYNC input. Both the polarity and duration of this output can

be programmed via serial bus registers. By maintaining alignment with DATACK and DATA, data timing with

respect to horizontal sync can always be determined. VSOUT Vertical Sync Output.

The separated VSYNC from a composite signal or a direct pass through of the VSYNC signal. The polarity of this

output can be controlled via the serial bus bit (Register 0x24 [6]). O/E FIELD

Odd/Even Field Bit for Interlaced Video. This output identifies whether the current field (in an interlaced signal) is

odd or even. The polarity of this signal is programmable via Register 0x24[4]. DE Data Enable that defines valid video. Can be received in the signal or generated by the AD9398.

Rev. 0 | Page 7 of 44

Analog Power Supply and DVI Terminators 3.3 V Output Power Supply 1.8 V to 3.3 V PLL Power Supply 1.8 V Digital Logic Power Supply 1.8 V

Figure 8

AD9398

Mnemonic Description

RTERM

AUDIO DATA OUTPUT

S/PDIF Sony/Philips Digital Interface. Supports digital audio from 32 kbps to 192 kbps. I2S0 to I2S3 Inter-IC Sound Channel 0 through Channel 3. Each line supports two channels of digital audio. MCLKIN Master Audio Clock External. Used if internal MCLK is not generated. MCLKOUT Master Audio Clock Output to Drive Audio DACs. SCLK Serial Clock Out to support Digital Audio. LRCLK Data Output Clock for Left and Right Audio Channels.

SERIAL PORT

SDA Serial Port Data I/O for Programming AD9398 Registers—I2C Address is 0x98. SCL Serial Port Data Clock for Programming AD9398 Registers. DDCSDA Serial Port Data I/O for HDCP Communications to Transmitter—I2C Address is 0x74 or 0x76. DDCSCL Serial Port Data Clock for HDCP Communications to Transmitter. MDA Serial Port Data I/O to EEPROM with HDCP Keys—I2C Address is 0xA0. MCL Serial Port Data Clock to EEPROM with HDCP Keys.

DATA OUTPUTS

RED [7:0] Data Output, Red Channel. GREEN [7:0] Data Output, Green Channel. BLUE [7:0] Data Output, Blue Channel.

DATA CLOCK OUTPUT

DATACK Data Clock Output.

POWER SUPPLY

VD (3.3 V) Analog Power Supply.

VDD (1.8 V to 3.3 V) Digital Output Power Supply.

PVDD (1.8 V) Clock Generator Power Supply.

DVDD (1.8 V) Digital Input Power Supply.

GND Ground.

The supplies should be sequenced such that VD and VDD are never less than 300 mV below DVDD. At no time should DVDD be more than 300 mV greater than VD or VDD.

RTERM is the termination resistor used to drive the AD9398 internally to a precise 50 Ω termination for TMDS lines. This should be a 500 Ω 1% tolerance resistor.

The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed, but is different if the color space converter is used. When the sampling time is changed by adjusting the phase register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing relationship among the signals is maintained.

This is the main clock output signal used to strobe the output data and HSOUT into external logic. Four possible output clocks can be selected with Register 0x25 [7:6]. These are related to the pixel clock (1/2× pixel clock, 1× pixel clock, 2× frequency pixel clock, and a 90° phase shifted pixel clock). They are produced either by the internal PLL clock generator or EXTCLK and are synchronous with the pixel sampling clock. The polarity of DATACK can also be inverted via Register 0x24 [0]. The sampling time of the internal pixel clock can be changed by adjusting the phase register. When this is changed, the pixel-related DATACK timing is shifted as well. The DATA, DATACK, and HSOUT outputs are all moved, so the timing relationship among the signals is maintained.

These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible.

A large number of output pins (up to 27) switching at high speed (up to 150 MHz) generates many power supply transients (noise). These supply pins are identified separately from the V sensitive analog circuitry can be minimized. If the AD9398 is interfacing with lower voltage logic, V

pins, so output noise transferred into the

may be

connected to a lower supply voltage (as low as 1.8 V) for compatibility.

The most sensitive portion of the AD9398 is the clock generation circuitry. These pins provide power to the clock PLL and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins.

This supplies power to the digital logic.

The ground return for all circuitry on chip. It is recommended that the AD9398 be assembled on a single solid ground plane, with careful attention to ground current paths.

Rev. 0 | Page 8 of 44

AD9398

DESIGN GUIDE

GENERAL DESCRIPTION

The AD9398 is a fully integrated solution for receiving DVI/HDMI signals and is capable of decoding HDCPencrypted signals through connections to an external EEPROM. The circuit is ideal for providing an interface for HDTV monitors or as the front end to high performance video scan converters.

Implemented in a high performance CMOS process, the interface can capture signals with pixel rates of up to 150 MHz.

The AD9398 includes all necessary circuitry for decoding TMDS signaling including those encrypted with HDCP. Included in the output formatting is a color space converter (CSC), which accommodates any input color space and can output any color space. All controls are programmable via a 2wire serial interface. Full integration of these sensitive mixed signal functions makes system design straight-forward and less sensitive to the physical and electrical environments.

DIGITAL INPUTS

The digital control inputs (I2C) on the AD9398 operate to 3.3 V CMOS levels. In addition, all digital inputs, except the TMDS (HDMI/DVI) inputs, are 5 V tolerant (applying 5 V to them does not cause damage.) The TMDS input pairs (Rx0+/Rx0−, Rx1+/Rx1−, Rx2+/Rx2−, and RxC+/RxC−) must maintain a 100 Ω differential impedance (through proper PCB layout) from the connector to the input where they are internally terminated (50 Ω to 3.3 V). If additional ESD protection is desired, use of a California Micro Devices (CMD) CM1213 (among others) series low capacitance ESD protection offers 8 kV of protection to the HDMI TMDS lines.

SERIAL CONTROL PORT

The serial control port is designed for 3.3 V logic. However, it is tolerant of 5 V logic signals.

OUTPUT SIGNAL HANDLING

The digital outputs operate from 1.8 V to 3.3 V (VDD).

POWER MANAGEMENT

The AD9398 uses the activity detect circuits, the active interface bits in the serial bus, the active interface override bits, the power-down bit, and the power-down pin to determine the correct power state. There are four power states: full power, seek mode, auto power-down, and power-down. how the AD9398 determines the power mode to use and which circuitry is powered on/off in each of these modes. The powerdown command has priority and then the automatic circuitry. The power-down pin (Pin 81—polarity set by Register 0x26[3]) can drive the chip into four power-down options. Bit 2 and Bit 1 of Register 0x26 control these four options. Bit 0 controls whether the chip is powered down or the outputs are placed in high impedance mode (with the exception of SOG). Bit 7 to Bit 4 of Register 0x26 control whether the outputs, SOG, Sony Philips digital interface (SPDIF ) or Inter-IC sound bus (I IIS) outputs are in high impedance mode. See the Control Register Detail

section for the details.

Tabl e 7 summarizes

S or

2-Wire Serial

Table 7. Power-Down Mode Descriptions

Mode Power-Down

Full Power 1 1 X Everything Seek Mode 1 0 0 Everything Seek Mode 1 0 1 Serial bus, sync activity detect, SOG, band gap reference Power-Down 0 X Serial bus, sync activity detect, SOG, band gap reference

Power-down is controlled via Bit 0 in Serial Bus Register 0x26.

Sync detect is determined by OR’ing Bit 7 to Bit 2 in Serial Bus Register 0x15.

Auto power-down is controlled via Bit 7 in Serial Bus Register 0x27.

Inputs

Sync Detect

Auto PD Enable3Power-On or Comments

Rev. 0 | Page 9 of 44

AD9398

TIMING

The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally.

Figure 3 shows the timing operation of the AD9398.

PER

DCYCLE

DATAC

SKEW

DATA

HSOUT

05678-003

Figure 3. Output Timing

VSYNC FILTER AND ODD/EVEN FIELDS

The VSYNC filter is used to eliminate spurious VSYNCs, maintain a consistent timing relationship between the VSYNC and HSYNC output signals, and generate the odd/even field output.

The filter works by examining the placement of VSYNC with respect to HSYNC and, if necessary, slightly shifting it in time at the VSOUT output. The goal is to keep the VSYNC and HSYNC leading edges from switching at the same time, eliminating confusion as to when the first line of a frame occurs. Enabling the VSYNC filter is done with Register 0x21[5]. Use of the VSYNC filter is recommended for all cases, including interlaced video, and is required when using the HSYNC per VSYNC counter. illustrate even/odd field determination in two situations.

SYNC SEPARATOR THRESHOLD

FIELD 1 FIELD 0

QUADRAN

VSOUT

O/E FIELD

23 21431

HSIN

VSIN

Figure 4. VSYNC Filter—Even

Figure 4 and Figure 5

FIELD 1 FIELD 0

EVEN FIELD

05678-004

SYNC SEPARATOR THRESHOLD

FIELD 1 FIELD 0

QUADRAN

HSIN

VSIN

VSOUT

O/E FIELD

FIELD 1 FIELD 0

23 214431

ODD FIELD

Figure 5. VSYNC Filter—Odd

HDMI RECEIVER

The HDMI receiver section of the AD9398 allows the reception of a digital video stream, which is backward compatible with DVI and able to accommodate not only video of various formats (RGB, YCrCb 4:4:4, 4:2:2), but also up to eight channels of audio. Infoframes are transmitted carrying information about the video format, audio clocks, and many other items necessary for a monitor to use fully the information stream available.

The earlier digital visual interface (DVI) format was restricted to an RGB 24-bit color space only. Embedded in this data stream were HSYNCs, VSYNCs, and display enable (DE) signals, but no audio information. The HDMI specification allows transmission of all the DVI capabilities, but adds several YCrCb formats that make the inclusion of a programmable color space converter (CSC) a very desirable feature. With this, the scaler following the AD9398 can specify that it always wishes to receive a particular format—for instance, 4:2:2 YCrCb— regardless of the transmitted mode. If RGB is sent, the CSC can easily convert that to 4:2:2 YCrCb while relieving the scaler of this task.

In addition, the HDMI specification supports the transmission of up to eight channels of S/PDIF or I

S audio. The audio information is packetized and transmitted during the video blanking periods along with specific information about the clock frequency. Part of this audio information (audio infoframe) tells the user how many channels of audio are being transmitted, where they should be placed, information regarding the source (make, model), and other data.

DE GENERATOR

The AD9398 has an on-board generator for DE, for start of active video (SAV), and for end of active video (EAV), all of which are necessary for describing the complete data stream for a BT656-compatible output. In addition to this particular output, it is possible to generate the DE for cases in which a scaler is not used. This signal alerts the following circuitry as to which are displayable video pixels.

05678-005

Rev. 0 | Page 10 of 44

AD9398

4:4:4 TO 4:2:2 FILTER

The AD9398 contains a filter that allows it to convert a signal from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the maximum accuracy and fidelity of the original signal.

Input Color Space to Output Color Space

The AD9398 can accept a wide variety of input formats and either retain that format or convert to another. Input formats supported are:

• 4:4:4 YCrCb 8-bit

• 4:2:2 YCrCb 8-, 10-, and 12-bit

• RGB 8-bit

Output modes supported are:

• 4:4:4 YCrCb 8-bit

• 4:2:2 YCrCb 8-, 10-, and 12-bit

• Dual 4:2:2 YCrCb 8-bit

Color Space Conversion (CSC) Matrix

The CSC matrix in the AD9398 consists of three identical processing channels. In each channel, three input values are multiplied by three separate coefficients. Also included are an offset value for each row of the matrix and a scaling multiple for all values. Each value has a 13-bit, twos complement resolution to ensure the signal integrity is maintained. The CSC is designed to run at speeds up to 150 MHz, supporting resolutions up to 1080p at 60 Hz. With any-to-any color space support, formats such as RGB, YUV, YCbCr, and others are supported by the CSC.

The main inputs, R

, GIN, and BIN come from the 8- to 12-bit

inputs from each channel. These inputs are based on the input format detailed in CSC inputs is shown in

Tabl e 1 0 . The mapping of these inputs to the

Tabl e 8.

Table 8. CSC Port Mapping

Input Channel CSC Input Channel

R/CR R Gr/Y G B/CB BB

One of the three channels is represented in processing channel, the three inputs are multiplied by three separate coefficients marked a1, a2, and a3. These coefficients are divided by 4096 to obtain nominal values ranging from

−0.9998 to +0.9998. The variable labeled a4 is used as an offset control. The CSC_Mode setting is the same for all three processing channels. This multiplies all coefficients and offsets by a factor of 2

CSC_Mode

The functional diagram for a single channel of the CSC, as shown in

Figure 6, is repeated for the remaining G and B channels. The coefficients for these channels are b1, b2, b3, b4, c1, c2, c3, and c4.

a1[12:0]

4096

[11:0]

a2[12:0]

a3[12:0]

Figure 6. Single CSC Channel

A programming example and register settings for several common conversions are listed in the (CSC) Common Settings

section.

For a detailed functional description and more programming examples, refer to Application Note AN-795, AD9880 Color

Space Converter User's Guide.

Figure 6. In each

CSC_Mode[1:0]

a4[12:0]

×4

×2

OUT

Color Space Converter

[11:0]

05678-006

Rev. 0 | Page 11 of 44

AD9398

AUDIO PLL SETUP

Data contained in the audio infoframes, among other registers, define for the AD9398 HDMI receiver not only the type of audio, but the sampling frequency (f contains information about the N and CTS values used to recreate the clock. With this information, it is possible to regenerate the audio sampling frequency. The audio clock is regenerated by dividing the 20-bit CTS value into the TMDS clock, then multiplying by the 20-bit N value. This yields a multiple of the sampling frequency of either 128 × f It is possible for this to be specified up to 1024 × f

128 × f

VIDEO

CLOCK

N AND CTS VALUES ARE TRANSMITTED USING THE AUDIO CLOCK REGENERATION PACKET. VIDE CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.

DIVIDE

CYCLE

TIME

COUNTER

Figure 7. N and CTS for Audio Clock

). The audio infoframe also

SINK DEVICESOURCE DEVICE

CTS

TMDS

CLOCK

DIVIDE

CTS

MULTIPLY

or 256 × fS.

128 × f

05678-007

In order to provide the most flexibility in configuring the audio sampling clock, an additional PLL is employed. The PLL characteristics are determined by the loop filter design, the PLL charge pump current, and the VCO range setting. The loop filter design is shown in

Figure 8.

80nF

1.5kΩ

FILT

Figure 8. PLL Loop Filter Detail

05678-010

To fully support all audio modes for all video resolutions up to 1080p, it is necessary to adjust certain audio-related registers from their power-on default values.

Tabl e 9

describes these registers and gives the recommended settings.

Table 9. AD9398 Audio Register Settings

Recommended

Setting

Function Comments

0x01 7:0 0x00 PLL Divisor (MSBs) 0x02 7:4 0x40 PLL Divisor (LSBs) 0x03

7:6 01 VCO Range 5:3 010 Charge Pump Current 2 1 PLL Enable

0x34 4 0

Audio Frequency Mode Override

0x58

7 1 PLL Enable This enables the analog PLL to be used for audio MCLK generation. 6:4 011 MCLK PLL Divisor

3 0 N/CTS Disable The N and CTS values should always be enabled. 2:0 0** MCLK Sampling Frequency 000 = 128 × f

The analog video PLL is also used for the audio clock circuit when in HDMI mode. This is done automatically.

In HDMI mode, this bit enables a lower frequency to be used for audio MCLK generation.

Allows the chip to determine the low frequency mode of the audio PLL.

When the analog PLL is enabled for MCLK generation, another frequency divider is provided. These bits set the divisor to 4.

001 = 256 × f 010 = 384 × f 011 = 512 × f

Rev. 0 | Page 12 of 44

AD9398

AUDIO BOARD LEVEL MUTING

The audio can be muted through the infoframes or locally via the serial bus registers. This can be controlled with Register R0x57, Bits [7:4].

AVI Infoframes

The HDMI TMDS transmission contains infoframes with specific information for the monitor such as:

• Audio information

• 2 channels to 8 channels of audio identified

• Audio coding

• Audio sampling frequency

• Speaker placement

• N and CTS values (for reconstruction of the audio)

• Muting

• Source information

• CD

• SACD

• DVD

This information is the fundamental difference between DVI and HDMI transmissions and is located in read-only registers R0x5A to R0xEE. In addition to this information, registers are provided to indicate that new information has been received. Registers with addresses ending in 0xX7 or 0xXF beginning at R0x87 contain the new data flag (NDF) information. These registers contain the same information and all are reset once any of them are read. Although there is no external interrupt signal, it is very easy for the user to read any of these registers to see if there is new information to be processed.

OUTPUT DATA FORMATS

The AD9398 supports 4:4:4, 4:2:2, double data rate (DDR), and BT656 output formats. Register 0x25[3:0] controls the output mode. These modes and the pin mapping are listed in

Table 1 0.

• Video information

• Video ID code (per CEA861B)

• Color space

• Aspect ratio

• Horizontal and vertical bar information

• MPEG frame information (I, B, or P frame)

• Vendor (transmitter source) name and product model

Table 10.

Port Red Green Blue Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

4:4:4 Red/Cr [7:0] Green/Y [7:0] Blue/Cb [7:0] 4:2:2 CbCr [7:0] Y [7:0] 4:4:4 DDR

4:2:2 to 12 CbCr [11:0] Y [11:0]

Arrows in the table indicate clock edge. Rising edge of clock = ↑, falling edge = ↓.

DDR ↑ 1 G [3:0] DDR ↑ B [7:4] DDR ↑ B [3:0] DDR 4:2:2 ↑ CbCr [11:0] DDR

↓ R [7:0] DDR ↓ G [7:4] DDR 4:2:2 ↓ Y,Y [11:0]

DDR 4:2:2

↑ CbCr ↓ Y, Y

Rev. 0 | Page 13 of 44

AD9398

2-WIRE SERIAL REGISTER MAP

The AD9398 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port.

Table 11. Control Register Map

Read/Write

Bits

Default Value

This bit enables a lower frequency to be used for audio MCLK generation.

HSYNC Source Override

Channel Select Override

HSYNC Polarity Override

VSYNC Polarity Override

HSYNCs per VSYNC MSB

Rev. 0 | Page 14 of 44

0 = auto HSYNC source.

0 = auto-channel select.

0 = auto HSYNC polarity.

0 = auto VSYNC polarity.

MSB of HSYNCs per VSYNC.

HSYNC duration. Sets the duration of the output HSYNC in pixel clocks.

or Read

Hex Address

0x00 Read [7:0] 00000000 Chip Revision Chip revision ID. Revision is read [7:4]. [3:0]. 0x001 Read/Write [7:0] 01101001 PLL Divider MSB PLL feedback divider value MSB. 0x02 Read/Write [7:4] 1101**** PLL Divider PLL feedback divider value. 0x03 Read/Write [7:6] 01****** VCO Range VCO range. [5:3] **001*** Charge Pump Charge pump current control for PLL. [2] *****0** PLL Enable

0x11 Read/Write [7] 0******* HSYNC Source 0 = HSYNC. 1 = SOG. [6] *0******

1 = manual HSYNC source. [5] **0***** VSYNC Source 0 = VSYNC. 1 = VSYNC from SOG. [4] ***0**** VSYNC Source Override 0 = auto HSYNC source. 1 = manual HSYNC source. [3] ****0*** Channel Select 0 = Channel 0. 1 = Channel 1. [2] *****0**

1 = manual channel select. [1] ******0* Interface Select 0 = analog interface. 1 = digital interface. [0] *******0 Interface Override 0 = auto-interface select. 1 = manual interface select. 0x12 Read/Write [7] 1******* Input HSYNC Polarity 0 = active low. 1 = active high. [6] *0******

1 = manual HSYNC polarity. [5] **1***** Input VSYNC Polarity 0 = active low. 1 = active high. [4] ***0****

1 = manual VSYNC polarity. 0x17 Read [3:0] ****0000

0x18 Read [7:0] 00000000 HSYNCs per VSYNC HSYNCs per VSYNC count. 0x22 Read/Write [7:0] 4 VSYNC Duration VSYNC duration. 0x23 Read/Write [7:0] 32 HSYNC Duration

0x24 Read/Write [7] 1******* HSYNC Output Polarity Output HSYNC polarity. 0 = active low out. 1 = active high out. [6] *1****** VSYNC Output Polarity Output VSYNC polarity 0 = active low out. 1 = active high out.

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