Analog Devices AD9397 Service Manual

A

DVI Display Interface

FEATURES

DVI interface

Supports high-bandwidth digital content protection RGB to YCbCr 2-way color conversion

1.8 V/3.3 V power supply 100-lead, Pb-free LQFP RGB and YCbCr output formats

Digital video interface

DVI 1.0 150 MHz DVI receiver Supports high-bandwidth digital content protection

(HDCP 1.1)

APPLICATIONS

Advanced TVs HDTVs Projectors LCD monitors

SCL

SDA

Rx0+ Rx0– Rx1+ Rx1– Rx2+

Rx2– RxC+ RxC–

RTERM

DDCSCL DDCSD

MCL MDA

AD9397

FUNCTIONAL BLOCK DIAGRAM

SERIAL REGISTER

AND

POWER MANAGEMENT

DIGITAL INTERFACE

DVI RECEIVER

HDCP

R/G/B 8 × 3 OR YCbCr

2

DATACK DE HSYNC

VSYNC

Figure 1.

AD9397

R/G/B 8 × 3 YCbCr (4:2:2

OR 4:4:4) 2

RGB ↔YCbCr MATRIX

DATACK

HSOUT VSOUT

SOGOUT

DE

05691-001

GENERAL DESCRIPTION

The AD9397 is a digital visual interface (DVI) receiver integrated on a single chip. Also included is support for high bandwidth digital content protection (HDCP) with internal key storage.

The AD9397 contains a DVI 1.0-compatible receiver and supports all HDTV formats (up to 1080p and 720p) and display resolutions up to SXGA (1280 × 1024 @ 80 Hz). The receiver features an intrapair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays can receive encrypted

video content. The AD9397 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP 1.1 protocol.

Fabricated in an advanced CMOS process, the AD9397 is provided in a space-saving, 100-lead, surface-mount, Pb-free plastic LQFP and is specified over the 0°C to 70°C temperature range.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9397

TABLE OF CONTENTS

Features .............................................................................................. 1

DVI Receiver............................................................................... 11

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Digital Interface Electrical Characteristics ............................... 4

Absolute Maximum Ratings............................................................ 6

Explanation of Test Levels........................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Design Guide................................................................................... 10

General Description................................................................... 10

Digital Inputs ..............................................................................10

Serial Control Port ..................................................................... 10

DE Generator .............................................................................. 11

4:4:4 to 4:2:2 Filter...................................................................... 12

Output Data Formats................................................................. 12

2-Wire Serial Register Map ........................................................... 13

2-Wire Serial Control Register Details ........................................ 18

Chip Identification..................................................................... 18

BT656 Generation...................................................................... 20

Macrovision................................................................................. 21

Color Space Conversion............................................................ 21

2-Wire Serial Control Port ............................................................ 23

Data Transfer via Serial Interface............................................. 23

Serial Interface Read/Write Examples ..................................... 24

PCB Layout Recommendations.................................................... 25

Power Supply Bypassing ............................................................ 25

Outputs (Both Data and Clocks).............................................. 25

Output Signal Handling............................................................. 10

Power Management.................................................................... 10

Timing ..............................................................................................11

HSYNC Timing ..........................................................................11

VSYNC Filter and Odd/Even Fields ........................................ 11

REVISION HISTORY

10/05—Revision 0: Initial Version

Digital Inputs .............................................................................. 25

Color Space Converter (CSC) Common Settings...................... 26

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 28

Rev. 0 | Page 2 of 28

AD9397

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VDD, VD = 3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum.

Table 1.

AD9397KSTZ-100 AD9397KSTZ-150

Parameter Temp Test Level Min Typ Max Min Typ Max Unit

RESOLUTION 8 8 Bits

Data-to-Clock Skew Full IV −0.5 +2.0 −0.5 +2.0 ns Serial Port Timing

t

BUFF

t

STAH

t

DHO

t

DAL

t

DAH

t

DSU

t

STASU

t

STOSU

Full VI 4.7 4.7 μs Full VI 4.0 4.0 μs Full VI 0 0 μs Full VI 4.7 4.7 μs Full VI 4.0 4.0 μs Full VI 250 250 ns Full VI 4.7 4.7 μs Full VI 4.0 4.0 μs

DIGITAL INPUTS (5 V TOLERANT)

Input Voltage, High (VIH) Full VI 2.6 2.6 V Input Voltage, Low (VIL) Full VI 0.8 0.8 V Input Current, High (IIH) Full V −82 −82 μA Input Current, Low (IIL) Full V 82 82 μA Input Capacitance 25°C V 3 3 pF

DIGITAL OUTPUTS

Output Voltage, High (VOH) Full VI VDD − 0.1 VDD − 0.1 V Output Voltage, Low (VOL) Full VI 0.4 0.4 V Duty Cycle, DATACK Full V 45 50 55 45 50 55 % Output Coding Binary Binary

POWER SUPPLY

VD Supply Voltage Full IV 3.15 3.3 3.47 3.15 3.3 3.47 V DVDD Supply Voltage Full IV 1.7 1.8 1.9 1.7 1.8 1.9 V VDD Supply Voltage Full IV 1.7 3.3 3.47 1.7 3.3 3.47 V PVDD Supply Voltage Full IV 1.7 1.8 1.9 1.7 1.8 1.9 V ID Supply Current (VD) 25°C VI 260 300 330 mA I

Supply Current (DVDD) 25°C VI 45 60 85 mA

DVDD

IDD Supply Current (VDD) IP

Supply Current (P

VDD

1

) 25°C VI 10 15 20 mA

VDD

25°C VI 37 1002 1302mA

Total Power Full VI 1.1 1.4 1.15 1.4 W Power-Down Dissipation Full VI 130 130 mW

THERMAL CHARACTERISTICS

θJA Junction to Ambient V 35 35 °C/W

1

DATACK load = 15 pF, data load = 5 pF.

2

Specified current and power values with a worst-case pattern (on/off).

Rev. 0 | Page 3 of 28

AD9397

DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS

VDD = VD = 3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum.

Table 2.

Test AD9397KSTZ-100 AD9397KSTZ-150 Parameter Level Conditions Min Typ Max Min Typ Max Unit

RESOLUTION 8 8 Bit DC DIGITAL I/O SPECIFICATIONS

High Level Input Voltage, (VIH) VI 2.5 2.5 V Low Level Input Voltage, (VIL) VI 0.8 0.8 V High Level Output Voltage, (VOH) VI VDD − 0.1 V Low Level Output Voltage, (VOL) VI VDD − 0.1 0.1 0.1 V

DC SPECIFICATIONS

Output High Level IV Output drive = high 36 36 mA I

, (V

OHD

Output Low Level IV Output drive = high 12 12 mA I

OLD

DATACK High Level IV Output drive = high 40 40 mA V DATACK Low Level IV Output drive = high 30 30 mA V

Differential Input Voltage, Single-Ended

POWER SUPPLY

VD Supply Voltage IV 3.15 3.3 3.47 3.15 3.3 3.47 V VDD Supply Voltage IV 1.7 3.3 347 1.7 3.3 347 V DVDD Supply Voltage IV 1.7 1.8 1.9 1.7 1.8 1.9 V PVDD Supply Voltage IV 1.7 1.8 1.9 1.7 1.8 1.9 V IVD Supply Current (Typical Pattern) I

VDD

I

DVDD

I

PVDD

Power-Down Supply Current (IPD) VI 130 130 mA

= VOH) IV Output drive = low 24 24 mA

OUT

, (V

= VOL) IV Output drive = low 8 8 mA

OUT

, (V

OHC

OLC

= VOH) IV Output drive = low 20 20 mA

OUT

, (V

= VOL) IV Output drive = low 15 15 mA

OUT

IV 75 700 75 700 mV

Amplitude

1

Supply Current (Typical Pattern)

V 80 100 80 110 mA

2

V 40 1003 55 1753mA

1, 4

V 88 110 110 145 mA

1

V 26 35 30 40 mA

Rev. 0 | Page 4 of 28

AD9397

Test AD9397KSTZ-100 AD9397KSTZ-150 Parameter Level Conditions Min Typ Max Min Typ Max Unit

AC SPECIFICATIONS

Intrapair (+ to −) Differential Input Skew

(T

)

DPS

Channel to Channel Differential Input

CCS

)

Skew (T

Low-to-High Transition Time for Data

and Controls (D

LHT

)

IV

Low-to-High Transition Time for DATACK

)

(D

LHT

IV

High-to-Low Transition Time for Data

and Controls (D

HLT

)

IV

High-to-Low Transition Time for DATACK

(D

)

HLT

IV

Clock to Data Skew5 (T Duty Cycle, DATACK DATACK Frequency (F

1

The typical pattern contains a gray scale area, output drive = high. Worst-case pattern is alternating black and white pixels.

2

The typical pattern contains a gray scale area, output drive = high.

3

Specified current and power values with a worst-case pattern (on/off).

4

DATACK load = 10 pF, data load = 5 pF.

5

Drive strength = high.

) IV −0.5 +2.0 −0.5 +2.0 ns

SKEW

5

) VI 20 150 MHz

CIP

IV 360 ps

IV 6

Clock Period

IV

Output drive = high; C

= 10 pF

L

Output drive = low;

= 5 pF

C

L

Output drive = high;

= 10 pF

C

L

Output drive = low; C

= 5 pF

L

Output drive = high;

= 10 pF

C

L

Output drive = low;

= 5 pF

C

L

Output drive = high; C

= 10 pF

L

Output drive = low;

= 5 pF

C

L

900 ps

1300 ps

650 ps

1200 ps

850 ps

1250 ps

800 ps

1200 ps

IV 45 50 55 %

Rev. 0 | Page 5 of 28

AD9397

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

V

D

VDD 3.6 V DV

DD

PV

DD

Analog Inputs VD to 0.0 V Digital Inputs 5 V to 0.0 V Digital Output Current 20 mA Operating Temperature Range −25°C to + 85°C Storage Temperature Range −65°C to + 150°C Maximum Junction Temperature 150°C Maximum Case Temperature 150°C

3.6 V

1.98 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

EXPLANATION OF TEST LEVELS

Table 4.

Level Test

I 100% production tested. II

III Sample tested only. IV

V Parameter is a typical value only. VI

100% production tested at 25°C and sample tested at specified temperatures.

Parameter is guaranteed by design and characterization testing.

100% production tested at 25°C; guaranteed by design and characterization testing.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 6 of 28

AD9397

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND GREEN 7 GREEN 6 GREEN 5 GREEN 4 GREEN 3 GREEN 2 GREEN 1 GREEN 0

V

GND

BLUE 7 BLUE 6 BLUE 5 BLUE 4 BLUE 3 BLUE 2 BLUE 1 BLUE 0

NC NC NC

NC CTL3 CTL2

VDDRED 0

RED 1

RED 2

RED 3

RED 4

RED 5

RED 6

RED 7

GND

VDDDATACKDE

HSOUTNCVSOUT

FIELD

SDA

SCL

PWRDN

VDNC

99

98

100

1 2 3

4

5

6

7 8

9

10

DD

11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

PIN 1

95

93

97

96

92

94

898887

91

90

84

82

86

85

81

80

83

79

AD9397

TOP VIEW

(Not to Scale)

GNDNCV

787776

D

75

GND

74

NC

73

NC

72

V

D

71

NC

70

NC

69

GND

68

NC

67

V

D

66

NC

65

GND

64

NC

63

NC

62

NC

61

NC

60

NC

59

PV

DD

58

GND

57

NC

56

PV

DD

55

GND

54

PV

DD

53

GND

52

MDA

51

MCL

NC = NO CONNECT

26

CTL127CTL0

28

NC

29

GND

30

DV

31

33

34

32

D

DD

V

GND

Rx0–

DV

35

Rx0+

36

GND

37

38

39

42

41

Rx2+

GND

44

43

RxC–

RxC+

Rx1–

Rx1+

GND

40

Rx2–

48

49

47

GND

DV

50

DD

DDCSCL

DDCSDA

05691-002

45

46

D

V

RTERM

Figure 2. Pin Configuration

Table 5. Complete Pinout List

Pin Type Pin No. Mnemonic Function Value

INPUTS 81 PWRDN Power-Down Control 3.3 V CMOS DIGITAL VIDEO DATA INPUTS 35 Rx0+ Digital Input Channel 0 True TMDS 34 Rx0− Digital Input Channel 0 Complement TMDS 38 Rx1+ Digital Input Channel 1 True TMDS 37 Rx1− Digital Input Channel 1 Complement TMDS 41 Rx2+ Digital Input Channel 2 True TMDS 40 Rx2− Digital Input Channel 2 Complement TMDS DIGITAL VIDEO CLOCK INPUTS 43 RxC+ Digital Data Clock True TMDS 44 RxC− Digital Data Clock Complement TMDS OUTPUTS 92 to 99 RED [7:0] Outputs of Red Converter, Bit 7 is MSB V 2 to 9 GREEN [7:0] Outputs of Green Converter, Bit 7 is MSB V 12 to 19 BLUE [7:0] Outputs of Blue Converter, Bit 7 is MSB V 89 DATACK Data Output Clock V 87 HSOUT HSYNC Output Clock (Phase-Aligned with DATACK) V 85 VSOUT VSYNC Output Clock (Phase-Aligned with DATACK) V 84 O/E FIELD Odd/Even Field Output V 27, 26, 25, 24 CTL(0 to 3) Control 0, 1, 2, 3 V

DD

Rev. 0 | Page 7 of 28

AD9397

Pin Type Pin No. Mnemonic Function Value

POWER SUPPLY

80, 76, 72, 67,

V

D

45, 33 100, 90, 10 V 59, 56, 54 PV 48, 32, 30 DV

DD

GND Ground 0 V CONTROL 83 SDA Serial Port Data I/O 3.3 V CMOS 82 SCL Serial Port Data Clock 3.3 V CMOS HDCP 49 DDCSCL HDCP Slave Serial Port Data Clock 3.3 V CMOS 50 DDCSDA HDCP Slave Serial Port Data I/O 3.3 V CMOS 51 MCL HDCP Master Serial Port Data Clock 3.3 V CMOS 52 MDA HDCP Master Serial Port Data I/O 3.3 V CMOS DATA ENABLE 88 DE Data Enable 3.3 V CMOS RTERM 46 RTERM Sets Internal Termination Resistance 500 Ω

Table 6. Pin Function Descriptions

Pin Description

INPUTS

Rx0+ Digital Input Channel 0 True. Rx0− Digital Input Channel 0 Complement. Rx1+ Digital Input Channel 1 True. Rx1− Digital Input Channel 1 Complement. Rx2+ Digital Input Channel 2 True. Rx2− Digital input Channel 2 Complement.

These six pins receive three pairs of transition minimized differential signaling (TMDS ) pixel data

(at 10× the pixel rate) from a digital graphics transmitter.

RxC+ Digital Data Clock True. RxC− Digital Data Clock Complement.

This clock pair receives a TMDS clock at 1× pixel data rate.

PWRDN Power-Down Control/Three-State Control.

The function of this pin is programmable via Register 0x26 [2:1].

RTERM

RTERM is the termination resistor used to drive the AD9397 internally to a precise 50 Ω termination for

TMDS lines. This should be a 500 Ω 1% tolerance resistor. OUTPUTS

HSOUT Horizontal Sync Output.

A reconstructed and phase-aligned version of the HSYNC input. Both the polarity and duration of this

output can be programmed via serial bus registers. By maintaining alignment with DATACK and Data,

data timing with respect to horizontal sync can always be determined.

VSOUT Vertical Sync Output.

The separated VSYNC from a composite signal or a direct pass through of the VSYNC signal. The polarity

of this output can be controlled via the serial bus bit (Register 0x24 [6]).

FIELD

Odd/Even Field Bit for Interlaced Video. This output identifies whether the current field (in an interlaced

signal) is odd or even. The polarity of this signal is programmable via Register 0x24[4].

DE Data Enable that defines valid video. Can be received in the signal or generated by the AD9397. CTL(3-0)

Control 3, Control 2, Control 1, and Control 0 are output from the DVI stream. Refer to the DVI 1.0

specification for explanation. SERIAL PORT

SDA Serial Port Data I/O for Programming AD9397 Registers—I2C Address is 0x98. SCL Serial Port Data Clock for Programming AD9397 Registers. DDCSDA Serial Port Data I/O for HDCP Communications to Transmitter—I2C Address is 0x74 or 0x76. DDCSCL Serial Port Data Clock for HDCP Communications to Transmitter. MDA Serial Port Data I/O to EEPROM with HDCP Keys—I2C Address is 0xA0. MCL Serial Port Data Clock to EEPROM with HDCP Keys.

Analog Power Supply and DVI Terminators 3.3 V

Output Power Supply 1.8 V to 3.3 V PLL Power Supply 1.8 V Digital Logic Power Supply 1.8 V

Rev. 0 | Page 8 of 28

AD9397

Pin Description

DATA OUTPUTS

RED [7:0] Data Output, Red Channel. GREEN [7:0] Data Output, Green Channel. BLUE [7:0] Data Output, Blue Channel.

The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed, but is different if the color space converter is used. When the sampling time is changed by adjusting the phase register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing relationship among the signals is maintained.

DATA CLOCK OUTPUT

DATACK Data Clock Output.

This is the main clock output signal used to strobe the output data and HSOUT into external logic. Four possible output clocks can be selected with Register 0x25 [7:6]. These are related to the pixel clock (1/2× pixel clock, 1× pixel clock, 2× frequency pixel clock, and a 90° phase shifted pixel clock). They are produced either by the internal PLL clock generator or EXTCLK and are synchronous with the pixel sampling clock. The polarity of DATACK can also be inverted via Register 0x24 [0]. The sampling time of the internal pixel clock can be changed by adjusting the phase register. When this is changed, the pixelrelated DATACK timing is shifted as well. The DATA, DATACK, and HSOUT outputs are all moved, so the

POWER SUPPLY

1

VD (3.3 V) Analog Power Supply.

VDD (1.8 V to 3.3 V) Digital Output Power Supply.

PVDD (1.8 V) Clock Generator Power Supply.

DVDD (1.8 V) Digital Input Power Supply.

GND Ground.

1

The supplies should be sequenced such that VD and VDD are never less than 300 mV below DVDD. At no time should DVDD be more than 300 mV greater than VD or VDD.

timing relationship among the signals is maintained.

These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible.

A large number of output pins (up to 27) switching at high speed (up to 150 MHz) generates many power supply transients (noise). These supply pins are identified separately from the V

pins, so output noise

D

transferred into the sensitive analog circuitry can be minimized. If the AD9397 is interfacing with lower voltage logic, VDD may be connected to a lower supply voltage (as low as 1.8 V) for compatibility.

The most sensitive portion of the AD9397 is the clock generation circuitry. These pins provide power to the clock PLL and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins.

This supplies power to the digital logic.

The ground return for all circuitry on chip. It is recommended that the AD9397 be assembled on a single solid ground plane, with careful attention to ground current paths.

Rev. 0 | Page 9 of 28