Analog Devices AD9389 Service Manual

800 MHz High Performance

A

G

FEATURES

HDMI/DVI transmitter compatible with HDMI 1.1 and

HDCP 1.1 Single 1.8 V power supply Video/audio inputs are 3.3 V tolerant Supports HDCP 1.1 with encrypted internal HDCP key

storage 80-lead LQFP Digital video

80 MHz operation supports all video formats from 480i to

1080i and 720p Programmable 2-way color space converter Supports RGB, YCbCr, DDR, ITU656 formats Auto input video format detection

Digital audio

Supports standard S/PDIF for stereo or compressed audio

up to 192 kHz 8-channel LPCM I

Special features for easy system design

On-chip MPU to perform HDCP operations On-chip I

2

5 V tolerant I No audio master clock needed for S/PDIF support

2

S audio up to 192 kHz

C® master to handle EDID reading

2

C and MPD I/Os, no extra device needed

CLK VSYNC HSYNC

D[23:0]

S/PDIF

MCLK

I2S[3:0]

DE

HDMI™/DVI Transmitter

AD9389

FUNCTIONAL BLOCK DIAGRAM

SD

HTP

REGISTER

CONFIGURATION

LOGIC

VIDEO

DATA

CAPTURE

AUDIO

DATA

CAPTURE

SCL

I2C

SLAVE

COLOR SPACE

CONVERSION

4:2:2

TO

4:4:4

CONVERSION

2

I

C

MASTER

HDCP

CIPHER

MASK

Figure 1.

XOR

HDCP

CONTROLLER

HDM

ITX

CORE

AD9389

DDSDA DDCSCL

SWING_ADJ

Tx0[1:0] Tx1[1:0] Tx2[1:0] TxC[1:0]

05724-001

APPLICATIONS

DVD players and recorders Digital set-top boxes AV receivers Digital cameras and camcorders

GENERAL DESCRIPTION

The AD9389 is an 80 MHz high-definition multimedia interface (HDMI 1.1) transmitter. It supports HDTV formats up to 1080i and 720p, and graphic resolutions up to XGA (1024 × 768 @ 75 Hz). With the inclusion of HDCP, the AD9389 allows the secure transmission of protected content as specified by the HDCP 1.1 protocol.

2

The AD9389 supports both S/PDIF and 8-channel I

2

Its high fidelity 8-channel I

S can transmit either stereo or

7.1 surround audio at 192 kHz. The S/PDIF can carry stereo LPCM (linear pulse code modulation) audio or compressed audio including Dolby® Digital, DTS®, and THX®.

S audio.

The AD9389 helps to reduce system design complexity and cost by incorporating such features as HDCP master, I

2

C master for

EDID reading, a single 1.8 V power supply, and 5 V tolerance

2

on I

C and hot plug detect pins.

Fabricated in an advanced CMOS process, the AD9389 is provided in a space-saving, 80-lead, surface-mount, Pb-free plastic LQFP and is specified over the 0°C to 70°C temperature range.

EVALUATION KITS AND OTHER RESOURCES

Evaluation kits, reference design schematics, software quick start guide, and codes are available from the Analog Devices local sales and marketing personnel.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9389

REVISION HISTORY

1/06—Revision 0: Initial Version

Serial Interface Read/Write Examples..................................... 41

PCB Layout Recommendations.................................................... 42

Power Supply Bypassing ............................................................ 42

Digital Inputs .............................................................................. 42

Color Space Converter (CSC) Common Settings...................... 43

Outline Dimensions ....................................................................... 45

Ordering Guide .......................................................................... 45

Rev. 0 | Page 2 of 48

AD9389

ELECTRICAL SPECIFICATIONS

Table 1.

Parameter Temp Test Level1Min Typ Max Unit

DIGITAL INPUTS

Input Voltage, High (VIH) Full VI 1.4 V Input Voltage, Low (VIL) Full VI 0.7 V Input Current, High (VIH) Full V −1.0 mA Input Current, Low (VIL) Full V +1.0 mA Input Capacitance 25°C V 3 pF

DIGITAL OUTPUTS

Output Voltage, High (VOH) Full VI AVDD − 0.1 V Output Voltage, Low (VOL) Full VI 0.4 V

THERMAL CHARACTERISTICS

θ

Junction-to-Case

JC

Thermal Resistance V 25 °C/W

θJA Junction-to-Ambient

Thermal Resistance V 30 °C/W

Ambient Temperature Full V 0 25 70 °C

DC SPECIFICATIONS

Input Leakage Current, I

IL

Input Clamp Voltage (−16 mA) 25°C V −0.8 V Input Clamp Voltage (+16 mA) 25°C V +0.8 Differential High Level Output Voltage V AV Differential Output Short-Circuit Current V 10 µA

POWER SUPPLY

VDD (All) Supply Voltage Full IV 1.71 1.8 1.89 V VDD Supply Voltage Noise Full V 50 mV p-p Complete Power-Down Current

(Everything Except I

2

C)

Quiet Power Down Current

(Monitor Detect On)

Transmitter Supply Current

(27 MHz Typical Random Pattern)

Transmitter Supply Current

(80 MHz Typical Random Pattern)

Transmitter Total Power

(80 MHz Single Pixel Stripe Pattern; Worst Case Operating Conditions)

AC SPECIFICATIONS

CLK Frequency 25°C IV 13.5 80 MHz CLK Duty Cycle 25°C VII 40 60 % Worst Case CLK Input Jitter Full VI 1.0 ns Setup Time to CLK Falling Edge VI TBD TBD ns Hold Time to CLK Falling Edge VI TBD TBD ns TMDS Differential Swing VII 800 1000 1200 mV VSYNC and HSYNC Delay from DE Falling Edge VI 1 UI VSYNC and HSYNC Delay to DE Rising Edge VI 1 UI DE High Time 25°C VI 8191 UI DE Low Time 25°C VI 138 UI Differential Output Swing Low-to-High

Transition Time

Differential Swing Output High-to-Low

Transition Time

25°C VI −10 +10 µA

CC

V

25°C IV 6 13 mA

25°C VI 7 mA

25°C VI 165 mA

25°C IV 185 205 mA

Full VI 430 mW

25°C VII 75 490 ps

Rev. 0 | Page 3 of 48

AD9389

Parameter Temp Test Level1Min Typ Max Unit

AUDIO AC TIMING

Sample Rate (I2S and S/PDIF) Full IV 32 192 kHz I2S Cycle Time 25°C IV 1 UI I2S Setup Time 25°C IV 15 ns I2S Hold Time 25°C IV 0 ns Audio Pipeline Delay 25°C IV 75 s

1

See Table 3.

Rev. 0 | Page 4 of 48

AD9389

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Digital Inputs 5 V to 0.0 V Digital Output Current 20 mA Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Maximum Case Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

EXPLANATION OF TEST LEVELS

Table 3.

Level Test

I 100% production tested.

II

III Sample tested only.

IV

V Parameter is a typical value only.

VI

VII Limits defined by HDMI specification.

100% production tested at 25°C and sample tested at specified temperatures.

Parameter is guaranteed by design and characterization testing.

100% production tested at 25°C; guaranteed by design and characterization testing.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 5 of 48

AD9389

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DD

GND79GND78D177D276D375D474D573D672D771D870D969D1068D1167D1266D1365D1464DV

80

DD

DV

63

62

61

DV

DE

HSYNC

VSYNC

CLK

S/PDIF

MCLK

I2S0 I2S1 I2S2 I2S3

SCLK

LRCLK

GND

PV

GND

GND PV PV

1

DD

D0

10 11 12 13 14 15 16

DD

17 18 19

DD

20

DD

PIN 1

2 3 4 5 6 7 8 9

21

22

23

24

25

26

DD

PV

DD

EXT_SW

HPD

AV

GND

27

GND

(Not to Scale)

28

29

TxC–

TxC+

AD9389

TOP VIEW

30

31

DD

Tx0–

AV

32

33

34

35

36

37

38

GND

Tx0+

PD/A0

DD

Tx1–

Tx2–

Tx1+

Tx2+

AV

60

GND

59

GND

58

D15

57

D16

56

D17

55

D18

54

D19

53

D20

52

D21

51

D22

50

D23

49

NC

48

NC

47

SDA

46

SCL

45

DDSDA

44

DDCSCL

43

GND

42

GND

41

AV

DD

39

40

INT

GND

05724-002

Figure 2. Pin Configuration

Table 4. Complete Pinout List

Pin Type Pin No. Mnemonic Description Value

INPUTS

50 to 58,

D[23:0] Video Data Input 1.8 V CMOS

65 to 78, 2 6 CLK Video Clock Input 1.8 V CMOS 3 DE Data Enable Bit for Digital Video 1.8 V CMOS 4 HSYNC Horizontal SYNC Input 1.8 V CMOS 5 VSYNC Vertical SYNC Input 1.8 V CMOS 23 EXT_SW Differential Output Swing Adjustment 1.8 V CMOS 25 HPD Hot Plug Detect Signal 1.8 V CMOS 7 S/PDIF S/PDIF (Sony/Philips Digital Interface) Audio Input Pin 1.8 V CMOS 8 MCLK Audio Reference Clock, from 128 × fS to 512 × f

S

1.8 V CMOS 12 to 9 I2S[3:0] I2S Audio Data Inputs 1.8 V CMOS 13 SCLK I2S Audio Clock 1.8 V CMOS 14 LRCLK Left/Right Channel Selection 1.8 V CMOS 33 PD/A0 Power-Down Control 1.8 V CMOS

OUTPUTS

28, 27 TxC+ Differential Clock Output TMDS TxC− Differential Clock Output Complement 38, 37 Tx2+ Differential Output Channel 2 TMDS Tx2− Differential Output Channel 2 Complement 35, 34 Tx1+ Differential Output Channel 1 TMDS Tx1− Differential Output Channel 1 Complement

Rev. 0 | Page 6 of 48

AD9389

Pin Type Pin No. Mnemonic Description Value

31, 30 Tx0+ Differential Output Channel 0 TMDS Tx0− Differential Output Channel 0 Complement 40 INT Interrupt 1.8 V CMOS

POWER SUPPLY

24, 29, 36, 41 AV 1, 61, 62, 63, 64 DV 16, 19, 20, 21 PV

15, 17, 18, 22,

DD

GND Ground 0 V 26, 32, 39, 42, 43, 59, 60, 79, 80

CONTROL

47 SDA Serial Port Data I/O 3.3 V CMOS 46 SCL Serial Port Data Clock (100 kHz Maximum) 3.3 V CMOS 45 DDSDA Serial Port Data I/O to Receiver 3.3 V CMOS 44 DDCSCL Serial Port Data Clock to Receiver 3.3 V CMOS

NO CONNECT 48, 49 NC No Connect.

Table 5. Pin Function Descriptions

Pin Mnemonic Description

OUTPUTS

TxC+ Differential Clock Output at Pixel Clock Rate; Transition Minimized Differential Signaling (TMDS). TxC− Differential Clock Output Complement. Tx2+ Differential Output of the Red Data at 10× the Pixel Clock Rate; TMDS. Tx2− Differential Red Output Complement. Tx1+ Differential Output of the Green Data at 10× the Pixel Clock Rate; TMDS. Tx1− Differential Green Output Complement. Tx0+ Differential Output of the Blue Data at 10× the Pixel Clock Rate; TMDS. Tx0− Differential Blue Output Complement. INT Interrupt.

SERIAL PORT (2-WIRE)

SDA Serial Port Data I/O. SCL Serial Port Data Clock. DDSDA Serial Port Data I/O Master to Receiver. DDCSCL Serial Port Data Clock Master to Receiver.

For a full, functional description of the 2-wire serial register, refer to the 2-Wire Serial Control Port section.

INPUTS

D[23:0] Digital Input in RGB or YCbCr Format. CLK Video Clock Input. DE Data Enable for Video Data. HSYNC Horizontal Sync Input. VSYNC Vertical Sync Input. This is the input for vertical sync. EXT_SW Place an 887 Ω resistor (1% tolerance) between this pin and ground. HPD Hot Plug Detect. This indicates to the interface whether the receiver is connected. S/PDIF S/PDIF Audio Input. This is the audio input from a Sony/Philips Digital Interface. MCLK Audio Reference Clock. Can be set from 128 × fS to 512 × fS. I2S[3:0] I2S Audio Inputs. These represent the eight channels of audio (two per input) available through I2S. I2S CLK I2S Audio Clock. LRCLK Left/Right Channel Selection. PD/A0 Power Down.

Output Power Supply 1.8 V Digital and I/O Power Supply 1.8 V PLL Power Supply 1.8 V

Rev. 0 | Page 7 of 48

AD9389

Pin Mnemonic Description

POWER SUPPLY

DV

DD

AV

DD

PV

DD

GND

I2C ADDRESSES

The SDA/SCL programming address can be 0x72 or 0x7A based on whether the PD/A0 pin is pulled high (10 kΩ resistor = 0x7A) or pulled low (10 kΩ resistor = 0x72).

The EDID EEPROM on the receiver is expected to have an address of 0xA0.

LIST OF REFERENCE DOCUMENTS

Table 6.

Document Description

EIA/CEA-861B Describes audio and video infoframes as well as the E-EDID structure for HDMI. HDMI v1.1 Defining document for HDMI Version 1.1. Can be located at www.hdmi.org. HDCPv1.1 Defining document for HDCP Version 1.1. Can be located at www.digital-cp.com. ITU-R BT.656-3 Defining document for BT656.

Main Power Supply. These pins supply power to the main elements of the circuit. They should be filtered and as quiet as possible.

Output Power Supply. Clock Generator Power Supply. The most sensitive portion of the AD9389 is the clock generation circuitry. These

pins provide power to the clock PLL (phase-locked loop) and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins.

Ground. The ground return for all circuitry on-chip. It is recommended that the AD9389 be assembled on a single solid ground plane, with careful attention given to ground current paths.

FORMAT STANDARDS

In this document, data is represented in a variety of ways.

Table 7.

Data Type Format

0xNN Hexadecimal (base-16) numbers are represented using the C language notation, preceded by 0x. 0bNN Binary (base-2) numbers are represented using the C language notation, preceded by 0b. NN Decimal (base-10) numbers are represented using no additional prefixes or suffixes. Bit Bits are numbered in little-endian format, that is, the least significant bit (LSB) of a byte or word is referred to as Bit 0.

Rev. 0 | Page 8 of 48

AD9389

DESIGN GUIDE

GENERAL DESCRIPTION

The AD9389 HDMI transmitter provides a high bandwidth digital content protected (HDCP) digital link between a wide range of digital input formats—both audio and video (see output formats (see

Tabl e 9). Video and audio data are captured

and prepared for transmission while two separate I

Tabl e 8) and

2

C buses (one of which is a master) are used to program and provide content protection for the data to be transmitted.

VIDEO DATA CAPTURE

The AD9389 can accept video data from as few as eight pins (YCbCr DDR) representing 8-bit data or as many as 24 pins representing 12-bit data. The AD9389 is capable of detecting all of the 34 video formats defined in the EIA/CEA-861B specification. If video ID (VID) 32, 33, or 34 is present, the user needs to set Register 0x15[0] to 0b1, as these modes have V frequencies of 30 Hz or less. The user can read the detected video format at 0x3E[7:2]. Formats outside the EIA/CEA-861B specification can be read in 0x3F[7:5]. Detailed line count differences for 240p and 288p modes can be read from 0x3F[4:3]. In order to distinguish between an aspect ratio of 4:3 and one of 16:9, 0x17[1] should be set accordingly.

REF

Table 8. Input Formats Supported

No. of Bits Input Format

12 RGB (DDR) 12 YCbCr 4:4:4 (DDR) 24 RGB 4:4:4 24 YCbCr 4:4:4 16 YCbCr 4:2:2 (ITU.601) 20 YCbCr 4:2:2 (ITU.601) 24 YCbCr 4:2:2 (ITU.601) 8 YCbCr (DDR) 10 YCbCr (DDR) 12 YCbCr (DDR) 8 YCbCr 4:2:2 (ITU.656) 10 YCbCr 4:2:2 (ITU.656) 12 YCbCr 4:2:2 (ITU.656)

Table 9. Output Formats Supported

No. of Bits Output Format

24 RGB 4:4:4 24 YCbCr 4:4:4 16 YCbCr 4:2:2 20 YCbCr 4:2:2 24 YCbCr 4:2:2

INPUT FORMATS

INPUT CLOCK-

RISING EDGE

INPUT DATA:

D(23:0), DE , SYNCS

t

SETUP

t

HOLD

t

HOLD

Figure 3. Timing for Data Input

t

SETUP

t

HOLD

05724-013

Rev. 0 | Page 9 of 48

AD9389

Normal 4:4:4 Input Format (RGB or YCbCr) Input ID = 0

An input format of RGB 4:4:4 or YCbCr 4:4:4 can be selected by setting the input ID (0x15[3:1]) to 0b000. The input color space (CS) must be selected by setting 0x16[0] to 0b0 for RGB or 0b1 for YCbCr. There is no need to set the input style (0x16[3:2]).

Table 10.

Data[23:0]

Input Format

RGB 4:4:4 R[7:0] G[7:0] B[7:0] YCbCr 4:4:4 Cr[7:0] Y[7:0] Cb[7:0]

YCbCr 4:2:2 Formats (24 bits, 20 bits, or 16 bits) with Separate Sync, Input ID = 1

An input with YCbCr 4:2:2 with separate syncs can be selected by setting the Input ID (0x15[3:1]) to 0b001. The input CS (0x16[0]) must be set to 0b1 for proper operation. The data bit width (24 bits, 20 bits, or 16 bits) must be set with 0x16[5:4]. The three input pin assignment styles are shown in

Table 11.

Data[23:0] Input Format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

YCbCr 4:2:2 Sep. Cb[11:4] Y[11:4] Cb[3:0] Y[3:0] Sync (24 bit) Cr[11:4] Y[11:4] Cr[3:0] Y[3:0] YCbCr 4:2:2 Sep. Cb[9:2] Y[9:2] Cb[1:0] Y[1:0] Sync (20 bit) Cr[9:2] Y[9:2] Cr[1:0] Y[1:0] YCbCr 4:2:2 Sep. Cb[7:0] Y[7:0] Sync (20 bit) Cr[7:0] Y[7:0]

24-bit Cb[11:0] Y[11:0] Cr[11:0] Y[11:0] 20-bit Cb[9:0] Y[9:0] Cr[9:0] Y[9:0] 16-bit Cb[7:0] Y[7:0] Cr[7:0] Y[7:0]

24-bit Y[11:0] Cb[11:0] Y[11:0] Cr[11:0] 20-bit Y[9:0] Cb[9:0] Y[9:0] Cr[9:0] 16-bit Y[7:0] Cb[7:0] Y[7:0] Cr[7:0]

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Tabl e 1 1 . The input style can be set in 0x16[3:2].

Style 1

Style 2

Style 3

Rev. 0 | Page 10 of 48

AD9389

YCbCr 4:2:2 Formats (24 bits, 20 bits, or 16 bits) with Embedded Syncs, Input ID = 2

An input with YCbCr 4:2:2 with embedded syncs can be selected by setting the input ID (0x15[3:1]) to 0b010. HSYNC and VSYNC are embedded as Start of Active Video (SAV) and End of Active Video (EAV). The input CS (0x16[0]) must be set to 0b1 for proper operation. The data bit width (24 = 12 bits, 20 = 10 bits, or 16 = 8 bits) must be set with 0x16[5:4]. The three input pin assignment styles are shown in ID 2 are embedded in the data much like ITU 656 running at 1× clock and double width.

Table 12.

Data[23:0] Input Format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

YCbCr 4:2:2 Sep. Cb[11:4] Y[11:4] Cb[3:0] Y[3:0] Sync (24 bit) Cr[11:4] Y[11:4] Cr[3:0] Y[3:0] YCbCr 4:2:2 Sep. Cb[9:2] Y[9:2] Cb[1:0] Y[1:0] Sync (20 bit) Cr[9:2] Y[9:2] Cr[1:0] Y[1:0] YCbCr 4:2:2 Sep. Cb[7:0] Y[7:0] Sync (16 bit) Cr[7:0] Y[7:0]

24-bit Cb[11:0] Y[11:0] Cr[11:0] Y[11:0] 20-bit Cb[9:0] Y[9:0] Cr[9:0] Y[9:0] 16-bit Cb[7:0] Y[7:0] Cr[7:0] Y[7:0]

24-bit Y[11:0] Cb[11:0] Y[11:0] Cr[11:0] 20-bit Y[9:0] Cb[9:0] Y[9:0] Cr[9:0] 16-bit Y[7:0] Cb[7:0] Y[7:0] Cr[7:0]

Table 12. The input style can be set in 0x16[3:2]. The only difference between Input ID 1 and Input ID 2 is that the syncs on

Style 1

Style 2

Style 3

YCbCr 4:2:2 Formats (Double Data Rate) Formats (12 bits, 10 bits, or 8 bits) with Separate Syncs, Input ID = 3

An input with YCbCr 4:2:2 DDR data and separate syncs can be selected by setting the input ID (0x15[3:1]) to 0b011. The Input CS (0x16 [0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set with 0x16[5:4]. The two input pin assignment styles are shown in

Table 13. The input style can be set in 0x16[3:2].

Table 13.

Data[23:0]

Input Format

12-bit Cb/Y/Cr/Y[11:4] [3:0] 10-bit Cb/Y/Cr/Y[9:2] [1:0] 8-bit Cb/Y/Cr/Y[7:0]

12-bit Cb/Y/Cr/Y[11:0] 10-bit Cb/Y/Cr/Y[9:0] 8-bit Cb/Y/Cr/Y[7:0]

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Style 1

Style 2

Rev. 0 | Page 11 of 48

AD9389

YCbCr 4:2:2 DDR (Double Data Rate) Formats (12 bits, 10 bits, or 8 bits) with Embedded Syncs, Input ID = 4

An input with YCbCr 4:2:2 DDR data and embedded syncs (ITU 656) can be selected by setting the input ID (0x15[3:1]) to 0b100. The Input CS (0x16[0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set with 0x16[5:4]. The two input pin assignment styles are shown in example, 12 bit data is accepted as: Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3).

Table 14.

Input Format

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

12-bit Cb/Y/Cr/Y[11:4] [3:0] 10-bit Cb/Y/Cr/Y[9:2] [1:0] 8-bit Cb/Y/Cr/Y[7:0]

12-bit Cb/Y/Cr/Y[11:0] 10-bit Cb/Y/Cr/Y[9:0] 8-bit Cb/Y/Cr/Y[7:0]

Normal 4:4:4 Input Format (RGB or YCbCr) Clocked at Double Data Rate (DDR), Input ID = 5

An input with YCbCr 4:4:4 DDR data and separate syncs can be selected by setting the input ID (0x15[3:1]) to 0b011. The input CS (0x16[0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set with 0x16[5:4]. The three input pin assignment styles are shown in

Tabl e 15 . The input style can be set in 0x16[3:2].

Table 15.

Input Format

RGB 4:4:4 (DDR)

st

edge,

(1

nd

2

edge)

YCbCr 4:4:4 (DDR)

st

(1

edge,

nd

edge)

2

RGB 4:4:4 (DDR)

st

edge,

(1

nd

2

edge)

YCbCr 4:4:4 (DDR)

st

edge,

(1

nd

2

edge)

YCbCr 4:4:4 (DDR)

st

(1

edge,

nd

edge)

2

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

G[3:0] B[7:0]

R[7:0] G[7:4]

Y[3:0] Cb[7:0]

Cr[7:0] Y[7:4]

R[7:0] G[7:4]

G[3:0] B[7:0]

Cr[7:0] Y[7:4]

Y[3:0] Cb[7:0]

Y[7:0] Cb[7:4]

Cb[3:0] Cr[7:0]

Tabl e 1 4 . The input style can be set in 0x16[3:2]. The order of data input is the order in the table (for

Data[23:0]

Style 1

Style 2

Data[23:0]

Style 1

Style 2

Style 3

Rev. 0 | Page 12 of 48

AD9389

YCbCr 4:2:2 Formats (24 bits, 20 bits, or 16 bits) DDR with Separate Sync, Input ID = 6

An input format of YCbCr 4:2:2 DDR can be selected by setting the input ID (0x15[3:1]) to 0b110. The three different input pin assignment styles are shown in Tab le 1 6. The input style can be set in 0x16[3:2]. The input CS (0x16[0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set to with 0x16[5:4].

st

or the 2nd edge can be the rising or falling edge. The data input edge is defined in 0x16[1]. 0b0 = rising edge; 0b1 = falling edge.

The 1 Pixel 0 is the first pixel of the 4:2:2 word and should be where DE starts.

Table 16.

Data[23:0]

Input Format

YCbCr 4:2:2 Sep. Syncs (DDR)

12-bit

YCbCr 4:2:2 Sep. Syncs (DDR)

10-bit

YCbCr 4:2:2 Sep. Syncs (DDR)

8-bit

12-bit

10-bit

8-bit

12-bit

10-bit

8-bit

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Style 1

1

st

1

Pixel

nd

2

st

Edge Y[7:4] Cb[3:0] Y[3:0]

Cb[11:4] Y[11:8]

Edge

Y[7:4] Cr[3:0] Y[3:0]

2

nd

Pixel

Cr[11:4] Y[11:8] Y[5:4] Cb[3:0] Y[3:0] Cb[9:4] Y[9:6] Y[5:4] Cr[3:0] Y[3:0] Cr[9:4] Y[9:6] Cb[3:0] Y[3:0] Cb[7:4] Y[7:4] Cr[3:0] Y[3:0] Cr[7:4] Y[7:4]

Style 2

Y[11:0] Cb[11:0] Y[11:0] Cr[11:0] Y[9:0] Cb[9:0] Y[9:0] Cr[9:0] Y[7:0] Cb[7:0] Y[7:0] Cr[7:0]

Style 3

Cb[11:0] Y[11:0] Cr[11:0] Y[11:0] Cb[9:0] Y[9:0] Cr[9:0] Y[9:0] Cb[7:0] Y[7:0] Cr[7:0] Y[7:0]

Rev. 0 | Page 13 of 48

AD9389

4:2:2 TO 4:4:4 DATA CONVERSION DE GENERATION

The AD9389 has the ability to convert YCbCr video from 4:4:4 to 4:2:2 and 4:2:2 to 4:4:4. To convert from 4:4:4 to 4:2:2, the video data goes through a filter first to remove any artificial downsampling noise. To convert from 4:2:2 to 4:4:4, the AD9389 utilizes either the zero-order upconversion (pixel repetition) or first-order upconversion (linear interpolation). The upconversion and downconversions are used when the video output timing format does not match the video input timing format. The video output format is set by Register 0x16[7:6]. The video input format is set by the video ID (0x15[3:1]) and video color space (0x16[0]). The default mode for upconversion is pixel repetition. To use linear interpolation, set Register 0x17[2] to 1.

HORIZONTAL SYNC, VERTICAL SYNC, AND DE GENERATION

When transmitting video data across the TMDS interface, it is necessary to have an HSYNC, VSYNC, and data enable (DE) defined for the image. ITU-656 based sources have start of active video (SAV) and end of active video (EAV) signals built in, but the HSYNC and VSYNC must be generated (the DE is implied by the SAV and EAV signals). Other sources (with separate syncs) have HSYNC, VSYNC, and DE supplied at the same time as the pixel data.

The AD9389 offers a choice of DE from an external pin, or an internally generated DE. To activate the internal DE generation, set Register 0x17[0] to 1. Registers 0x35 to 0x3A are used to define the DE. 0x35 and 0x36[7:6] define the number of pixels from the HS leading edge to the DE leading edge. 0x36[5:0] are the number of HSYNCs between the leading edge of VS and DE. 0x37[7:5] defines the difference of HS counts during VS blanking for interlace video. 0x37[4:0] and 0x38[7:1] indicate the width of the DE. 0x39 and 0x3A[7:4] are the number of lines of active video (see Figure 4).

HSYNC AND VSYNC GENERATION

For video with embedded HSYNC and VSYNC, such as EAV and SAV, found in ITU 656 format, it is necessary to reconstruct HSYNC and VSYNC. This is done with registers 0x30 to 0x34. 0x30 and 0x31[7:6] specify the number of pixels between the HSYNC leading edge and the trailing edge of DE. Register 0x31[5:0] and Register 0x32[7:4] are the duration of the HSYNC in pixel clocks. 0x32[3:0] and 0x33[7:2] are the number of HS pulses between the trailing edge of the last DE and the leading edge of the VSYNC pulse. Register 0x33[1:0] and 0x34[7:0] are the duration of VSYNC in units of HSYNCs. HSYNC and VSYNC polarity can be specified by setting 0x17[6] (for VSYNC) and 0x17[5] (for HSYNC).

VS DELAY R0x36[5:0]

HS DELAY

R0x35, R0x36[7:6]

EAV

b

HSYNC

a: HSYNC PLACEMENT R0x30, R0x31[7:6]

b: HSYNC DURATION R0x31[5:0], R0x32[7:4]

a

ACTIVE

VIDEO

WIDTH

R0x37[4:0], R0x38[7:1]

Figure 4. Active Video

SAV

Figure 5. HSYNC Reconstruction

HEIGHT R0x39, R0x3A[7:4]

05724-003

05724-005

Rev. 0 | Page 14 of 48

AD9389

G

EAV

VSYNC

a: VSYNC PLACEMENT R0x32[3:0], R0x33[7:2]

b: VSYNC DU RATION R0x33[1:0], R0x34

ab

SAV

05724-006

Figure 6. VSYNC Reconstruction

CSC_Mode[1:0]

a1[12:0]

1

R

[11:0]

IN

a2[12:0]

B

[11:0]

IN

a3[12:0]

×

4096

1

4096

+ + +

a4[12:0]

×4

×2

2

1

0

[11:0]

R

OUT

1

IN

[11:0]

×

4096

Figure 7. Single CSC Channel

COLOR SPACE CONVERSION MATRIX (CSC)

The color space conversion matrix in the AD9389 consists of three identical processing channels. In each channel, three input values are multiplied by three separate coefficients. Also included are an offset value for each row of the matrix and a scaling multiple for all values. Each value is 13-bit, twos complement resolution to ensure the signal integrity is maintained. The CSC is designed to run at speeds up to 80 MHz supporting resolutions up to 1080i at 60 Hz and UXGA at 60 Hz. With any-to-any color space support, RGB, YUV, YCbCr, and other formats are supported by the CSC.

The main inputs, R inputs from each channel. These inputs are based on the input format detailed in inputs to the CSC inputs is shown in

Table 17. CSC Port Mapping

Input Channel CSC Input Channel

R/Cr R Gr/Y G B/Cb BB

, GIN, and BIN come from the 8-bit to 12-bit

IN

Tabl e 1 0 to Tabl e 16. The mapping of these

Tabl e 17 .

IN

05724-008

One of the three channels is represented in Figure 7. In each processing channel, the three inputs are multiplied by three separate coefficients marked a1, a2, and a3. These coefficients are divided by 4096 to obtain nominal values ranging from

−0.9998 to +0.9998. The variable labeled a4 is used as an offset control. The CSC_Mode setting is the same for all three processing channels. This multiplies all coefficients and offsets by a factor of 2CSC_Mode.

The functional diagram for a single channel of the CSC, as per Figure 7, is repeated for the remaining G and B channels. The coefficients for these channels are b1, b2, b3, b4, c1, c2, c3, and c4.

Register settings for several common conversions are listed in the

Color Space Converter (CSC) Common Settings section.

For a detailed functional description and more programming examples, refer to AN-795, The AD9880 Color Space Converter

User's Guide.

Rev. 0 | Page 15 of 48

Analog Devices AD9389 Service Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

EVALUATION KITS AND OTHER RESOURCES

TABLE OF CONTENTS

REVISION HISTORY

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

EXPLANATION OF TEST LEVELS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

I2C ADDRESSES

LIST OF REFERENCE DOCUMENTS

FORMAT STANDARDS

DESIGN GUIDE

GENERAL DESCRIPTION

VIDEO DATA CAPTURE

INPUT FORMATS

4:2:2 TO 4:4:4 DATA CONVERSION DE GENERATION

HORIZONTAL SYNC, VERTICAL SYNC, AND DE GENERATION

HSYNC AND VSYNC GENERATION

COLOR SPACE CONVERSION MATRIX (CSC)