ANALOG DEVICES AD9388A Service Manual

10-Bit Integrated, Multiformat, HDTV Video Decoder,

www.BDTIC.com/IC

RGB Graphics Digitizer, and 2:1 Multiplexed

HDMI/DVI Interface

FEATURES

Mutliformat decoder

Three 10-bit analog-to-digital converters (ADCs) ADC sampling rates up to 170 MHz Mux with 12 analog input channels 525i-/625i-component SD support 525p-/625p-component progressive scan support 720p-/1080i-/1080p-component HDTV support Digitizes RGB graphics up to 1600 × 1200 at 60 Hz (UXGA) VBI data slicer (including teletext) Analog-to-HDMI fast switching

Dual High-Definition Multimedia Interface (HDMI) Rx

2:1 multiplexed HDMI receiver HDMI 1.3, DVI 1.0 225 MHz HDMI receiver Repeater support High-bandwidth digital content protection (HDCP 1.3) 36-bit deep color support S/PDIF (IEC60958-compatible) digital audio output Multichannel I Adaptive equalizer for cable lengths up to 30 meters Internal EDID RAM

General

Highly flexible output interface STDI function support standard identification 2 any-to-any 3 × 3 color-space conversion matrices Programmable interrupt request output pins

APPLICATIONS

Advanced TVs

PDP HDTVs LCD TVs (HDTV ready) LCD/DLP® rear projection HDTVs CRT HDTVs

LCoS® HDTVs Audio/video receivers (AVRs) LCD/DLP front projectors HDTV STBs with PVR DVD recorders with progressive scan input support

2

S audio output (up to 8 channels)

AD9388A

GENERAL DESCRIPTION

The AD9388A is a high quality, single-chip graphics digitizer with an integrated 2:1 multiplexed HDMI™ receiver.

The AD9388A contains one main component processor (CP) that processes YPrPb and RGB component formats, including RGB graphics. The CP also processes the video signals from the HDMI receiver. The AD9388A can keep the HDCP link between an HDMI source and the selected HDMI port active in analog mode operation. This allows for fast switching between the analog and HDMI modes.

The AD9388A supports the decoding of a component RGB or YPrPb video signal into a digital YCrCb or RGB pixel output stream. The support for component video includes 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and 1250i standards, as well as many other HD and SMPTE standards.

Graphic digitization is also supported by the AD9388A. The AD9388A is capable of digitizing RGB graphics signals from VGA to UXGA rates and converting them into a digital RGB or YCrCb pixel output stream.

The AD9388A incorporates a dual input, HDMI 1.3-compatible receiver that supports HDTV formats up to 1080p and display resolutions up to UXGA (1600 × 1200 at 60 Hz). The reception of encrypted video is possible with the inclusion of HDCP. In addition, the inclusion of adaptive equalization ensures robust operation of the interface with cable lengths up to 30 meters. The HDMI receiver has an advanced audio functionality, such as a mute controller that prevents audible extraneous noise in the audio output.

Derivative parts of the AD9388A are available; AD9388ABSTZA5 is composed of one analog and one digital input. To facilitate professional applications, where HDCP processing and decryption are not required, the AD9388ABSTZ-5P derivative is available. This allows users who are not HDCP adopters to purchase the AD9388A. See the Ordering Guide for details on these derivative parts.

Fabricated in an advanced CMOS process, the AD9388A is available in a space saving, 144-lead, surface-mount, RoHScompliant, plastic LQFP and is specified over the −40°C to +85°C temperature range.

B

Rev.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of p atents or other rights of third parties that may result from its use. Specifications subject to chan ge without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

AD9388A

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REVISION HISTORY

7/08—Rev. SpA to Rev. B

5/08—Rev. Sp0 to Rev. SpA

Changes to General Description .................................................... 1

Added Figure 6 ................................................................................ 13

Added Table 7 .................................................................................. 13

Changes to Component Processor Pixel Data Output Modes

Section .............................................................................................. 16

Changes to Component Processor (CP) Section........................ 17

Added AD9388A/ADV7441A Evaluation Platform Section .... 24

Changes to Ordering Guide .......................................................... 25

10/07—Revsion Sp0: Initial Version

Rev. B | Page 2 of 28

AD9388A

A

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FUNCTIONAL BLOCK DIAGRAM

06915-001

P0 TO

P910P10 TO

P1910P20 TO

P29

PIXEL

DATA

10

INT1

SYNC EXTRACT

COMPONENT PRO CESSOR

DIGI TAL PROCESSI NG BLOCK

AD9388A

EMBEDDED

DATA

PREPROCESSOR

HS/CS

VS/FIELD

DE/FIELD

LLC

SYNC_OUT/

INT2

OUTPUT FORMATTER

DATA

ADDER

AV CODE

INSERTION

STANDARD

IDENTIFICATION

POLARITY DETECT

SYNC SOURCE AND

SYNC

OFFSET

HSYNC DEPTH

ACTIVE PEAK AND

GAIN

CONTROL

CGMS DETECT ION

MACROVISION AND

FINE

CLAMP

DIGITAL

PROG.

(A)

CONVERTER

COLOR SPACE

(A)

NOISE AND C ALIBRATI ON

DELAY

(B)

(C)

AND

FILTERS

DECIMATION

DOWNSAM PLING

(B)

(C)

ANCILLARY

DATA

ANCILLARY

FORMATTER

VBI DATA PROCESSOR

VBI

DECODER

S

2

LRCLK

SCLK

MCLKOUT

SPDIF

I

AUDIO

PROCESSING

ANALOG I NTERFACE

101010

ADC0

CLAMP

RGB

MUX

4:4:4

4:2:2 TO

CONVERSION

XOR

DEVSHS

HDMI

DECODE

DATA

RECOVERY

ALIGNM ENT

MUX

SAMPLEREQUALIZER

SAMPLER

MUX PLL

EQUALIZER

SCL

FILTER

CONTROL

C

2

I

CONTROL INTERFACE

SDA

ALSB

HS/CS, VS

ADC1

ADC2

CLAMP

INPUT

MATRIX

YPrPb

CONTROL

CONTROL AND DATA

LLC GENERATI ON

CLOCK GENER ATION

SYNC PROCESSING AND

SOY

SOG

VS_IN

HS_IN/C S_IN

PACKET/

MEMORY

INFOFRAME

PACKET

PROCESSOR

HDCP

EDID/

REPEATER

EEPROM

ENGINE

CONTROLLER

MCL

MDA

DDCB_SCL

DDCB_SD

DDCA_SD

DDCA_SCL

RXA_0

RXA_1

RXA_2

RXB_0

RXB_1

RXA_C

RXB_2

RXB_C

Figure 1.

Rev. B | Page 3 of 28

AD9388A

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SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to

3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter

STATIC PERFORMANCE

Resolution (Each ADC) N 10 Bits Integral Nonlinearity INL BSL at 27 MHz (@ a 10-bit level) –0.5/+2 –4/+6 LSB BSL at 54 MHz (@ a 10-bit level) –0.5/+2 LSB BSL at 74 MHz (@ a 10-bit level) –0.5/+1.5 LSB BSL at 110 MHz (@ a 10-bit level) –0.7/+2 LSB BSL at 170 MHz (@ an 8-bit level) –0.25/+0.5 LSB Differential Nonlinearity DNL At 27 MHz (@ a 10-bit level) –0.5/+0.5 –0.95/+2 LSB At 54 MHz (@ a 10-bit level) ±0.5 LSB At 74 MHz (@ a 10-bit level) ±0.5 LSB At 110 MHz (@ a 10-bit level) ±0.5 LSB At 170 MHz (@ an 8-bit level) –0.25/+0.2 LSB

DIGITAL INPUTS

Input High Voltage HS_IN, VS_IN low trigger mode 0.7 V Input Low Voltage HS_IN, VS_IN low trigger mode 0.3 V Input Current IIN

All input pins other than Pin 21 –10 +10 μA

Input Capacitance

DIGITAL OUTPUTS

Output High Voltage Output Low Voltage High Impedance Leakage Current I Output Capacitance

POWER REQUIREMENTS

Digital Core Power Supply DVDD 1.62 1.8 1.98 V Digital I/O Power Supply DVDDIO 2.97 3.3 3.63 V PLL Power Supply PVDD 1.71 1.8 1.89 V Analog Power Supply AVDD 1.71 1.8 1.89 V Terminator Power Supply TVDD 3.135 3.3 3.465 V Comparator Power Supply CVDD 1.71 1.8 1.89 V Digital Core Supply Current I YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz Digital I/O Supply Current I YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz HDMI Comparators I

1

2

3

4

5

V

4

C

4

Symbol Test Conditions Min Typ Max Unit

VIH 2 V

VIL 0.8 V

Pin 21 (RESET

)

–60 +60 μA

CIN 10 pF

VOH I

I

OL

10 μA

LEAK

20 pF

OUT

Graphics RGB sampling @ 108 MHz6 141 252 mA

DVDD

Graphics RGB sampling @ 108 MHz

DVDDIO

Graphics RGB sampling @ 108 MHz

CVDD

= 0.4 mA 2.4 V

SOURCE

= 3.2 mA 0.4 V

SINK

6

203 263 mA

7, 8

242 329 mA

7, 8

242 326 mA

6

17 37 mA

6

42 62 mA

7, 8

17 34 mA

7, 8

20 34 mA

6

56 78 mA

Rev. B | Page 4 of 28

AD9388A

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Parameter

TMDS PLL and Equalizer

1

Symbol Test Conditions Min Typ Max Unit

6

YPrPb 1080p sampling @ 148.5 MHz

56 79 mA

Supply Current

7, 8

HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz Analog Supply Current I

Graphics RGB sampling @ 108 MHz

AVDD

YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz Terminator Supply Current I

Graphics RGB sampling @ 108 MHz

TVDD

YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz Audio and Video Supply Current I

Graphics RGB sampling @ 108 MHz

PVDD

YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz Power-Down Current I Power-Up Time t

1

The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range (T

2

All ADC linearity tests performed at input range of full scale − 12.5% and at zero scale + 12.5%.

3

Pin 1, Pin 105, Pin 106, and Pin 144 are 5 V tolerant.

4

Guaranteed by characterization.

5

VOH and VOL levels obtained using default drive strength value (0x15) in User Map Register 0xF4.

6

Current measurements for analog inputs were made with HDMI/analog simultaneous mode disabled (User Map Register 0xBA Bit 7 programmed with Value 0) and no

HDMI sources connected to the part.

7

Current measurements for HDMI inputs were made with a source connected to the active HDMI port and no source connected to the inactive HDMI port.

8

Audio stream is uncompressed stereo audio sampling frequency of fS = 48 kHz and MCLKOUT = 256 fS.

9

The terminator supply current may vary with the HDMI source in use.

11.6 mA

PWRDN

25 ms

PWRUP

86 105 mA

7, 8

95 118 mA

6

174 278 mA

6

180 284 mA

7, 8

0 2 mA

7, 8

0 2 mA

6

12 18 mA

6

12 18 mA

7, 8, 9

42 47 mA

7, 8, 9

63 69 mA

6

14 21 mA

6

19 24 mA

7, 8

10 19 mA

7, 8

15 20 mA

to T

MAX

).

MIN

Rev. B | Page 5 of 28

AD9388A

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ANALOG AND HDMI SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to

3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted.

Table 2.

Parameter

ANALOG

Clamp Circuitry

HDMI SPECIFICATIONS

Intrapair (Positive-to-Negative) Differential Input Skew 0.4 t

Channel-to-Channel Differential Input Skew

1

The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range.

2

Guaranteed by characterization.

3

Guaranteed by design.

4

t

is 1/10 the pixel period of the TMDS clock.

bit

5

t

pixel

1, 2

Test Conditions Min Typ Max Unit

External Clamp Capacitor 0.1 μF Input Impedance (Except Pin 74) Clamps switched off 10 MΩ Input Impedance of Pin 74 20 kΩ CML 0.88 V ADC Full-Scale Level CML + 0.5 V ADC Zero-Scale Level CML − 0.5 V ADC Dynamic Range 1 V Clamp Level (When Locked) Component input (Y signal) CML − 0.120 V Component input (Pr signal) CML V Component input (Pb signal) CML V PC RGB input (R, G, B signals) CML − 0.120 V

3

is the period of the TMDS clock.

4

bit

5

0.2 t

+ 1.78 ns

pixel

Rev. B | Page 6 of 28

AD9388A

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DATA AND I2C TIMING CHARACTERISTICS

AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to

3.465 V, CVDD = 1.71 V to 1.89 V; operating temperature range is −40°C to +85°C, unless otherwise noted.

Table 3.

1, 2

Parameter

Symbol Test Conditions Min Typ Max Unit

SYSTEM CLOCK AND CRYSTAL

Crystal Nominal Frequency 28.6363 MHz Crystal Frequency Stability ±50 ppm Horizontal Sync Input Frequency 14.8 110 kHz LLC Frequency Range 12.825 170 MHz

3

I2C PORTS (FAST MODE)

xCL Frequency xCL Minimum Pulse Width High xCL Minimum Pulse Width Low

4

t

4

t

400 kHz

0.6 μs

1

1.3 μs

2

Hold Time (Start Condition) t3 0.6 μs Setup Time (Start Condition) t4 0.6 μs xDA Setup Time xCL and xDA Rise Times xCL and xDA Fall Times

4

t

4

t

4

t

100 ns

5

300 ns

6

300 ns

7

Setup Time (Stop Condition) t8 0.6 μs

I2C PORTS (NORMAL MODE)

xCL Frequency 100 kHz xCL Minimum Pulse Width High t1 4 μs xCL Minimum Pulse Width Low t2 4.7 μs Hold Time (Start Condition) t3 4 μs Setup Time (Start Condition) t4 4.7 μs xDA Setup Time t5 250 ns xCL and xDA Rise Times t6 1000 ns xCL and xDA Fall Times t7 300 ns Setup Time (Stop Condition) t8 4 μs

RESET FEATURE

Reset Pulse Width 5 ms

CLOCK OUTPUTS

LLC Mark Space Ratio t9:t10 45:55 55:45

% duty cycle

DATA AND CONTROL OUTPUTS

Data Output Transition Time SDR (CP) t

5

t11 End of valid data to negative clock edge 2 ns

Negative clock edge to start of valid data 0.5 ns

12

I2S PORT (MASTER MODE)

SCLK Mark Space Ratio t13:t14

45:55 55:45

% duty

cycle LRCLK Data Transition Time t15 LRCLK Data Transition Time t16 I2Sx Data Transition Time I2Sx Data Transition Time MCLKOUT Frequency

1

The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range (T

2

Guaranteed by characterization.

3

Refers to all I2C pins (DDC and control port).

4

The prefix x refers to pin names beginning with S, DDCA_S, and DDCB_S.

5

CP timing figures were obtained using the maximum drive strength value (0x3F) in User Map Register 0xF4.

6

The suffix x refers to pin names ending with 0, 1, 2, and 3.

6

t

17

18

4.096 24.576 MHz

End of valid data to negative SCLK edge 10 ns Negative SCLK edge to start of valid data 10 ns End of valid data to negative SCLK edge 5 ns Negative SCLK edge to start of valid data 5 ns

to T

MAX

).

MIN

Rev. B | Page 7 of 28

AD9388A

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Timing Diagrams

t

3

xDA

t

6

1

xCL

t

2

NOTES

1. THE PREF IX x REFERS TO PIN NAMES BEGINNING WITH S, DDCA_S, AND DDCB_S.

t

7

Figure 2. I

t

5

2

C Timing

t

3

t

4

t

8

06915-002

LLC

P0 TO P29, VS,

HS, FIEL D/DE

t

9

t

11

t

10

t

12

06915-004

Figure 3. Pixel Port and Control CP Output Timing (CP Core)

t

13

SCLK

t

14

t

15

LRCLK

t

16

t

LEFT-JUSTIFIED

RIGHT -JUSTI FIED

I2Sx

MODE

I2Sx

2

I

S MODE

I2Sx

MODE

NOTES

1. THE SUF FIX x REFE RS TO PI N NAMES ENDING W ITH 0, 1, 2, AND 3.

17

MSB MSB – 1

t

18

MSB

t

17

t

18

Figure 4. I

MSB – 1

2

S Timing

t

17

LSBMSB

t

18

06915-005

Rev. B | Page 8 of 28

AD9388A

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ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

AVDD to AGND 2.2 V DVDD to DGND 2.2 V PVDD to PGND 2.2 V DVDDIO to DGND 4 V CVDD to CGND 2.2 V TVDD to TGND 4 V DVDDIO to AVDD −0.3 V to +3.6 V DVDDIO to TVDD −3.6 V to +3.6 V DVDDIO to DVDD −2 V to +2 V CVDD to DVDD −2 V to +0.3 V PVDD to DVDD −2 V to +0.3 V AVDD to CVDD −2 V to +2 V AVDD to PVDD −2 V to +2 V AVDD to DVDD −2 V to +2 V AVDD to TVDD −3.6 V to +0.3 V TVDD to DVDD −2 V to +2 V Digital Inputs

Voltage to DGND DGND − 0.3 V to DVDDIO + 0.3 V

Digital Outputs

Voltage to DGND

Analog Inputs

Voltage to AGND

Maximum Junction

Temperature (T Storage Temperature Range −65°C to +150°C Infrared Reflow,

Soldering (20 sec)

) 125°C

J_MAX

DGND − 0.3 V to DVDDIO + 0.3 V

AGND − 0.3 V to AVDD + 0.3 V

260°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

Table 5.

Package Type Ψ

144-Lead LQFP (ST-144) 1.62 °C/W

1

Junction-to-package surface thermal resistance.

1

Unit

JT

PACKAGE THERMAL PERFORMANCE

To reduce power consumption during AD9388A operation, turn off unused ADCs.

On a four-layer PCB that includes a solid ground plane, the θ

JA

value is 25.3°C/W. However, due to variations within the PCB metal and, therefore, variations in PCB heat conductivity, the value of θ

may differ for various PCBs.

JA

The most efficient measurement technique is to use the surface temperature of the package to estimate the die temperature because this is not affected by the variance associated with the θ

value.

JA

The maximum junction temperature (T

) of 125°C must not

J_MAX

be exceeded. The following equation calculates the junction temperature using the measured surface temperature of the package and applies only when no heat sink is used on DUT:

T

= TS + (ΨJT × W

J_MAX

TOTAL

)

where:

T

is the surface temperature of the package expressed in

S

degrees Celsius.

Ψ

is the junction-to-package surface thermal resistance.

JT

W

= {(AV D D × IAVDD) + (DVDD × IDVDD) + (DVDDIO

TOTAL

× IDVDDIO) + (PVDD × IPVDD) + (CVDD × ICVDD) + (TVDD × ITVDD)}.

Contact an Analog Devices, Inc., representative for more details on package thermal performance at video.products@analog.com.

ESD CAUTION

Rev. B | Page 9 of 28

ANALOG DEVICES AD9388A Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

ANALOG AND HDMI SPECIFICATIONS

DATA AND I2C TIMING CHARACTERISTICS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

PACKAGE THERMAL PERFORMANCE

ESD CAUTION