Analog Devices AD9380 Service Manual

Analog/HDMI

FEATURES

Internal key storage for HDCP Analog/HDMI dual interface

Supports high bandwidth digital content protection RGB-to-YCbCr 2-way color conversion Automated clamping level adjustment

1.8 V/3.3 V power supply 100-lead, Pb-free LQFP RGB and YCbCr output formats

Analog interface

8-bit triple ADC 100 MSPS maximum conversion rate Macrovision® detection 2:1 input mux Full sync processing Sync detect for hot plugging Midscale clamping

Digital video interface

HDMI 1.1, DVI 1.0 150 MHz HDMI receiver Supports HDCP 1.1

Digital audio interface

HDMI 1.1-compatible audio interface S/PDIF (IEC90658-compatible) digital audio output Multichannel I

APPLICATIONS

Advanced TVs HDTV Projectors LCD monitor

GENERAL DESCRIPTION

The AD9380 offers designers the flexibility of an analog interface and high definition multimedia interface (HDMI) receiver integrated on a single chip. Also included is support for high bandwidth digital content protection (HDCP).

The AD9380 is a complete 8-bit, 150 MSPS, monolithic analog interface optimized for capturing component video (YPbPr) and RGB graphics signals. Its 150 MSPS encode rate capability and full power analog bandwidth of 330 MHz supports all HDTV formats (up to 1080p and FPD resolutions up to SXGA (1280 × 1024 @ 75 Hz).

The analog interface includes a 150 MHz triple ADC with internal 1.25 V reference, a phase-locked loop (PLL), and programmable gain, offset, and clamp control. The user provides only 1.8 V and 3.3 V power supplies, analog input, and HSYNC . Three-state CMOS outputs can be powered from 1.8 V to 3.3 V. An on-chip PLL generates a pixel clock from HSYNC.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

S audio output (up to 8 channels)

Dual-Display Interface

AD9380

FUNCTIONAL BLOCK DIAGRAM

COAST

FILT

CKINV

CKEXT

SCL SDA

Rx0+ Rx0– Rx1+ Rx1– Rx2+

Rx2– RxC+ RxC–

RTERM

IN0 IN1

ANALOG INTERFACE

2:1

CLAMP

MUX

2:1

MUX

2:1

MUX

2:1

MUX

POWER MANAGEMENT

DIGITAL INTERFACE

SYNC

PROCESSING

AND

CLOCK

GENERATION

SERIAL REGISTER

AND

HDMI RECEIVER

HDCP

R/G/B OR YPbPr R/G/B OR YPbPr

HSYNC 0 HSYNC 1

SOGIN 0 SOGIN 1

DDCSDA

DDCSCL

Figure 1.

Pixel clock output frequencies range from 12 MHz to 150 MHz. PLL clock jitter is typically less than 700 ps p-p at 150 MHz. The AD9380 also offers full sync processing for composite sync and sync-on-green (SOG) applications.

The AD9380 contains an HDMI 1.1-compatible receiver and supports all HDTV formats (up to 1080p and 720p) and display resolutions up to SXGA (1280 × 1024 @ 75 Hz). The receiver features an intrapair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays can now receive encrypted video content. The AD9380 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of the authentication during transmission, as specified by the HDCP 1.1 protocol.

Fabricated in an advanced CMOS process, the AD9380 is provided in a space-saving, 100-lead, surface-mount, Pb-free plastic LQFP and is specified over the 0°C to 70°C temperature range.

A/D

REFOUT

REFIN

HDCP KEYS

R/G/B 8 × 3 OR YCbCr

DATACK HSOUT VSOUT SOGOUT

REF

R/G/B 8 × 3 OR YCbCr

DATACK DE HSYNC VSYNC

MUXES

AD9380

R/G/B 8 × 3 YCbCr (4:2:2

OR 4:4:4) 2

DATACK HSOUT

RGB YCbCr MATRIX

VSOUT SOGOUT

S/PDIF 8-CHANNEL

SCLK MCLK LRCLK

05688-001

AD9380

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Specifications..................................................................................... 3

Analog Interface Electrical Characteristics............................... 3

Digital Interface Electrical Characteristics ............................... 4

Absolute Maximum Ratings............................................................ 6

Explanation of Test Levels........................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Design Guide................................................................................... 12

General Description................................................................... 12

Digital Inputs ..............................................................................12

Analog Input Signal Handling.................................................. 12

2-Wire Serial Register Map ........................................................... 23

2-Wire Serial Control Register DetailS........................................ 37

Chip Identification..................................................................... 37

PLL Divider Control.................................................................. 37

Clock Generator Control .......................................................... 37

Input Gain ................................................................................... 38

Input Offset ................................................................................. 38

Sync .............................................................................................. 39

Coast and Clamp Controls........................................................ 39

Status of Detected Signals ......................................................... 39

Polarity Status ............................................................................. 40

BT656 Generation...................................................................... 44

Macrovision................................................................................. 45

Color Space Conversion............................................................ 46

2-Wire Serial Control Port ............................................................ 53

HSYNC and VSYNC Inputs...................................................... 12

Serial Control Port ..................................................................... 12

Output Signal Handling............................................................. 12

Clamping ..................................................................................... 12

Timing.......................................................................................... 16

HDMI Receiver........................................................................... 20

DE Generator ..............................................................................20

4:4:4 to 4:2:2 Filter...................................................................... 20

Audio PLL Setup......................................................................... 21

Audio Board Level Muting........................................................ 21

Timing Diagrams........................................................................ 22

REVISION HISTORY

10/05—Revision 0: Initial Version

Data Transfer via Serial Interface............................................. 53

Serial Interface Read/Write Examples ..................................... 54

PCB Layout Recommendations.................................................... 55

Analog Interface Inputs............................................................. 55

Power Supply Bypassing ............................................................ 55

PLL ............................................................................................... 55

Outputs (Both Data and Clocks).............................................. 56

Digital Inputs .............................................................................. 56

Color Space Converter (CSC) Common Settings...................... 57

Outline Dimensions ....................................................................... 59

Ordering Guide .......................................................................... 59

Rev. 0 | Page 2 of 60

AD9380

SPECIFICATIONS

ANALOG INTERFACE ELECTRICAL CHARACTERISTICS

VDD, VD = 3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum.

Table 1.

AD9380KSTZ-100 AD9380KSTZ-150 Parameter Temp Test Level Min Typ Max Min Typ Max Unit

RESOLUTION 8 8 Bits DC ACCURACY

Differential Nonlinearity 25°C I −0.6 +1.6/−1.0 ±0.7 +1.8/−1.0 LSB Integral Nonlinearity 25°C I ±1.0 ±2.1 ±1.1 ±2.25 LSB No Missing Codes Full I Guaranteed Guaranteed V

ANALOG INPUT

Input Voltage Range

Minimum Full VI 0.5 0.5 V p–p

Maximum Full VI 1.0 1.0 V p–p Gain Tempco 25°C V 100 220 ppm/°C Input Bias Current 25°C V 0.2 1 μA Input Full-Scale Matching

25°C Full

VI VI

1.25

1.50

5 7

1.25

1.50

5 7

Offset Adjustment Range Full V 50 50 %FS

SWITCHING PERFORMANCE

Maximum Conversion Rate Full VI 100 150 MSPS Minimum Conversion Rate Full VI 10 10 MSPS Data-to-Clock Skew Full IV −0.5 +2.0 −0.5 +2.0 ns

SERIAL PORT TIMING

BUFF

STAH

DHO

DAL

DAH

DSU

STASU

STOSU

Full VI 4.7 4.7 μs Full VI 4.0 4.0 μs Full VI 0 0 μs Full VI 4.7 4.7 μs Full VI 4.0 4.0 μs Full VI 250 250 ns Full VI 4.7 4.7 μs

Full VI 4.0 4.0 μs HSYNC Input Frequency Full VI 15 110 15 110 kHz Maximum PLL Clock Rate Full VI 100 150 MHz Minimum PLL Clock Rate Full IV 12 12 MHz PLL Jitter 25°C IV 700 700 ps p-p Sampling Phase Tempco Full IV 15 15 ps/°C

DIGITAL INPUTS, 5 V TOLERANT

Input Voltage, High (VIH) Full VI 2.6 2.6 V Input Voltage, Low (VIL) Full VI 0.8 0.8 V Input Current, High (IIH) Full V −82 −82 μA Input Current, Low (IIL) Full V 82 82 μA Input Capacitance 25°C V 3 3 pF

DIGITAL OUTPUTS

Output Voltage, High (VOH) Full VI VDD − 0.1 VDD − 0.1 V Output Voltage, Low (VOL) Full VI 0.4 0.4 V Duty Cycle, DATACK Full V 45 50 55 45 50 55 % Output Coding Binary Binary

%FS %FS

Rev. 0 | Page 3 of 60

AD9380

AD9380KSTZ-100 AD9380KSTZ-150 Parameter Temp Test Level Min Typ Max Min Typ Max Unit

POWER SUPPLY

VD Supply Voltage Full IV 3.15 3.3 3.47 3.15 3.3 3.47 V DVDD Supply Voltage Full IV 1.7 1.8 1.9 1.7 1.8 1.9 V VDD Supply Voltage Full IV 1.7 3.3 3.47 1.7 3.3 3.47 V PVDD Supply Voltage Full IV 1.7 1.8 1.9 1.7 1.8 1.9 V ID Supply Current (VD) 25°C VI 260 300 330 mA I

Supply Current (DVDD) 25°C VI 45 60 85 mA

DVDD

IDD Supply Current (VDD) IP

Supply Current (P

VDD

Total Power Full VI 1.1 1.4 1.15 1.4 W Power-Down Dissipation Full VI 130 130 mW

DYNAMIC PERFORMANCE

Analog Bandwidth,

Full Power

Signal–to–Noise Ratio (SNR) 25°C I 46 46 dB

Without Harmonics

fIN = 40.7 MHz Full V 45 45 dB

Crosstalk Full V 60 60 dBc

THERMAL CHARACTERISTICS

θJA Junction-to-Ambient V 35 35 °C/W

Drive strength = high.

DATACK load = 15 pF, data load = 5 pF.

Specified current and power values with a worst-case pattern (on/off).

VDD

25°C VI 37 100

) 25°C VI 10 15 20 mA

25°C

330

130

330

MHz

DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS

VDD = VD =3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum.

Table 2.

AD9380KSTZ-100

AD9380KSTZ-150

Te st

Parameter

Level

Conditions Min Typ Max Min Typ Max Unit

RESOLUTION 8 8 Bit DC DIGITAL I/O SPECIFICATIONS

High-Level Input Voltage (VIH) VI 2.5 2.5 V Low-Level Input Voltage (VIL) VI 0.8 0.8 V High-Level Output Voltage (VOH) VI VDD − 0.1 V Low-Level Output Voltage (VOL) VI VDD − 0.1 0.1 0.1 V

DC SPECIFICATIONS

Output High Level IV Output drive = high 36 36 mA

OHD

= VOH) IV Output drive = low 24 24 mA

OUT

Output Low Level IV Output drive = high 12 12 mA

OLD

= VOL) IV Output drive = low 8 8 mA

OUT

DATACK High Level IV Output drive = high 40 40 mA

OHC

= VOH) IV Output drive = low 20 20 mA

OUT

DATACK Low Level IV Output drive = high 30 30 mA

= VOL) IV Output drive = low 15 15 mA

OLC

OUT

Differential Input Voltage, Single-

Ended Amplitude

700 75

700 mV

Rev. 0 | Page 4 of 60

AD9380

AD9380KSTZ-100

AD9380KSTZ-150

Te st

Parameter

Level

Conditions Min Typ Max Min Typ Max Unit

POWER SUPPLY

VD Supply Voltage IV 3.15 3.3 3.47 3.15 3.3 3.47 V VDD Supply Voltage IV 1.7 3.3 347 1.7 3.3 347 V DVDD Supply Voltage IV 1.7 1.8 1.9 1.7 1.8 1.9 V PVDD Supply Voltage IV 1.7 1.8 1.9 1.7 1.8 1.9 V

IVD Supply Current (Typical Pattern) I

Supply Current (Typical Pattern)

VDD

Supply Current (Typical Pattern)

DVDD

Supply Current (Typical Pattern)

PVDD

V 80 100 80 110 mA

V 40 1003 55 1753

1, 4

V 88 110 110 145 mA

V 26 35 30 40 mA

Power-Down Supply Current (IPD) VI 130 130 mA

AC SPECIFICATIONS

Intrapair (+ to −) Differential Input Skew

)

DPS

Channel to Channel Differential Input

CCS

)

Skew (T

Low-to-High Transition Time for Data and

Controls (D

LHT

)

Low-to-High Transition Time for

DATACK (D

LHT

)

High-to-Low Transition Time for Data and

Controls (D

HLT

)

High-to-Low Transition Time for

DATACK (D

HLT

)

IV Clock-to-Data Skew5 (T Duty Cycle, DATACK DATACK Frequency (F

The typical pattern contains a gray scale area, output drive = high. Worst-case pattern is alternating black and white pixels.

The typical pattern contains a gray scale area, output drive = high.

Specified current and power values with a worst-case pattern (on/off).

DATACK load = 10 pF, data load = 5 pF.

Drive strength = high.

) IV –0.5 +2.0 −0.5 +2.0 ns

SKEW

) VI 20 150 MHz

CIP

IV 45 50 55 %

360 ps

Output drive = high;

= 10 pF

Output drive = low; C

= 5 pF

Output drive = high;

= 10 pF

Output drive = low;

= 5 pF

Output drive = high; C

= 10 pF

Output drive = low;

= 5 pF

Output drive = high; C

= 10 pF

Output drive = low;

= 5 pF

900 ps

1300 ps

650 ps

1200 ps

850 ps

1250 ps

800 ps

1200 ps

Clock Period

Rev. 0 | Page 5 of 60

AD9380

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VDD 3.6 V DV

Analog Inputs VD to 0.0 V Digital Inputs 5 V to 0.0 V Digital Output Current 20 mA Operating Temperature Range −25°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Maximum Case Temperature 150°C

3.6 V

1.98 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

EXPLANATION OF TEST LEVELS

Table 4.

Level Test

I 100% production tested. II

III Sample tested only. IV

V Parameter is a typical value only. VI

100% production tested at 25°C and sample tested at specified temperatures.

Parameter is guaranteed by design and characterization testing.

100% production tested at 25°C; guaranteed by design and characterization testing.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 6 of 60

AD9380

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AIN0

AIN1

VDDRED 0

100

RED 1

RED 2

RED 3

RED 4

RED 5

RED 6

RED 7

GND

VDDDATACKDEHSOUT

898887

SOGOUT

VSOUT

O/E FIELD

SDA

SCL

PWRDN

VDR

GND

787776

GND GREEN 7 GREEN 6 GREEN 5 GREEN 4 GREEN 3 GREEN 2 GREEN 1 GREEN 0

GND

BLUE 7 BLUE 6 BLUE 5 BLUE 4 BLUE 3 BLUE 2 BLUE 1 BLUE 0

MCLKIN

MCLKOUT

SCLK

LRCLK

I2S3 I2S2

4 5 6

8 9

15 16 17 18 19 20 21 22 23 24 25

PIN 1

2 3

AD9380

TOP VIEW

(Not to Scale)

S/PDIF

GND

RxC–

RxC+

GND

Rx0–

Rx0+

GND

Rx1–

Rx2–

Rx1+

Rx2+

GND

RTERM

Figure 2. Pin Configuration

GND

AIN0

SOGIN 0

AIN1

SOGIN 1

GND

AIN0

AIN1

GND

HSYNC 0

HSYNC 1

EXTCLK/COAST

VSYNC 0

VSYNC 1

GND

FILT

GND

ALGND

PU1

PU2

DDCSCL

DDCSDA

05688-002

Table 5. Complete Pinout List

Pin Type Pin No. Mnemonic Function Value

INPUTS 79 R 77 R 74 G 71 G 68 BB 66 BB

AIN0

AIN1

AIN0

AIN1

AIN0

AIN1

Analog Input for Converter R Channel 0 0.0 V to 1.0 V Analog Input for Converter R Channel 1 0.0 V to 1.0 V Analog Input for Converter G Channel 0 0.0 V to 1.0 V Analog Input for Converter G Channel 1 0.0 V to 1.0 V Analog Input for Converter B Channel 0 0.0 V to 1.0 V

Analog Input for Converter B Channel 1 0.0 V to 1.0 V 64 HSYNC 0 Horizontal SYNC Input for Channel 0 3.3 V CMOS 63 HSYNC 1 Horizontal SYNC Input for Channel 1 3.3 V CMOS 61 VSYNC 0 Vertical SYNC Input for Channel 0 3.3 V CMOS 60 VSYNC 1 Vertical SYNC Input for Channel 1 3.3 V CMOS 73 SOGIN 0 Input for Sync-on-Green Channel 0 0.0 V to 1.0 V 70 SOGIN 1 Input for Sync-on-Green Channel 1 0.0 V to 1.0 V 62 EXTCLK External Clock Input—Shares Pin with COAST 3.3 V CMOS 62 COAST PLL COAST Signal Input—Shares Pin with EXTCLK 3.3 V CMOS 81 PWRDN Power-Down Control 3.3 V CMOS

Rev. 0 | Page 7 of 60

AD9380

Pin Type Pin No. Mnemonic Function Value

OUTPUTS 92 to 99 RED [7:0] Outputs of Red Converter, Bit 7 is MSB V 2 to 9 GREEN [7:0] Outputs of Green Converter, Bit 7 is MSB V 12 to 19 BLUE [7:0] Outputs of Blue Converter, Bit 7 is MSB V 89 DATACK Data Output Clock V 87 HSOUT HSYNC Output Clock (Phase-Aligned with DATACK) V 85 VSOUT VSYNC Output Clock (Phase-Aligned with DATACK) V 86 SOGOUT SOG Slicer Output V 84 O/E FIELD Odd/Even Field Output V REFERENCES 57 FILT Connection for External Filter Components For PLL POWER SUPPLY

80, 76, 72,

Analog Power Supply and DVI Terminators 3.3 V

67, 45, 33 100, 90, 10 V 59, 56, 54 PV 48, 32, 30 DV

Output Power Supply 1.8 V to 3.3 V PLL Power Supply 1.8 V

Digital Logic Power Supply 1.8 V GND Ground 0 V CONTROL 82 SCL Serial Port Data Clock 3.3 V CMOS 83 SDA Serial Port Data I/O 3.3 V CMOS HDCP 49 DDCSCL HDCP Slave Serial Port Data Clock 3.3 V CMOS 50 DDCSDA HDCP Slave Serial Port Data I/O 3.3 V CMOS 51 PU2 Should be tied to 3.3 V through a 10 kΩ resistor 3.3 V CMOS 52 PU1 Should be tied to 3.3 V through a 10 kΩ resistor 3.3 V CMOS AUDIO DATA OUTPUTS 28 S/PDIF S/PDIF Digital Audio Output V 27 I2S0 I2S Audio (Channel 1, Channel 2) V 26 I2S1 I2S Audio (Channel 3, Channel 4) V 25 I2S2 I2S Audio (Channel 5, Channel 6) V 24 I2S3 I2S Audio (Channel 7, Channel 8) V 20 MCLKIN External Reference Audio Clock In V 21 MCLKOUT Audio Master Clock Output V 22 SCLK Audio Serial Clock Output V 23 LRCLK Data Output Clock for Left And Right Audio Channels V DIGITAL VIDEO DATA TMDS 34 Rx0− Digital Input Channel 0 Complement TMDS 35 Rx0+ Digital Input Channel 0 True 37 Rx1− Digital Input Channel 1 Complement TMDS 38 Rx1+ Digital Input Channel 1 True 40 Rx2− Digital Input Channel 2 Complement 41 Rx2+ Digital Input Channel 2 True TMDS DIGITAL VIDEO CLOCK

43 RxC+ Digital Data Clock True TMDS

INPUTS 44 RxC− Digital Data Clock Complement TMDS DATA ENABLE 88 DE Data Enable 3.3 V CMOS RTERM 46 RTERM Sets Internal Termination Resistance 500 Ω

Rev. 0 | Page 8 of 60

AD9380

Table 6. Pin Function Descriptions

Mnemonic Description

INPUTS

AIN0

AIN1

Rx0+ Digital Input Channel 0 True. Rx0− Digital Input Channel 0 Complement. Rx1+ Digital Input Channel 1 True. Rx1− Digital Input Channel 1 Complement. Rx2+ Digital Input Channel 2 True. Rx2− Digital input Channel 2 Complement.

RxC+ Digital Data Clock True. RxC− Digital Data Clock Complement.

HSYNC 0 Horizontal Sync Input Channel 0. HSYNC 1 Horizontal Sync Input Channel 1.

VSYNC0 Vertical Sync Input Channel 0. VSYNC1 Vertical Sync Input Channel 1.

SOGIN 0 Sync-on-Green Input Channel 0. SOGIN 1 Sync-on-Green Input Channel 1.

EXTCLK/COAST

Analog Input for the Red Channel 0. Analog Input for the Green Channel 0. Analog Input for the Blue Channel 0. Analog Input for the Red Channel 1. Analog Input for the Green Channel 1. Analog Input for Blue Channel 1. High impedance inputs that accept the red, green, and blue channel graphics signals, respectively. The three

channels are identical and can be used for any colors, but colors are assigned for convenient reference. They accommodate input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation (see Figure 3 for an input reference circuit).

These six pins receive three pairs of transition minimized differential signaling (TMDS) pixel data (at 10× the pixel rate) from a digital graphics transmitter.

This clock pair receives a TMDS clock at 1× pixel data rate.

These inputs receive a logic signal that establishes the horizontal timing reference and provides the frequency reference for pixel clock generation. The logic sense of this pin is controlled by Serial Register 0x12 Bits 5:4 (HSYNC polarity). Only the leading edge of HSYNC is active; the trailing edge is ignored. When HSYNC polarity = 0, the falling edge of HSYNC is used. When HSYNC polarity = 1, the rising edge is active. The input includes a Schmitt trigger for noise immunity.

These are the inputs for vertical sync.

These inputs are provided to assist with processing signals with embedded sync, typically on the green channel. The pin is connected to a high speed comparator with an internally generated threshold. The threshold level can be programmed in 10 mV steps to any voltage between 10 mV and 330 mV above the negative peak of the input signal. The default voltage threshold is 150 mV. When connected to an ac-coupled graphics signal with embedded sync, it produces a noninverting digital output on SOGOUT. (This is usually a composite sync signal, containing both vertical and horizontal sync (HSYNC ) information that must be separated before passing the horizontal sync signal to HSYNC.) When not used, this input should be left unconnected. For more details on this function and how it should be configured, see the

HSYNC and VSYNC Inputs section.

Coast Input to Clock Generator (Optional). This input can be used to cause the pixel clock generator to stop synchronizing with HSYNC and continue producing a clock at its current frequency and phase. This is useful when processing signals from sources that fail to produce horizontal sync pulses during the vertical interval. The coast signal is generally not required for PCgenerated signals. The logic sense of this pin is controlled by coast polarity (Register 0x18, Bits 6:5). When not used, this pin can be grounded and input coast polarity programmed to 1 (Register 0x18, Pin 5) or tied high (to V

through a 10 kΩ resistor) and input coast polarity programmed to 0. Input coast polarity defaults to 1 at

power-up. This pin is shared with the EXTCLK function, which does not affect coast functionality. For more details on coast, see the Clock Generation section.

Rev. 0 | Page 9 of 60

AD9380

Mnemonic Description

EXTCLK/COAST External Clock.

PWRDN

FILT External Filter Connection.

OUTPUTS

HSOUT

VSOUT

SOGOUT

O/E FIELD

SERIAL PORT

SDA Serial Port Data I/O for Programming AD9380 Registers—I2C Address is 0x98.

SCL Serial Port Data Clock for Programming AD9380 Registers.

DDCSDA Serial Port Data I/O for HDCP Communications to Transmitter—I2C Address is 0x74 or 0x76.

DDCSCL Serial Port Data Clock for HDCP Communications to Transmitter.

DATA OUTPUTS

Red [7:0] Data Output, Red Channel.

Green [7:0] Data Output, Green Channel.

Blue [7:0] Data Output, Blue Channel.

DATA CLOCK OUTPUT

DATACK

This allows the insertion of an external clock source rather than the internally generated PLL-locked clock. This pin is shared with the coast function, which does not affect EXTCLK functionality.

Power-Down Control/Three-State Control. The function of this pin is programmable via Register 0x26 [2:1].

For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in to this pin. For optimal performance, minimize noise and parasitics on this node. For more information see the PCB Layout Recommendations section .

Horizontal Sync Output. A reconstructed and phase-aligned version of the HSYNC input. Both the polarity and duration of this output can be programmed via serial bus registers. By maintaining alignment with DATACK and data, data timing with respect to horizontal sync can always be determined.

Vertical Sync Output. The separated VSYNC from a composite signal or a direct pass through of the VSYNC signal. The polarity of this output can be controlled via the serial bus bit (Register 0x24 [6]).

Sync-on-Green Slicer Output. This pin outputs one of four possible signals (controlled by Register 0x1D [1:0]): raw SOG, raw HSYNC, regenerated HSYNC from the filter, or the filtered HSYNC. See the Sync processing block diagram (see connections). Note that besides slicing off SOG, the output from this pin is not processed on the AD9380. VSYNC separation is performed via the sync separator.

Odd/Even Field Bit for Interlaced Video. This output identifies whether the current field (in an interlaced signal) is odd or even. The polarity of this signal is programmable via Register 0x24[4].

Should be tied to 3.3 V through a 10 kΩ resistor.

The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed, but is different if the color space converter is used. When the sampling time is changed by adjusting the phase register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing relationship among the signals is maintained.

Data Clock Output. This is the main clock output signal used to strobe the output data and HSOUT into external logic. Four possible output clocks can be selected with Register 0x25 [7:6]. These are related to the pixel clock (1/2× pixel clock, 1× pixel clock, 2× frequency pixel clock, and a 90° phase shifted pixel clock). They are produced either by the internal PLL clock generator or EXTCLK and are synchronous with the pixel sampling clock. The polarity of DATACK can also be inverted via Register 0x24 [0]. The sampling time of the internal pixel clock can be changed by adjusting the phase register. When this is changed, the pixel-related DATACK timing is shifted as well. The DATA, DATACK, and HSOUT outputs are all moved, so the timing relationship among the signals is maintained.

Figure 6

Figure 8 for pin

Rev. 0 | Page 10 of 60

AD9380

Mnemonic Description

POWER SUPPLY

VD (3.3 V)

VDD (1.8 V to 3.3 V)

PVDD (1.8 V)

DVDD (1.8 V)

GND

The supplies should be sequenced such that VD and VDD are never less than 300 mV below DVDD. At no time should DVDD be more than 300 mV greater than VD or VDD.

Analog Power Supply. These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible.

Digital Output Power Supply. A large number of output pins (up to 27) switching at high speed (up to 150 MHz) generates many power supply transients (noise). These supply pins are identified separately from the VD pins, so output noise transferred into the sensitive analog circuitry can be minimized. If the AD9380 is interfacing with lower voltage logic, V

may be

connected to a lower supply voltage (as low as 1.8 V) for compatibility. Clock Generator Power Supply.

The most sensitive portion of the AD9380 is the clock generation circuitry. These pins provide power to the clock PLL and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins.

Digital Input Power Supply. This supplies power to the digital logic.

Ground. The ground return for all circuitry on chip. It is recommended that the AD9380 be assembled on a single solid ground plane, with careful attention to ground current paths.

Rev. 0 | Page 11 of 60

AD9380

DESIGN GUIDE

GENERAL DESCRIPTION

The AD9380 is a fully integrated solution for capturing analog RGB or YUV signals and digitizing them for display on flat panel monitors, projectors, or plasma display panels (PDPs). In addition, the AD9380 has a digital interface for receiving DVI/HDMI signals and is capable of decoding HDCPencrypted signals through connections to an internal EEPROM. The circuit is ideal for providing an interface for HDTV monitors or as the front end to high performance video scan converters.

Implemented in a high performance CMOS process, the interface can capture signals with pixel rates of up to 150 MHz.

The AD9380 includes all necessary input buffering, signal dc restoration (clamping), offset and gain (brightness and contrast) adjustment, pixel clock generation, sampling phase control, and output data formatting. Included in the output formatting is a color space converter (CSC), which accommodates any input color space and can output any color space. All controls are programmable via a 2-wire serial interface. Full integration of these sensitive analog functions makes system design straightforward and less sensitive to the physical and electrical environments.

DIGITAL INPUTS

All digital control inputs (HSYNC, VSYNC, and I2C) on the AD9380 operate to 3.3 V CMOS levels. In addition, all digital inputs, except the TMDS (HDMI/DVI) inputs, are 5 V tolerant. (Applying 5 V to them does not cause any damage.) TMDS inputs (Rx0+/Rx0−, Rx1+/Rx1−, Rx2+/Rx2−, and RxC+/RxC−) must maintain a 100 Ω differential impedance (through proper PCB layout) from the connector to the input where they are internally terminated (50 Ω to 3.3 V). If additional ESD protection is desired, use of a California Micro Devices (CMD) CM1213 series low capacitance ESD protection (among others) offers 8 kV of protection to the HDMI TMDS lines.

ANALOG INPUT SIGNAL HANDLING

The AD9380 has six high impedance analog input pins for the red, green, and blue channels. They accommodate signals ranging from 0.5 V p-p to 1.0 V p-p.

Signals are typically brought onto the interface board via a DVI-I connector, a 15-pin D connector, or RCA-type connectors. The AD9380 should be located as close as practical to the input connector. Signals should be routed via 75  matched impedance traces to the IC input pins.

At the input of the AD9380, the signal should be resistively terminated (75  to the signal ground return) and capacitively coupled to the AD9380 inputs through 47 nF capacitors. These capacitors form part of the dc restoration circuit.

Rev. 0 | Page 12 of 60

In an ideal world of perfectly matched impedances, the best performance can be obtained with the widest possible signal bandwidth. The ultrawide bandwidth inputs of the AD9380 (330 MHz) can track the input signal continuously as it moves from one pixel level to the next, and digitizes the pixel during a long, flat pixel time. In many systems, however, there are mismatches, reflections, and noise, which can result in excessive ringing and distortion of the input waveform. This makes it more difficult to establish a sampling phase that provides good image quality. It has been shown that a small inductor in series with the input is effective in rolling off the input bandwidth slightly, and providing a high quality signal over a wider range of conditions. Using a Fair-Rite #2508051217Z0 high speed signal chip bead inductor in the circuit, as shown in

Figure 3,

gives good results in most applications.

RGB

INPUT

Figure 3. Analog Input Interface Circuit

47nF

75Ω

AIN

05688-003

HSYNC AND VSYNC INPUTS

The interface also takes a horizontal sync signal, which is used to generate the pixel clock and clamp timing. This can be either a sync signal directly from the graphics source or a preprocessed TTL or CMOS level signal.

The HSYNC input includes a Schmitt trigger buffer for immunity to noise and signals with long rise times. In typical PC-based graphic systems, the sync signals are simply TTLlevel drivers feeding unshielded wires in the monitor cable. As such, no termination is required.

SERIAL CONTROL PORT

The serial control port is designed for 3.3 V logic. However, it is tolerant of 5 V logic signals.

OUTPUT SIGNAL HANDLING

The digital outputs (VDD) operate from 1.8 V to 3.3 V.

CLAMPING

RGB Clamping

To properly digitize the incoming signal, the dc offset of the input must be adjusted to fit the range of the on-board ADC.

Most graphics systems produce RGB signals with black at ground and white at approximately 0.75 V. However, if sync signals are embedded in the graphics, the sync tip is often at ground and black is at 300 mV. Then white is at approximately

1.0 V. Some common RGB line amplifier boxes use emitterfollower buffers to split signals and increase drive capability. This introduces a 700 mV dc offset to the signal, which must be removed for proper capture by the AD9380.

AD9380

The key to clamping is to identify a portion (time) of the signal when the graphic system is known to be producing black. An offset is then introduced which results in the ADCs producing a black output (Code 0x00) when the known black input is present. The offset then remains in place when other signal levels are processed, and the entire signal is shifted to eliminate offset errors.

In most pc graphics systems, black is transmitted between active video lines. With CRT displays, when the electron beam has completed writing a horizontal line on the screen (at the right side), the beam is deflected quickly to the left side of the screen (called horizontal retrace) and a black signal is provided to prevent the beam from disturbing the image.

In systems with embedded sync, a blacker-than-black signal (HSYNC) is produced briefly to signal the CRT that it is time to begin a retrace. For obvious reasons, it is important to avoid clamping on the tip of HSYNC. Fortunately, there is virtually always a period following HSYNC, called the back porch, where a good black reference is provided. This is the time when clamping should be done.

Clamp timing employs the AD9380 internal clamp timing generator. The clamp placement register is programmed with the number of pixel periods that should pass after the trailing edge of HSYNC before clamping starts. A second register (clamp duration) sets the duration of the clamp. These are both 8-bit values, providing considerable flexibility in clamp generation. The clamp timing is referenced to the trailing edge of HSYNC because, though HSYNC duration can vary widely, the back porch (black reference) always follows HSYNC. A good starting point for establishing clamping is to set the clamp placement to 0x08 (providing 8 pixel periods for the graphics signal to stabilize after sync) and to set the clamp duration to 0x14 (giving the clamp 20 pixel periods to re-establish the black reference). For three-level syncs embedded on the green channel, it is necessary to increase the clamp placement to beyond the positive portion of the sync. For example, a good clamp placement (Register 0x19) for a 720p input is 0x26. This delays the start of clamp by 38 pixel clock cycles after the rising edge of the three-level sync, allowing plenty of time for the signal to return to a black reference.

YUV Clamping

YUV graphic signals are slightly different from RGB signals in that the dc reference level (black level in RGB signals) can be at the midpoint of the graphics signal rather than at the bottom. For these signals, it can be necessary to clamp to the midscale range of the ADC range (128) rather than thebottom of the ADC range (0).

Clamping to midscale rather than ground can be accomplished by setting the clamp select bits in the serial bus register. Each of the three converters has its own selection bit so that they can be clamped to either midscale or ground independently. These bits are located in Register 0x1B [7:5]. The midscale reference voltage is internally generated for each converter.

Auto-Offset

The auto-offset circuit works by calculating the required offset setting to yield a given output code during clamp. When this block is enabled, the offset setting in the I clamp code rather than an actual offset. The circuit compares the output code during clamp to the desired code and adjusts the offset up or down to compensate.

The offset on the AD9380 can be adjusted automatically to a specified target code. Using this option allows the user to set the offset to any value and be assured that all channels with the same value programmed into the target code match. This eliminates any need to adjust the offset at the factory. This function is capable of running continuously any time the clamp is asserted.

There is an offset adjust register for each channel, namely the offset registers at the 0x08, 0x0A, and 0x0C addresses. The offset adjustment is a signed (twos complement) number with a ±64 LSB range. The offset adjustment is added to whatever offset the auto-offset comes up with. For example, using a ground clamp, the target code is set to 4. To get this code, the auto-offset generates an offset of 68. If the offset adjustment is set to +10, the offset sent to the converter is 78. Likewise, if the offset adjust is set to −10, the offset sent to the converter is +58. Refer to Application Note

Offset Function of the AD9880, for a detailed description of how

to use this function.

AN-775, Implementing the Auto-

C is seen as a desired

Clamping is accomplished by placing an appropriate charge on the external input coupling capacitor. The value of this capacitor affects the performance of the clamp. If it is too small, there is a significant amplitude change during a horizontal line time (between clamping intervals). If the capacitor is too large, then it takes excessively long for the clamp to recover from a large change in the incoming signal offset. The recommended value (47 nF) results in recovering from a step error of 100 mV to within ½ LSB in 10 lines with a clamp duration of 20 pixel periods on a 75 Hz SXGA signal.

Rev. 0 | Page 13 of 60

Sync-on-Green (SOG)

The SOG input operates in two steps. First, it sets a baseline clamp level from the incoming video signal with a negative peak detector. Second, it sets the sync trigger level to a programmable level (typically 150 mV) above the negative peak. The SOG input must be ac-coupled to the green analog input through its own capacitor. The value of the capacitor must be 1 nF ± 20%. If SOG is not used, this connection is not required. Note that the SOG signal is always negative polarity.

AD9380

For more detail on setting the SOG threshold and other SOGrelated functions, see the

Figure 4. Typical Clamp Configuration for RGB/YUV Applications

Clock Generation

A PLL is employed to generate the pixel clock. In this PLL, the HSYNC input provides a reference frequency. A voltage controlled oscillator (VCO) generates a much higher pixel clock frequency. This pixel clock is divided by the PLL divide value (Register 0x01 and Register 0x02) and phase compared with the HSYNC input. Any error is used to shift the VCO frequency and maintain lock between the two signals.

The stability of this clock is a very important element in providing the clearest and most stable image. During each pixel time, there is a period during which the signal slews from the old pixel amplitude and settles at its new value. This is followed by a time when the input voltage is stable before the signal must slew to a new value. The ratio of the slewing time to the stable time is a function of the bandwidth of the graphics DAC and the bandwidth of the transmission system (cable and termination). It is also a function of the overall pixel rate. Clearly, if the dynamic characteristics of the system remain fixed, then the slewing and settling time is likewise fixed. This time must be subtracted from the total pixel period, leaving the stable period. At higher pixel frequencies, the total cycle time is shorter and the stable pixel time also becomes shorter.

PIXEL CLOCK INVALID SAMPLE TIMES

Sync Processing section.

47nF

1nF

AIN

SOG

05688-004

47nF

The PLL characteristics are determined by the loop filter design, the PLL charge pump current, and the VCO range setting. The loop filter design is shown in

Figure 6. Recommended settings of the VCO range and charge pump current for VESA standard display modes are listed in

Tabl e 9 .

80nF

1.5kΩ

FILT

Figure 6. PLL Loop Filter Detail

05688-006

Four programmable registers are provided to optimize the performance of the PLL. These registers are:

• The 12-bit divisor register (R0x01, R0x02). The input

HSYNC frequency range can be any frequency which, combined with the PLL_Div, does not exceed the VCO range . The PLL multiplies the frequency of the HSYNC signal, producing pixel clock frequencies in the range of 10 MHz to 100 MHz. The divisor register controls the exact multiplication factor.

• The 2-bit VCO range register (R0x03[7:6]). To improve the

noise performance of the AD9380, the VCO operating frequency range is divided into four overlapping regions. The VCO range register sets this operating range. The frequency ranges for the lowest and highest regions are shown in

Tabl e 7.

Table 7.

VCORNGE Pixel Rate Range

00 12 to 30 01 30 to 60 10 60 to 120 11 120 to 150

• The 5-bit phase adjust register (R0x04). The phase of the

generated sampling clock can be shifted to locate an optimum sampling point within a clock cycle. The phase adjust register provides 32 phase-shift steps of 11.25° each. The HSYNC signal with an identical phase shift is available through the HSOUT pin.

The coast pin or the internal coast is used to allow the PLL to

05688-005

Figure 5. Pixel Sampling Times

Any jitter in the clock reduces the precision with which the sampling time can be determined and must also be subtracted from the stable pixel time. Considerable care has been taken in the design of the AD9380 clock generation circuit to minimize jitter. The clock jitter of the AD9380 is less than 13% of the total pixel time in all operating modes, making the reduction in the valid sampling time due to jitter negligible.

continue to run at the same frequency, in the absence of the incoming HSYNC signal or during disturbances in HSYNC (such as equalization pulses). Coasting can be used during the vertical sync period or any other time that the HSYNC signal is unavailable. The polarity of the coast signal can be set through the coast polarity register. Also, the polarity of the HSYNC signal can be set through the HSYNC polarity register. For both HSYNC and coast, a value of 1 is active high. The internal coast function is driven off the VSYNC signal, which is typically a time when HSYNC signals can be disrupted with extra equalization pulses.

Rev. 0 | Page 14 of 60

AD9380

Power Management

The AD9380 uses the activity detect circuits, the active interface bits in the serial bus, the active interface override bits, the power-down bit, and the power-down pin to determine the correct power state. There are four power states: full-power, seek mode, auto power-down, and power-down.

Table 8 summarizes how the AD9380 determines the power mode and the circuitry that is powered on/off in each of these modes. The power-down command has priority and then the

Table 8. Power-Down Mode Descriptions

Inputs Mode Power-Down1 Sync Detect2 Auto PD Enable3 Power-On or Comments

Full Power 1 1 X Everything Seek Mode 1 0 0 Everything Seek Mode 1 0 1

Power-Down 0 X

Power-down is controlled via Bit 0 in Serial Bus Register 0x26.

Sync detect is determined by OR’ing Bit 7 to Bit 2 in Serial Bus Register 0x15.

Auto power-down is controlled via Bit 7 in Serial Bus Register 0x27.

Table 9. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats

Standard

Resolution

Refresh Rate (Hz)

Horizontal Frequency (kHz)

VGA 640 × 480 60 31.5 25.175 00 101 72 37.7 31.500 01 011 75 37.5 31.500 01 100 85 43.3 36.000 01 100 SVGA 800 × 600 56 35.1 36.000 01 100 60 37.9 40.000 01 101 72 48.1 50.000 01 110 75 46.9 49.500 01 110 85 53.7 56.250 01 110 XGA 1024 × 768 60 48.4 65.000 10 011 70 56.5 75.000 10 100 75 60.0 78.750 10 100 80 64.0 85.500 10 101 85 68.3 94.500 10 110 SXGA 1280 × 1024 60 64.0 108.000 10 110 1280 × 1024 75 80.0 135.000 11 110 TV 480i 60 15.75 13.51 00 010 480p 60 31.47 27 00 101 720p 60 45 74.25 10 100 1035i 60 33.75 74.25 10 100 1080i 60 33.75 74.25 10 100 1080p 60 67.5 148.5 11 110

These are preliminary recommendations for the analog PLL and are subject to change without notice.

automatic circuitry. The power-down pin (Pin 81—polarity set by Register 0x26[3]) can drive the chip into four power-down options. Bit 2 and Bit 1 of Register 0x26 control these four options. Bit 0 controls whether the chip is powered down or the outputs are placed in high impedance mode (with the exception of SOG). Bit 7 to Bit 4 of Register 0x26 control whether the

outputs, SOG, Sony Philips digital interface (SPDIF ) or I

S (IIS or Inter-IC Sound bus) outputs are in high impedance mode or not. (See the 2-Wire Serial Control Register Detail section for more detail.)

Serial bus, sync activity detect, SOG, band gap reference

Pixel Rate (MHz)

VCO Range

Current1

Rev. 0 | Page 15 of 60

AD9380

TIMING

The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally.

There is a pipeline in the AD9380, which must be flushed before valid data becomes available. This means 23 data sets are presented before valid data is available.

Figure 7 shows the timing of the AD9380.

PER

DCYCLE

DATAC

SKEW

DATA

HSOUT

Figure 7. Output Timing

HSYNC Timing

Horizontal sync (HSYNC) is processed in the AD9380 to eliminate ambiguity in the timing of the leading edge with respect to the phase-delayed pixel clock and data.

The HSYNC input is used as a reference to generate the pixel sampling clock. The sampling phase can be adjusted, with respect to HSYNC, through a full 360° in 32 steps via the phase adjust register (to optimize the pixel sampling time). Display systems use HSYNC to align memory and display write cycles, so it is important to have a stable timing relationship between the HSYNC output (HSOUT) and data clock (DATACK).

05688-007

Three things happen to HSYNC in the AD9380. First, the polarity of the HSYNC input is determined and thus has a known output polarity. The known output polarity can be programmed either active high or active low (Register 0x24, Bit 7). Second, HSOUT is aligned with DATACK and the data outputs. Third, the duration of HSOUT (in pixel clocks) is set via Register 0x23. HSOUT is the sync signal to use to drive the rest of the display system.

Coast Timing

In most computer systems, the HSYNC signal is provided continuously on a dedicated wire. In these systems, the coast input and function are unnecessary and should not be used. The pin should be permanently connected to the inactive state.

In some systems, however, HSYNC is disturbed during the vertical sync period (VSYNC). In some cases, HSYNC pulses disappear. In other systems, such as those that employ composite sync (Csync) signals or embedded SOG, HSYNC includes equalization pulses or other distortions during VSYNC. To avoid upsetting the clock generator during VSYNC, it is important to ignore these distortions. If the pixel clock PLL sees extraneous pulses, it attempts to lock to this new frequency, and changes frequency by the end of the VSYNC period. It then takes a few lines of correct HSYNC timing to recover at the beginning of a new frame, which tears the image at the top of the display.

The coast input is provided to eliminate this problem. It is an asynchronous input that disables the PLL input and allows the clock to free run at its then-current frequency. The PLL can free-run for several lines without significant frequency drift.

Coast can be generated internally by the AD9380 (see Register 0x12 [1]), can be driven directly from a VSYNC input, or can also be provided externally by the graphics controller.

Rev. 0 | Page 16 of 60

AD9380

Sync Processing

The inputs of the AD9380 sync processing section are combinations of digital HSYNCs and VSYNCs, analog sync-ongreen signal, sync-on-Y signal, and an optional external coast signal. From these signals, the AD9380 generates a precise, jitter-free (9% or less at 95 MHz) clock from its PLL; an odd/even field signal; HSYNC and VSYNC out signals; a count of HSYNCs per VSYNC; and a programmable SOG output. The main sync processing blocks are the sync slicer, sync separator, HSYNC filter, HSYNC regenerator, VSYNC filter, and coast generator.

The sync slicer extracts the sync signal from the green graphics or luminance video signal that is connected to the SOGIN input and outputs a digital composite sync. The sync separator’s task

is to extract VSYNC from the composite sync signal, which can come from either the sync slicer or the HSYNC input. The HSYNC filter is used to eliminate any extraneous pulses from the HSYNC or SOGIN inputs, outputting a clean, low jitter signal that is appropriate for mode detection and clock generation. The HSYNC regenerator is used to recreate a clean, although not low jitter, HSYNC signal that can be used for mode detection and for counting HSYNCs per VSYNC. The VSYNC filter is used to eliminate spurious VSYNCs, maintain a stable timing relationship between the VSYNC and HSYNC output signals, and generate the odd/even field output. The coast generator creates a robust coast signal that allows the PLL to maintain its frequency in the absence of HSYNC pulses.

HSYNC 0

HSYNC 1

SOGIN 0

SOGIN 1

VSYNC 0

VSYNC 1

COAST

SYNC

SLICER

SYNC

SLICER

AD9380

ACTIVITY DETECT

POLARITY DETECT

REGENERATED HSYNC

FILTERED HSYNC

SET POLARITY

MUX

FILTER COAST VSYNC

MUX

CHANNEL SELECT

VSYNC

0x12:0

[0x11:3]

PROCESSOR

VSYNC FILTER

HSYNC SELECT

SP SYNC FILTER EN

SYNC

AND

PLL SYNC FILTER EN

MUX

COAST SELECT

0x12:1

Figure 8. Sync Processing Block Diagram

MUX

0x21:7

0x21:6

COAST

[0x11:7]

MUX

HSYNC

MUX

PLL CLOCK

GENERATOR

HSYNC FILTER

AND

REGENERATOR

SOGOUT SELECT

FILTERED

HSYNC/VSYNC

COUNTER

REG 26H, 27H

0x24:2,1

VSYNC

VSYNC FILTER EN

MUX

0x21:5

5MUX

SOGOUT

VSOUT

O/E

FIELD

HSOUT

DATACK

05688-008

Rev. 0 | Page 17 of 60

AD9380

Sync Slicer

The purpose of the sync slicer is to extract the sync signal from the green graphics or luminance video signal that is connected to the SOGIN input. The sync signal is extracted in a two-step process. First, the SOG input (typically 0.3 V below the black level) is detected and clamped to a known dc voltage. Next, the signal is routed to a comparator with a variable trigger level (set by Register 0x1D, Bits [7:3]), but nominally 0.128 V above the clamped voltage. The sync slicer output is a digital composite sync signal containing both HSYNC and VSYNC information (see Figure 9).

Sync Separator

As part of sync processing, the sync separator’s task is to extract VSYNC from the composite sync signal. It works on the idea that the VSYNC signal stays active for a much longer time than the HSYNC signal. By using a digital low-pass filter and a digital comparator, it rejects pulses with small durations (such as HSYNCs and equalization pulses) and only passes pulses with large durations, such as VSYNC (see Figure 9).

The threshold of the digital comparator is programmable for maximum flexibility. To program the threshold duration, write a value (N) to Register 0x11. The resulting pulse width is N × 200 ns. So, if N = 5 the digital comparator threshold is 1 µs. Any pulses less than 1 µs are rejected, while any pulses greater than 1 µs pass through.

The sync separator on the AD9380 is simply an 8-bit digital counter with a 6 MHz clock. It works independently of the polarity of the composite sync signal. Polarities are determined elsewhere on the chip. The basic idea is that the counter counts up when HSYNC pulses are present. But because HSYNC pulses are relatively short in width, the counter only reaches a

value of N before the pulse ends. It then starts counting down until eventually reaching 0 before the next HSYNC pulse arrives. The specific value of N varies for different video modes, but is always less than 255. For example, with a 1 s width HSYNC, the counter only reaches 5 (1 s/200 ns = 5). Now, when VSYNC is present on the composite sync, the counter also counts up. However, because the VSYNC signal is much longer, it counts to a higher number, M. For most video modes, M is at least 255. So VSYNC can be detected on the composite sync signal by detecting when the counter counts to higher than N. The specific count that triggers detection, T, can be programmed through the Serial Register 0x11.

Once VSYNC has been detected, there is a similar process to detect when it goes inactive. At detection, the counter first resets to 0, then starts counting up when VSYNC finishes. As in the previous case, it detects the absence of VSYNC when the counter reaches the threshold count, T. In this way, it rejects noise and/or serration pulses. Once VSYNC is detected to be absent, the counter resets to 0 and begins the cycle again.

There are two things to keep in mind when using the sync separator. First, the resulting clean VSYNC output is delayed from the original VSYNC by a duration equal to the digital comparator threshold (N × 200 ns). Second, there is some variability to the 200 ns multiplier value. The maximum variability over all operating conditions is ±20% (160 ns to 240 ns). Because normal VSYNC and HSYNC pulse widths differ by a factor of about 500 or more, 20% variability is not an issue.

NEGATIVE PULSE WIDTH = 40 SAMPLE CLOCKS

700mV MAXIMUM

HSIN

+300mV

0mV

–300mV

Figure 9. Sync Slicer and Sync Separator Output

05688-009

SOGIN

OGOUT OUTPUT CONNECTED TO

COMPOSITE

SYNC

AT HSIN

VSOUT

FROM SYNC

SEPARATOR

Rev. 0 | Page 18 of 60

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