ANALOG DEVICES AD9289 Service Manual

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2.3MHz Typical at Nominal Conditions, 2VFS Int Ref

Rev. PrJ

6/25/2004

Quad 8-Bit, 65 MSPS

Serial LVDS 3V A/D Converter

Preliminary Technical Data AD9289

FEATURES

• Four ADCs in one package

• Serial LVDS digital output data rates up to 520 Mbps (ANSI-

644)

• Data clock output provided

• SNR = 47 dB (to Nyquist)

• Excellent Linearity:

DNL = ±0.25 LSB (Typical) INL = ±0.5 LSB (Typical)

• 400 MHz full power analog bandwidth

• Power dissipation = 112 mW Core ADC Power

per channel at 65 MSPS

• 1 Vpp – 2 Vpp input voltage range

• +3.0 V supply operation

• Power down mode

APPLICATIONS

• Tape drives

• Medical imaging

PRODUCT DESCRIPTION

The AD9289 is a quad 8-bit, 65 MSPS analog–to–digital converter with an on–chip track–and–hold circuit and is designed for low cost, low power, small size and ease of use. The product operates up to 65 MSPS conversion rate and is optimized for outstanding dynamic performance where a small package size is critical.

The ADC requires a single+3V power supply and an LVDS compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. A separate output power supply pin supports LVDS compatible serial digital output levels.

The ADC automatically multiplies up the sample rate clock for the appropriate LVDS serial data rate. An FCO trigger is provided to signal a new output byte. Power down is supported, and the ADC consumes less than 10mW when enabled.

Fabricated on an advanced CMOS process, the AD9289 is available in a 64-ball mini-BGA package (64 CSP_BGA) specified over the industrial temperature range (–40°C to +85°C).

FUNCTIONAL BLOCK DIAGRAM

VIN+A

VIN-A

VIN+D VIN-D

VREF

SENSE

REFT_A REFB_A REFT_B REFB_B

SHARED_REF CML

AVDD DRVDD

DRGND

Ref

Select

Figure 1. Functional Block Diagram

PDWN

AD9289

SHA

0.5 V

Pipeline

ADC

Pipeline

ADC

FCO+ FCO-

Data Rate

Multiplier

CLK+ CLK-AGND

Serial LVDS

OR+ OR-S1

PRODUCT HIGHLIGHTS

1. Four analog-to-digital converters are contained in one small,

space saving package.

2. A Data Clock Out (DCO) is provided which operates up to

260 MHz.

3. The outputs of each ADC are serialized and provided on the

rising and falling edge of DCO). Output data rates up to 520 Mbps (8 bits x 65 MSPS) are available.

4. The AD9289 operates from a single 3V power supply.

5. The clock duty cycle stabilizer maintains performance over a

wide range of input clock duty cycles

AD9289 R1

SNR = 49.1dB, SFDR = 71.9dB

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100 0 5 10 15 20 25 30

D1+A D1-A

D1+D D1-D

LVDSBIAS LOCK

DCO+ DCO-

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

Figure 2. Measured FFT

AD9289 Preliminary Technical Data

TABLE OF CONTENTS

AD9289—Specifications ............................................................ 3

DIGITAL SPECIFICATIONS ................................................. 4

AC SPECIFICATIONS........................................................... 4

SWITCHING SPECIFICATIONS........................................... 5

EXPLANATION OF TEST LEVELS...................................... 5

Absolute Maximum Ratings........................................................ 6

Definitions .................................................................................7

Theory of Operation ...................................................................9

Clock Input............................................................................. 9

Analog Inputs......................................................................... 9

Voltage Reference....................................................................9

Internal Reference Connection ...............................................10

External Reference Operation ................................................10

Digital Outputs......................................................................11

Timing..................................................................................11

PLL

CML Pin ............................................................................... 11

Overange............................................................................... 11

Pin Configurations ....................................................................13

Timing Diagram........................................................................14

Ordering Guide .....................................................................16

Output ................................................................ 11

LOCK

REVISION HISTORY

Revision PrA: Initial Version

Revision PrB: Updated specifications

Revision PrC: Added application section

Revision PrD: Revised block diagram, added LOCK/ output to timing diagram, added offset and gain matching definitions, updated Theory of Operation

Revision PrE: Updated timing diagram and PLL description

Revision PrF: Updated Timing Specs, Pin Function Description (Added DNC pins), Added Pin Configuration Diagram and Package Outline

Revision PrG: Added DCR pin info, updated lvdsbias resistor value,

Revision H: Updated reference description, Removed S3, Added scope plot, Added FFT, Updated Tpd, Tcpd, Tmsb, Power, Updated LVDSBIAS Resistor value, Min Encodeà 20MSPS

Revision I: Updated Power Supply Range, Added thermal impedance number,

Revision J: Added CML description, Modified Timing Diagram, Changed MSB naming to FCO,Removed S2, Modified Tpd,

Rev. PrJ | Page 2 of 16 6/25/2004

Preliminary Technical Data AD9289

AD9289—SPECIFICATIONS

AVDD = 3.0V, DRVDD = 3.0V; INT REF; DIFFERENTIAL ANALOG AND CLOCK INPUTS

Parameter Temp Test Level Min Typ Max Unit

RESOLUTION 8 Bits

No Missing Codes Full VI Guaranteed Offset Matching Gain Matching2

ACCURACY

TEMPERATURE DRIFT

REFERENCE

ANALOG INPUTS

POWER SUPPLY

CROSSTALK Crosstalk Full V 70 dB

Differential Nonlinearity (DNL) Full VI LSB Integral Nonlinearity (INL) Full VI LSB Offset Error Full V Gain Error2 Full V Reference Full V Internal Reference Voltage Output Current Full V uA Input Current Full V uA Input Resistance Full V 7 Differential Input Voltage Range 1 –2 Vpp Common Mode Voltage Full V 1.5 V Input Resistance Full V tbd Input Capacitance Full V 5 pF Analog Bandwidth, Full Power Full V 400 MHz AVDD Full IV 2.85 3.0 3.15 V DRVDD Full IV 2.85 3.0 3.15 V Power Dissipation3 Full VI 558 mW Power Down Dissipation Full VI <10 mW Power Supply Rejection Ratio

(PSRR) IAVDD3 Full VI 150 mA DRVDD3 Full VI 36 mA

25°C 25°C 25°C

25°C

Table 1

I I I

± 25

± 2

± 0.25

± 0.5

± 16

± 150

I 0.5 V

I mV/V

mV % FS LSB

LSB

ppm/°C ppm/°C ppm/°C

kΩ

Specifications subject to change without notice

Gain error and gain temperature coefficients are based on the ADC only (with a fixed 0.5 V external reference and a 1 V p-p differential analog input).

Power dissipation measured with rated encode and a dc analog input (Outputs Static, I

0.5dBFS. Rev. PrJ | Page 3 of 16 6/25/2004

VDD

= 0.). I

VCC

and I

measured with TBD MHz analog input @

VDD

AD9289 Preliminary Technical Data

DIGITAL SPECIFICATIONS

AVDD = 3.0V, DRVDD = 3.0V

Parameter Temp Test

Min Typ Max Unit

Level

Differential Input Voltage1 Full IV 247 mVpp CLOCK INPUTS (CLK+, CLK-)

LOGIC INPUTS

(LVDS Mode)

Input Common Mode Voltage Full IV 1.25 V

Input Resistance Full IV

Input Capacitance

Logic ‘1’ Voltage Full IV 2.0 V

Logic ‘0’ Voltage Full IV 0.8 V

Input Resistance Full IV 30

Input Capacitance Full IV 4 PF

Differential Output Voltage (VOD) Full IV 247 454 mV

Output Offset Voltage (VOS) Full IV 1.125 1.375 V DIGITAL OUTPUTS

Output Coding Full IV Twos Complement or

Table 2: Digital Specifications

25°C

IV pF

Binary

kΩ

AC SPECIFICATIONS2

AVDD = 3.0 V, DRVDD = 3.0 V; INTERNAL REF; DIFFERENTIAL ANALOG AND CLOCK INPUT, LVDS OUTPUT MODE

Parameter Temp Test

Level

SIGNAL TO NOISE RATIO (SNR) –

Without Harmonics

SIGNAL TO NOISE RATIO (SINAD) –

With Harmonics

EFFECTIVE NUMBER OF BITS

(ENOB)

SPURIOUS FREE DYNAMIC RANGE

(SFDR)

SECOND AND THIRD HARMONIC

DISTORTION

TOTAL HARMONIC DISTORTION (THD)

Clock Inputs are LVDS compatible .Clock Inputs require external DC bias and cannot be AC coupled.

SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 1 Vpp full-scale input range.

fIN= 10.3 MHz

fIN= 19.6 MHz

fIN= 32.5 MHz

fIN= 51 MHz

fIN= 10.3 MHz

fIN= 19.6 MHz

fIN= 32.5 MHz

fIN= 51 MHz

fIN= 10.3 MHz

fIN= 19.6 MHz

fIN= 32.5 MHz

fIN= 51 MHz

fIN= 10.3 MHz

fIN= 19.6 MHz

fIN= 32.5 MHz

fIN= 51 MHz

fIN= 10.3 MHz

fIN= 19.6 MHz

fIN= 32.5 MHz

fIN= 51 MHz

fIN= 10.3 MHz

fIN= 19.6 MHz

fIN= 32.5 MHz

fIN= 51 MHz

25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C

V 47.5 dB V dB

I 47.5 dB V dB V 47 dB V dB

I 47 dB V dB V 7.5 Bits V Bits

I 7.5 Bits V Bits V 62 dB V dB

I 59 dB V dB V 62 dBc V dBc

I 59 dBc V dBc V 60 dBc V dBc

I 58 dBc V dBc

Min Typ Max Unit

Rev. PrJ | Page 4 of 16 6/25/2004

Preliminary Technical Data AD9289

Parameter Temp Test

Level

INTERMOD DISTORTION (IMD)

= 19 MHz, f

IN1

= xx MHz, f

IN1

= 20 MHz

IN2

= xx MHz

IN2

25°C 25°C

Table 3: AC Specifications

V dBc TWO TONE V dBc

SWITCHING SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V; DIFFERENTIAL ENCODE INPUT

Parameter Temp Test Level Min Typ Max Unit

Maximum Clock Rate Full VI 65 MSPS

CLOCK

OUTPUT PARAMETERS IN

LVDS MODE

APERTURE

Minimum Clock Rate Full VI 20 MSPS Clock Pulse Width High (tEH) Full IV 6.9 ns Clock Pulse Width Low (tEL) Full IV 6.9 ns Valid Time (tV)1 Full VI ns Propagation Delay (tPD) 1 Full VI 10 ns MSB Propagation Delay (t

) 1 Full VI 10 ns

MSB

Rise Time (tR) (20% to 80%) Full V 0.5 ns Fall Time (tF) (20% to 80%) Full V 0.5 ns DCO Propagation Delay (t Data to DCO Skew (tPD – t

) Full VI 10 ns

CPD

) Full IV

CPD

Pipeline Latency Full VI 6 cycles Aperture Delay (tA) Aperture Uncertainty (Jitter)

Table 4: Switching Specifications

25°C 25°C

Min Typ Max Unit

+/- 100

V ps V <1 ps rms

EXPLANATION OF TEST LEVELS

TEST LEVEL

I 100% production tested.

II 100% production tested at +25°C and guaranteed by design and characterization at specified temperatures.

III Sample Tested Only

IV Parameter is guaranteed by design and characterization testing.

V Parameter is a typical value only.

VI 100% production tested at +25°C and guaranteed by design and characterization for industrial temperature range.

tV and t

not to exceed an ac load of 5 pF or a dc current of ±40 µA. Rise and fall times measured from 20% to 80%.

are measured from the transition points of the CLK input to the 50%/50% levels of the digital outputs swing. The digital output load during test is

Rev. PrJ | Page 5 of 16 6/25/2004

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