Analog Devices AD9287 Service Manual

Quad, 8-Bit, 100 MSPS

A

V

W

FEATURES

4 ADCs integrated into 1 package
133 mW ADC power per channel at 100 MSPS
SNR = 49 dB (to Nyquist)
ENOB = 7.85 bits
SFDR = 65 dBc (to Nyquist)
Excellent linearity

DNL = ±0.2 LSB (typical)
INL = ±0.2 LSB (typical)

Serial LVDS (AN SI-644, default)

Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
295 MHz full-power analog bandwidth
2 V p-p input voltage range

1.8 V supply operation
Serial port control

Full-chip and individual-channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

APPLICATIONS

Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tap e dr ive s
Optical networking
Test equipment

GENERAL DESCRIPTION

The AD9287 is a quad, 8-bit, 100 MSPS analog-to-digital con­verter (ADC) with an on-chip sample-and-hold circuit designed
for low cost, low power, small size, and ease of use. The product
operates at a conversion rate of up to 100 MSPS and is optimized
for outstanding dynamic performance and low power in
applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.

The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

Serial LVDS 1.8 V A/D Converter

AD9287

FUNCTIONAL BLOCK DIAGRAM

DD

VIN + A

VIN – A

VIN + B

VIN – B

VIN + C

VIN – C

VIN + D

VIN – D

VREF

SENSE

REFT

REFB

SELECT

REF

+
–

AGND

capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.

The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user­defined test patterns entered via the serial port interface (SPI).

The AD9287 is available in a RoHS compliant, 48-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Small Footprint. Four ADCs are contained in a small, space-

saving package.

2. Low power of 133 mW/channel at 100 MSPS.

3. Ease of Use. A data clock output (DCO) is provided that

operates at frequencies of up to 400 MHz and supports
double data rate (DDR) operation.

4. User Flexibility. SPI control offers a wide range of flexible

features to meet specific system requirements.

5. Pin-Compatible Family. This includes the AD9219 (10-bit),

AD9228 (12-bit), and AD9259 (14-bit).

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2007 Analog Devices, Inc. All rights reserved.

PD

AD9287

T/H

T/H

T/H

T/H

0.5V

SERIAL PORT

INTERFACE

CSB

SDIO/ODMRBIAS

N

Figure 1.

PIPELINE

ADC

PIPELINE

ADC

PIPELINE

ADC

PIPELINE

ADC

SCLK/DTP

DRVDD

8

SERIAL

8

SERIAL

8

SERIAL

8

SERIAL

DATA RATE

MULTIPLIER

CLK+

DRGND

LVDS

LVDS

LVDS

LVDS

CLK–

D + A
D – A

D + B
D – B

D + C
D – C

D + D
D – D

FCO+

FCO–

DCO+
DCO–

05966-001

AD9287

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Diagrams.............................................................................. 7

Absolute Maximum Ratings............................................................ 9

Thermal Impedance..................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Analog Input Considerations ................................................... 18

Clock Input Considerations...................................................... 20

Serial Port Interface (SPI).............................................................. 28

Hardware Interface..................................................................... 28

Memory Map .................................................................................. 30

Reading the Memory Map Table.............................................. 30

Reserved Locations .................................................................... 30

Default Values............................................................................. 30

Logic Levels................................................................................. 30

Evaluation Board ............................................................................ 34

Power Supplies ............................................................................ 34

Input Signals................................................................................ 34

Output Signals ............................................................................ 34

Default Operation and Jumper Selection Settings................. 35

Alternative Analog Input Drive Configuration...................... 36

Equivalent Circuits......................................................................... 12

Typical Performance Characteristics ........................................... 14

Theory of Operation ...................................................................... 18

REVISION HISTORY

5/07—Rev. 0 to Rev. A

Changes to Logic Output (SDIO/ODM)....................................... 5

Change to Pipeline Latency............................................................. 6

Added Endnote 2 to Table 4 ............................................................ 6

Changes to Figure 2 to Figure 4...................................................... 7

Changes to Figure 10...................................................................... 12

Change to Figure 15 Caption........................................................ 14

Changes to Figure 29...................................................................... 16

Changes to Figure 41...................................................................... 19

Changes to Clock Duty Cycle Considerations Section.............. 20

Changes to Power Dissipation and Power-Down Mode Section ...21

Changes to Figure 50 to Figure 52 Captions............................... 23

Change to Table 8 ........................................................................... 23

Changes to Table 9 Endnote.......................................................... 24

Changes to Digital Outputs and Timing Section ....................... 25

Added Table 10 ............................................................................... 25

Changes to RBIAS Pin Section ..................................................... 26

Outline Dimensions ....................................................................... 50

Ordering Guide .......................................................................... 50

Deleted Figure 53 and Figure 54 .................................................. 26

Changes to Figure 56...................................................................... 27

Changes to Hardware Interface Section ...................................... 28

Added Figure 57 ............................................................................. 29

Changes to Table 15 ....................................................................... 29

Changes to Reading the Memory Map Table Section ............... 30

Changes to Output Signals Section.............................................. 34

Changes to Figure 60...................................................................... 34

Changes to Default Operation and

Jumper Selection Settings Section........................................... 35

Changes to Alternative Analog Input Drive

Configuration Section............................................................... 36

Changes to Figure 63...................................................................... 38

Changes to Table 17 ....................................................................... 46

Changes to Ordering Guide.......................................................... 50

7/06—Revision 0: Initial Version

Rev. A | Page 2 of 52

AD9287

SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 1.

Parameter

1

Temp Min Typ Max Unit

RESOLUTION 8 Bits
ACCURACY

No Missing Codes Full Guaranteed
Offset Error Full ±5 ±23.4 mV
Offset Matching Full ±5 ±23.4 mV
Gain Error Full ±6 % FS
Gain Matching Full ±0.5 ±2 % FS
Differential Nonlinearity (DNL) Full ±0.2 ±0.8 LSB
Integral Nonlinearity (INL) Full ±0.2 ±0.65 LSB

TEMPERATURE DRIFT

Offset Error Full ±2 ppm/°C
Gain Error Full ±17 ppm/°C
Reference Voltage (1 V Mode) Full ±21 ppm/°C

REFERENCE

Output Voltage Error (V
Load Regulation at 1.0 mA (V

= 1 V) Full ±5 ±30 mV

REF

= 1 V) Full 3 mV

REF

Input Resistance Full 6 kΩ

ANALOG INPUTS

Differential Input Voltage (V

= 1 V) Full 2 V p-p

REF

Common-Mode Voltage Full AVDD/2 V
Differential Input Capacitance Full 7 pF
Analog Bandwidth, Full Power Full 295 MHz

POWER SUPPLY

AVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 V
I

AVDD

I

DRVDD

Full 260 274 mA

Full 34.5 38 mA
Total Power Dissipation (Including Output Drivers) Full 530 562 mW
Power-Down Dissipation Full 2 4 mW
Standby Dissipation

2

Full 72 mW

CROSSTALK Full −100 dB
CROSSTALK (Overrange Condition)

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Can be controlled via the SPI.

3

Overrange condition is specific with 6 dB of the full-scale input range.

3

Full −100 dB

Rev. A | Page 3 of 52

AD9287

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 2.

Parameter

1

Temp Min Typ Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 2.4 MHz Full 49.2 dB
fIN = 49.7 MHz Full 46.5 49.0 dB
fIN = 70 MHz Full 49.0 dB

SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)

fIN = 2.4 MHz Full 49.0 dB
fIN = 49.7 MHz Full 46.0 48.5 dB
fIN = 70 MHz Full 48.5 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.4 MHz Full 7.88 Bits
fIN = 49.7 MHz Full 7.43 7.85 Bits
fIN = 70 MHz Full 7.85 Bits

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.4 MHz Full 70.0 dBc
fIN = 49.7 MHz Full 54.0 65.0 dBc
fIN = 70 MHz Full 62.0 dBc

WORST HARMONIC (Second or Third)

fIN = 2.4 MHz Full −70.0 dBc
fIN = 49.7 MHz Full −65.0 −54.0 dBc
fIN = 70 MHz Full −62.0 dBc

WORST OTHER (Excluding Second or Third)

fIN = 2.4 MHz Full −77.0 dBc
fIN = 49.7 MHz Full −74.0 −58.5 dBc
fIN = 70 MHz Full −71.0 dBc

TWO-TONE INTERMODULATION DISTORTION (IMD)—

AIN1 AND AIN2 = −7.0 dBFS
f

= 15 MHz,

IN1

f

= 16 MHz

IN2

f

= 70 MHz,

IN1

= 71 MHz

f

IN2

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

25°C 70.0 dBc

25°C 68.5 dBc

Rev. A | Page 4 of 52

AD9287

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 3.

Parameter

1

Temp Min Typ Max Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage

2

Full 250 mV p-p
Input Common-Mode Voltage Full 1.2 V
Input Resistance (Differential) 25°C 20 kΩ
Input Capacitance 25°C 1.5 pF

LOGIC INPUTS (PDWN, SCLK/DTP)

Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 0.5 pF

LOGIC INPUT (CSB)

Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 70 kΩ
Input Capacitance 25°C 0.5 pF

LOGIC INPUT (SDIO/ODM)

Logic 1 Voltage Full 1.2 DRVDD + 0.3 V
Logic 0 Voltage Full 0 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF

LOGIC OUTPUT (SDIO/ODM)

3

Logic 1 Voltage (IOH = 800 μA) Full 1.79 V
Logic 0 Voltage (IOL = 50 μA) Full 0.05 V

DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)

Logic Compliance LVDS
Differential Output Voltage (VOD) Full 247 454 mV
Output Offset Voltage (VOS) Full 1.125 1.375 V
Output Coding (Default) Offset binary

DIGITAL OUTPUTS (D + x, D − x),

(Low Power, Reduced Signal Option)
Logic Compliance LVDS
Differential Output Voltage (VOD) Full 150 250 mV
Output Offset Voltage (VOS) Full 1.10 1.30 V
Output Coding (Default) Offset binary

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

This is specified for LVDS and LVPECL only.

3

This is specified for 13 SDIO pins sharing the same connection.

Rev. A | Page 5 of 52

AD9287

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 4.

Parameter

CLOCK

1, 2

3

Temp Min Typ Max Unit

Maximum Clock Rate Full 100 MSPS
Minimum Clock Rate Full 10 MSPS
Clock Pulse Width High (tEH) Full 5 ns
Clock Pulse Width Low (tEL) Full 5 ns

OUTPUT PARAMETERS

3

Propagation Delay (tPD) Full 2.0 2.7 3.5 ns
Rise Time (tR) (20% to 80%) Full 300 ps
Fall Time (tF) (20% to 80%) Full 300 ps
FCO Propagation Delay (t
DCO Propagation Delay (t

DCO to Data Delay (t

DATA

DCO to FCO Delay (t
Data to Data Skew

(t

DATA-MAX

− t

DATA-MIN

)

) Full 2.0 2.7 3.5 ns

FCO

4

FRAME

)

CPD

4

)

4

)

Full

Full (t
Full (t

SAMPLE

SAMPLE

/16) − 300 (t
/16) − 300 (t

+

t

FCO

(t

/16)

SAMPLE

/16) (t

SAMPLE

/16) (t

SAMPLE

ns

/16) + 300 ps

SAMPLE

/16) + 300 ps

SAMPLE

Full ±50 ±150 ps

Wake-Up Time (Standby) 25°C 600 ns
Wake-Up Time (Power-Down) 25°C 375 μs
Pipeline Latency Full 8 CLK cycles

APERTURE

Aperture Delay (tA) 25°C 500 ps
Aperture Uncertainty (Jitter) 25°C <1 ps rms
Out-of-Range Recovery Time 25°C 2 CLK cycles

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured on standard FR-4 material.

3

Can be adjusted via the SPI.

4

t

/16 is based on the number of bits multiplied by 2; delays are based on half duty cycles.

SAMPLE

Rev. A | Page 6 of 52

AD9287

TIMING DIAGRAMS

N – 1

AIN

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D – x

D + x

t

A

N – 1

N

D4

N – 9

D3

N – 9

t

EL

t

DATA

D2

N – 9

D1

N – 9

D0

N – 9

MSB
N – 8

D6

N – 8

D5

N – 8D4N – 8

D3

N – 8D2N – 8

D1

N – 8

5966-040

t

EH

t

CPD

MSB
N – 9

t

FRAME

D6

N – 9

D5

N – 9

t

FCO

t

PD

Figure 2. 8-Bit Data Serial Stream, MSB First (Default)

AIN

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D – x

D + x

t

A

N

t

t

t

FCO

PD

CPD

t

EH

t

FRAME

MSB

D10

N – 9

N – 9D9N – 9D8N – 9D7N – 9D6N – 9D5N – 9D4N – 9D3N – 9

Figure 3. 12-Bit Data Serial Stream, MSB First

t

EL

t

DATA

D2

D1

N – 9

0

D0

N – 9

0

N – 9

0

0

MSB
N – 8

D10

N – 8

5966-039

Rev. A | Page 7 of 52

AD9287

N – 1

AIN

t

A

N

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D – x

D + x

t

EH

t

CPD

t

FCO

t

PD

t

FRAME

LSB

N – 9D0N – 9D1N – 9D2N – 9D3N – 9D4N – 9D5N – 9D6N – 9

t

EL

t

DATA

LSB

N – 8D0N – 8D1N – 8D2N – 8D3N – 8D4N – 8

05966-041

Figure 4. 8-Bit Data Serial Stream, LSB First

Rev. A | Page 8 of 52

AD9287

ABSOLUTE MAXIMUM RATINGS

Table 5.

With

Parameter

ELECTRICAL

AVDD AGND −0.3 V to +2.0 V
DRVDD DRGND −0.3 V to +2.0 V
AGND DRGND −0.3 V to +0.3 V
AVDD DRVDD −2.0 V to +2.0 V
Digital Outputs

(D + x, D − x, DCO+,

DCO−, FCO+, FCO−)
CLK+, CLK− AGND −0.3 V to +3.9 V
VIN + x, VIN − x AGND −0.3 V to +2.0 V
SDIO/ODM AGND −0.3 V to +2.0 V
PDWN, SCLK/DTP, CSB AGND −0.3 V to +3.9 V
REFT, REFB, RBIAS AGND −0.3 V to +2.0 V
VREF, SENSE AGND −0.3 V to +2.0 V

ENVIRONMENTAL

Operating Temperature

Range (Ambient)
Maximum Junction

Temperature
Lead Temperature

(Soldering, 10 sec)
Storage Temperature

Range (Ambient)

Respect To

DRGND −0.3 V to +2.0 V

−40°C to +85°C

150°C

300°C

−65°C to +150°C

Rating

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL IMPEDANCE

Table 6.

Air Flow Velocity (m/sec) θ

0.0 24 °C/W

1.0 21 12.6 1.2 °C/W

2.5 19 °C/W

1

θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad

soldered to PCB.

1

θ

JA

θ

JB

Unit

JC

ESD CAUTION

Rev. A | Page 9 of 52

AD9287

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD

AVDD

VIN – D

VIN + D

AVDD

AVDD

CLK–

CLK+

AVDD

AVDD

DRGND

DRVDD

VIN – C

VIN + C

47

48

PIN 1

1

2

3

4

5

6

7

8

9

10

11

12

INDICATOR

14

13

D – D

D + D

REFT

REFB

43

44

AD9287

TOP VIEW

17

18

D – B

D + B

VREF

42

19

D – A

AVDD

AVDD

45

46

EXPOSED PADDLE, PIN 0
(BOTTO M OF PACKAGE)

16

15

D – C

D + C

SENSE

41

20

D + A

VIN + B

VIN – B

AVDD

RBIAS

37

38

39

40

36

AVDD

35

AVDD

34

VIN – A

33

VIN + A

32

AVDD

31

PDWN

30

CSB

29

SDIO/ODM

28

SCLK/DTP

27

AVDD

26

DRGND

25

DRVDD

222123

24

FCO–

FCO+

DCO–

DCO+

Figure 5. 48-Lead LFCSP Pin Configuration, Top View

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

0 AGND Analog Ground (Exposed Paddle)
1, 2, 5, 6, 9, 10, 27, 32,

35, 36, 39, 45, 46
11, 26
12, 25
3
4
7

AVDD 1.8 V Analog Supply

DRGND Digital Output Driver Ground
DRVDD 1.8 V Digital Output Driver Supply
VIN − D ADC D Analog Input Complement
VIN + D ADC D Analog Input True

CLK− Input Clock Complement
8 CLK+ Input Clock True
13
14
15
16
17
18

D − D ADC D Digital Output Complement

D + D ADC D Digital Output True

D − C ADC C Digital Output Complement

D + C ADC C Digital Output True

D − B ADC B Digital Output Complement

D + B ADC B Digital Output True
19 D − A ADC A Digital Output Complement
20 D + A ADC A Digital Output True
21
22
23
24

FCO− Frame Clock Output Complement

FCO+ Frame Clock Output True

DCO− Data Clock Output Complement

DCO+ Data Clock Output True
28 SCLK/DTP Serial Clock/Digital Test Pattern
29
30

SDIO/ODM Serial Data IO/Output Driver Mode

CSB Chip Select Bar
31 PDWN Power-Down
33
34

VIN + A ADC A Analog Input True

VIN − A ADC A Analog Input Complement

Rev. A | Page 10 of 52

05966-003

AD9287

Pin No. Mnemonic Description

37
38
40
41
42
43
44
47
48

VIN − B ADC B Analog Input Complement
VIN + B ADC B Analog Input True
RBIAS External resistor sets the internal ADC core bias current
SENSE Reference Mode Selection
VREF Voltage Reference Input/Output
REFB Differential Reference (Negative)
REFT Differential Reference (Positive)
VIN + C ADC C Analog Input True
VIN − C ADC C Analog Input Complement

Rev. A | Page 11 of 52

AD9287

V



C

S

EQUIVALENT CIRCUITS

DRVDD

IN ± x

Figure 6. Equivalent Analog Input Circuit

LK+

CLK–

10

10k

10k

10

1.25V

V

D– D+

V

05966-030

DRGND

V

V

5966-005

Figure 9. Equivalent Digital Output Circuit

SCLK/DTP

AND

PDWN

1k

30k

Figure 7. Equivalent Clock Input Circuit

DIO/ODM

350

30k

Figure 8. Equivalent SDIO/ODM Input Circuit

05966-032

05966-033

Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit

RBIAS

05966-035

100

05966-031

Figure 11. Equivalent RBIAS Circuit

Rev. A | Page 12 of 52

AD9287

A

V

DD

70k

CSB

Figure 12. Equivalent CSB Input Circuit

1k

VREF

6k

05966-034

5966-037

Figure 14. Equivalent VREF Circuit

SENSE

1k

05966-036

Figure 13. Equivalent SENSE Circuit

Rev. A | Page 13 of 52

AD9287

TYPICAL PERFORMANCE CHARACTERISTICS

–10

–30

AIN = –0.5dBF S

SNR = 49.21dB

ENOB = 7.88 BI TS

SFDR = 70.89dBc

–10

–30

AIN = –0.5dBF S

SNR = 48.36dB

ENOB = 7.74 BITS

SFDR = 65.17dBc

–50

–70

AMPLITUDE (dBFS)

–90

–110

05

5 1015202530354045

FREQUENCY (MHz )

Figure 15. Single-Tone 32k FFT with f

–10

–30

–50

–70

AMPLITUDE (dBFS)

–90

= 2.4 MHz, f

IN

SAMPLE

AIN = –0.5dBF S

SNR = 49.17dB

ENOB = 7.87 BITS

SFDR = 62.44dBc

0

05966-055

= 100 MSPS

–50

–70

AMPLITUDE (dBFS)

–90

–110

050

5 1015202530354045

Figure 18. Single-Tone 32k FFT with f

–10

–30

–50

–70

AMPLITUDE ( dBFS)

–90

FREQUENCY (MHz )

= 170 MHz, f

IN

= 100 MSPS

SAMPLE

AIN = –0.5dBF S

SNR = 48.07dB

ENOB = 7.69 BI TS

SFDR = 61.37dBc

05966-051

–110

05

5 1015202530354045

FREQUENCY (MHz )

Figure 16. Single-Tone 32k FFT with f

–10

–30

–50

–70

AMPLITUDE ( dBFS)

–90

–110

05

5 1015202530354045

FREQUENCY (MHz )

Figure 17. Single-Tone 32k FFT with f

= 70 MHz, f

IN

= 120 MHz, f

IN

SAMPLE

AIN = –0.5dBF S

SNR = 49.16dB

ENOB = 7.87 BITS

SFDR = 70.32dBc

SAMPLE

0

05966-059

= 100 MSPS

0

05966-060

= 100 MSPS

–110

050

5 1015202530354045

Figure 19. Single-Tone 32k FFT with f

–10

–30

–50

–70

AMPLITUDE ( dBFS)

–90

–110

050

5 1015202530354045

Figure 20. Single-Tone 32k FFT with f

FREQUENCY (MHz)

= 190 MHz, f

IN

FREQUENCY (MHz )

= 225 MHz, f

IN

= 100 MSPS

SAMPLE

AIN = –0.5dBF S

SNR = 48.32dB

ENOB = 7.73 BITS

SFDR = 54.48dBc

= 100 MSPS

SAMPLE

05966-052

05966-053

Rev. A | Page 14 of 52

AD9287

80

80

75

70

2V p-p, SFDR

65

60

55

SNR/SFDR (dB)

50

2V p-p, SNR

45

40

10 100

20 30 40 50 60 70 80 90

f

(MSPS)

SAMPLE

Figure 21. SNR/SFDR vs. f

80

70

2V p-p, SFDR

60

, fIN = 10.3 MHz, f

SAMPLE

SAMPLE

= 100 MSPS

70

60

50

40

30

SNR/SFDR (dB)

20

10

0

–60 0

–50 –40 –30 –20 –10

05966-061

ANALOG INP UT LEVEL (dBFS)

Figure 24. SNR/SFDR vs. Analog Input Level, f

–10

–30

–50

2V p-p, SFDR

60dB REFERENCE

2V p-p, SNR

= 35 MHz, f

IN

AIN1 AND AIN2 = –7dBF S

SAMPLE

SFDR = 72.90dBc

IMD2 = 70.43dBc
IMD3 = 71.97dBc

05966-058

= 100 MSPS

50

SNR/SFDR (dB)

2V p-p, SNR

40

30

10 100

20 30 40 50 60 70 80 90

f

(MSPS)

SAMPLE

Figure 22. SNR/SFDR vs. f

80

70

60

50

40

30

SNR/SFDR (dB)

20

10

0

–60 0

–50 –40 –30 –20 –10

ANALOG INP UT LEVEL (dBFS)

, fIN = 35 MHz, f

SAMPLE

2V p-p, SNR

Figure 23. SNR/SFDR vs. Analog Input Level, f

SAMPLE

2V p-p, SFDR

60dB REFERENCE

= 10.3 MHz, f

IN

= 100 MSPS

= 100 MSPS

SAMPLE

–70

AMPLITUDE (dBFS)

–90

–110

05

5 1015202530354045

= 16 MHz, f

f

IN2

= 71 MHz, f

f

IN2

FREQUENCY (MHz )

= 100 MSPS

SAMPLE

FREQUENCY (MHz )

= 100 MSPS

SAMPLE

= 15 MHz and

IN1

= 70 MHz and

IN1

05966-062

Figure 25. Two-Tone 32k FFT with f

AIN1 AND AIN2 = –7dBF S
SFDR = 71.14dBc

–10

IMD2 = 69.46d Bc
IMD3 = 70.33d Bc

–30

–50

–70

AMPLITUDE ( dBFS)

–90

–110

05

5 1015202530354045

05966-057

Figure 26. Two-Tone 32k FFT with f

0

05966-049

0

05966-050

Rev. A | Page 15 of 52

AD9287

–

80

75

70

65

60

55

50

SNR/SFDR (dB)

45

40

35

30

1

2V p-p, SFDR (dBc)

2V p-p, SNR ( dB)

10 100

ANALOG INPUT FREQUENCY (MHz)

Figure 27. SNR/SFDR vs. Analog Input Frequency, f

SAMPLE

1000

= 100 MSPS

05966-063

0.5

0.4

0.3

0.2

0.1

0

DNL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0

50 100 150 200 250

Figure 30. DNL, f

CODE

= 2.4 MHz, f

IN

SAMPLE

= 100 MSPS

05966-066

80

75

70

2V p-p, SFDR

65

60

55

SNR/SFDR (dB)

50

2V p-p, SNR

45

40

–40

–200 20406080

TEMPERATURE (°C)

Figure 28. SINAD/SFDR vs. Temperature, f

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 50 100 150 200 250

CODE

Figure 29. INL, f

= 2.4 MHz, f

IN

= 10.3 MHz, f

IN

= 100 MSPS

SAMPLE

= 100 MSPS

SAMPLE

45.0

–45.5

–46.0

–46.5

CMRR (dB)

–47.0

–47.5

–48.0

10 15 20 25 35 4530 40 50

05966-064

Figure 31. CMRR vs. Analog Input Frequency, f

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

INPUT FULL-SCALE AMPL ITUDE (dB)

–1.8

–2.0

10 100

05966-065

Figure 32. Input Full-Scale Amplitude vs. f

ANALOG INPUT FREQUENCY (MHz)

= 100 MSPS

SAMPLE

20 30 40 50 60 70 80 90

f

(MSPS)

SAMPLE

SAMPLE

05966-075

05966-048

Rev. A | Page 16 of 52