ANALOG DEVICES AD9284 Service Manual
8-Bit, 250 MSPS, 1.8 V Dual
FEATURES
Single 1.8 V supply operation
SNR: 49.3 dBFS at 200 MHz input at 250 MSPS
SFDR: 65 dBc at 200 MHz input at 250 MSPS
Low power: 314 mW at 250 MSPS
On-chip reference and track-and-hold
1.2 V p-p analog input range for each channel
Differential input with 500 MHz bandwidth
LVDS-compliant digital output
DNL: ±0.2 LSB
Serial port control options
Offset binary, Gray code, or twos complement data format
Optional clock duty cycle stabilizer
Built-in selectable digital test pattern generation
Pin-programmable power-down function
Available in 48-lead LFCSP
APPLICATIONS
Communications
Diversity radio systems
I/Q demodulation systems
Battery-powered instruments
Handheld scope meters
Low cost digital oscilloscopes
OTS: video over fiber
Analog-to-Digital Converter (ADC)
AD9284
GENERAL DESCRIPTION
The AD9284 is a dual 8-bit, monolithic sampling, analog-to-digital
converter (ADC) that supports simultaneous operation and is
optimized for low cost, low power, and ease of use. Each ADC
operates at up to a 250 MSPS conversion rate with outstanding
dynamic performance.
The ADC requires a single 1.8 V supply and an encode clock for
full performance operation. No external reference components
are required for many applications. The digital outputs are LVDS
compatible.
The AD9284 is available in a Pb-free, 48-lead LFCSP that is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Integrated Dual 8-Bit, 250 MSPS ADC.
2. Single 1.8 V Supply Operation with LVDS Outputs.
3. Power-Down Option Controlled via a Pin-Programmable
Setting.
FUNCTIONAL BLOCK DIAGRAM
CLK+
CLK–
VIN+A
VIN–A
VCM
VREF
1.0V
V
REF
VIN–B
VIN+B
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
REF
SELECT
RBIAS AGND AVDD DRVDD DRGND
ADC
×1.5
ADC
SDIO/
CSB
PWDNOESCLK
CLOCK
MANAGEMENT
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
SPI
LVDS
OUTPUT BUFFER
DCO
GENERATI ON
LVDS
OUTPUT BUFFER
AD9284
D7+ (MSB), D7– (MSB)
D0+ (LSB), D0– (LSB)
(CHANNEL A)
DCO+
DCO–
D7+ (MSB), D7– (MSB)
D0+ (LSB), D0– (LSB)
(CHANNEL B)
09085-001
AD9284
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications.............................................................. 6
SPI Timing Specifications ........................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Equivalent Circuits......................................................................... 12
Theory of Operation ...................................................................... 13
ADC Architecture ......................................................................13
Analog Input Considerations.................................................... 13
Voltage Reference....................................................................... 13
RBIAS........................................................................................... 13
Clock Input Considerations...................................................... 14
Digital Outputs........................................................................... 14
Built-In Self-Test (BIST) and Output Test .................................. 15
Built-In Self-Test (BIST)............................................................ 15
Output Test Modes..................................................................... 15
Serial Port Interface (SPI).............................................................. 16
Configuration Using the SPI..................................................... 16
Hardware Interface..................................................................... 17
Configuration Without the SPI................................................ 17
SPI Accessible Features.............................................................. 17
Memory Map .................................................................................. 18
Reading the Memory Map Register Table............................... 18
Memory Map Register Table..................................................... 19
Memory Map Register Descriptions........................................ 21
Applications Information.............................................................. 22
Design Guidelines ...................................................................... 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
1/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD9284
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, unless otherwise noted.
Table 1.
Parameter1 Temperature Min Typ Max Unit
RESOLUTION Full 8 Bits
DC ACCURACY
Differential Nonlinearity Full ±0.2 ±0.4 LSB
Integral Nonlinearity Full ±0.1 ±0.3 LSB
No Missing Codes Full Guaranteed
Offset Error Full 0 ±0.4 ±2.1 % FS
Gain Error Full 0 ±2.5 ±2.8 % FS
MATCHING CHARACTERISTICS
Offset Error Full 0 ±0.5 ±2.6 % FS
Gain Error Full 0 ±0.1 ±0.7 % FS
TEMPERATURE DRIFT
Offset Error Full ±2 ppm/°C
Gain Error Full ±20 ppm/°C
ANALOG INPUT
Input Span Full 1.2 V p-p
Input Common-Mode Voltage Full 1.4 V
Input Resistance (Differential) Full 16 kΩ
Input Capacitance (Differential) Full 250 fF
Full Power Bandwidth Full 700 MHz
VOLTAGE REFERENCE
Internal Reference Full 0.97 0.98 0.99 V
Input Resistance Full 3 kΩ
POWER SUPPLIES
Supply Voltage
AVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 V
Supply Current
I
Full 124 128 mA
AVDD
I
Full 51 54 mA
DRVDD
POWER CONSUMPTION
Sine Wave Input2 Full 314 330 mW
Power-Down Power Full 0.3 1.7 mW
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were
completed.
2
Measured with a low frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Rev. 0 | Page 3 of 24
AD9284
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, maximum sample rate, VIN = −1.0 dBFS differential input, unless
otherwise noted.
Table 2.
Parameter Temperature Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 10.3 MHz 25°C 49.3 dBFS
fIN = 70 MHz 25°C 49.3 dBFS
fIN = 96.6 MHz Full 48.7 49.3 dBFS
fIN = 220 MHz 25°C 49.3 dBFS
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
fIN = 10.3 MHz 25°C 49.2 dBFS
fIN = 70 MHz 25°C 49.2 dBFS
fIN = 96.6 MHz Full 48.5 49.2 dBFS
fIN = 220 MHz 25°C 49.2 dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10.3 MHz 25°C 7.9 Bits
fIN = 70 MHz 25°C 7.9 Bits
fIN = 96.6 MHz Full 7.8 7.9 Bits
fIN = 220 MHz 25°C 7.9 Bits
WORST SECOND OR THIRD HARMONIC
fIN = 10.3 MHz 25°C −70 dBc
fIN = 70 MHz 25°C −70 dBc
fIN = 96.6 MHz Full −70 −61 dBc
fIN = 220 MHz 25°C −65 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 10.3 MHz 25°C 70 dBc
fIN = 70 MHz 25°C 70 dBc
fIN = 96.6 MHz Full 61 69 dBc
fIN = 220 MHz 25°C 65 dBc
WORST OTHER HARMONIC OR SPUR
fIN = 10.3 MHz 25°C −71 dBc
fIN = 70 MHz 25°C −71 dBc
fIN = 96.6 MHz Full −70 −64 dBc
fIN = 220 MHz 25°C −67 dBc
CROSSTALK Full −80 dBc
Rev. 0 | Page 4 of 24
AD9284
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature, unless otherwise noted.
Table 3.
Parameter1 Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance LVDS/PECL
Internal Common-Mode Bias Full 1.2 V
Differential Input Voltage2 Full 0.2 6 V p-p
Input Voltage Range Full AVDD − 0.3 AVDD + 1.6 V
High Level Input Voltage Full 1.2 3.6 V
Low Level Input Voltage Full 0 0.8 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full −10 +10 μA
Input Resistance (Differential) 25°C 20 kΩ
Input Capacitance 25°C 4 pF
LOGIC INPUTS
CSB
High Level Input Voltage Full 1.2 DRVDD + 0.3 V
Low Level Input Voltage Full 0 0.8 V
High Level Input Current Full −5 −0.4 +5 μA
Low Level Input Current Full −80 −63 −50 μA
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF
SCLK, SDIO/PWDN, OE
High Level Input Voltage Full 1.2 DRVDD + 0.3 V
Low Level Input Voltage Full 0 0.8 V
High Level Input Current Full 50 57 70 μA
Low Level Input Current Full −5 −0.4 +5 μA
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF
DIGITAL OUTPUTS (D7+, D7− to D0+, D0−), LVDS
DRVDD = 1.8 V
Differential Output Voltage (VOD) Full 290 345 400 mV
Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V
Output Coding (Default) Offset binary
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were
completed.
2
Specified for LVDS and LVPECL only.
Rev. 0 | Page 5 of 24
AD9284
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, −1.0 dBFS dierential input, 1.0 V internal reference, unless otherwise noted.
Table 4.
Parameter Temperature Min Typ Max Unit
CLOCK INPUT PARAMETERS
Input Clock Rate Full 30 250 MHz
CLK Period (t
CLK Pulse Width High (tCH) Full 3.7 ns
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD) 3.7 ns
DCO Propagation Delay (t
DCO to Data Skew (t
Pipeline Delay (Latency) Full 10.5 Cycles
Aperture Delay (tA) Full 1.0 ns
Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms
Wake-Up Time1 Full 500 μs
OUT-OF-RANGE RECOVERY TIME Full 2 Cycles
1
Wake-up time is dependent on the value of the decoupling capacitors.
SPI TIMING SPECIFICATIONS
) Full 7.4 ns
CLK
) Full 3.7 ns
DCO
) Full −280 −60 +100 ps
SKEW
Table 5.
Parameter Description Min Typ Max Unit
SPI TIMING REQUIREMENTS
tDS Setup time between the data and the rising edge of SCLK 2 ns
tDH Hold time between the data and the rising edge of SCLK 2 ns
t
Period of the SCLK 40 ns
CLK
tS Setup time between CSB and SCLK 2 ns
tH Hold time between CSB and SCLK 2 ns
t
SCLK pulse width high 10 ns
HIGH
t
SCLK pulse width low 10 ns
LOW
t
EN_SDIO
Time required for the SDIO pin to switch from an input
10 ns
to an output relative to the SCLK falling edge
t
DIS_SDIO
Time required for the SDIO pin to switch from an output
10 ns
to an input relative to the SCLK rising edge
Timing Diagram
M – 1
VIN±A
N – 1
VIN±B
t
CH
CLK+
CLK–
DCO+, DCO–
CH A, CH B
DATA CH A, CH B
M
t
A
M + 1
N
N + 1
t
CLK
t
DCO
t
SKEW
N – 11 M – 10 N – 10 M – 9 N – 9 M – 8 N – 8 M – 7 N – 7
t
PD
M + 2
N + 2
M + 3
N + 3
Figure 2. Output Data Timing
Rev. 0 | Page 6 of 24
M + 4
N + 4
M + 5
N + 5
09085-002
AD9284
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Electrical
AVDD to AGND −0.3 V to +2.0 V
DRVDD to DRGND −0.3 V to +2.0 V
AGND to DRGND −0.3 V to +0.3 V
AVDD to DRVDD −2.0 V to +2.0 V
D0+/D0− through D7+/D7−
to DRGND
DCO+, DCO− to DRGND −0.3 V to DRVDD + 0.3 V
CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V
VIN±A, VIN±B to AGND −0.3 V to AVDD + 0.2 V
SDIO/PWDN to DRGND −0.3 V to DRVDD + 0.3 V
CSB to AGND −0.3 V to DRVDD + 0.3 V
SCLK to AGND −0.3 V to DRVDD + 0.3 V
Environmental
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature
(Soldering, 10 sec)
Junction Temperature 150°C
−0.3 V to DRVDD + 0.3 V
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
Package Type θJA θ
48-Lead LFCSP (CP-48-12) 30.4 2.9 °C/W
Unit
JC
ESD CAUTION
Rev. 0 | Page 7 of 24
AD9284
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVDD
VIN–B
VIN+B
AVDD
AVDD
VREF
AVDD
VCM
AVDD
VIN+A
VIN–A
4847464544434241403938
AVDD
37
D6+
AVDD36
35
AVDD
34
CLK+
33
CLK–
32
CSB
31
SDIO/PWDN
30
SCLK
29
OE
28
DRGND
27
DRVDD
26
D7+ (MSB)
25
D7– (MSB)
09085-003
AVDD
1
AVDD
2
DNC
3
DNC
4
RBIAS
5
DNC
6
DRGND
7
DRVDD
D0– (LSB)
D0+ (LSB)
NOTES
1. DNC = DO NOT CONNECT. DO NOT CO NNE CT TO T HIS PIN.
2. THE EXPOSED PADDLE MUS T BE SOLDERED TO THE PCB ANALOG
8
9
10
D1–
11
D1+
12
GROUND TO ENS URE P RO P ER F UNCTIONALITY AND HEAT
DISSIPAT I ON, NOIS E , AND ME CHANI CAL STRENGTH BENEFIT S .
PIN 1
INDICATOR
AD9284
TOP VIEW
(Not to Scale)
13141516171819
D2–
D3–
D2+
D3+
DCO–
DCO+
2021222324
D4–
D5–
D4+
D5+
D6–
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Type Description
ADC Power Pins
1, 2, 35, 36, 37, 40, 42,
AVDD Supply Analog Power Supply (1.8 V Nominal).
44, 45, 48
8, 27 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal).
7, 28 DRGND Ground Digital Output Ground.
0 AGND Ground
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the
package. This is the only ground connection, and it must be soldered to
the PCB analog ground to ensure proper functionality and heat dissipation,
noise, and mechanical strength benefits.
ADC Analog Pins
39 VIN+A Input Differential Analog Input Pin (+) for Channel A.
38 VIN−A Input Differential Analog Input Pin (−) for Channel A.
46 VIN+B Input Differential Analog Input Pin (+) for Channel B.
47 VIN−B Input Differential Analog Input Pin (−) for Channel B.
43 VREF Input/output Voltage Reference Input/Output.
5 RBIAS Input/output External Reference Bias Resistor. Connect 10 kΩ from RBIAS to AGND.
41 VCM Output Common-Mode Level Bias Output for Analog Inputs.
34 CLK+ Input ADC Clock Input—True.
33 CLK− Input ADC Clock Input—Complement.
Digital Input
29
OE
Input Digital Enable (Active Low) to Tristate Output Data Pins.
Digital Outputs
26 D7+ (MSB) Output Channel A/Channel B LVDS Output Data 7—True.
25 D7− (MSB) Output Channel A/Channel B LVDS Output Data 7—Complement.
24 D6+ Output Channel A/Channel B LVDS Output Data 6—True.
23 D6− Output Channel A/Channel B LVDS Output Data 6—Complement.
22 D5+ Output Channel A/Channel B LVDS Output Data 5—True.
21 D5− Output Channel A/Channel B LVDS Output Data 5—Complement.
20 D4+ Output Channel A/Channel B LVDS Output Data 4—True.
19 D4− Output Channel A/Channel B LVDS Output Data 4—Complement.
Rev. 0 | Page 8 of 24
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