Analog Devices AD9280ARSRL, AD9280ARS, AD9280-EB Datasheet

Complete 8-Bit, 32 MSPS, 95 mW

a

FEATURES
CMOS 8-Bit 32 MSPS Sampling A/D Converter
Pin-Compatible with AD876-8
Power Dissipation: 95 mW (3 V Supply)
Operation Between +2.7 V and +5.5 V Supply
Differential Nonlinearity: 0.2 LSB
Power-Down (Sleep) Mode
Three-State Outputs
Out-of-Range Indicator
Built-In Clamp Function (DC Restore)
Adjustable On-Chip Voltage Reference
IF Undersampling to 135 MHz

PRODUCT DESCRIPTION

The AD9280 is a monolithic, single supply, 8-bit, 32 MSPS
analog-to-digital converter with an on-chip sample-and-hold
amplifier and voltage reference. The AD9280 uses a multistage
differential pipeline architecture at 32 MSPS data rates and
guarantees no missing codes over the full operating temperature
range.

The input of the AD9280 has been designed to ease the devel­opment of both imaging and communications systems. The user
can select a variety of input ranges and offsets and can drive the
input either single-ended or differentially.

The sample-and-hold amplifier (SHA) is equally suited for both
multiplexed systems that switch full-scale voltage levels in suc­cessive channels and sampling single-channel inputs at frequen­cies up to and beyond the Nyquist rate. AC-coupled input
signals can be shifted to a predetermined level, with an onboard
clamp circuit. The dynamic performance is excellent.

The AD9280 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy and
temperature drift requirements of the application.

CMOS A/D Converter

AD9280

A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range signal (OTR) indicates an over­flow condition which can be used with the most significant bit
to determine low or high overflow.

The AD9280 can operate with a supply range from +2.7 V to
+5.5 V, ideally suiting it for low power operation in high speed
applications.

The AD9280 is specified over the industrial (–40°C to +85°C)

temperature range.

PRODUCT HIGHLIGHTS
Low Power

The AD9280 consumes 95 mW on a 3 V supply (excluding the
reference power). In sleep mode, power is reduced to below
5 mW.

Very Small Package

The AD9280 is available in a 28-lead SSOP package.

Pin Compatible with AD876-8

The AD9280 is pin compatible with the AD876-8, allowing
older designs to migrate to lower supply voltages.

300 MHz Onboard Sample-and-Hold

The versatile SHA input can be configured for either single­ended or differential inputs.

Out-of-Range Indicator

The OTR output bit indicates when the input signal is beyond
the AD9280’s input range.

Built-In Clamp Function

Allows dc restoration of video signals.

FUNCTIONAL BLOCK DIAGRAM

CLAMP

VINA

REFTF
REFTS

REFBS
REFBF

VREF

REFSENSE

CLAMP

IN

SHA

A/D

1V

AVSS

CLK

SHA SHAGAIN SHA GAINGAIN

D/A

A/D

AD9280

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AVDD

D/A

DRVDD

STBY

SHA GAIN

D/A

A/D

CORRECTION LOGIC

OUTPUT BUFFERS

DRVSS

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

A/D D/A

A/D

MODE

THREE-

STATE

OTR
D7 (MSB)
D0 (LSB)

(AVDD = +3 V, DRVDD = +3 V, FS = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input

AD9280–SPECIFICATIONS

Span from 0.5 V to 2.5 V, External Reference, T

Parameter Symbol Min Typ Max Units Condition

RESOLUTION 8 Bits

CONVERSION RATE F

S

32 MHz

DC ACCURACY

Differential Nonlinearity DNL ± 0.2 ±1.0 LSB REFTS = 2.5 V, REFBS = 0.5 V
Integral Nonlinearity INL ±0.3 ±1.5 LSB

Offset Error E
Gain Error E

ZS

FS

±0.2 ±1.8 % FSR
±1.2 ±3.9 % FSR

REFERENCE VOLTAGES

Top Reference Voltage REFTS 1 AVDD V
Bottom Reference Voltage REFBS GND AVDD – 1 V
Differential Reference Voltage 2 V p-p
Reference Input Resistance

1

10 kΩ REFTS, REFBS: MODE = AVDD

4.2 kΩ Between REFTF & REFBF: MODE = AVSS

ANALOG INPUT

Input Voltage Range AIN REFBS REFTS V REFBS Min = GND: REFTS Max = AVDD
Input Capacitance C
Aperture Delay t
Aperture Uncertainty (Jitter) t

IN

AP

AJ

1 pF Switched
4ns
2ps

Input Bandwidth (–3 dB) BW

Full Power (0 dB) 300 MHz

DC Leakage Current 43 µA Input = ±FS

INTERNAL REFERENCE

Output Voltage (1 V Mode) VREF 1 V REFSENSE = VREF

Output Voltage Tolerance (1 V Mode) ±10 ±25 mV

Output Voltage (2 V Mode) VREF 2 V REFSENSE = GND
Load Regulation (1 V Mode) 0.5 2 mV 1 mA Load Current

POWER SUPPLY

Operating Voltage AVDD 2.7 3 5.5 V

DRVDD 2.7 3 5.5 V
Supply Current IAVDD 31.7 36.7 mA AVDD = 3 V, MODE = AVSS
Power Consumption P

D

95 110 mW AVDD = DRVDD = 3 V, MODE = AVSS

Power-Down 4 mW STBY = AVDD, MODE and CLOCK

= AVSS

Gain Error Power Supply Rejection PSRR 1 % FS

DYNAMIC PERFORMANCE (AIN = 0.5 dBFS)

Signal-to-Noise and Distortion SINAD

f = 3.58 MHz 46.4 49 dB
f = 16 MHz 48 dB

Effective Bits

f = 3.58 MHz 7.8 Bits
f = 16 MHz 7.7 Bits

Signal-to-Noise SNR

f = 3.58 MHz 47.8 49 dB
f = 16 MHz 48 dB

Total Harmonic Distortion THD

f = 3.58 MHz –62 –49.5 dB
f = 16 MHz –58 dB

Spurious Free Dynamic Range SFDR

f = 3.58 MHz 66 51.4 dB

f = 16 MHz 61 dB
Differential Phase DP 0.2 Degree NTSC 40 IRE Mod Ramp
Differential Gain DG 0.08 %

MIN

to T

unless otherwise noted)

MAX

–2–

REV. D

Parameter Symbol Min Typ Max Units Condition

DIGITAL INPUTS

High Input Voltage V
Low Input Voltage V

IH

IL

2.4 V

0.3 V

DIGITAL OUTPUTS

High-Z Leakage I
Data Valid Delay t
Data Enable Delay t
Data High-Z Delay t

OZ

OD

DEN

DHZ

–10 +10 µA Output = GND to VDD

25 ns CL = 20 pF
25 ns
13 ns

LOGIC OUTPUT (with DRVDD = 3 V)

High Level Output Voltage (I
High Level Output Voltage (I
Low Level Output Voltage (I
Low Level Output Voltage (I

= 50 µA) V

OH

= 0.5 mA) V

OH

= 1.6 mA) V

OL

= 50 µA) V

OL

OH

OH

OL

OL

+2.95 V
+2.80 V

+0.4 V
+0.05 V

LOGIC OUTPUT (with DRVDD = 5 V)

High Level Output Voltage (I
High Level Output Voltage (I
Low Level Output Voltage (I
Low Level Output Voltage (I

= 50 µA) V

OH

= 0.5 mA) V

OH

= 1.6 mA) V

OL

= 50 µA) V

OL

OH

OH

OL

OL

+4.5 V
+2.4 V

+0.4 V
+0.1 V

CLOCKING

Clock Pulsewidth High t
Clock Pulsewidth Low t

CH

CL

14.7 ns

14.7 ns

Pipeline Latency 3 Cycles

CLAMP

Clamp Error Voltage E

Clamp Pulsewidth t

NOTES

1

See Figures 1a and 1b.

Specifications subject to change without notice.

OC

CPW

±60 ± 80 mV CLAMPIN = +0.5 V to +2.0 V,

= 10 Ω

R

2 µsC

IN

= 1 µF (Period = 63.5 µs)

IN

AD9280

REFTS

REFTF

REFBF

REFBS

MODE

AV

DD

REFTS

REFBS

MODE

10kV

10kV

AD9280

0.4 3 V

DD

a. b.

Figure 1. Equivalent Input Load

AD9280

4.2kV

REV. D

–3–

AD9280

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

With
Respect

Parameter to Min Max Units

AVDD AVSS –0.3 +6.5 V
DRVDD DRVSS –0.3 +6.5 V
AVSS DRVSS –0.3 +0.3 V
AVDD DRVDD –6.5 +6.5 V
MODE AVSS –0.3 AVDD + 0.3 V
CLK AVSS –0.3 AVDD + 0.3 V
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
AIN AVSS –0.3 AVDD + 0.3 V
VREF AVSS –0.3 AVDD + 0.3 V
REFSENSE AVSS –0.3 AVDD + 0.3 V
REFTF, REFTB AVSS –0.3 AVDD + 0.3 V
REFTS, REFBS AVSS –0.3 AVDD + 0.3 V

Junction Temperature +150 °C
Storage Temperature –65 +150 °C

Lead Temperature

10 sec +300 °C

AVDD

DRVDD

AVDD

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*

AD9280ARS –40°C to +85°C 28-Lead SSOP RS-28
AD9280ARSRL –40°C to +85°C 28-Lead SSOP (Reel) RS-28

AD9280-EB Evaluation Board

*RS = Shrink Small Outline.

AVDD

AVDD

AVDD

DRVSS

DRVSS

AVSS

a. D0–D7, OTR

AVDD

AVSS

d. AIN

AVDD

AVSS

b. Three-State, Standby, Clamp

AVDD

25

REFBS

AVDD

24

REFBF

AVDD

AVSS

AVSSAVSS

AVSS

AVSS

e. Reference

AVDD

AVSS

f. CLAMPIN g. MODE h. REFSENSE i. VREF

Figure 2. Equivalent Circuits

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9280 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REFTF

REFTS

AVSS

AVDD

22

AVDD

21

AVSS

c. CLK

AVSS

AVSS

AVDD

AVSS

REV. D

PIN CONFIGURATION

28-Lead Wide Body (SSOP)

AD9280

1

AVSS

2

DRVDD

3

NC

4

NC

5

D0

AD9280

6

D1

TOP VIEW

(Not to Scale)

7

D2

8

D3

9

D4

10

D5 CLAMP

11

D6

12

D7

13

OTR

14

DRVSS

NC = NO CONNECT

28

AVDD

27

AIN

26

VREF

25

REFBS

24

REFBF

23

MODE
REFTF

22
21

REFTS

20

CLAMPIN

19
18

REFSENSE
STBY

17
16

THREE-STATE

15

CLK

PIN FUNCTION DESCRIPTIONS

SSOP
Pin No. Name Description

1 AVSS Analog Ground
2 DRVDD Digital Driver Supply
3 NC No Connect
4 NC No Connect
5 D0 Bit 0
6 D1 Bit 1
7 D2 Bit 2
8 D3 Bit 3

9 D4 Bit 4
10 D5 Bit 5
11 D6 Bit 6
12 D7 Bit 7, Most Significant Bit
13 OTR Out-of-Range Indicator
14 DRVSS Digital Ground
15 CLK Clock Input
16 THREE-STATE HI: High Impedance State. LO: Normal Operation
17 STBY HI: Power-Down Mode. LO: Normal Operation
18 REFSENSE Reference Select
19 CLAMP HI: Enable Clamp Mode. LO: No Clamp
20 CLAMPIN Clamp Reference Input
21 REFTS Top Reference
22 REFTF Top Reference Decoupling
23 MODE Mode Select
24 REFBF Bottom Reference Decoupling
25 REFBS Bottom Reference
26 VREF Internal Reference Output
27 AIN Analog Input
28 AVDD Analog Supply

REV. D

–5–

AD9280

DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity (INL)

Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale.” The
point used as “zero” occurs 1/2 LSB before the first code transi­tion. “Full scale” is defined as a level 1 1/2 LSB beyond the last
code transition. The deviation is measured from the center of
each particular code to the true straight line.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) are guaranteed.

(AVDD = +3 V, DRVDD = +3 V, FS = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input

Typical Characterization Curves

1.0

0.5

0

DNL

–0.5

–1.0

0 24032

64 96 128 160 192 224

CODE OFFSET

Figure 3. Typical DNL

Span from 0.5 V to 2.5 V, External Reference, unless otherwise noted)

Offset Error

The first transition should occur at a level 1 LSB above “zero.”
Offset is defined as the deviation of the actual first code transi­tion from that point.

Gain Error

The first code transition should occur for an analog value 1 LSB
above nominal negative full scale. The last transition should
occur for an analog value 1 LSB below the nominal positive full
scale. Gain error is the deviation of the actual difference be­tween first and last code transitions and the ideal difference
between the first and last code transitions.

Pipeline Delay (Latency)

The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every rising edge.

60

55

50

45

40

SNR– dB

35

30

25

20

1.00E+05 1.00E+081.00E+06 1.00E+07

–0.5 AMPLITUDE

–6.0 AMPLITUDE

–20.0 AMPLITUDE

INPUT FREQUENCY – Hz

Figure 5. SNR vs. Input Frequency

1.0

0.5

0

INL

–0.5

–1.0

0 24032 64 96 128 160 192 224

CODE OFFSET

Figure 4. Typical INL

–6–

60

55

50

45

40

35

SINAD – dB

30

25

20

1.00E+05 1.00E+081.00E+06

–0.5 AMPLITUDE

–6.0 AMPLITUDE

–20.0 AMPLITUDE

INPUT FREQUENCY – Hz

1.00E+07

Figure 6. SINAD vs. Input Frequency

REV. D

AD9280

SINGLE-TONE FREQUENCY DOMAIN

30

0E+0 4E+6 8E+6

20
10

0
–10
–20
–30

–40
–50
–60
–70
–80
–90

–100
–110
–120

12E+6 16E+6

FIN = 1MHz
F

S

= 32MHz

FUND

2nd

3rd

5th

6th

4th

7th

8th

9th

–30

–35

–40

–45

–50

THD – dB

–55

–60

–65

–70

1.00E+05 1.00E+081.00E+06 1.00E+07

–20.0 AMPLITUDE

–6.0 AMPLITUDE

–0.5 AMPLITUDE

INPUT FREQUENCY – Hz

Figure 7. THD vs. Input Frequency

–80

–70

–60

–50

–40

THD – dB

–30

–20

–10

0

1.00E+06 1.00E+081.00E+07

AIN = –0.5dBFS

CLOCK FREQUENCY – Hz

105

100

95

90

85

POWER CONSUMPTION – mW

80

75

0405

10

15 20 25 30 35

CLOCK FREQUENCY – MHz

Figure 10. Power Consumption vs. Clock Frequency
(MODE = AVSS)

900k
800k
700k
600k
500k

HITS

400k
300k
200k

100k

1M

0

0

N–1 N

CODE

1M

0

N+1

1.01

1.009

1.008

– V

REF

V

1.007

1.006

1.005

Figure 9. Voltage Reference Error vs. Temperature

REV. D

Figure 8. THD vs. Clock Frequency

–10

–50 90–30

10 30 50 70

TEMPERATURE – °C

Figure 11. Grounded Input Histogram

CLOCK = 32MHz

Figure 12. Single-Tone Frequency Domain

–7–

AD9280

0

–3

–6

–9

–12

–15

–18

SIGNAL AMPLITUDE – dB

–21

–24

1.0E+6 1.0E+91.0E+7
FREQUENCY – Hz

1.0E+8

Figure 13. Full Power Bandwidth

50
40
30
20
10

0

– mA

B

I

–10
–20
–30
–40
–50

0 3.01.0 2.0

INPUT VOLTAGE – V

REFBS = 0.5V
REFTS = 2.5V
CLOCK = 32MHz

2.50.5 1.5

Figure 14. Input Bias Current vs. Input Voltage

APPLYING THE AD9280

THEORY OF OPERATION

The AD9280 implements a pipelined multistage architecture to
achieve high sample rate with low power. The AD9280 distrib­utes the conversion over several smaller A/D subblocks, refining
the conversion with progressively higher accuracy as it passes
the results from stage to stage. As a consequence of the distrib­uted conversion, the AD9280 requires a small fraction of the
256 comparators used in a traditional flash type A/D. A sample­and-hold function within each of the stages permits the first
stage to operate on a new input sample while the second, third
and fourth stages operate on the three preceding samples.

OPERATIONAL MODES

The AD9280 is designed to allow optimal performance in a
wide variety of imaging, communications and instrumentation
applications, including pin compatibility with the AD876-8 A/D.
To realize this flexibility, internal switches on the AD9280 are
used to reconfigure the circuit into different modes. These modes
are selected by appropriate pin strapping. There are three parts
of the circuit affected by this modality: the voltage reference, the
reference buffer, and the analog input. The nature of the appli­cation will determine which mode is appropriate: the descrip­tions in the following sections, as well as Table I should assist in
selecting the desired mode.

Table I. Mode Selection

Input Input MODE REFSENSE

Modes Connect Span Pin Pin REF REFTS REFBS Figure

TOP/BOTTOM AIN 1 V AVDD Short REFSENSE, REFTS and VREF Together AGND 18

AIN 2 V AVDD AGND Short REFTS and VREF Together AGND 19

CENTER SPAN AIN 1 V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 20

AIN 2 V AVDD/2 AGND No Connect AVDD/2 AVDD/2

Differential AIN Is Input 1 1 V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 29

REFTS and
REFBS Are
Shorted Together
for Input 2 2 V AVDD/2 AGND No Connect AVDD/2 AVDD/2

External Ref AIN 2 V max AVDD AVDD No Connect Span = REFTS 21, 22

– REFBS (2 V max)

AGND Short to Short to 23

VREFTF VREFBF

AD876-8 AIN 2 V Float or AVDD No Connect Short to Short to 30

AVSS VREFTF VREFBF

–8–

REV. D