Analog Devices AD9271 Service Manual
Octal LNA/VGA/AAF/ADC
Preliminary Technical Data
FEATURES
8 channels of LNA, VGA, AAF, and ADC
Low noise preamplifier (LNA)
Input-referred noise = 1.2 nV/√Hz @ 7.5 MHz typical
SPI-programmable gain = 14 dB/15.6 dB/18 dB
Single-ended input; V
333 mV p-p/250 mV p-p
Dual mode, active input impedance match
Bandwidth (BW) > 70 MHz
Full-scale (FS) output = 2 V p-p diff
Variable gain amplifier (VGA)
Gain range = −6 dB to +24 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
rd
-order Butterworth cutoff
3
Programmable from 8 MHz to 18 MHz
Analog-to-digital converter (ADC)
12 bits at 10 MSPS to 50 MSPS
SNR = 70 dB
SFDR = 80 dB
Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)
Data and frame clock outputs
Includes crosspoint switch to support
continuous wave (CW) Doppler
Low power, 150 mW/channel at 12 bits/40 MSPS (TGC)
60 mW/channel in CW Doppler
Single 1.8 V supply (3.3 V supply for CW Doppler output bias)
Flexible power-down modes
Overload recovery in <10 ns
Fast recovery from low power standby mode, <2 μs
100-pin TQFP
APPLICATIONS
Medical imaging/ultrasound
Automotive radar
GENERAL DESCRIPTION
The AD9271 is designed for low cost, low power, small size, and
ease of use. It contains eight channels of a variable gain amplifier
(VGA) with low noise preamplifier (LNA); an antialiasing filter
(AAF); and a 12-bit, 10 MSPS to 50 MSPS analog-to-digital
converter (ADC).
maximum = 400 mV p-p/
IN
and Crosspoint Switch
AD9271
The LNA has a single-ended-to-differential gain that is selectable
through the SPI. The LNA input noise is typically 1.2 nV/√Hz,
FUNCTIONAL BLOCK DIAGRAM
LOSW-A
LO-A
LI-A
LG-A
LOSW-B
LO-B
LI-B
LG-B
LOSW-C
LO-C
LI-C
LG-C
LOSW-D
LO-D
LI-D
LG-D
LOSW-E
LO-E
LI-E
LG-E
LOSW-F
LO-F
LI-F
LG-F
LOSW-G
LO-G
LI-G
LG-G
LO-H
LOSW-H
LI-H
LG-H
LNA
LNA
LNA
LNA
LNA
LNA
LNA
LNA
SWITCH
ARRAY
CWVDD
AVDD
VGA
VGA
VGA
VGA
VGA
VGA
VGA
VGA
g
m
6
GAIN–
GAIN+
CWD+/–[5:0]
Figure 1.Block Diagram
STDBY
PWDN
AAF
AAF
AAF
AAF
AAF
AAF
AAF
AAF
REFERENCE
VREF
REFB
SENSE
AD9271
12-BIT
PIPELINE
ADC
12-BIT
PIPELINE
ADC
12-BIT
PIPELINE
ADC
12-BIT
PIPELINE
ADC
12-BIT
PIPELINE
ADC
12-BIT
PIPELINE
ADC
12-BIT
PIPELINE
ADC
12-BIT
PIPELINE
ADC
REFT
RBIAS
DRVDD
CLK +
DOUT + A
DOUT – A
DOUT + B
DOUT – B
DOUT + C
DOUT – C
DOUT + D
DOUT – D
DOUT + E
DOUT – E
DOUT + F
DOUT – F
DOUT + G
DOUT – G
DOUT + H
DOUT – H
FCO+
FCO–
RATE
DCO+
MULTIPLIER
DCO–
CLK –
06304-001
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
DATA
PORT
SERIAL
INTERFACE
CSB
SDIO
SCLK
Each channel features a variable gain range of 30 dB, a fully
differential signal path, an active input preamplifier termination, a
maximum gain of up to 40 dB, and an ADC with a conversion
rate of up to 50 MSPS. The channel is optimized for dynamic
performance and low power in applications where a small
package size is critical.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
and the combined input-referred noise of the entire channel
is 1.4 nV/√Hz at maximum gain. Assuming a 15 MHz noise
bandwidth (NBW) and a 15.6 dB LNA gain, the input SNR is
roughly 86 dB. In CW Doppler mode, the LNA output drives a
transconductance amp that is switched through an 8 × 6,
differential crosspoint switch. The switch is programmable
through the SPI.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
AD9271 Preliminary Technical Data
TABLE OF CONTENTS
Features.............................................................................................. 1
Input Overdrive.......................................................................... 23
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram ..............................................................1
Revision History ...............................................................................2
Product Highlights........................................................................... 3
Specifications..................................................................................... 4
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 8
Switching Specifications.............................................................. 9
ADC Timing Diagrams .................................................................10
Absolute Maximum Ratings.......................................................... 11
Thermal Impedance................................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Equivalent Circuits......................................................................... 15
CW Doppler Operation............................................................. 23
TGC Operation........................................................................... 25
A/D Converter............................................................................ 28
Clock Input Considerations...................................................... 28
Serial Port Interface (SPI).............................................................. 35
Hardware Interface..................................................................... 35
Memory Map .................................................................................. 37
Reading the Memory Map Table.............................................. 37
Reserved Locations .................................................................... 37
Default Values............................................................................. 37
Logic Levels................................................................................. 37
Evaluation Board............................................................................ 42
Power Supplies............................................................................ 42
Input Signals................................................................................ 42
Output Signals ............................................................................42
Typical Performance Characteristics........................................... 17
Theory of Operation ......................................................................20
Ultrasound................................................................................... 20
Channel Overview...................................................................... 21
REVISION HISTORY
x/07—Revision 0: Initial Version
Default Operation and Jumper Selection Settings................. 43
Outline Dimensions....................................................................... 56
Ordering Guide .......................................................................... 56
Rev. PrA | Page 2 of 58
Preliminary Technical Data AD9271
The AD9271 requires a LVPECL-/CMOS-/LVDS-compatible
sample rate clock for full performance operation. No external
reference or driver components are required for many
applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock (DCO) for
capturing data on the output and a frame clock (FCO) trigger
for signaling a new output byte are provided.
Powering down individual channel is supported to increase battery
life for portable applications. There is also a standby mode option
that allows quick power-up for power cycling. In CW Doppler
operation, the VGA, AAF, and ADC are powered down. The
power of the TGC path scales with selectable speed grades.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as a programmable clock, data
alignment, and programmable digital test pattern generation. The
digital test patterns include built-in fixed patterns, built-in
pseudorandom pattern, and custom user-defined test patterns
entered via the serial port interface.
Fabricated in an advanced CMOS process, the AD9271 is
available in a 14 mm × 14 mm, Pb-free, 100-lead TQFP. It is
specified over the industrial temperature range of –40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight channels are contained in a small,
space-saving package. Full TGC path, ADC, and crosspoint
switch contained within a 100-lead, 16 mm × 16 mm, TQFP.
2. Low power of 150 mW/channel at 40 MSPS.
3. Integrated Crosspoint Switch. This switch allows numerous
multichannel configuration options to enable the CW
Doppler mode.
4. Ease of Use. A data clock output (DCO) operates up to
300 MHz and supports double data rate operation (DDR).
5. User Flexibility. Serial port interface (SPI) control offers a wide
range of flexible features to meet specific system requirements.
6. Integrated Third-Order Antialiasing Filter. This filter is
placed between TGC path and ADC and is programmable
from 8 MHz to 18 MHz.
Rev. PrA | Page 3 of 58
AD9271 Preliminary Technical Data
SPECIFICATIONS
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 1.0 V internal ADC reference, AIN = 5 MHz, RS = 50 Ω, LNA gain = 15.6 dB (6),
unless otherwise noted.
Table 1.
AD9271-25 AD9271-40 AD9271-50
Parameter1 Conditions Min Typ Max Min Typ Max Min Typ Max Unit
LNA
CHARACTERISTICS
Gain = 5/6/8 Single-ended
Single-ended
Input Voltage
Range, Gain =
5/6/8
Input Common
Mode
Input Resistance RFB = 200 Ω, 50 50 50 Ω
RFB = 400 Ω, 100 100 100 Ω
RFB = ∞ 15 15 15 kΩ
Input Capacitance LI-x 15 15 15 pF
−3 dB Bandwidth 40 60 70 MHz
Input Noise
Voltage,
Gain = 5/6/8
1 dB Input
Compression
Point
Gain = 5/6/8
Active
Termination
Match
Unterminated RFB = ∞ 4.9 4.4 4.2 dB
FULL-CHANNEL (TGC)
CHARACTERISTICS
AAF High-Pass
Cutoff
AAF Low-Pass
Cutoff
Group Delay
Variation
Bandwidth
Tolerance
Input-Referred
Noise Voltage,
LNA Gain =
5/6/8
Correlated Noise No signal −30 −30 −30 dB
Output Offset AAF high-pass
Signal-to-Noise
Ratio (SNR)
FIN = 5 MHz at −7
dBFS
input to
differential
output
input to
single-ended
output
LNA output
limited to
2 V p-p
differential
output
1.4 1.4 1.4 V
R
= 0 Ω, RFB = ∞ 1.4/1.4/1.3 1.3/1.2/1.1 1.3/1.2/1.1 nV/√Hz
S
V
= 0 V 782.6/649.1/508.8 782.6/649.1/508.8 782.6/649.1/508.8 mV p-p
GAIN
Ω, RFB = 200 Ω 6.7 6.7 6.7 dB
−3 dB DC/350/700 DC/350/700 DC/350/700 kHz
−3 dB,
programmable
f = 1 MHz to
10 MHz, gain =
0 V to 1 V
±15 ±15 ±15 %
RFB = ∞ 1.7/1.6/1.5 1.6/1.4/1.3 1.6/1.4/1.2 nV/√Hz
= 700 kHz
GAIN pin = 0 V 65 65 65 dBFS
14/15.6/18 14/15.6/18 14/15.6/18 dB
8/9.6/12 8/9.6/12 8/9.6/12 dB
400/333/250 400/333/250 400/333/250 mV p-p
1/3 × f
(8 to 18)
±1 ±1 ±1 ns
TBD TBD TBD LSB
SAMPLE
1/3 × f
(8 to 18)
SAMPLE
1/3 × f
(8 to 18)
SAMPLE
MHz
2
SE
Rev. PrA | Page 4 of 58
Preliminary Technical Data AD9271
AD9271-25 AD9271-40 AD9271-50
Parameter1 Conditions Min Typ Max Min Typ Max Min Typ Max Unit
FIN = 5 MHz at −1
dBFS
Harmonic
Distortion
Second Harmonic,
= 5 MHz at
F
IN
−7 dBFS
Second Harmonic,
= 5 MHz at
F
IN
−1 dBFS
Third Harmonic,
F
= 5 MHz at
IN
−7 dBFS
Third Harmonic,
F
= 5 MHz at
IN
−1 dBFS
Two-Tone IMD3
(2 × F1 − F2)
Distortion
F
= 5.0 MHz at
IN1
−1 dBFS
= 5.1 MHz at
F
IN2
−26 dBFS
Channel-to-
Channel
Crosstalk
Channel-to-
Channel
Crosstalk
(Overrange
Condition)
Overload Recovery LNA or VGA 10 10 10 ns
GAIN ACCURACY
Absolute Gain
Error
0.1 V < V
0.9 V < V
Channel-to-
Channel
Matching
GAIN CONTROL
INTERFACE
Normal Operating
Range
Gain Range 0 V to 1 V 10.6 40.6 10.6 40.6 10.6 40.6 dB
Scale Factor 32 32 32 dB/V
Response Time 30 dB change 350 350 350 ns
CW DOPPLER MODE
Transconductance,
LNA Gain =
5/6/8
Common Mode CW Doppler
Input-Referred
Noise Voltage,
LNA Gain =
5/6/8
Output DC Bias Per channel 2.4 2.4 2.4 mA
Maximum Output
Swing
POWER SUPPLY
AVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
GAIN pin = 1 V 65 65 65 dBFS
GAIN pin = 0 V −65 −65 −65 dBFS
GAIN pin = 1 V −65 −65 −65 dBFS
GAIN pin = 0 V −70 −70 −70 dBFS
GAIN pin = 1 V −70 −70 −70 dBFS
GAIN pin = 1 V −65 −65 −65 dB
−70 −70 −70 dB
−70 −70 −70 dB
3
0 < V
< 0.1 V −1.0 +0.5 +2.0 −1.0 +0.5 +2.0 −1.0 +0.5 +2.0 dB
GAIN
<
GAIN
−1.0 +0.3 +1.0 −1.0 +0.3 +1.0 −1.0 +0.3 +1.0 dB
0.9 V, 1σ
<
GAIN
−2.0 -0.5 +1.0 −2.0 -0.5 +1.0 −2.0 -0.5 +1.0 dB
1 V
0.1 V < V
GAIN
<
1 1 1 dB
0.9 V
0 1 0 1 0 1 V
10/12/16 10/12/16 10/12/16 mA/V
1.5 3.6 1.5 3.6 1.5 3.6 V
output pins
R
= 0 Ω, RFB = ∞ 1.8 /1.7/1.5 1.7 /1.5/1.4 1.7 /1.5/1.3 nV/√Hz
S
Per channel ±2 ±2 ±2 mA p-
Rev. PrA | Page 5 of 58
p
AD9271 Preliminary Technical Data
AD9271-25 AD9271-40 AD9271-50
Parameter1 Conditions Min Typ Max Min Typ Max Min Typ Max Unit
DRVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
CWVDD 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6
I
Full-channel
AVDD
CW Doppler
I
49 49 49 mA
DRVDD
Total Power
Dissipation
(Including
Output Drivers)
CW Doppler
Power-Down
Dissipation
Standby Power
Dissipation
Power Supply
Rejection Ratio
(PSRR)
ADC RESOLUTION 12 12 12 Bits
mode
mode with
four channels
enabled
Full-channel
mode
mode with
four channels
enabled
10 mW
65 65 65 mW
1 1 1 mV/V
500 622 746 mA
136 160 170 mA
984 1200 1400 mW
192 216 224 mW
Rev. PrA | Page 6 of 58
Preliminary Technical Data AD9271
AD9271-25 AD9271-40 AD9271-50
Parameter1 Conditions Min Typ Max Min Typ Max Min Typ Max Unit
ADC REFERENCE
Output Voltage
Error (VREF = 1
V)
Load Regulation @
1.0 mA (VREF =
1 V)
Input Resistance 6 6 6 kΩ
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
SE = single ended.
3
The overrange condition is specified as being 6 dB more than the full-scale input range.
±2 ±2 ±2 mV
3 3 3 mV
Rev. PrA | Page 7 of 58
AD9271 Preliminary Technical Data
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 m V p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless
otherwise noted.
Table 2.
Parameter1 Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage2 Full 250 mV p-p
Input Common-Mode Voltage Full 1.2 V
Input Resistance (Differential) 25°C 20 kΩ
Input Capacitance 25°C 1.5 pF
LOGIC INPUTS (PDWN, STBY, SCLK)
Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC INPUT (CSB)
Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 70 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC INPUT (SDIO)
Logic 1 Voltage Full 1.2 DRVDD + 0.3 V
Logic 0 Voltage Full 0 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 A) Full 1.79 V
Logic 0 Voltage (IOL = 50 A) Full 0.05 V
DIGITAL OUTPUTS (D+, D−), (ANSI-644)1
Logic Compliance LVDS
Differential Output Voltage (VOD) Full 247 454 mV
Output Offset Voltage (VOS) Full 1.125 1.375 V
Output Coding (Default) Offset binary
DIGITAL OUTPUTS (D+, D−),
(Low Power, Reduced Signal Option)
1
Logic Compliance LVDS
Differential Output Voltage (VOD) Full 150 250 mV
Output Offset Voltage (VOS) Full 1.10 1.30 V
Output Coding (Default) Offset binary
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
Specified for LVDS and LVPECL only.
3
Specified for 13 SDIO pins sharing the same connection.
Rev. PrA | Page 8 of 58
Preliminary Technical Data AD9271
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 m V p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless
otherwise noted.
Table 3.
Parameter1 Temp Min Typ Max Unit
CLOCK2
Maximum Clock Rate Full 50 MSPS
Minimum Clock Rate Full 10 MSPS
Clock Pulse Width High (tEH) Full 10.0 ns
Clock Pulse Width Low (tEL) Full 10.0 ns
OUTPUT PARAMETERS
Propagation Delay (tPD) Full
Rise Time (tR) (20% to 80%) Full
Fall Time (tF) (20% to 80%) Full
FCO Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Delay (t
DCO to FCO Delay (t
Data-to-Data Skew
DATA-MAX
− t
(t
Wake-Up Time (Standby) 25°C
Wake-Up Time (Power-Down) 25°C
Pipeline Latency Full
APERTURE
Aperture Uncertainty (Jitter) 25°C
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
Can be adjusted via the SPI interface.
3
Measurements were made using a part soldered to FR4 material.
4
t
/24 is based on the number of bits divided by 2, because the delays are based on half duty cycles.
SAMPLE
2, 3
DATA-MIN
) Full
FCO
)4 Full
CPD
)4 Full (t
DATA
)4 Full (t
FRAME
Full
)
1.5 2.3 3.1
300
300
1.5 2.3 3.1
+
t
FCO
/24)
(t
SAMPLE
/24) − 300 (t
SAMPLE
/24) − 300 (t
SAMPLE
±50 ±200
600
375
8
/24) (t
SAMPLE
/24) (t
SAMPLE
ns
/24) + 300 ps
SAMPLE
/24) + 300 ps
SAMPLE
ns
ps
ps
ns
ps
ns
s
CLK
cycles
<1
ps rms
Rev. PrA | Page 9 of 58
AD9271 Preliminary Technical Data
ADC TIMING DIAGRAMS
N – 1
AIN
CLK–
CLK+
DCO–
DCO+
FCO–
FCO+
DOUT–
DOUT+
N – 1
t
A
N
t
FCO
t
t
EH
t
CPD
t
FRAME
PD
MSB
D10
N – 8
N – 8D9N – 8D8N – 8D7N – 8D6N – 8D5N – 8D4N – 8D3N – 8D2N – 8D1N – 8D0N – 8
t
EL
t
DATA
D10
MSB
N – 7
N – 7
6304-002
Figure 2. 12-(Preliminary) Bit Data Serial Stream (Default)
AIN
CLK–
CLK+
DCO–
DCO+
FCO–
FCO+
DOUT–
DOUT+
t
A
N
t
EH
t
CPD
t
FCO
t
PD
t
FRAME
LSB
(N – 8)D0(N – 8)D1(N – 8)D2(N – 8)D3(N – 8)D4(N – 8)D5(N – 8)D6(N – 8)D7(N – 8)D8(N – 8)D9(N – 8)
t
EL
t
DATA
D10
(N – 8)
LSB
(N – 7)
D0
(N – 7)
06304-004
Figure 3. 12-(Preliminary) Bit Data Serial Stream, LSB First
Rev. PrA | Page 10 of 58
Preliminary Technical Data AD9271
ABSOLUTE MAXIMUM RATINGS
Table 4.
With
Parameter
Respect To Rating
ELECTRICAL
AVDD GND −0.3 V to +2.0 V
DRVDD GND −0.3 V to +2.0 V
CWVDD GND −0.3 V to +3.9 V
GND GND −0.3 V to +0.3 V
AVDD DRVDD −2.0 V to +2.0 V
Digital Outputs
GND −0.3 V to +2.0 V
(DOUT+, DOUT−, DCO+,
DCO−, FCO+, FCO−)
CLK+, CLK− GND −0.3 V to +3.9 V
LI-x LG-x −0.3 V to +2.0 V
LO-x LG-x −0.3 V to +2.0 V
LOSW-x LG-x −0.3 V to +2.0 V
CWDx−, CWDx+ GND −0.3 V to +2.0 V
SDIO, GAIN+,GAIN− GND −0.3 V to +2.0 V
PDWN, STBY, SCLK, CSB GND −0.3 V to +3.9 V
REFT, REFB, RBIAS GND −0.3 V to +2.0 V
VREF, SENSE GND −0.3 V to +2.0 V
ENVIRONMENTAL
Operating Temperature
−40°C to +85°C
Range (Ambient)
Maximum Junction
150°C
Temperature
Lead Temperature
300°C
(Soldering, 10 sec)
Storage Temperature
−65°C to +150°C
Range (Ambient)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL IMPEDANCE
Table 5.
Air Flow Velocity (m/s) θ
0.0 20.3°C/W
1.0 14.4°C/W 7.6°C/W 4.7°C/W
2.5 12.9°C/W
1
θ
for a 4-layer PCB with solid ground plane (simulated). Exposed pad
JA
soldered to PCB.
1
θ
JA
JB
θJC
ESD CAUTION
Rev. PrA | Page 11 of 58
AD9271 Preliminary Technical Data
G
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LOSW-D
LO–D
CWD0–
CWD0+
CWD1–
CWD1+
CWD2–
CWD2+
CWVD-D
GAIN–
GAIN+
RBIAS
SENSE
VREF
REFB
REFT
AVDD
CWD3–
CWD3+
CWD4–
CWD4+
CWD5–
CWD5+
LO–E
LOSW-E
LI-E
LG-E
AVDD
AVDD
LO-F
LOSW-F
LI-F
LG-F
AVDD
AVDD
LO-G
LOSW-
LI-G
LG-G
AVDD
AVDD
LO-H
LOSW-H
LI-H
LG-H
AVDD
AVDD
CLK–
CLK+
AVDD
9998979695949392919089888786858483828180797877
100
PIN 1
1
INDICATOR
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD9271
TOP VIEW
(Not to Scale)
76
LI-D
75
LG-D
74
AVDD
73
AVDD
72
LO-C
71
LOSW-C
70
LI-C
69
LG-C
68
AVDD
67
AVDD
66
LO-B
65
64
LOSW-B
LI-B
63
LG-B
62
AVDD
61
AVDD
60
59
LO-A
58
LOSW-A
57
LI-A
LG-A
56
AVDD
55
54
AVDD
53
CSB
52
SDIO
SCLK
51
2627282930313233343536373839404142434445464748
FCO–
DRVDD
DCO–
DOUT + F
DOUT – H
DOUT + H
DOUT – G
DOUT + G
DOUT – F
DOUT – E
DOUT + E
FCO+
DCO+
DOUT – B
DOUT – C
DOUT – D
DOUT + D
DOUT + B
DOUT + C
DRVDD
DOUT – A
DOUT + A
50
49
STBY
AVDD
PWDN
Figure 4. 100-Lead TQFP
Table 6. Pin Function Descriptions
Pin No. Name Description
0 GND Ground (Exposed paddle should be tied to a quiet analog ground)
3, 4, 9, 10, 15,
AVDD 1.8 V Analog Supply
16, 21, 22, 25,
50, 54, 55, 60,
61, 66, 67, 72,
73,92
26, 47 DRVDD 1.8 V Digital Output Driver Supply
84 CWVDD 3.3 V Analog Supply
1 LI-E LNA Analog Input for Channel E
2 LG-E LNA Ground for Channel E
5 LO-F LNA Analog Output for Channel F
6 LOSW-F LNA Analog Output Complement for Channel F
7 LI-F LNA Analog Input for Channel F
8 LG-F LNA Ground for Channel F
11 LO-G LNA Analog Output for Channel G
12 LOSW-G LNA Analog Output Complement for Channel G
13 LI-G LNA Analog Input for Channel G
14 LG-G LNA Ground for Channel G
06304-005
Rev. PrA | Page 12 of 58
Preliminary Technical Data AD9271
Pin No. Name Description
17 LO-H LNA Analog Output for Channel H
18 LOSW-H LNA Analog Output Complement for Channel H
19 LI-H LNA Analog Input for Channel H
20 LG-H LNA Ground for Channel H
23 CLK− Clock Input Complement
24 CLK+ Clock Input True
27 DOUT − H ADC H Digital Output Complement
28 DOUT + H ADC H True Digital Output True
29 DOUT − G ADC C Digital Output Complement
30 DOUT + G ADC C True Digital Output
31 DOUT − F ADC B Digital Output Complement
32 DOUT + F ADC B True Digital Output True
33 DOUT − E ADC A Digital Output Complement
34 DOUT + E ADC A True Digital Output True
35 DCO− Frame Clock Digital Output Complement
36 DCO+ Frame Clock Digital Output True
37 FCO− Frame Clock Digital Output Complement
38 FCO+ Frame Clock Digital Output True
39 DOUT − D ADC H Digital Output Complement
40 DOUT + D ADC H True Digital Output True
41 DOUT − C ADC C Digital Output Complement
42 DOUT + C ADC C True Digital Output
43 DOUT − B ADC B Digital Output Complement
44 DOUT + B ADC B True Digital Output True
45 DOUT − A ADC A Digital Output Complement
46 DOUT + A ADC A True Digital Output True
48 STDBY Standby Power Down
49 PDWN Full Power Down
51 SCLK Serial Clock
52 SDIO Serial Data Input/Output
53 CSB Chip Select Bar
56 LG-A LNA Ground for Channel A
57 LI-A LNA Analog Input for Channel A
58 LOSW-A LNA Analog Output Complement for Channel A
59 LO-A LNA Analog Output for Channel A
62 LG-B LNA Ground for Channel B
63 LI-B LNA Analog Input for Channel B
64 LOSW-B LNA Analog Output Complement for Channel B
65 LO-B LNA Analog Output for Channel B
68 LG-C LNA Ground for Channel C
69 LI-C LNA Analog Input for Channel C
70 LOSW-C LNA Analog Output Complement for Channel C
71 LO-C LNA Analog Output for Channel C
74 LG-D LNA Ground for Channel D
75 LI-D LNA Analog Input for Channel D
76 LOSW-D LNA Analog Output Complement for Channel D
77 LO-D LNA Analog Output for Channel D
78 CWD0− CW Doppler Output Complement for Channel 0
79 CWD0+ CW Doppler Output True for Channel 0
80 CWD1− CW Doppler Output Complement for Channel 1
81 CWD1+ CW Doppler Output True for Channel 1
82 CWD2− CW Doppler Output Complement for Channel 2
83 CWD2+ CW Doppler Output True for Channel 2
Rev. PrA | Page 13 of 58
AD9271 Preliminary Technical Data
Pin No. Name Description
85 GAIN− GAIN Control Voltage Input Complement
86 GAIN+ GAIN Control Voltage Input True
87 RBIAS External resistor sets the internal ADC core bias current
88 SENSE Reference Mode Selection
89 VREF Voltage Reference Input/Output
90 REFB Differential Reference (Negative)
91 REFT Differential Reference (Positive)
93 CWD3− CW Doppler Output Complement for Channel 3
93 CWD3+ CW Doppler Output True for Channel 3
95 CWD4− CW Doppler Output Complement for Channel 4
96 CWD4+ CW Doppler Output True for Channel 4
97 CWD5− CW Doppler Output Complement for Channel 5
98 CWD5+ CW Doppler Output True for Channel 5
99 LO-E LNA Analog Output for Channel E
100 LOSW-E LNA Analog Output Complement for Channel E
Rev. PrA | Page 14 of 58
Preliminary Technical Data AD9271
V
Ω
A
S
EQUIVALENT CIRCUITS
CM
15kΩ
06304-073
LI-x,
LG-x
AVDD
Figure 5. Equivalent LNA Input Circuit
AVDD
LO-x,
LOSW-x
10Ω
Figure 6. Equivalent LNA Output Circuit
VDD
SDIO
350Ω
30kΩ
06304-008
Figure 8. Equivalent SDIO Input Circuit
DRVDD
V
DOUT– DOUT+
V
06304-075
DRGND
V
V
6304-009
Figure 9. Equivalent Digital Output Circuit
CLK+
CLK–
10
10kΩ
10kΩ
10Ω
Figure 7. Equivalent Clock Input Circuit
1.25V
06304-007
Rev. PrA | Page 15 of 58
CLK OR PDWN
OR STBY
1kΩ
30kΩ
Figure 10. Equivalent SCLK Input Circuit
06304-010
AD9271 Preliminary Technical Data
A
V
C
Ω
AVDD
RBIAS
100Ω
Figure 11. Equivalent RBIAS Circuit
DD
70kΩ
CSB
1kΩ
Figure 12. Equivalent CSB Input Circuit
AVDD
VREF
6kΩ
06304-011
6304-014
Figure 14. Equivalent VREF Circuit
GAIN
06304-012
50Ω
06304-074
Figure 15. Equivalent GAIN Input Circuit
SENSE
Figure 13. Equivalent SENSE Circuit
1kΩ
WDx+,
CWDx–
06304-013
10
06304-076
Figure 16. Equivalent CWD Output Circuit
Rev. PrA | Page 16 of 58
Preliminary Technical Data AD9271
TYPICAL PERFORMANCE CHARACTERISTICS
(f
= 50 MSPS, AIN = 5 MHz, LPF = 1/3 × f
SAMPLE
, LNA gain = 6×)
SAMPLE
2.00
1.50
1.00
0.50
0.00
Absolute Error (dB)
-0.50
-1.00
-1.50
-2.00
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Figure 17. Absolute Gain Error vs. V
85C
25C
-40C
Vgain (V)
at Three Temperatures
GAIN
2000000
1800000
1600000
1400000
1200000
1000000
Number of Hits
800000
600000
400000
200000
0
-5-4-3-2-1012345
Figure 20. Output-Referred Noise Histogram with Gain Pin at 0.0V, AD9271-
Codes
50
1200000
1000000
800000
600000
Number of Hits
400000
Figure 18. Gain Error Histogram
Figure 19. Gain Match Histogram for V
= 0.2 V and 0.7 V
GAIN
200000
0
-5-4-3-2-1012345
Codes
Figure 21. Output-Referred Noise Histogram with Gain Pin at 1.0V, AD9271-
50
4.5
4
3.5
3
2.5
2
Input-referred Noise (nV/sqrt-Hz )
1.5
1
0.5
0
0 5 10 15 20 25
LNA Gain = 5x
LNA Gain = 6x
LNA Gain = 8x
Frequency (MHz)
Figure 22. Short-Circuit, Input-Referred Noise vs. Frequency
Rev. PrA | Page 17 of 58
AD9271 Preliminary Technical Data
-99
-100
LNA Gain = 5x
LNA Gain = 6x
-101
LNA Gain = 8x
-102
-103
-104
-105
Output-referred Noise (d BFS/rt-Hz)
-106
-107
-108
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Figure 23. Short-Circuit, Output-Referred Noise vs. V
66
64
62
SNR (dBFS)
SINAD (dB)
SINAD (dBFS)
60
SNR/SINAD
58
56
54
52
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Vgain (V)
GAIN
Vgain (V)
Figure 24. SNR/SINAD vs. Gain
1.7
1.65
1.6
1.55
0
-5
-3dB line
-10
-15
-20
Fundamental (dBFS)
-25
-30
-35
-40
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25
Figure 26. Antialiasing Filter (AAF) Pass-Band Response
400
350
300
250
200
Group Delay (ns)
150
100
Vgain = 0.0 V
Vgain = 0.5 V
50
Vgain = 1.0 V
0
0.1 1 10 100
Frequency (MHz)
Analog Input Frequency (MHz)
(1/3)*25MHz
(1/3)*50MHz
(1/3)*40MHz
Figure 27. Antialiasing Filter (AAF) Group Delay Response
-50
-55
-60
-65
H2 (dBFS)
-70
Vgain=0.2V
Vgain=1V
1.5
Input-referred noise (nV/rt-Hz)
1.45
1.4
-40-200 20406080
Temperature (C)
Figure 25. Short-Circuit, Input-Referred Noise vs. Temperature
Rev. PrA | Page 18 of 58
-75
-80
-85
2 4 6 8 10 12 14 16
Vgain=0.5V
Fin (MHz)
Figure 28. Second-Order Harmonic Distortion vs. Frequency
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