ANALOG DEVICES AD9269 Service Manual

16-Bit, 20/40/65/80 MSPS,

O

A

V

1.8 V Dual Analog-to-Digital Converter

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply Integrated quadrature error correction (QEC) SNR

77.6 dBFS at 9.7 MHz input 71 dBFS at 200 MHz input

SFDR

93 dBc at 9.7 MHz input 80 dBc at 200 MHz input

Low power

44 mW per channel at 20 MSPS

100 mW per channel at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = −0.5/+1.1 LSB Serial port control options

Offset binary, gray code, or twos complement data format

Optional clock duty cycle stabilizer (DCS)

Integer 1-to-6 input clock divider

Data output multiplex option

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock output (DCO) with programmable clock and

data alignment

APPLICATIONS

Communications Diversity radio systems Multimode digital receivers

GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR

AD9269

FUNCTIONAL BLOCK DIAGRAM

DCS

SPI

CSB

MUX OPTION

CONTROLS

PDWN DFSCLK+ CLK–

MODE

CMOS

OEB

ORA

D15A

D0A

OUTPUT BUFFER

DCOA

DRVDD

ORB

D15B

D0B

OUTPUT BUFFE R

DCOB

SDI

PROGRAMMING DATA

QUADRATURE

ERROR

CORRECTION

DUTY CYCLE

STABILIZER

Figure 1.

VIN+A VIN–A

VREF

SENSE

VCM

RBIAS

VIN–B VIN+B

GND

DD SCLK

AD9269

ADC

REF

SELECT

ADC

DIVIDE

1TO 6

SYNC

PRODUCT HIGHLIGHTS

1. The AD9269 operates from a single 1.8 V analog power

supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.

2. The patented sample-and-hold circuit maintains excellent

performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.

3. An optional SPI selectable dc correction and quadrature

error correction (QEC) feature corrects for dc offset, gain, and phase mismatches between the two channels.

4. A standard serial port interface (SPI) supports various

product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing and offset adjustments, and voltage reference modes.

5. The AD9269 is packaged in a 64-lead RoHS-compliant

LFCSP that is pin compatible with the AD9268 16-bit ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC the AD9231 12-bit ADC, the AD6659 12-bit baseband diversity receiver, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.

08538-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9269

REVISION HISTORY

1/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

AD9269

GENERAL DESCRIPTION

The AD9269 is a monolithic, dual-channel, 1.8 V supply, 16-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.

The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.

The AD9269 incorporates an optional integrated dc correction and quadrature error correction block (QEC) that corrects for dc offset, gain, and phase mismatch between the two channels. This functional block can be very beneficial to complex signal processing applications such as direct conversion receivers.

The ADC also contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).

A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.

The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported, and output data can be multiplexed onto a single output bus.

The AD9269 is available in a 64-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).

Rev. 0 | Page 3 of 40

AD9269

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.

Table 1.

AD9269-20/AD9269-40 AD9269-65 AD9269-80

Parameter Temp

RESOLUTION Full 16 16 16 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.05 ±0.40 ±0.05 ±0.50 ±0.05 ±0.50 % FSR Gain Error Differential

1

Full −2.0 −2.0 −2.0 % FSR

Nonlinearity

2

(DNL)

Full −0.9/+1.2 −0.9/+1.4 −0.9/+1.65 LSB

25°C −0.5/+0.6 −0.5/+1.1 −0.5/+1.1 LSB Integral Nonlinearity

2

(INL)

Full ±5.50 ±6.50 ±6.50 LSB

25°C ±2.0 ±2.2 ±3.3 LSB

MATCHING

CHARACTERISTICS Offset Error 25°C ±0.0 ±0.50 ±0.0 ±0.55 ±0.0 ±0.65 % FSR Gain Error

1

25°C ±0.2 ±0.2 ±0.2 % FSR

TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ±2 ppm/°C

INTERNAL VOLTAGE

REFERENCE Output Voltage

Full 0.981 0.993 1.005 0.981 0.993 1.005 0.981 0.993 1.005 V

(1 V Mode)

Load Regulation

Full 2 2 2 mV

Error at 1.0 mA

INPUT-REFERRED NOISE

VREF = 1.0 V 25°C 2.8 2.8 2.8 LSB

ANALOG INPUT

Input Span,

Full 2 2 2 V p-p

VREF = 1.0 V Input Capacitance Input Common-

3

Full 6.5 6.5 6.5 pF

Full 0.9 0.9 0.9 V

Mode Voltage Input Common-

Full 0.5 1.3 0.5 1.3 0.5 1.3 V

Mode Range

REFERENCE INPUT

Full 7.5 7.5 7.5 kΩ

RESISTANCE

POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V Supply Current

2

IAVDD

IDRVDD2 (1.8 V)

IDRVDD2 (3.3 V)

Full 50.0/69.3 52.5/72.6 96.6 101.2 113 119 mA Full 3.9/6.4 9.6 11.8 mA Full 7.4/12.4 18.7 23 mA

Unit Min Typ Max Min Typ Max Min Typ Max

rms

Rev. 0 | Page 4 of 40

AD9269

AD9269-20/AD9269-40 AD9269-65 AD9269-80

Parameter Temp

POWER

CONSUMPTION DC Input Full 87.7/121.7 170.7 200 mW Sine Wave Input2

Full 96.9/136.3 102.0/142.3 191.2 199.8 224.6 240 mW

(DRVDD = 1.8 V)

Sine Wave Input2

Full 114.4/165.7 235.6 279 mW

(DRVDD = 3.3 V)

Standby Power

4

Full 37/37 37 37 mW

Power-Down Power Full 1.0 1.0 1.0 mW

1

Measured with a 1.0 V external reference.

2

Measured with a 10 MHz input frequency at a rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.

3

Input capacitance refers to the effective capacitance between one differential input pin and AGND.

4

Standby power is measured with a dc input and the CLK+, CLK− active.

Unit Min Typ Max Min Typ Max Min Typ Max

Rev. 0 | Page 5 of 40

AD9269

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.

Table 2.

1

Parameter

Temp

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 9.7 MHz 25°C 78.0 77.5 77.6 dBFS fIN = 30.5 MHz 25°C 77.5 77.5 77.2 dBFS Full 76.5 76.5 dBFS fIN = 70 MHz 25°C 76.5 76.5 76.3 dBFS Full 75.5 dBFS fIN = 200 MHz 25°C 71.0 dBFS

SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)

fIN = 9.7 MHz 25°C 77.9 77.4 77.4 dBFS fIN = 30.5 MHz 25°C 77.2 77.2 76.9 dBFS Full 76.0 76.0 dBFS fIN = 70 MHz 25°C 76.4 76.4 76.1 dBFS Full 75.0 dBFS fIN = 200 MHz 25°C 69.4 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz 25°C 12.6 12.6 12.6 Bits fIN = 30.5 MHz 25°C 12.5 12.5 12.5 Bits fIN = 70 MHz 25°C 12.4 12.4 12.3 Bits fIN = 200 MHz 25°C 11.2 Bits

WORST SECOND OR THIRD HARMONIC

fIN = 9.7 MHz 25°C −95 −97 −93 dBc fIN = 30.5 MHz 25°C −90 −93 −92 dBc Full −80 −80 dBc fIN = 70 MHz 25°C −89 −97 −90 dBc Full −80 dBc fIN = 200 MHz 25°C −80 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 9.7 MHz 25°C 95 95 93 dBc fIN = 30.5 MHz 25°C 90 91 92 dBc Full 80 80 dBc fIN = 70 MHz 25°C 89 95 90 dBc Full 80 dBc fIN = 200 MHz 25°C 80 dBc

WORST OTHER (HARMONIC OR SPUR)

fIN = 9.7 MHz 25°C −99 −89 −99 dBc fIN = 30.5 MHz 25°C −100 −100 −99 dBc Full −90 −91 dBc fIN = 70 MHz 25°C −99 −100 −97 dBc Full −89 dBc fIN = 200 MHz 25°C −86 dBc

TWO-TONE SFDR

fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 90 90 90 dBc

CROSSTALK

2

Full −110 −110 −110 dBc

ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.

AD9269-20/AD9269-40 AD9269-65 AD9269-80

Unit Min Typ Max Min Typ Max Min Typ Max

Rev. 0 | Page 6 of 40

AD9269

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,

unless otherwise noted.

Table 3.

AD9269-20/AD9269-40/AD9269-65/AD9269-80

Parameter Temp

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 0.2 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 8 10 12 kΩ Input Capacitance Full 4 pF

LOGIC INPUTS (SCLK/DFS, SYNC, PDWN)

1

High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF

LOGIC INPUTS (CSB)

2

High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 135 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUTS (SDIO/DCS)

2

High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 130 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

DIGITAL OUTPUTS

DRVDD = 3.3 V

High Level Output Voltage, IOH = 50 μA Full 3.29 V High Level Output Voltage, IOH = 0.5 mA Full 3.25 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 μA Full 0.05 V

DRVDD = 1.8 V

High Level Output Voltage, IOH = 50 μA Full 1.79 V High Level Output Voltage, IOH = 0.5 mA Full 1.75 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 μA Full 0.05 V

1

Internal 30 kΩ pull-down.

2

Internal 30 kΩ pull-up.

Unit Min Typ Max

Rev. 0 | Page 7 of 40

AD9269

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.

Table 4.

AD9269-20/AD9269-40 AD9269-65 AD9269-80

Parameter Temp

CLOCK INPUT PARAMETERS

Input Clock Rate Full 480 480 480 MHz Conversion Rate CLK Period—Divide-by-1 Mode (t

1

Full 3 20/40 3 65 3 80 MSPS

) Full

CLK

50/25

15.38 12.5 ns CLK Pulse Width High (tCH) 25.0/12.5 7.69 6.25 ns Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD) Full DCO Propagation Delay (t DCO to Data Skew (t

SKEW

) Full 3

DCO

) Full 0.1

3

3 3

0.1

3 ns 3 ns

0.1 ns

Pipeline Delay (Latency) Full 9 9 9 Cycles

With QEC Active Full 11 11 11 Cycles

Wake-Up Time

2

Full 350 350 350 μs

Standby Full 600/400 300 260 ns

OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles

1

Conversion rate is the clock rate after the CLK divider.

2

Wake-up time is dependent on the value of the decoupling capacitors.

Unit Min Typ Max Min Typ Max Min Typ Max

VIN

CLK+ CLK–

DCOA/DCOB

CH A/CH B DATA

N – 1

t

A

N

N + 1

t

CH

t

CLK

t

DCO

t

SKEW

N – 9

t

PD

N + 2

N – 8 N – 7 N – 6 N – 5

N + 3

N + 4

N + 5

08538-002

Figure 2. CMOS Output Data Timing

VIN

CLK+ CLK–

DCOA/DCOB

CH A/CH B DATA

N – 1

t

A

N

N + 1

t

CH

t

CLK

t

DCO

t

SKEW

CH A

CH B N – 9

CH A N – 8

N – 9

t

PD

Figure 3. CMOS Interleaved Output Timing

Rev. 0 | Page 8 of 40

N + 2

CH B N – 8

CH A N – 7

N + 3

CH B N – 7

CH A N – 6

N + 4

CH B N – 6

CH A N – 5

N + 5

08538-003

AD9269

TIMING SPECIFICATIONS

Table 5.

Parameter Conditions Min Typ Max Unit

SYNC TIMING REQUIREMENTS

t

SYNC to rising edge of CLK setup time 0.24 ns

SSYNC

t

SYNC to rising edge of CLK hold time 0.40 ns

HSYNC

SPI TIMING REQUIREMENTS

tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns t

Period of the SCLK 40 ns

CLK

tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns t

SCLK pulse width high 10 ns

HIGH

t

SCLK pulse width low 10 ns

LOW

t

EN_SDIO

t

DIS_SDIO

Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge

Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge

CLK+

10 ns

t

SSYNC

SYNC

Figure 4. SYNC Input Timing Requirements

t

HSYNC

08538-004

Rev. 0 | Page 9 of 40

AD9269

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

AVDD to AGND −0.3 V to +2.0 V DRVDD to AGND −0.3 V to +3.9 V VIN+A, VIN+B, VIN−A, VIN−B to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V SYNC to AGND −0.3 V to DRVDD + 0.3 V VREF to AGND −0.3 V to AVDD + 0.2 V SENSE to AGND −0.3 V to AVDD + 0.2 V VCM to AGND −0.3 V to AVDD + 0.2 V RBIAS to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.3 V SCLK/DFS to AGND −0.3 V to DRVDD + 0.3 V SDIO/DCS to AGND −0.3 V to DRVDD + 0.3 V OEB to AGND −0.3 V to DRVDD + 0.3 V PDWN to AGND −0.3 V to DRVDD + 0.3 V D0x through D15x to AGND DCOx to AGND Operating Temperature Range (Ambient) −40°C to +85°C Maximum Junction Temperature Under Bias 150°C Storage Temperature Range (Ambient) −65°C to +150°C

−0.3 V to DRVDD + 0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

The exposed paddle is the only ground connection for the chip. The exposed paddle must be soldered to the AGND plane of the user’s PCB. Soldering the exposed paddle to the user’s board also increases the reliability of the solder joints and maximizes the thermal capability of the package.

Table 7. Thermal Resistance

Airflow Veloc ity

Packa ge Type

64-Lead LFCSP

9 mm × 9 mm (CP-64-4)

1

Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-Std 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

(m/sec) θ

0 23 2.0 °C/W

1.0 20 12 °C/W

2.5 18 °C/W

1, 2

JA

1, 3

θ

JC

1, 4

θ

Unit

JB

Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown in Ta b l e 7 , airflow improves heat dissipation, which reduces θ

. In addition, metal in direct contact with the

JA

package leads from metal traces, through holes, ground, and power planes, reduces the θ

.

JA

ESD CAUTION

Rev. 0 | Page 10 of 40

AD9269

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD

VIN+B

VIN–B

AVDD

RBIAS

VCM

SENSE

VREF

AVDD

VIN–A

VIN+A

AVDD

646362616059585756555453525150

AVDD 49

CLK+ CLK–

SYNC

D0B (LSB)

D1B D2B D3B D4B D5B

DRVDD

10

D6B

11

D7B

12

D8B

13

D9B

14

D10B

15

D11B

16

NOTES

1. THE EXPOSED PADDLE MUS T BE SOLDERE D TO THE PCB ANAL OG GROUND TO ENSURE PRO P E R HE AT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENE FITS.

PIN 1

1

INDICATOR

2 3 4 5 6 7 8 9

171819202122232425262728293031

D12B

D13B

D14B

DRVDD

AD9269

TOP VIEW

(Not to S cale)

ORB

DCOA

DCOB

D15B (MSB)

D1A

D2A

D3A

D4A

DRVDD

D0A (LSB)

48

PDWN

47

OEB

46

CSB

45

SCLK/DFS

44

SDIO/DCS

43

ORA

42

D15A (MSB )

41

D14A

40

D13A

39

D12A

38

D11A

37

DRVDD

36

D10A

35

D9A

34

D8A

33

D7A

32

D5A

D6A

Figure 5. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

0, EP AGND

The exposed paddle is the only ground connection. It must be soldered to the PCB analog ground to

ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. 1, 2 CLK+, CLK− Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. 3 SYNC Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down. 4 to 9, 11 to

18, 20, 21

D0B (LSB) to D15B (MSB)

Channel B Digital Outputs. D0B is the LSB; D15B is the MSB.

10, 19, 28, 37 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 22 ORB Channel B Out-of-Range Digital Output. 23 DCOB Channel B Data Clock Digital Output. 24 DCOA Channel A Data Clock Digital Output. 25 to 27, 29 to

36, 38 to 42

D0A (LSB) to D15A (MSB)

Channel A Digital Outputs. D0A is the LSB; D15A is the MSB.

43 ORA Channel A Out-of-Range Digital Output. 44 SDIO/DCS

SPI Data Input/Output (SDIO). Bidirectional SPI data I/O in SPI mode. 30 kΩ internal pull-down in SPI mode.

Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode. 30 kΩ internal

pull-up in non-SPI (DCS) mode. 45 SCLK/DFS

SPI Clock (SCLK). Input in SPI mode. 30 kΩ internal pull-down.

Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal pull-down.

DFS high: twos complement output.

DFS low: offset binary output. 46 CSB SPI Chip Select. Active low enable; 30 kΩ internal pull-up. 47 OEB

Digital Input. 30 kΩ internal pull-down.

Low: enable Channel A and Channel B digital outputs.

High: three-state outputs. 48 PDWN

Digital Input. 30 kΩ internal pull-down.

High: power down device.

Low: run device, normal operation.

08538-005

Rev. 0 | Page 11 of 40

AD9269

Pin No. Mnemonic Description

49, 50, 53, 54, 59, 60, 63, 64

51, 52 VIN+A, VIN−A Channel A Analog Inputs. 55 VREF Voltage Reference Input/Output. 56 SENSE Reference Mode Selection. 57 VCM Analog Output Voltage at Midsupply. Sets the common mode of the analog inputs. 58 RBIAS Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 61, 62 VIN−B, VIN+B Channel B Analog Inputs.

AVDD 1.8 V Analog Supply Pins.

Rev. 0 | Page 12 of 40

ANALOG DEVICES AD9269 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS