ANALOG DEVICES AD9268 Service Manual

16-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual

S

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FEATURES

SNR = 78.2 dBFS @ 70 MHz and 125 MSPS SFDR = 88 dBc @ 70 MHz and 125 MSPS Low power: 750 mW @ 125 MSPS

1.8 V analog supply operation

1.8 V CMOS or LVDS output supply Integer 1-to-8 input clock divider IF sampling frequencies to 300 MHz

−153.6 dBm/Hz small-signal input noise with 200 Ω input impedance @ 70 MHz and 125 MSPS

Optional on-chip dither Programmable internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range: 1 V p-p to 2 V p-p Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes

APPLICATIONS

Communications Diversity radio systems Multimode digital receivers (3G)

GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA

I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipment

Analog-to-Digital Converter (ADC)

AD9268

FUNCTIONAL BLOCK DIAGRAM

SDIO/

SCLK/

DCS

DFS

AD9268

VIN+A VIN–A

VREF ENSE

SELECT

VCM

RBIAS

VIN–B

VIN+B

NOTES

1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FORLVDS PIN NAMES.

REF

MULTICHIP

ADC

SYNC

SYNCAGND

SPI

PROGRAMMI NG DATA

CMOS/LVDS

OUTPUT BUFFER

DIVIDE 1

TO 8

DUTY CYCLE

STABILIZER

CMOS/LVDS

OUTPUT BUFFER

PDWN OEB

Figure 1.

PRODUCT HIGHLIGHTS

1. On-chip dither option for improved SFDR performance

with low power analog input.

2. Proprietary differential input that maintains excellent SNR

performance for input frequencies up to 300 MHz.

3. Operation from a single 1.8 V supply and a separate digital

output driver supply accommodating 1.8 V CMOS or LVDS outputs .

4. Standard serial port interface (SPI) that supports various

product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode.

5. Pin compatibility with the AD9258, allowing a simple

migration from 16 bits to 14 bits. The AD9268 is also pin compatible with the AD9251, AD9231, and AD9204 family of products for lower sample rate, low power applications.

DRVDDCSBAVDD

DCO

GENERATION

ORA D15A (MSB)

16

TO D0A (LSB)

CLK+ CLK–

DCOA DCOB

ORB D15B (MSB)

16

TO D0B (LSB)

08123-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9268

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REVISION HISTORY

9/09—Rev. 0 to Rev. A

Changes to Features List .................................................................. 1

Changes to Specifications Section .................................................. 4

Changes to Table 5 .......................................................................... 10

Changes to Typical Performance Characteristics Section ......... 17

5/09—Revision 0: Initial Version

Rev. A | Page 2 of 44

AD9268

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GENERAL DESCRIPTION

The AD9268 is a dual, 16-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC). The AD9268 is designed to support communications applications where high performance, combined with low cost, small size, and versatility, is desired.

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

The ADC output data can be routed directly to the two external 16-bit output ports. These outputs can be set to either 1.8 V CMOS or LVDS.

Flexible power-down options allow significant power savings, when desired.

Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.

The AD9268 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

Rev. A | Page 3 of 44

AD9268

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SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.

Table 1.

AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit

RESOLUTION Full 16 16 16 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.2 ±0.4 ±0.2 ±0.5 ±0.4 ±0.65 % FSR Gain Error Full ±0.4 ±2.5 ±0.4 ±2.5 ±0.4 ±2.5 % FSR Differential

Nonlinearity (DNL)

25°C ±0.65 ±0.7 ±0.7 LSB

Integral Nonlinearity

1

(INL) 25°C ±2.0 ±3.0 ±3.0 LSB MATCHING

CHARACTERISTIC

Offset Error Full ±0.1 ±0.4 ±0.1 ±0.4 ±0.2 ±0.45 % FSR Gain Error Full ±0.3 ±1.3 ±0.3 ±1.3 ±0.3 ±1.3 % FSR

TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ±2 ppm/°C Gain Error Full ±15 ±15 ±15 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error

(1 V Mode)

Load Regulation @

1.0 mA

INPUT REFERRED NOISE

VREF = 1.0 V 25°C 2.17 2.23 2.27

ANALOG INPUT

Input Span, VREF =

1.0 V Input Capacitance Input Common-

Mode Voltage

REFERENCE INPUT RESISTANCE

POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

Supply Current

1

IAVDD

Full 234 240 293 300 390 400 mA

IDRVDD1 (1.8 V

CMOS)

IDRVDD1 (1.8 V

LVD S)

Full −1.0 +1.4 −1.0 +1.3 −1.0 +1.2 LSB

1

Full ±4.5 ±5.1 ±5.5 LSB

Full ±5 ±12 ±5 ±12 ±5 ±12 mV

Full 5 5 5 mV

LSB rms

Full 2 2 2 V p-p

2

Full 8 8 8 pF

Full 0.9 0.9 0.9 V

Full 6 6 6 kΩ

Full 35 45 55 mA

Full 89 89 94 mA

Rev. A | Page 4 of 44

AD9268

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AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit

POWER CONSUMPTION

DC Input Full 420 450 565 590 750 777 mW Sine Wave Input1

(DRVDD = 1.8 V CMOS Output Mode)

Sine Wave Input1

(DRVDD = 1.8 V LVDS Output

Mode) Standby Power Power-Down Power Full 0.5 2.5 0.5 2.5 0.5 2.5 mW

1

Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND.

3

Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).

Full 485 608 800 mW

Full 582 685 870 mW

3

Full 45 45 45 mW

Rev. A | Page 5 of 44

AD9268

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ADC AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.

Table 2.

AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 Parameter

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 2.4 MHz 25°C 79.7 78.9 78.8 dBFS fIN = 70 MHz 25°C 78.3 79.0 77.2 78.8 77.2 78.2 dBFS Full 78.0 77.1 76.5 dBFS fIN = 140 MHz 25°C 77.4 76.9 77.1 dBFS fIN = 200 MHz 25°C 75.5 75.0 75.5 dBFS

SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)

fIN = 2.4 MHz 25°C 79.4 78.3 78.3 dBFS fIN = 70 MHz 25°C 78.1 78.5 77.1 78.6 76.8 77.7 dBFS Full 77.7 76.8 76.2 dBFS fIN = 140 MHz 25°C 75.4 75.9 75.8 dBFS fIN = 200 MHz 25°C 74.3 72.2 74.0 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.4 MHz 25°C 12.9 12.7 12.7 Bits fIN = 70 MHz 25°C 12.8 12.7 12.6 Bits fIN = 140 MHz 25°C 12.2 12.3 12.3 Bits fIN = 200 MHz 25°C 12.0 11.7 12.0 Bits

WORST SECOND OR THIRD HARMONIC

fIN = 2.4 MHz 25°C −92 −87 −90 dBc fIN = 70 MHz 25°C −91 −88 −93 −87 −88 −85 dBc Full −87 −87 −84 dBc fIN = 140 MHz 25°C −80 −84 −83 dBc fIN = 200 MHz 25°C −82 −77 −79 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.4 MHz 25°C 92 87 90 dBc fIN = 70 MHz 25°C 88 91 87 93 85 88 dBc Full 87 87 84 dBc fIN = 140 MHz 25°C 80 84 83 dBc fIN = 200 MHz 25°C 82 77 79 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

Without Dither (AIN@ −23 dBFS)

With On-Chip Dither (AIN @ −23 dBFS)

1

Temp Min Typ Max Min Typ Max Min Typ Max Unit

fIN = 2.4 MHz 25°C 93 100 88 dBFS fIN = 70 MHz 25°C 95 96 89 dBFS fIN = 140 MHz 25°C 98 96 90 dBFS fIN = 200 MHz 25°C 102 100 89 dBFS

fIN = 2.4 MHz 25°C 107 106 106 dBFS fIN = 70 MHz 25°C 107 109 106 dBFS fIN = 140 MHz 25°C 106 104 104 dBFS fIN = 200 MHz 25°C 104 108 105 dBFS

Rev. A | Page 6 of 44

AD9268

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AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 Parameter

WORST OTHER (HARMONIC OR SPUR)

Without Dither

With On-Chip Dither

TWO-TONE SFDR, WITHOUT DITHER

fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS) 25°C 93 92 90 dBc fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS) 25°C 81 80 82 dBc

CROSSTALK ANALOG INPUT BANDWIDTH 25°C 650 650 650 MHz

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel.

1

Temp Min Typ Max Min Typ Max Min Typ Max Unit

fIN = 2.4 MHz 25°C −99 −100 −100 dBc

fIN = 70 MHz 25°C −100 −96 −99 −94 −100 −94 dBc

Full −96 −94 −94 dBc

fIN = 140 MHz 25°C −98 −98 −98 dBc

fIN = 200 MHz 25°C −96 −94 −96 dBc

fIN = 2.4 MHz 25°C −108 −107 −108 dBc

fIN = 70 MHz 25°C −106 −96 −107 −95 −106 −95 dBc

Full −96 −95 −95 dBc

fIN = 140 MHz 25°C −105 −104 −103 dBc

fIN = 200 MHz 25°C −102 −102 −99 dBc

2

Full −95 −95 −95 dB

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.

Table 3.

Parameter Temperature Min Typ Max Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ

SYNC INPUT

Logic Compliance CMOS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ

Rev. A | Page 7 of 44

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Parameter Temperature Min Typ Max Unit

LOGIC INPUT (CSB)1

High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUT (SCLK/DFS)2

High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUT/OUTPUT (SDIO/DCS)

High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

LOGIC INPUTS (OEB, PDWN)

High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −90 −134 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

DIGITAL OUTPUTS

CMOS Mode—DRVDD = 1.8 V

High Level Output Voltage

IOH = 50 μA Full 1.79 V IOH = 0.5 mA Full 1.75 V

Low Level Output Voltage

IOL = 1.6 mA Full 0.2 V IOL = 50 μA Full 0.05 V

LVDS Mode—DRVDD = 1.8 V

Differential Output Voltage (VOD), ANSI Mode Full 290 345 400 mV Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V Differential Output Voltage (VOD), Reduced Swing Mode Full 160 200 230 mV Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V

1

Pull up.

2

Pull down.

1

2

Rev. A | Page 8 of 44

AD9268

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SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.

Table 4.

AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit

CLOCK INPUT PARAMETERS

Input Clock Rate Full 625 625 625 MHz Conversion Rate1

DCS Enabled Full 20 80 20 105 20 125 MSPS

DCS Disabled Full 10 80 10 105 10 125 MSPS CLK Period—Divide-by-1 Mode (t CLK Pulse Width High (tCH)

Divide-by-1 Mode, DCS Enabled Full

Divide-by-1 Mode, DCS Disabled Full

Divide-by-2 Mode Through Divide-

by-8 Mode Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.07 0.07 0.07

DATA OUTPUT PARAMETERS

CMOS Mode

Data Propagation Delay (tPD) Full DCO Propagation Delay (t

DCO to Data Skew (t

SKEW

LVDS Mode

Data Propagation Delay (tPD) Full 2.9 3.7 4.5 2.9 3.7 4.5 2.9 3.7 4.5 ns DCO Propagation Delay (t DCO to Data Skew (t

SKEW

CMOS Mode Pipeline Delay

(Latency)

LVDS Mode Pipeline Delay (Latency)

Channel A/Channel B Wake-Up Time3 Full 500 500 500 μs Out-of-Range Recovery Time Full 2 2 2 Cycles

1

Conversion rate is the clock rate after the divider.

2

Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17).

3

Wake-up time is defined as the time required to return to normal operation from power-down mode.

) Full 12.5 9.5 8 ns

CLK

3.75

6.25

5.95

6.25

Full 0.8

8.75 2.85

6.55 4.5

0.8

4.75

6.65

2.4 4 5.6 ns

5.0

3.8 4 4.2 ns

0.8

ns

ps rms

)2 Full

DCO

2.8

3.5

3.1

4.2 2.8

3.5

3.1

4.2

2.8 3.5 4.2 ns

3.1

ns

) Full −0.6 −0.4 0 −0.6 −0.4 0 −0.6 −0.4 0 ns

)2 Full

DCO

3.9

ns

) Full −0.1 +0.2 +0.5 −0.1 +0.2 +0.5 −0.1 +0.2 +0.5 ns

Full 12 12 12 Cycles

Full 12/12.5 12/12.5 12/12.5 Cycles

Rev. A | Page 9 of 44

AD9268

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TIMING SPECIFICATIONS

Table 5.

Parameter Conditions Limit

SYNC TIMING REQUIREMENTS

t

SYNC to rising edge of CLK+ setup time 0.3 ns typ

SSYNC

t

SYNC to rising edge of CLK+ hold time 0.40 ns typ

HSYNC

SPI TIMING REQUIREMENTS

tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min t

Period of the SCLK 40 ns min

CLK

tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min t

SCLK pulse width high 10 ns min

HIGH

t

SCLK pulse width low 10 ns min

LOW

t

EN_SDIO

t

DIS_SDIO

Timing Diagrams

CH A/CH B DATA

VIN

CLK+ CLK–

DCOA/DCOB

VIN

CLK+ CLK–

DCOA/DCOB

Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge

Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge

N – 1

t

CH

t

A

N

N + 1

t

CLK

t

DCO

t

SKEW

N – 12N – 13

t

PD

N + 2

N – 11 N – 10 N – 9 N – 8

Figure 2. CMOS Default Output Mode Data Output Timing

N – 1

t

CH

t

DCO

t

A

N

N + 1

t

CLK

t

SKEW

t

PD

CH A

CH B

N – 12

CH A

N – 11

N + 2

CH B

N – 11

CH A

N – 10

Figure 3. CMOS Interleaved Output Mode Data Output Timing

N + 3

CH B

N – 10

CH A N – 9

N + 4

CH B N – 9

CH A N – 8

N + 5

10 ns min

08123-002

08123-057

Rev. A | Page 10 of 44

AD9268

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VIN

CLK+ CLK–

DCOA/DCOB

CH A/CH B DATA

N – 1

CH A N – 9

N + 4

CH B N – 9

CH A N – 8

N + 5

08123-003

t

A

N

N + 1

t

CH

t

DCO

t

CLK

t

SKEW

PD

CH A

CH B

N – 12

CH A

N – 11

N + 2

CH B

N – 11

CH A

N – 10

N + 3

CH B

N – 10

Figure 4. LVDS Mode Data Output Timing

CLK+

t

HSYNC

08123-004

SYNC

t

SSYNC

Figure 5. SYNC Input Timing Requirements

Rev. A | Page 11 of 44

AD9268

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ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

ELECTRICAL1

AVDD to AGND −0.3 V to +2.0 V DRVDD to AGND −0.3 V to +2.0 V VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V SYNC to AGND −0.3 V to AVDD + 0.2 V VREF to AGND −0.3 V to AVDD + 0.2 V SENSE to AGND −0.3 V to AVDD + 0.2 V VCM to AGND −0.3 V to AVDD + 0.2 V RBIAS to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.2 V SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V SDIO/DCS to AGND −0.3 V to DRVDD + 0.2 V OEB −0.3 V to DRVDD + 0.2 V PDWN −0.3 V to DRVDD + 0.2 V D0A/D0B through D15A/D15B to

AGND

DCOA/DCOB to AGND

−0.3 V to DRVDD + 0.2 V

ENVIRONMENTAL

Operating Temperature Range

−40°C to +85°C

(Ambient)

Maximum Junction Temperature

150°C

Under Bias

Storage Temperature Range

−65°C to +150°C

(Ambient)

1

The inputs and outputs are rated to the supply voltage (AVDD or ARVDD) +

0.2 V but should not exceed 2.1 V.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the PCB increases the reliability of the solder joints and maximizes the thermal capability of the package.

Typical θ

is specified for a 4-layer PCB with a solid ground

JA

plane. As shown in Ta b l e 7 , airflow improves heat dissipation, which reduces θ

. In addition, metal in direct contact with the

JA

package leads from metal traces, through holes, ground, and power planes, reduces θ

.

JA

Table 7. Thermal Resistance

Airflow

Packa ge Type

64-Lead LFCSP (CP-64-6)

Veloc ity (m/sec) θ

0 18.5 1.0 °C/W

1.0 16.1 9.2 °C/W

1, 2

JA

1, 3

θ

JC

1, 4

θ

Unit

JB

2.5 14.5 °C/W

1

Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-Std 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

ESD CAUTION

Rev. A | Page 12 of 44

AD9268

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AVDD

VIN+B

VIN–B

AVDD

RBIAS

VCM

SENSE

VREF

AVDD

VIN–A

VIN+A

AVDD

646362616059585756555453525150

AVDD 49

CLK+ CLK–

SYNC

D0B (LSB)

D1B D2B D3B D4B D5B

DRVDD

10

D6B

11

D7B

12

D8B

13

D9B

14

D10B

15

D11B

16

NOTES

1. THE EXPOSED THERMAL PAD O N THE BOTTOM OF T HE PACKAGE PROVIDES THE ANALOG G ROUND FOR THE PART. THIS E X P OSED PAD MUST BE CONNECTED TO GROUND FOR PROPE R OPERATIO N.

PIN 1

1

INDICATOR

2 3 4 5 6 7 8 9

171819202122232425262728293031

D12B

PARALLEL CMOS

(Not to Scale)

D13B

D14B

DRVDD

D15B (MSB)

AD9268

TOP VIEW

ORB

DCOA

DCOB

D0A (LSB)

D1A

D2A

D3A

D4A

DRVDD

48

PDWN

47

OEB

46

CSB

45

SCLK/DFS

44

SDIO/DCS

43

ORA

42

D15A (MSB)

41

D14A

40

D13A

39

D12A

38

D11A

37

DRVDD

36

D10A

35

D9A

34

D8A

33

D7A

32

D5A

D6A

05

08123-0

Figure 6. LFCSP Parallel CMOS Pin Configuration (Top View)

Table 8. Pin Function Descriptions (Parallel CMOS Mode)

Pin No. Mnemonic Type Description

ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54, 59,

AVDD Supply Analog Power Supply (1.8 V Nominal).

60, 63, 64 0

AGND, Exposed Pad

Ground

The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper

operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Voltage Reference Mode Select. See Tab le 11 for details. 58 RBIAS Input/Output External Reference Bias Resistor. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 25 D0A (LSB) Output Channel A CMOS Output Data. 26 D1A Output Channel A CMOS Output Data. 27 D2A Output 29 D3A Output 30 D4A Output 31 D5A Output

Channel A CMOS Output Data.

Channel A CMOS Output Data. 32 D6A Output Channel A CMOS Output Data.

Rev. A | Page 13 of 44

ANALOG DEVICES AD9268 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

ADC DC SPECIFICATIONS

ADC AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING SPECIFICATIONS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS