ANALOG DEVICES AD9266-EP Service Manual

1.8 V Analog-to-Digital Converter

AD9266-EP

Rev. A

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VIN+
VIN–

VREF

SENSE

OR

D1_D0

D15_D14

8

DCO

SDIOAGND DRVDDAVDD

SCLK

SPI

PROGRAMMI NG DATA

VCM

RBIAS

PDWN DFS

CLK+ CLK–

MODE

CONTROLS

DUTY CYCLE

STABILIZER

DIVIDE

1 TO 8

MODE

CSB

REF

SELECT

ADC

CORE

CMOS

OUTPUT BUFFER

AD9266-EP

10476-001

Enhanced Product

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply
SNR

77.6 dBFS at 9.7 MHz input

76.4 dBFS at 70 MHz input

SFDR

94 dBc at 9.7 MHz input
93 dBc at 70 MHz input

Low power

111 mW at 65 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = −0.5/+1.0 LSB
Interleaved data output for reduced pin-count interface
Serial port control options

Offset binary, Gray code, or twos complement data format

Optional clock duty cycle stabilizer

Integer 1-to-8 input clock divider

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock output (DCO) with programmable clock and

data alignment

ENHANCED PRODUCT FEATURES

Supports defense and aerospace applications (AQEC standard)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
Enhanced product change notification
Qualification data available on request

APPLICATIONS

Communications
Diversity radio systems
Multimode digital receivers

GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
PET/SPECT imaging

Information furnishe d by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

16-Bit, 65 MSPS,

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

PRODUCT HIGHLIGHTS

1. The AD9266-EP operates from a single 1.8 V analog power

supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.

2. The patented sample-and-hold circuit maintains excellent

performance at high input frequencies and is designed for
low cost, low power, and ease of use.

3. A standard serial port interface supports various product

features and functions, such as data output formatting,
internal clock divider, power-down, DCO and data output
(D15_D14 to D1_D0) timing and offset adjustments, and
voltage reference modes.

4. The AD9266-EP is packaged in a 32-lead RoHS-compliant

LFCSP that is pin compatible with the AD9609 10-bit
ADC, the AD9629 12-bit ADC, and the AD9649 14-bit
ADC, enabling a simple migration path between 10-bit and
16-bit converters sampling at 65 MSPS.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

AD9266-EP Enhanced Product

TABLE OF CONTENTS

Features .............................................................................................. 1

Enhanced Product Features ............................................................ 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications ..................................................................................... 4

DC Specifications ......................................................................... 4

AC Specifications .......................................................................... 5

REVISION HISTORY

7/12—Rev. 0 to Rev. A

Changes to Resolution Parameter, Table 1 and Note 3, Table 1 ........ 4

1/12—Revision 0: Initial Version

Digital Specifications ....................................................................6

Switching Specifications ...............................................................7

Timing Specifications ...................................................................8

Absolute Maximum Ratings ............................................................9

Thermal Characteristics ...............................................................9

ESD Caution...................................................................................9

Pin Configuration and Function Descriptions ........................... 10

Outline Dimensions ....................................................................... 11

Ordering Guide .......................................................................... 11

Rev. A | Page 2 of 12

Enhanced Product AD9266-EP

GENERAL DESCRIPTION

The AD9266-EP is a monolithic, single-channel 1.8 V supply,
16-bit, 65 MSPS analog-to-digital converter (ADC). It features a
high performance sample-and-hold circuit and on-chip voltage
reference.

The product uses multistage differential pipeline architecture
with output error correction logic to provide 16-bit accuracy at
65 MSPS data rates and to guarantee no missing codes over the
full operating temperature range.

The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom
user-defined test patterns entered via the serial port interface (SPI).

A differential clock input with a selectable internal 1-to-8 divide
ratio controls all internal conversion cycles. An optional duty cycle
stabilizer (DCS) compensates for wide variations in the clock duty
cycle while maintaining excellent overall ADC performance.

The interleaved digital output data is presented in offset binary,
gray code, or twos complement format. A data output clock
(DCO) is provided to ensure proper latch timing with receiving
logic. CMOS levels from 1.8 V through 3.3 V are supported.

The AD9266-EP is available in a 32-lead RoHS-compliant LFCSP
and is specified over the −55°C to +125°C temperature range.

Additional application and technical information can be found
in the AD9266 data sheet.

This product is protected by a U.S. patent.

Rev. A | Page 3 of 12

AD9266-EP Enhanced Product

ANALOG INPUT

IAVDD2

Full 56.3

62.2

mA

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.

Table 1.

Parameter Temp Min Typ Max Unit
RESOLUTION Full 16 Bits
ACCURACY

No Missing Codes Full Guaranteed
Offset Error Full +0.05 ±0.30 % FSR
Gain Error1 25°C −1.3 % FSR
Differential Nonlinearity (DNL)2 Full −0.9/+1.7 LSB
25°C −0.5/+1.0 LSB
Integral Nonlinearity (INL)2 Full ±6.5 LSB
25°C ±2.6 LSB

TEMPERATURE DRIFT

Offset Error Full ±2 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mo de) Full 0.983 0.995 1.007 V
Load Regulation Error at 1.0 mA 25°C 2 mV

INPUT-REFERRED NOISE

VREF = 1.0 V 25°C 2.8 LSB rms

Input Span, VREF = 1.0 V 25°C 2 V p-p
Input Capacitance3 25°C 6.5 pF
Input Common-Mode Voltage 25°C 0.9 V

Input Common-Mode Range Full 0.5 1.3 V
REFERENCE INPUT RESISTANCE Full 7.5 kΩ
POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 3.6 V

Supply Current

IDRVDD2 (1.8 V) 25°C 5.2 mA

IDRVDD2 (3.3 V) 25°C 9.3 mA

POWER CONSUMPTION

DC Input 25°C 107 mW

Sine Wave Input2 (DRVDD = 1.8 V) Full 111 122 mW

Sine Wave Input2 (DRVDD = 3.3 V) 25°C 132 mW

Standby Power4 25°C 44 mW

Power-Down Power 25°C 0.5 mW

1

Measured with 1.0 V external reference.

2

Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.

3

Input capacitance refers to the effective capacitance between the differential inputs.

4

Standby power is measured with a dc input and the CLK active.

Rev. A | Page 4 of 12