Analog Devices AD9254 Service Manual

14-Bit, 150 MSPS, 1.8 V

A

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply
SNR = 71.8 dBc (72.8 dBFS) to 70 MHz input
SFDR = 84 dBc to 70 MHz input
Low power: 430 mW @ 150 MSPS
Differential input with 650 MHz bandwidth
On-chip voltage reference and sample-and-hold amplifier
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary, Gray code, or twos complement data format
Clock duty cycle stabilizer
Data output clock
Serial port control

Built-in selectable digital test pattern generation
Programmable clock and data alignment

APPLICATIONS

Ultrasound equipment
IF sampling in communications receivers

CDMA2000, WCDMA, TD-SCDMA, and WiMax
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes

Macro, micro, and pico cell infrastructure

GENERAL DESCRIPTION

The AD9254 is a monolithic, single 1.8 V supply, 14-bit, 150 MSPS
analog-to-digital converter (ADC), featuring a high performance
sample-and-hold amplifier (SHA) and on-chip voltage reference.
The product uses a multistage differential pipeline architecture
with output error correction logic to provide 14-bit accuracy at
150 MSPS data rates and guarantees no missing codes over the
full operating temperature range.

The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets, including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9254 is suitable for applications in communications,
imaging, and medical ultrasound.

A differential clock input controls all internal conversion cycles.
A duty cycle stabilizer (DCS) compensates for wide variations in
the clock duty cycle while maintaining excellent overall ADC
performance.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

Analog-to-Digital Converter

AD9254

FUNCTIONAL BLOCK DIAGRAM

MODE

SELECT

DRVDD

A/D

3

VDD

AD9254

VIN+

VIN–

REFT

REFB

VREF

SENSE

SHA

REF

SELECT

MDAC1

A/D

0.5V

AGND

8-STAGE

1 1/2-BIT PIPELINE

4

CORRECTION LOGIC

OUTPUT BUFF ERS

CLOCK

DUTY CYCLE

STABILIZER

CLK+

Figure 1.

8

15

CLK– PDWN DRGND

The digital output data is presented in offset binary, Gray code, or
twos complement formats. A data output clock (DCO) is provided
to ensure proper latch timing with receiving logic.

The AD9254 is available in a 48-lead LFCSP_VQ and is specified
over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. The AD9254 operates from a single 1.8 V power supply

and features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.

2. The patented SHA input maintains excellent performance

for input frequencies up to 225 MHz.

3. The clock DCS maintains overall ADC performance over a

wide range of clock pulse widths.

4. A standard serial port interface supports various product

features and functions, such as data formatting (offset
binary, twos complement, or Gray coding), enabling the
clock DCS, power-down, and voltage reference mode.

5. The AD9254 is pin-compatible with the AD9233, allowing

a simple migration from 12 bits to 14 bits.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

OR

DCO

D13 (MSB)

D0 (LSB)

SCLK/DFS

SDIO/DCS

CSB

06216-001

AD9254

TABLE OF CONTENTS

Features.............................................................................................. 1

Timing ......................................................................................... 20

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications.............................................................. 6

Timing Diagram........................................................................... 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Serial Port Interface (SPI).............................................................. 21

Configuration Using the SPI..................................................... 21

Hardware Interface..................................................................... 21

Configuration Without the SPI................................................ 21

Memory Map .................................................................................. 22

Reading the Memory Map Register Table............................... 22

Memory Map Register Table..................................................... 23

Layout Considerations................................................................... 25

Power and Ground Recommendations................................... 25

CML ............................................................................................. 25

RBIAS........................................................................................... 25

Reference Decoupling................................................................ 25

Evaluation Board............................................................................ 26

Power Supplies............................................................................ 26

Input Signals................................................................................ 26

Equivalent Circuits........................................................................... 9

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 14

Analog Input Considerations.................................................... 14

Differential Input Configurations............................................ 15

Voltage Reference....................................................................... 16

Clock Input Considerations...................................................... 17

Jitter Considerations .................................................................. 19

Power Dissipation and Standby Mode..................................... 19

Digital Outputs ........................................................................... 20

REVISION HISTORY

10/06—Revision 0: Initial Version

Output Signals ............................................................................ 26

Default Operation and Jumper Selection Settings................. 27

Alternative Clock Configurations............................................ 27

Alternative Analog Input Drive Configuration...................... 27

Schematics................................................................................... 29

Evaluation Board Layout........................................................... 34

Bill of Materials........................................................................... 37

Outline Dimensions....................................................................... 40

Ordering Guide .......................................................................... 40

Rev. 0 | Page 2 of 40

AD9254

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.

Table 1.

AD9254BCPZ-150

Parameter Temperature

Min Typ Max

RESOLUTION Full 14 Bits
ACCURACY

No Missing Codes Full Guaranteed
Offset Error Full ±0.3 ±0.8 % FSR
Gain Error Full ±0.6 ±4.5 % FSR
Differential Nonlinearity (DNL)

1

25°C ±0.4 LSB

Full ±1.0 LSB

Integral Nonlinearity (INL)

1

25°C ±1.5 LSB
Full ±5.0 LSB
TEMPERATURE DRIFT

Offset Error Full ±15 ppm/°C
Gain Error Full ±95 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) Full ±5 ±35 mV
Load Regulation @ 1.0 mA Full 7 mV

INPUT REFERRED NOISE

VREF = 1.0 V 25°C 1.3 LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V Full 2 V p-p
Input Capacitance

2

Full 8 pF
REFERENCE INPUT RESISTANCE Full 6 kΩ
POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 2.5 3.6 V

Supply Current

1

IAVDD

Full 240 260 mA

IDRVDD1(DRVDD = 1.8 V) Full 11 mA
IDRVDD1 (DRVDD = 3.3 V) Full 23 mA

POWER CONSUMPTION

DC Input Full 430 470 mW
Sine Wave Input1 (DRVDD = 1.8 V) Full 450 mW
Sine Wave Input1 (DRVDD = 3.3 V) Full 506 mW
Standby Power
Power-Down Power Full 1.8 mW

1

Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.

3

Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).

3

Full 40 mW

Unit

Rev. 0 | Page 3 of 40

AD9254

AC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.

Table 2.

Parameter

1

Temperature

SIGNAL-TO-NOISE-RATIO (SNR)

fIN = 2.4 MHz 25°C 72.0 dBc
fIN = 70 MHz 25°C 71.8 dBc
Full 70.0 dBc
fIN = 100 MHz 25°C 71.6 dBc
fIN = 170 MHz 25°C 70.8 dBc

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 2.4 MHz 25°C 71.7 dBc
fIN = 70 MHz 25°C 71.0 dBc
Full 69.0 dBc
fIN = 100 MHz 25°C 70.6 dBc
fIN = 170 MHz 25°C

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz

25°C
25°C
25°C
25°C

WORST SECOND OR THIRD HARMONIC

fIN = 2.4 MHz
fIN = 70 MHz

fIN = 100 MHz
fIN = 170 MHz

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.4 MHz
fIN = 70 MHz

fIN = 100 MHz
fIN = 170 MHz

25°C
25°C
Full
25°C
25°C

25°C
25°C
Full
25°C
25°C

WORST OTHER (HARMONIC OR SPUR)

fIN = 2.4 MHz
fIN = 70 MHz

fIN = 100 MHz
fIN = 170 MHz

TWO-TONE SFDR

fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS )
fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS )

ANALOG INPUT BANDWIDTH

1

See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

25°C
25°C
Full
25°C
25°C

25°C
25°C
25°C

AD9254BCPZ-150

Min Typ Max

69.8

11.7

11.7

11.6

11.5

dBc

−90

−84

−74

−83

−80

90
84
74
83
80

−93

−93

−85

−90

−90

90
90
650

Unit

Bits
Bits
Bits
Bits

dBc
dBc
dBc
dBc
dBc

dBc
dBc
dBc
dBc
dBc

dBc
dBc
dBc
dBc
dBc

dBFS
dBFS
MHz

Rev. 0 | Page 4 of 40

AD9254

DIGITAL SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.

Table 3.

AD9254BCPZ-150

Parameter Temperature

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage Full 0.2 6
Input Voltage Range Full AVDD − 0.3 AVDD + 1.6
Input Common-Mode Range Full 1.1 AVDD
High Level Input Voltage (VIH) Full 1.2 3.6 V
Low Level Input Voltage (VIL) Full
High Level Input Current (IIH) Full −10 +10 µA
Low Level Input Current (IIL) Full −10 +10 µA
Input Resistance Full 8 10 12
Input Capacitance Full 4

LOGIC INPUTS (SCLK/DFS, OEB, PWDN)

High Level Input Voltage (VIH) Full 1.2 3.6 V
Low Level Input Voltage (VIL) Full 0 0.8 V
High Level Input Current (IIH) Full
Low Level Input Current (IIL) Full
Input Resistance Full 30 kΩ
Input Capacitance Full 2 pF

LOGIC INPUTS (CSB)

High Level Input Voltage (VIH) Full 1.2 3.6 V
Low Level Input Voltage (VIL) Full 0 0.8 V
High Level Input Current (IIH) Full −10 +10 µA
Low Level Input Current (IIL) Full
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF

LOGIC INPUTS (SDIO/DCS)

High Level Input Voltage (VIH) Full 1.2 DRVDD + 0.3 V
Low Level Input Voltage (VIL) Full 0 0.8 V
High Level Input Current (IIH) Full −10 +10 µA
Low Level Input Current (IIL) Full
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF

DIGITAL OUTPUTS

DRVDD = 3.3 V

High Level Output Voltage (VOH, IOH = 50 µA) Full 3.29 V
High Level Output Voltage (VOH, IOH = 0.5 mA) Full 3.25 V
Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V
Low Level Output Voltage (VOL, IOL = 50 µA) Full 0.05 V

DRVDD = 1.8 V

High Level Output Voltage (VOH, IOH = 50 µA) Full 1.79 V
High Level Output Voltage (VOH, IOH = 0.5 mA) Full 1.75 V
Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V
Low Level Output Voltage (VOL, IOL = 50 µA) Full 0.05 V

CMOS/LVDS/LVPECL
Full 1.2 V

Min Typ Max

0 0.8

−50 −75

−10 +10

+40 +135

+40 +130

Unit

V p-p
V
V

V

kΩ
pF

µA
µA

µA

µA

Rev. 0 | Page 5 of 40

AD9254

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.

Table 4.

Parameter

1

Temperature

Min Typ Max

CLOCK INPUT PARAMETERS

Conversion Rate, DCS Enabled Full 20 150 MSPS
Conversion Rate, DCS Disabled Full 10 150 MSPS
CLK Period Full 6.7 ns
CLK Pulse Width High, DCS Enabled Full 2.0 3.3 4.7 ns
CLK Pulse Width High, DCS Disabled Full 3.0 3.3 3.7 ns

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD)
DCO Propagation Delay (t

2

) Full 4.4 ns

DCO

Full 3.1 3.9 4.8 ns

Setup Time (tS) Full 1.9 2.9 ns
Hold Time (tH) Full 3.0 3.8 ns
Pipeline Delay (Latency) Full 12 Cycles
Aperture Delay (tA) Full 0.8 ns
Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms
Wake-Up Time

3

Full 350 µs
OUT-OF-RANGE RECOVERY TIME Full 3 Cycles
SERIAL PORT INTERFACE

SCLK Period (t

4

) Full 40 ns

CLK

SCLK Pulse Width High Time (tHI) Full 16 ns
SCLK Pulse Width Low Time (tLO) Full 16 ns
SDIO to SCLK Setup Time (tDS) Full 5 ns
SDIO to SCLK Hold Time (tDH) Full 2 ns
CSB to SCLK Setup Time (tS) Full 5 ns
CSB to SCLK Hold Time (tH) Full 2 ns

1

See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

3

Wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 µF capacitor across REFT and REFB.

4

See Figure 50 and the Serial Port Interface (SPI) section.

AD9254BCPZ-150

Unit

TIMING DIAGRAM

CLK+

CLK–

DATA

DCO

N – 13

N+ 2

N+ 1

N

t

A

t

CLK

t

PD

N – 12 N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4

t

S

t

H

N+ 3

t

DCO

N+ 4

N+ 5

N+ 6

t

CLK

N+ 7

Figure 2. Timing Diagram

Rev. 0 | Page 6 of 40

N+ 8

06216-002

AD9254

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

ELECTRICAL

AVDD to AGND −0.3 V to +2.0 V
DRVDD to DGND −0.3 V to +3.9 V
AGND to DGND −0.3 V to +0.3 V
AVDD to DRVDD −3.9 V to +2.0 V
D0 through D13 to DGND −0.3 V to DRVDD + 0.3 V
DCO to DGND −0.3 V to DRVDD + 0.3 V
OR to DGND −0.3 V to DRVDD + 0.3 V
CLK+ to AGND −0.3 V to +3.9 V
CLK− to AGND −0.3 V to +3.9 V
VIN+ to AGND −0.3 V to AVDD + 0.2 V
VIN− to AGND −0.3 V to AVDD + 0.2 V
VREF to AGND −0.3 V to AVDD + 0.2 V
SENSE to AGND −0.3 V to AVDD + 0.2 V
REFT to AGND −0.3 V to AVDD + 0.2 V
REFB to AGND −0.3 V to AVDD + 0.2 V
SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V
PDWN to AGND −0.3 V to +3.9 V
CSB to AGND −0.3 V to +3.9 V
SCLK/DFS to AGND −0.3 V to +3.9 V
OEB to AGND −0.3 V to +3.9 V

ENVIRONMENTAL

Storage Temperature Range –65°C to +125°C
Operating Temperature Range –40°C to +85°C
Lead Temperature

(Soldering 10 Sec)
Junction Temperature 150°C

300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

The exposed paddle must be soldered to the ground plane for
the LFCSP_VQ package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.

Table 6. Thermal Resistance

Package Type θJA θ

48-lead LFCSP_VQ (CP-48-3) 26.4 2.4 °C/W

Unit

JC

Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θ

JA

. In
addition, metal in direct contact with the package leads from
metal traces and through holes, ground, and power planes,
reduces the θ

.

JA

ESD CAUTION

Rev. 0 | Page 7 of 40

AD9254

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DRVDD

DRGNDD1D0 (LSB)

DCO

OEB

AVDD

AGND

AVDD

CLK–

CLK+

4847464544434241403938

AGND

37

AVDD

35
34
33

32
31
30
29

28
27

26
25

PDWN36

RBIAS
CML
AVDD

AGND
VIN–
VIN+
AGND

REFT
REFB

VREF
SENSE

06216-003

DRGND

DRVDD

D10

D11

D2

1

D3

2

D4

3

D5

4

D6

5

D7

6

7

8

D8

9

D9

10
11

12

PIN 1
INDICATO R

AD9254

TOP VIEW

(Not to Scale)

13141516171819

OR

D12

DRVDD

DRGND

D13 (MSB)

SDIO/DCS

2021222324

CSB

AGND

SCLK/DFS

AVDD

AGND

Figure 3. Pin Configuration

Table 7. Pin Function Description

Pin No. Mnemonic Description

0, 21, 23, 29, 32,

AGND Analog Ground. (Pin 0 is the exposed thermal pad on the bottom of the package.)

37, 41
45, 46, 1 to 6,

D0 (LSB) to D13 (MSB) Data Output Bits.

9 to 14
7, 16, 47 DRGND Digital Output Ground.
8, 17, 48 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V).
15 OR Out-of-Range Indicator.
18 SDIO/DCS

Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select
(External Pin Mode). See

Table 10.
19 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
20 CSB Serial Port Interface Chip Select (Active Low). See Tab le 10.
22, 24, 33, 40, 42 AVDD Analog Power Supply.

25 SENSE Reference Mode Selection. See Table 9.
26 VREF Voltage Reference Input/Output.
27 REFB Differential Reference (−).
28 REFT Differential Reference (+).
30 VIN+ Analog Input Pin (+).
31 VIN– Analog Input Pin (−).
34 CML Common-Mode Level Bias Output.
35 RBIAS

External Bias Resistor Connection. A 10 kΩ resistor must be connected between this pin and

analog ground (AGND).
36 PDWN Power-Down Function Select.
38 CLK+ Clock Input (+).
39 CLK– Clock Input (−).
43 OEB Output Enable (Active Low).
44 DCO Data Clock Output.

Rev. 0 | Page 8 of 40

AD9254

V

C

S

S

Ω

V

A

V

EQUIVALENT CIRCUITS

LK+

IN

06216-004

Figure 4. Equivalent Analog Input Circuit

AVDD

1.2V

10kΩ 10kΩ

Figure 5. Equivalent Clock Input Circuit

DRVDD

DIO/DCS

1kΩ

CLK–

CLK/DFS

OEB

PDWN

30kΩ

1kΩ

06216-008

Figure 8. Equivalent SCLK/DFS, OEB, PDWN Input Circuit

AVDD

26kΩ

CSB

06216-005

1kΩ

06216-009

Figure 9. Equivalent CSB Input Circuit

SENSE

1k

06216-010

06216-011

Figure 6. Equivalent SDIO/DCS Input Circuit

DRVDD

DRGND

Figure 7. Equivalent Digital Output Circuit

06216-006

06216-007

Figure 10. Equivalent Sense Circuit

DD

REF

6kΩ

Figure 11. Equivalent VREF Circuit

Rev. 0 | Page 9 of 40

AD9254

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V; DRVDD = 2.5 V; maximum sample rate, DCS enabled, 1 V internal reference; 2 V p-p differential input; AIN = −1.0 dBFS;
64k sample; T

–20

–40

= 25°C, unless otherwise noted.

A

0

150MSPS

2.3MHz @ –1dBFS
SNR = 72.0dBc (73. 0dBFS)
ENOB = 11.7 BITS
SFDR = 90.0dBc

0

150MSPS

100.3MHz @ –1dBF S
SNR = 71.6dBc (72.6dBFS)

–20

ENOB = 11.6 BI TS
SFDR = 83dBc

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

Figure 12. AD9254 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

Figure 13. AD9254 Single-Tone FFT with f

FREQUENCY (MHz )

150MSPS

30.3MHz @ –1dBFS
SNR = 71.9dBc (72. 9dBFS)
ENOB = 11.7 BITS
SFDR = 88d Bc

FREQUENCY (MHz )

= 2.3 MHz

IN

= 30.3 MHz

IN

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

06216-012

Figure 15. AD9254 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

06216-013

Figure 16. AD9254 Single-Tone FFT with f

FREQUENCY (MHz )

150MSPS

140.3MHz @ –1dBF S
SNR = 71.5dBc (72. 5dBFS)
ENOB = 11.5 BI TS
SFDR = 81dBc

FREQUENCY (MHz )

= 100.3 MHz

IN

= 140.3 MHz

IN

06216-015

06216-016

0

150MSPS

70.3MHz @ –1dBF S
SNR = 71.8dBc (72.8dBFS)

–20

ENOB = 11.7 BI TS
SFDR = 84dBc

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

Figure 14. AD9254 Single-Tone FFT with f

FREQUENCY (MHz )

= 70.3 MHz

IN

06216-014

Rev. 0 | Page 10 of 40

0

–20

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

FREQUENCY (MHz )

Figure 17. AD9254 Single-Tone FFT with f

150MSPS

170.3MHz @ –1dBF S
SNR = 70.8dBc (71. 8dBFS)
ENOB = 11.5 BI TS
SFDR = 80dBc

= 170.3 MHz

IN

06216-017

AD9254

0

150MSPS

250.3MHz @ –1dBF S
SNR = 69.3dBc (70. 3dBFS)

–20

ENOB = 11.3 BITS
SFDR = 79dBc

–40

120

100

80

SFDR (dBFS)

SNR (dBFS)

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

Figure 18. AD9254 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

Figure 19. AD9254 Two-Tone FFT with f

90

85

80

FREQUENCY (MHz )

IN

150MSPS

f

= 29.1MHz @ –7d BFS

IN1

f

= 32.1MHz @ –7d BFS

IN2

SFDR = 83.2dBc (90.2dBFS )
WoIMD3 = –83.9dBc (–90. 9dBFS)

FREQUENCY (MHz )

= 29.1 MHz, f

IN1

SFDR –40°C

= 250.3 MHz

SFDR +25°C

= 32.1 MHz

IN2

60

40

SFDR (dBc)

SNR/SFDR (dBc an d dBFS )

20

SNR (dBc)

0

–90 0–20 –10–30–40–50–60–70–80

06216-018

INPUT AMPLI TUDE (dBFS)

85dBc
REFERENCE LINE

06216-021

Figure 21. AD9254 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)

= 2.4 MHz

with f

IN

0

–20

–40

WORST I MD3 (dBc)

–60

–80

–100

SFDR/WORST IMD3 (d Bc and dBFS)

–120

–90 –78 –66 –54 –42 –30 –18 –6

06216-019

SFDR (–dBc)

SFDR (–dBFS)

WORST I MD3 (dBFS)

INPUT AMPLITUDE (dBFS)

06216-022

Figure 22. AD9254 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)

= 29.1 MHz, f

with f

IN1

90

85

80

= 32.1 MHz

IN2

SFDR +25°C

SFDR –40°C

SNR/SFDR (dBc)

75

70

65

60

0435030025020015010050

INPUT FREQUENCY (MHz)

SNR –40°C

SNR +25°C

Figure 20. AD9254 Single-Tone SNR/SFDR vs. Input Frequency (f

Temperature with 2 V p-p Full Scale

75

SFDR +85°C

SNR +85°C

00

06216-020

) and

IN

SNR/SFDR (dBc)

70

65

60

Figure 23. AD9254 Single-Tone SNR/SFDR vs. Input Frequency (f

Rev. 0 | Page 11 of 40

SNR +25°C

0435030025020015010050

INPUT FREQ UENCY (MHz)

Temperature with 1 V p-p Full Scale

SFDR +85°C

SNR –40°C

SNR +85°C

00

06216-023

) and

IN

AD9254

0

–20

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

FREQUENCY (MHz )

Figure 24. AD9254 Two-Tone FFT with f

95

90

85

80

150MSPS

f

= 169.1MHz @ –7dBF S

IN1

f

= 172.1MHz @ –7dBF S

IN2

SFDR = 83dBc (90d BFS)
WoIMD3 = –83d Bc (90dBFS)

= 169.1 MHz, f

IN1

SFDR

= 172.1 MHz

IN2

2.0

1.5

1.0

0.5

0

–0.5

INL ERROR (LSB)

–1.0

–1.5

–2.0

0 163841433612288102408192614440962048

06216-024

Figure 27. AD9254 INL with f

12000

10000

8000

6000

OUTPUT CODE

= 10.3 MHz

IN

32768 SAMPLES

1.25 LSB rms

06216-031

SNR/SFDR (dBc)

75

70

65

10 1501401301201101009080706050403020

CLOCK FREQUE NCY (MSPS)

Figure 25. AD9254 Single-Tone SNR/SFDR vs. Clock Frequency (f

0

–20

–40

WORST I MD3 (dBc)

–60

–80

–100

SFDR/WORST IMD3 (d Bc and dBFS)

–120

–90 –78 –66 –54 –42 –30 –18 –6

SFDR (–dBc)

SFDR (–dBFS)

INPUT AMPLITUDE (dBFS)

= 2.4 MHz

with f

IN

WORST I MD3 (dBFS)

SNR

CLK

Figure 26. AD9254 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)

with f

= 169.1 MHz, f

IN1

= 172.11 MHz

IN2

NUMBER OF HIT S

4000

2000

0

N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5

06216-025

)

ERROR (%FS)

06216-027

Figure 28. AD9254 Grounded Input Histogram

0

–0.5

–1.0

–1.5

–2.0

–2.5

–40–200 20406080

CODE

OFFSET ERROR

GAIN ERROR

TEMPERATURE (° C)

06216-032

06216-033

Figure 29. AD9254 Gain and Offset vs. Temperature

Rev. 0 | Page 12 of 40

AD9254

0.5

0.4

0.3

0.2

0.1

0

–0.1

DNL ERROR (LSB)

–0.2

–0.3

–0.4

–0.5

0 163841433612288102408192614440962048

Figure 30. AD9254 DNL with f

OTUPUT CODE

= 10.3 MHz

IN

06216-034

Rev. 0 | Page 13 of 40

AD9254

THEORY OF OPERATION

The AD9254 architecture consists of a front-end sample-and­hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 14-bit result in the digital correction logic. The pipeline
architecture permits the first stage to operate on a new input
sample, while the remaining stages operate on preceding samples.
Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage consists only of a flash ADC.

The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The output
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9254 is a differential switched
capacitor SHA that has been designed for optimum
performance while processing a differential input signal.

The clock signal alternately switches the SHA between sample
mode and hold mode (see
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within one-half of a clock
cycle. A small resistor in series with each input can help reduce
the peak transient current required from the output stage of the
driving source.

A shunt capacitor can be placed across the inputs to provide
dynamic charging currents. This passive network creates a low­pass filter at the ADC input; therefore, the precise values are
dependent upon the application.

Figure 31). When the SHA is switched

VIN+

VIN–

S

C

PIN, PAR

C

PIN, PAR

S

Figure 31. Switched-Capacitor SHA Input

C

S

H

C

S

For best dynamic performance, the source impedances driving
VIN+ and VIN− should match such that common-mode settling
errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.

An internal differential reference buffer creates two reference
voltages used to define the input span of the ADC core. The
span of the ADC core is set by the buffer to be 2 × VREF. The
reference voltages are not available to the user. Two bypass points,
REFT and REFB, are brought out for decoupling to reduce the
noise contributed by the internal reference buffer. It is recom­mended that REFT be decoupled to REFB by a 0.1 μF capacitor,
as described in the

Layout Considerations section.

Input Common Mode

The analog inputs of the AD9254 are not internally dc-biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device such that V
recommended for optimum performance; however, the device
functions over a wider range with reasonable performance (see
Figure 30). An on-board common-mode voltage reference is
included in the design and is available from the CML pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the CML pin voltage
(typically 0.55 × AVDD). The CML pin must be decoupled to
ground by a 0.1 μF capacitor, as described in the
Considerations

section.

S

C

H

C

H

S

= 0.55 × AVDD is

CM

Layout

06216-035

In IF undersampling applications, any shunt capacitors should
be reduced. In combination with the driving source impedance,
these capacitors would limit the input bandwidth. For more
information, see Application Note
Response of Switched-Capacitor ADCs; Application Note

AN-742, Frequency Domain

AN-827,

A Resonant Approach to Interfacing Amplifiers to Switched­Capacitor ADCs; and the Analog Dialogue article,

“Transformer-

Coupled Front-End for Wideband A/D Converters.”

Rev. 0 | Page 14 of 40

AD9254

A

V

DIFFERENTIAL INPUT CONFIGURATIONS

Optimum performance is achieved by driving the AD9254 in a
differential input configuration. For baseband applications, the

AD8138 differential driver provides excellent performance and a

flexible interface to the ADC. The output common-mode voltage
of the

AD8138 is easily set with the CML pin of the AD9254 (see
Figure 32), and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.

1V p-p

For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration (see
connected to the center tap of the secondary winding of the
transformer to bias the analog input.

The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz, and excessive signal power can cause
core saturation, which leads to distortion.

2V p-p

At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9254. For applications
where SNR is a key parameter, transformer coupling is the
recommended input. For applications where SFDR is a key
parameter, differential double balun coupling is the recom­mended input configuration (see

49.9Ω

0.1µF

499Ω

523Ω

499Ω

AD8138

499Ω

R

C

R

VIN+

AD9254

VIN–

AVDD

Figure 32. Differential Input Configuration Using the AD8138

Figure 33). The CML voltage can be

R

49.9Ω

0.1µF

C

R

Figure 33. Differential Transformer-Coupled Configuration

VIN+

AD9254

VIN–

CML

Figure 35).

CML

06216-036

06216-037

As an alternative to using a transformer-coupled input at
frequencies in the second Nyquist zone, the
driver can be used (see

Figure 36).

AD8352 differential

In any configuration, the value of the shunt capacitor, C,
is dependent on the input frequency and source impedance and
may need to be reduced or removed.

Tabl e 8 displays recom­mended values to set the RC network. However, these values are
dependent on the input signal and should only be used as a
starting guide.

Table 8. RC Network Recommended Values

Frequency Range (MHz) R Series (Ω) C Differential (pF)

0 to 70 33 15
70 to 200 33 5
200 to 300 15 5
>300 15 Open

Single-Ended Input Configuration

Although not recommended, it is possible to operate the
AD9254 in a single-ended input configuration, as long as the
input voltage swing is within the AVDD supply. Single-ended
operation can provide adequate performance in cost-sensitive
applications.

In this configuration, SFDR and distortion performance
degrade due to the large input common-mode swing. If the
source impedances on each input are matched, there should be
little effect on SNR performance.

Figure 34 details a typical

single-ended input configuration.

1V p-p

10µF

49.9Ω

10µF

0.1µF

0.1µF

Figure 34. Single-Ended Input Configuration

AVD D

1kΩ

1kΩ

1kΩ

1kΩ

DD

R

C

R

VIN+

AD9254

VIN–

06216-038

Rev. 0 | Page 15 of 40

AD9254

V

2V p-p

0.1µF

S

SP

A

0.1µF

25Ω

P

0.1µF

25Ω

0.1µF

R

C

R

VIN+

AD9254

VIN–

CML

06216-039

Figure 35. Differential Double Balun Input Configuration

CC

0.1µF

C

D

0.1µF

0Ω

16

1

2

R

R

D

G

3

4

5

0Ω

8, 13

AD8352

14

0.1µF

0.1µF

11

10

0.1µF

0.1µF

200Ω

200Ω

R

R

0.1µF

VIN+

C

AD9254

VIN–

CML

06216-040

Figure 36. Differential Input Configuration Using the AD8352

Table 9. Reference Configuration Summary

Resulting Differential

Selected Mode SENSE Voltage Resulting VREF (V)

Span (V p-p)

External Reference AVDD N/A 2 × external reference
Internal Fixed Reference VREF 0.5 1.0
Programmable Reference 0.2 V to VREF

R

2

⎞

⎛

15.0

+×

(see Figure 38)

⎟

⎜

R

1

⎠

⎝

2 × VREF

Internal Fixed Reference AGND to 0.2 V 1.0 2.0

VOLTAGE REFERENCE

A stable and accurate voltage reference is built into the AD9254.
The input range is adjustable by varying the reference voltage
applied to the AD9254, using either the internal reference or an
externally applied reference voltage. The input span of the ADC
tracks reference voltage changes linearly. The various reference
modes are summarized in the following sections. The
Decoupling

section describes the best practices and require-

ments for PCB layout of the reference.

Internal Reference Connection

A comparator within the AD9254 detects the potential at the

Reference

Connecting the SENSE pin to VREF switches the reference
amplifier input to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected external to the chip, as shown in

Figure 38, the
switch sets to the SENSE pin. This puts the reference amplifier
in a noninverting mode with the VREF output defined as

VREF 15.0

⎛
⎜
⎝

+=

⎟

R1

⎠

R2

⎞

If the SENSE pin is connected to AVDD, the reference amplifier
is disabled, and an external reference voltage can be applied to
the VREF pin (see the

External Reference Operation section).

SENSE pin and configures the reference into four possible
states, as summarized in

Tabl e 9. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see

Figure 37), setting VREF to 1 V.

The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.

Rev. 0 | Page 16 of 40

AD9254

External Reference Operation

The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift
characteristics. Figure 40 shows the typical drift characteristics
of the internal reference in both 1 V and 0.5 V modes.

10

8

6

VREF = 0.5V

VREF = 1V

0.1µF0.1µF

SENSE

VIN+
VIN–

VREF

SELECT

LOGIC

ADC

CORE

––

REFT

0.1µF

REFB

0.5V

AD9254

06216-041

Figure 37. Internal Reference Configuration

VIN+
VIN–

VREF

0.1µF0.1µF

R2

SENSE

R1

SELECT

LOGIC

ADC

CORE

––

REFT

0.1µF

REFB

0.5V

AD9254

06216-042

Figure 38. Programmable Reference Configuration

If the internal reference of the AD9254 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 39 depicts
how the internal reference voltage is affected by loading.

0

VREF = 0.5V

–0.25

VREF = 1V

–0.50

4

2

REFERENCE VOLTAGE ERROR ( mV )

0

–40

–20

0 204060

TEMPERATURE ( °C)

80

06216-044

Figure 40. Typical VREF Drift

When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
resistor divider loads the external reference with an equivalent
6 kΩ load (see Figure 11). In addition, an internal buffer
generates the positive and negative full-scale references for the
ADC core. Therefore, the external reference must be limited to
a maximum of 1 V.

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9254 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ pin and the
CLK− pin via a transformer or capacitors. These pins are biased
internally (see Figure 5) and require no external bias.

Clock Input Options

The AD9254 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal used, the jitter of the clock
source is of the most concern, as described in the Jitter
Considerations section.

–0.75

Figure 41 shows one preferred method for clocking the
AD9254. A low jitter clock source is converted from single­ended to a differential signal using an RF transformer. The

REFERENCE VOLTAGE ERROR (%)

–1.00

back-to-back Schottky diodes across the transformer secondary
limit clock excursions into the AD9254 to approximately 0.8 V p-p

–1.25

02.0

0.5 1.0 1.5
LOAD CURRENT (mA)

06216-043

Figure 39. VREF Accuracy vs. Load

Rev. 0 | Page 17 of 40

differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9254,
while preserving the fast rise and fall times of the signal, which
are critical to a low jitter performance.

AD9254

K

MINI-CIRCUITS

CLOC

INPUT

50Ω

ADT1–1WT, 1:1Z

100Ω

XFMR

0.1µF

0.1µF0.1µF

0.1µF

SCHOTTKY

DIODES:
HMS2812

CLK+

ADC

AD9254

CLK–

Figure 41. Transformer Coupled Differential Clock

If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins as shown in

Figure 42. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515 family of clock drivers offers

excellent jitter performance.

CLOCK

INPUT

CLOCK

INPUT

1

50Ω

1

50Ω RESIST ORS ARE OPTIONAL .

Figure 42. Differential PECL Sample Clock

0.1µF

0.1µF

50Ω

CLK

AD951x

PECL DRIV ER

CLK

1

0.1µF

CLK+

100Ω

0.1µF

240Ω240Ω

ADC

AD9254

CLK–

A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in

Figure 43. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515 family of clock

drivers offers excellent jitter performance.

CLOCK

INPUT

CLOCK

INPUT

50Ω

1

50Ω RESISTO RS ARE OPTIONAL .

0.1µF

0.1µF

1

50Ω

Figure 43. Differential LVDS Sample Clock

CLK

AD951x

LVDS DRIV ER

CLK

1

0.1µF

100Ω

0.1µF

CLK+

ADC

AD9254

CLK–

In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
directly drive CLK+ from a CMOS gate, while bypassing the
CLK− pin to ground using a 0.1 μF capacitor in parallel with a
39 kΩ resistor (see

Figure 44). CLK+ can be directly driven
from a CMOS gate. This input is designed to withstand input
voltages up to 3.6 V, making the selection of the drive logic
voltage very flexible. When driving CLK+ with a 1.8 V CMOS
signal, biasing the CLK− pin with a 0.1 μF capacitor in parallel
with a 39 kΩ resistor (see

Figure 44) is required. The 39 kΩ
resistor is not required when driving CLK+ with a 3.3 V CMOS
signal (see

Figure 45).

CLOCK

INPUT

06216-045

CLOCK

INPUT

1

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may

06216-046

be sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.

The AD9254 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling, or falling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9254. Noise and distortion performance are nearly flat
for a wide range of duty cycles when the DCS is on, as shown in
Figure 28.

Jitter in the rising edge of the input is still of paramount concern
and is not reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than

06216-047

20 MHz nominally. The loop has a time constant associated
with it that needs to be considered in applications where the
clock rate can change dynamically. This requires a wait time
of 1.5 μs to 5 μs after a dynamic clock frequency increase (or
decrease) before the DCS loop is relocked to the input signal.
During the time period the loop is not locked, the DCS loop is
bypassed, and the internal device timing is dependent on the
duty cycle of the input clock signal. In such an application, it
may be appropriate to disable the duty cycle stabilizer. In all
other applications, enabling the DCS circuit is recommended
to maximize ac performance.

VCC

0.1µF

1kΩ

AD951x

1kΩ

CMOS DRIVER

1

50Ω

1

50Ω RESISTOR IS OPTIONAL.

0.1µF

OPTIONAL

100Ω

39kΩ

Figure 44. Single-Ended 1.8 V CMOS Sample Clock

VCC

0.1µF

1kΩ

AD951x

1kΩ

CMOS DRIVER

1

50Ω

50Ω RESISTOR I S OPTI ONAL.

OPTIONAL

100Ω

Figure 45. Single-Ended 3.3 V CMOS Sample Clock

0.1µF

0.1µF

0.1µF

CLK+

ADC

AD9254

CLK–

CLK+

ADC

AD9254

CLK–

06216-048

06216-049

Rev. 0 | Page 18 of 40

AD9254

The DCS can be enabled or disabled by setting the SDIO/DCS
pin when operating in the external pin mode (see Table 10), or
via the SPI, as described in Table 13.

Table 10. Mode Selection (External Pin Mode)

Voltage at Pin SCLK/DFS SDIO/DCS

AGND Binary (default) DCS disabled
AVDD Twos complement

DCS enabled
(default)

JITTER CONSIDERATIONS

High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (f

SNR = −20 log (2π × f

In the equation, the rms aperture jitter represents the root mean
square of all jitter sources, which include the clock input, analog
input signal, and ADC aperture jitter specification. IF under­sampling applications are particularly sensitive to jitter, as
shown in Figure 46.

SNR (dBc)

Treat the clock input as an analog signal in cases where aperture
jitter can affect the dynamic range of the AD9254. Power supplies
for clock drivers should be separated from the ADC output
driver supplies to avoid modulating the clock signal with digital
noise. The power supplies should also not be shared with analog
input circuits, such as buffers, to avoid the clock modulating onto
the input signal or vice versa. Low jitter, crystal-controlled oscil­lators make the best clock sources. If the clock is generated from
another type of source (by gating, dividing, or other methods),
it should be retimed by the original clock at the last step.

Refer to Application Notes AN-501, Aperture Uncertainty and

ADC System Performance; and AN-756, Sampled Systems and
the Effects of Clock Phase Noise and Jitter, for more in-depth

information about jitter performance as it relates to ADCs.

) due to jitter (tJ) is calculated as follows:

IN

× tJ)

IN

75

70

MEASURED

PERFORMANCE

65

60

55

50

45

40

1 10 100 1000

Figure 46. SNR vs. Input Frequency and Jitter

INPUT FREQ UE NCY ( MHz )

0.05ps

0.20ps

0.5ps

1.0ps

1.50ps

2.00ps

2.50ps

3.00ps

06216-050

POWER DISSIPATION AND STANDBY MODE

The power dissipated by the AD9254 is proportional to its sample
rate (see Figure 47). The digital power dissipation is determined
primarily by the strength of the digital drivers and the load on each
output bit. Maximum DRVDD current (I

f

LOAD

CLK

2

CVI

DRVDDDRVDD

where N is the number of output bits, 14 in the AD9254.

This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency, f

/2. In practice, the DRVDD current is

CLK

established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal. Reducing the capacitive load
presented to the output drivers can minimize digital power
consumption. The data in Figure 47 was taken under the same
operating conditions as the data for the Typical Performance
Characteristics section, with a 5 pF load on each output driver.

500

480

460

440

420

400

380

POWER (mW)

360

340

320

300

0 102030405060708090100110120130140150

Figure 47. AD9254 Power and Current vs. Clock Frequency f

I (AVDD)

POWER

I (DRVDD)

CLOCK FREQUE NCY (MHz)

Power-Down Mode

By asserting the PDWN pin high, the AD9254 is placed in power­down mode. In this state, the ADC typically dissipates 1.8 mW.
During power-down, the output drivers are placed in a high
impedance state. Reasserting the PDWN pin low returns the
AD9254 to its normal operational mode. This pin is both 1.8 V
and 3.3 V tolerant.

Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and then must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in power-down mode;
and shorter power-down cycles result in proportionally shorter
wake-up times. With the recommended 0.1 μF decoupling capaci­tors on REFT and REFB, it takes approximately 0.25 ms to fully
discharge the reference buffer decoupling capacitors and 0.35 ms to
restore full operation.

) can be calculated as

DRVDD

N

×××=

300

250

200

150

100

50

0

= 30 MHz

IN

CURRENT (mA)

06216-051

Rev. 0 | Page 19 of 40

AD9254

Standby Mode

When using the SPI port interface, the user can place the ADC
in power-down or standby modes. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required (see the Memory Map section).

DIGITAL OUTPUTS

The AD9254 output drivers can be configured to interface with

1.8 V to 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.

The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when operat­ing in the external pin mode (see Table 10). As detailed in the

Interfacing to High Speed ADCs via SPI user manual, the data

format can be selected for either offset binary, twos complement,
or Gray code when using the SPI control.

Out-of-Range (OR) Condition

An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR is a digital output
that is updated along with the data output corresponding to the
particular sampled input voltage. Thus, OR has the same
pipeline latency as the digital data.

OR DATA OUTPUTS

1

11

1111

1111

0

11

1111

1111

0

11

1111

1111

0
0
1

0000

00

0000

0000

00

0000

0000

00

0000

Figure 48. OR Relation to Input Voltage and Output Data

1111
1111
1110

0001
0000
0000

OR

–FS + 1/2 LSB

–FS – 1/2 L SB

OR is low when the analog input voltage is within the analog
input range and high when the analog input voltage exceeds the
input range, as shown in Figure 48. OR remains high until the
analog input returns to within the input range and another
conversion is completed.

+FS – 1 LSB

+FS–FS

+FS – 1/2 LS B

06216-052

By logically AND’ing the OR bit with the MSB and its complement,
overrange high or underrange low conditions can be detected.
Table 11 is a truth table for the overrange/underrange circuit in
Figure 49, which uses NAND gates.

MSB

OR

MSB

Figure 49. Overrange/Underrange Logic

OVER = 1

UNDER = 1

06216-053

Table 11. Overrange/Underrange Truth Table

OR MSB Analog Input Is:

0 0 Within range
0 1 Within range
1 0 Underrange
1 1 Overrange

Digital Output Enable Function (OEB)

The AD9254 has three-state ability. If the OEB pin is low, the
output data drivers are enabled. If the OEB pin is high, the
output data drivers are placed in a high impedance state. This is
not intended for rapid access to the data bus. Note that OEB is
referenced to the digital supplies (DRVDD) and should not
exceed that supply voltage.

TIMING

The lowest typical conversion rate of the AD9254 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.

The AD9254 provides latched data outputs with a pipeline delay
of twelve clock cycles. Data outputs are available one propaga­tion delay (t

The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9254. These transients can degrade the dynamic performance
of the converter.

Data Clock Output (DCO)

The AD9254 also provides data clock output (DCO) intended for
capturing the data in an external register. The data outputs are valid
on the rising edge of DCO, unless the DCO clock polarity has been
changed via the SPI. See Figure 2 for a graphical timing
description.

) after the rising edge of the clock signal.

PD

Table 12. Output Data Format

Gray Code Mode

Input (V) Condition (V) Binary Output Mode Twos Complement Mode

(SPI Accessible)

OR

VIN+ – VIN– < –VREF – 0.5 LSB 00 0000 0000 0000 10 0000 0000 0000 11 0000 0000 0000 1
VIN+ – VIN– = –VREF 00 0000 0000 0000 10 0000 0000 0000 11 0000 0000 0000 0
VIN+ – VIN– = 0 10 0000 0000 0000 00 0000 0000 0000 00 0000 0000 0000 0
VIN+ – VIN– = +VREF – 1.0 LSB 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000 0
VIN+ – VIN– > +VREF – 0.5 LSB 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000 1

Rev. 0 | Page 20 of 40

AD9254

SERIAL PORT INTERFACE (SPI)

The AD9254 serial port interface (SPI) allows the user to
configure the converter for specific functions or operations
through a structured register space provided inside the ADC.
This provides the user added flexibility and customization
depending on the application. Addresses are accessed via the
serial port and may be written to or read from via the port.
Memory is organized into bytes that are further divided into
fields, as documented in the Memory Map section. For detailed
operational information, see the Interfacing to High Speed ADCs

via SPI user manual.

CONFIGURATION USING THE SPI

As summarized in Table 13, three pins define the SPI of this
ADC. The SCLK/DFS pin synchronizes the read and write data
presented to the ADC. The SDIO/DCS dual-purpose pin allows
data to be sent to and read from the internal ADC memory map
registers. The CSB pin is an active low control that enables or
disables the read and write cycles.

Table 13. Serial Port Interface Pins

Pin Name Function

SCLK/DFS

SDIO/DCS

CSB

The falling edge of the CSB in conjunction with the rising edge
of the SCLK determines the start of the framing. Figure 50 and
Table 14 provide examples of the serial timing and its definitions.

Other modes involving the CSB are available. The CSB can be
held low indefinitely to permanently enable the device (this is
called streaming). The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in a high impedance mode. This mode
turns on any SPI pin secondary functions.

During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase and the length is determined
by the W0 bit and the W1 bit. All data is composed of 8-bit
words. The first bit of each individual byte of serial data
indicates whether a read or write command is issued. This
allows the serial data input/output (SDIO) pin to change
direction from an input to an output.

SCLK (serial clock) is the serial shift clock in. SCLK
synchronizes serial interface reads and writes.
SDIO (serial data input/output) is a dual-purpose
pin. The typical role for this pin is an input and
output, depending on the instruction being sent
and the relative position in the timing frame.
CSB (chip select bar) is an active-low control that
gates the read and write cycles.

In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip as well as read the
contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data
input/output (SDIO) pin to change direction from an input to
an output at the appropriate point in the serial frame.

Data can be sent in MSB- or in LSB-first mode. MSB first is the
default on power-up and can be changed via the configuration
register. For more information, see the Interfacing to High Speed

ADCs via SPI user manual.

Table 14. SPI Timing Diagram Specifications

Name Description

tDS Setup time between data and rising edge of SCLK
tDH Hold time between data and rising edge of SCLK
t

Period of the clock

CLK

tS Setup time between CSB and SCLK
tH Hold time between CSB and SCLK
tHI

tLO

Minimum period that SCLK should be in a logic
high state

Minimum period that SCLK should be in a logic
low state

HARDWARE INTERFACE

The pins described in Table 13 comprise the physical interface
between the user’s programming device and the serial port of
the AD9254. The SCLK and CSB pins function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.

The SPI interface is flexible enough to be controlled by either
PROM or PIC microcontrollers. This provides the user with the
ability to use an alternate method to program the ADC. One
method is described in detail in Application Note AN-812,
Microcontroller-Based Serial Port Interface Boot Circuit.

When the SPI interface is not used, some pins serve a dual
function. When strapped to AVDD or ground during device
power on, the pins are associated with a specific function.

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers,
the SDIO/DCS and SCLK/DFS pins serve as stand-alone
CMOS-compatible control pins. When the device is powered
up, it is assumed that the user intends to use the pins as static
control lines for the output data format and duty cycle stabilizer
(see Table 10). In this mode, the CSB chip select should be
connected to AVDD, which disables the serial port interface.
For more information, see the Interfacing to High Speed ADCs

via SPI user manual.

Rev. 0 | Page 21 of 40

AD9254

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight address
locations. The memory map is roughly divided into three
sections: the chip configuration registers map (Address 0x00 to
Address 0x02), the device index and transfer registers map
(Address 0xFF), and the ADC functions map (Address 0x08 to
Address 0x18).

Table 15 displays the register address number in hexadecimal in
the first column. The last column displays the default value for
each hexadecimal address. The Bit 7 (MSB) column is the start
of the default hexadecimal value given. For example,
Hexadecimal Address 0x14, output_phase, has a hexadecimal
default value of 0x00. This means Bit 3 = 0, Bit 2 = 0, Bit 1 = 1,
and Bit 0 = 1 or 0011 in binary. This setting is the default output
clock or DCO phase adjust option. The default value adjusts the
DCO phase 90° relative to the nominal DCO edge and 180°
relative to the data edge. For more information on this function,
consult the Interfacing to High Speed ADCs via SPI user manual.

Open Locations

Locations marked as open are currently not supported for this
device. When required, these locations should be written with
0s. Writing to these locations is required only when part of an
address location is open (for example, Address 0x14). If the
entire address location is open (Address 0x13), then the address
location does not need to be written.

Default Values

Coming out of reset, critical registers are loaded with default
values. The default values for the registers are shown in
Table 15.

Logic Levels

An explanation of two registers follows:

• “Bit is set” is synonymous with “Bit is set to Logic 1” or

“Writing Logic 1 for the bit.”

• “Clear a bit” is synonymous with “Bit is set to Logic 0” or

“Writing Logic 0 for the bit.”

SPI-Accessible Features

A list of features accessible via the SPI and a brief description of
what the user can do with these features follows. These features
are described in detail in the Interfacing to High Speed ADCs via

SPI user manual.

• Modes: Set either power-down or standby mode.

• Clock: Access the DCS via the SPI.

• Offset: Digitally adjust the converter offset.

• Te st I /O : Set test modes to have known data on output bits.

• Output Mode: Setup outputs, vary the strength of the

output drivers.

• Output Phase: Set the output clock polarity.

CSB

SCLK

SDIO

DON’T CARE

t

DS

t

S

R/W W1 W0 A12 A11 A10 A9 A8 A7

t

DH

t

HI

Figure 50. Serial Port Interface Timing Diagram

t

CLK

t

LO

• VREF: Set the reference voltage.

D5 D4 D3 D2 D1 D0

t

H

DON’T CARE

DON’T CAREDON’T CARE

06216-054

Rev. 0 | Page 22 of 40

AD9254

MEMORY MAP REGISTER TABLE

Table 15. Memory Map Register

Default
Addr.
(Hex)

Chip Configuration Registers

00 chip_port_config 0 LSB first

01 chip_id 8-bit Chip ID Bits 7:0

02 chip_grade Open Open Open Open Child ID

Device Index and Transfer Registers

FF device_update Open Open Open Open Open Open Open SW

Global ADC Functions

08 modes Open Open PDWN

09 clock Open Open Open Open Open Open Open Duty

Parameter Name

Bit 7
(MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

0 = Off
(Default)

1 = On

Soft
reset

0 = Off
(Default)

1 = On

0—Full
1—

Standby

1 1 Soft

reset
0 = Off

(Default)
1 = On

(AD9254 = 0x00), (default)

Open Open Open Read
0 = 150
MSPS

Open Open Internal power-down mode

000—normal (power-up)

001—full power-down

010—standby

011—normal (power-up)

Note: External PDWN pin

overrides this setting.

LSB first
0 = Off

(Default)
1 = On

Bit 0
(LSB)

0 0x18 The nibbles

transfer

cycle
stabilizer
0—
disabled
1—
enabled

Value
(Hex)

Read
only

only

0x00 Synchronously

0x00 Determines

Default Notes/
Comments

should be
mirrored. See
the

Interfacing to
High Speed ADCs
via SPI

user

manual.
Default is unique

chip ID, different
for each device.

Child ID used to
differentiate
speed grades.

transfers data
from the master
shift register to
the slave.

various generic
modes of chip
operation. See
the

Power
Dissipation and
Standby Mode

SPI-

and the

Accessible

0x01

Features

sections.

See the

Duty Cycle

section and the

Clock

SPI-Accessible
Features

section.

Rev. 0 | Page 23 of 40

AD9254

Addr.
(Hex)

Flexible ADC Functions

10 offset

0D test_io PN23

14 output_mode Output Driver

16 output_phase Output Clock

18 VREF Internal Reference

1

Parameter Name

External output enable (OEB) pin must be high.

Bit 7
(MSB)

Configuration
00 for DRVDD = 2.5 V to

3.3 V
10 for DRVDD = 1.8 V

Polarity
1 = inverted
0 = normal
(Default)

Resistor Divider
00—VREF = 1.25 V

01—VREF = 1.5 V
10—VREF = 1.75 V
11—VREF = 2.00 V
(Default)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Open Open Open Open Open Open Open 0x00

Digital Offset Adjust<5:0>
011111
011110
011101
…
000010
000001
000000
111111
111110
111101
...
100001
100000

0 = normal
(Default)
1 = reset

Open Output

Open Open Open Open Open Open 0xC0

PN9
0 = normal
(Default)
1 = reset

Disable
1—
disabled
0—

1

enabled

Bit 0
(LSB)

Offset in LSBs

+31
+30
+29

+2
+1
0 (Default)
1

−2

−3

−31

−32

Global Output Test Options

Open Output

000—off
001—midscale short

010—+FS short
011—−FS short

100—checker board output
101—PN 23 sequence
110—PN 9
111—one/zero word toggle

Data Format Select
Data
Invert
1 =
invert

00—offset binary

(default)

01—twos

complement

10—Gray Code

0x00 Adjustable for

Default
Value
(Hex)

0x00 See the

0x00 Configures the

Default
Notes/
Comments

offset inherent
in the
converter. See

SPI­Accessible
Features

section.

Interfacing to
High Speed
ADCs via SPI

user manual.

outputs and
the format of
the data.

See the

SPI­Accessible
Features

section.

See the

SPI­Accessible
Features

section.

Rev. 0 | Page 24 of 40

AD9254

LAYOUT CONSIDERATIONS

POWER AND GROUND RECOMMENDATIONS

When connecting power to the AD9254, it is recommended
that two separate supplies be used: one for analog (AVDD, 1.8 V
nominal) and one for digital (DRVDD, 1.8 V to 3.3 V nominal).
If only a single 1.8 V supply is available, it is routed to AVDD
first, then tapped off and isolated with a ferrite bead or filter
choke with decoupling capacitors proceeding connection to
DRVDD. The user can employ several different decoupling
capacitors to cover both high and low frequencies. These should
be located close to the point of entry at the PC board level and
close to the parts with minimal trace length.

A single PC board ground plane is sufficient when using the
AD9254. With proper decoupling and smart partitioning of
analog, digital, and clock sections of the PC board, optimum
performance is easily achieved.

Exposed Paddle Thermal Heat Slug Recommendations

It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9254. An
exposed, continuous copper plane on the PCB should mate to
the AD9254 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.

To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous plane by overlaying a silkscreen
on the PCB into several uniform sections. This provides several
tie points between the two during the reflow process. Using one
continuous plane with no partitions guarantees only one tie point
between the ADC and PCB. See
example. For detailed information on packaging and the PCB
layout of chip scale packages, see

A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package.

Figure 51 for a PCB layout

Application Note AN-772,

CML

The CML pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in

RBIAS

The AD9254 requires the user to place a 10 kΩ resistor between
the RBIAS pin and ground. This resister sets the master current
reference of the ADC core and should have at least a 1% tolerance.

REFERENCE DECOUPLING

The VREF pin should be externally decoupled to ground with a
low ESR 1.0 μF capacitor in parallel with a 0.1 μF ceramic low
ESR capacitor. In all reference configurations, REFT and REFB
are bypass points provided for reducing the noise contributed
by the internal reference buffer. It is recommended that an
external 0.1 μF ceramic capacitor be placed across REFT/REFB.
While placement of this 0.1 μF capacitor is not required, the SNR
performance degrades by approximately 0.1 dB without it. All
reference decoupling capacitors should be placed as close to the
ADC as possible with minimal trace lengths.

SILKSCREEN PARTITION

PIN 1 INDICATOR

Figure 51. Typical PCB Layout

Figure 33.

06216-055

Rev. 0 | Page 25 of 40

AD9254

EVALUATION BOARD

The AD9254 evaluation board provides all of the support circuitry
required to operate the ADC in its various modes and configu­rations. The converter can be driven differentially through a double
balun configuration (default) or through the

AD8352 differential

driver. The ADC can also be driven in a single-ended fashion.
Separate power pins are provided to isolate the DUT from the
AD8352 drive circuitry. Each input configuration can be selected
by proper connection of various components (see

Figure 53 to
Figure 63). Figure 52 shows the typical bench characterization
setup used to evaluate the ac performance of the AD9254.

It is critical that the signal sources used for the analog input and
clock have very low phase noise (<1 ps rms jitter) to realize the
optimum performance of the converter. Proper filtering of the
analog input signal to remove harmonics and lower the integrated
or broadband noise at the input is also necessary to achieve the
specified noise performance.

Figure 53 to Figure 57 for the complete schematics and

See
layout diagrams that demonstrate the routing and grounding
techniques that should be applied at the system level.

POWER SUPPLIES

This evaluation board comes with a wall-mountable switching
power supply that provides a 6 V, 2 A maximum output.
Connect the supply to the rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter
jack that connects to the PCB at P500. Once on the PC board,
the 6 V supply is fused and conditioned before connecting to
five low dropout linear regulators that supply the proper bias to
each of the various sections on the board.

When operating the evaluation board in a nondefault condition,
L501, L503, L504, L508, and L509 can be removed to disconnect
the switching power supply. This enables the user to individually
bias each section of the board. Use P501 to connect a different
supply for each section. At least one 1.8 V supply is needed with
a 1 A current capability for AVDD_DUT and DRVDD_DUT;
however, it is recommended that separate supplies be used for
analog and digital. To operate the evaluation board using the
AD8352 option, a separate 5.0 V supply (AMP_VDD) with a
1 A current capability is needed. To operate the evaluation
board using the alternate SPI options, a separate 3.3 V analog
supply is needed, in addition to the other supplies. The 3.3 V
supply (AVDD_3.3V) should have a 1 A current capability as
well. Solder Jumpers J501, J502, and J505 allow the user to
combine these supplies (see

Figure 57 for more details).

INPUT SIGNALS

When connecting the clock and analog source, use clean signal
generators with low phase noise, such as Rohde & Schwarz SMHU
or Agilent HP8644 signal generators or the equivalent. Use one
meter long, shielded, RG-58, 50 Ω coaxial cable for making
connections to the evaluation board. Enter the desired frequency
and amplitude for the ADC. Typically, most evaluation boards
from Analog Devices, Inc. can accept a ~2.8 V p-p or 13 dBm
sine wave input for the clock. When connecting the analog
input source, it is recommended to use a multipole, narrow­band, band-pass filter with 50 Ω terminations. Analog Devices
uses TTE®, Allen Avionics, and K&L® types of band-pass filters.
Connect the filter directly to the evaluation board, if possible.

OUTPUT SIGNALS

The parallel CMOS outputs interface directly with the Analog
Devices standard single-channel FIFO data capture board
(HSC-ADC-EVALB-SC). For more information on the FIFO
boards and their optional settings, visit

www.analog.com/FIFO.

WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz

6V DC

SWITCHING

ROHDE & SCHWARZ,

SMHU,
2V p-p SIGNAL
SYNTHESIZ ER

ROHDE & SCHWARZ,

SMHU,
2V p-p SIGNAL
SYNTHESIZER

POWER
SUPPLY

2A MAX

BAND-PASS

FILTER

AIN

CLK

5.0V

–+

GND

AMP_VDD

1.8V

GND

2.5V

–+–+

GND

AVDD_DUT

AD9254

EVALUATION BOARD

–+

DRVDD_DUT

3.3V

GND

–+

VDL

PARALLEL

3.3V

GND

AVD D_3. 3V

14-BIT

CMOS

SPI SPISPI

3.3V

–+

VCC

GND

HSC-ADC-EVALB-SC

FIFO DATA

CAPTURE

BOARD

USB

CONNECTION

PC

RUNNING

ADC

ANALYZER

AND SPI

USER

SOFTWARE

06216-056

Figure 52. Evaluation Board Connection

Rev. 0 | Page 26 of 40

AD9254

DEFAULT OPERATION AND JUMPER SELECTION SETTINGS

The following is a list of the default and optional settings or
modes allowed on the AD9254 Rev. A evaluation board.

POWER

Connect the switching power supply that is supplied in the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P500.

VIN

The evaluation board is set up for a double balun configuration
analog input with optimum 50 Ω impedance matching out to
70 MHz. For more bandwidth response, the differential capacitor
across the analog inputs can be changed or removed (see Table 8).
The common mode of the analog inputs is developed from the
center tap of the transformer via the CML pin of the ADC (see
the Analog Input Considerations section).

VREF

VREF is set to 1.0 V by tying the SENSE pin to ground via
JP507 (Pin 1 and Pin 2). This causes the ADC to operate in

2.0 V p-p full-scale range. A separate external reference option
is also included on the evaluation board. Connect JP507
between Pin 2 and Pin 3, connect JP501, and provide an external
reference at E500. Proper use of the VREF options is detailed
in the Voltage Reference section.

RBIAS

RBIAS requires a 10 kΩ resistor (R503) to ground and is used to
set the ADC core bias current.

CLOCK

The default clock input circuitry is derived from a simple
transformer-coupled circuit using a high bandwidth 1:1
impedance ratio transformer (T503) that adds a very low amount
of jitter to the clock path. The clock input is 50 Ω terminated
and ac-coupled to handle single-ended sine wave inputs. The
transformer converts the single-ended input to a differential
signal that is clipped before entering the ADC clock inputs.

SCLK/DFS

If the SPI port is in external pin mode, the SCLK/DFS pin sets the
data format of the outputs. If the pin is left floating, the pin is
internally pulled down, setting the default condition to binary.
Connecting JP2 Pin 2 and Pin 3 sets the format to twos comple­ment. If the SPI port is in serial pin mode, connecting JP2 Pin 1
and Pin 2 connects the SCLK pin to the on-board SPI circuitry
(see the Serial Port Interface (SPI) section).

SDIO/DCS

If the SPI port is in external pin mode, the SDIO/DCS pin acts
to set the duty cycle stabilizer. If the pin is left floating, the pin is
internally pulled up, setting the default condition to DCS enabled.
To disable the DCS, connect JP3 Pin 2 and Pin 3. If the SPI port
is in serial pin mode, connecting JP3 Pin 1 and Pin 2 connects the
SDIO pin to the on-board SPI circuitry (see the Serial Port
Interface (SPI) section).

ALTERNATIVE CLOCK CONFIGURATIONS

A differential LVPECL clock can also be used to clock the ADC
input using the AD9515 (U500). When using this drive option,
the components listed in Table 16 need to be populated. Consult
the AD9515 data sheet for further information.

To configure the analog input to drive the AD9515 instead of
the default transformer option, the following components need
to be added, removed, and/or changed.

1. Remove R507, R508, C532, and C533 in the default clock

path.

2. Populate R505 with a 0 Ω resistor and C531 in the default

clock path.

3. Populate R511, R512, R513, R515 to R524, U500, R580,

R582, R583, R584, C536, C537, and R586.

If using an oscillator, two oscillator footprint options are also
available (OSC500) to check the performance of the ADC.
JP508 provides the user flexibility in using the enable pin, which
is common on most oscillators. Populate OSC500, R575, R587,
and R588 to use this option.

PDWN

To enable the power-down feature, connect JP506, shorting the
PDWN pin to AVDD.

CSB

The CSB pin is internally pulled-up, setting the chip into
external pin mode, to ignore the SDIO and SCLK information.
To connect the control of the CSB pin to the SPI circuitry on the
evaluation board, connect JP1 Pin 1 and Pin 2. To set the chip
into serial pin mode, and enable the SPI information on the
SDIO and SCLK pins, tie JP1 low (connect Pin 2 and Pin 3) in
the always enabled mode.

Rev. 0 | Page 27 of 40

ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION

This section provides a brief description of the alternative
analog input drive configuration using the AD8352. When
using this particular drive option, some components need to be
populated, as listed in Table 16. For more details on the AD8352
differential driver, including how it works and its optional pin
settings, consult the AD8352 data sheet.

AD9254

To configure the analog input to drive the AD8352 instead of
the default transformer option, the following components need
to be added, removed, and/or changed:

1. Remove C1 and C2 in the default analog input path.

2. Populate R3 and R4 with 200 Ω resistors in the analog

input path.

3. Populate the optional amplifier input path with all

components except R594, R595, and C502.

Note that to terminate the input path, only one of the
following components should be populated: R9, R592, or
the combination of R590 and R591).

4. Populate C529 with a 5 pF capacitor in the analog input

path.

Currently, R561 and R562 are populated with 0 Ω resistors to
allow signal connection. This area allows the user to design a
filter if additional requirements are necessary.

Rev. 0 | Page 28 of 40

AD9254

SCHEMATICS

2

DUTAVDD

D501

DNI

1

3

HSMS2812

2

DUTAVDD

D500

DNI

1

3

HSMS2812

DNI

.1UF

C502

DNI

R595

10K

AMPVDD

31

disable

R594

10K

DNI

J500

OPTIONAL AMP INPUT

AMPVDD

AMPOUT+

.1UF

C504

DNI

DNI

RC0402

0R535

11

12

GND

VOP

VCC

13

VCM

15

ENB

2

16 14

VIP

enable

0

R593

C500

.1UF

DNI

RDP

2

DNI

AMPOUT-

C505

DNI

.1UF

DNI

RC0402

R536 0

9

10

GND

VON

8

VCC

GND

67

5

VIN

AMPVDD

0

DNI

R596

.1UF

DNI

C503

AD8352

DNI

U511

SIGNAL=GND;17

RGN

RDN

RGP

413

R598

100

0.3PF

C501

DNI DNI DNI

4.3K

R597

R592

DNI

CC0402

C529

DNI

DNI

CML

RC0402

DNI

20PF

RC0402RC0402

213

VIN-

VIN-

RC0402

33

R567

RC0402

0

R562

.1UF

C510

25

R4

VIN+

AMPOUT-

C2

.1UF

4

When using R1, remove R3, R4,R6.

Replace C1, C2 w ith 0 oh m resistors.

ETC1-1-13

Replace R5 wi th 0.1UF cap

0

R5

RC0402

VIN+

R563

RC0402

RC0402

R566

33

R574

RC0402

RC0402

R561

0

0

R571

25

R3

AMPOUT+

RC0402

R565

C1

.1UF

5

T501

SP

DOUBLE BALUN / XFMR INPUT

1234

SP

T500

5

0

R2

CC0402

0.1UF

C528

RC0603

R560

0

12

GND;3,4,5

SMAEDGE

S500

Ain

DNI

R1

RC0402

CML

6

DNI

T502

ETC1-1-13

RC0402

DNI

50

R502

1

34

25

C509

.1UF

R6

DNI

RC0402

CML

CC0402

DNI

C3

RC0603

R7

DNI

12

RC0603

GND;3,4 ,5

SMAEDGE

S503

Ain/

Remove R3, R4. Pl ace R6, R502,.

When usi ng T502, remove T 500, T501.

Repalce C1, C2 w ith 0 oh m resistors.

R8

DNI

RC0603

C4

R10

S504

DNI

CC0402

0

21

RC0603

DNI

0

SMA200UP

Ampin

Figure 53. Evaluation Board Schematic, DUT Analog Inputs

R590

25

25

R591

DNI

DNI

2

1

SP

T1

DNI

5

43

0

C5

R12

DNI

CC0402

RC0603

DNI

0

R590/R591,R9,R592 On ly one should be installed at a time.

Install all optional Amp input components.

Remove C1, C2.

Set R3=R4=200 OHM.

For ampli fier (AD8352):

12

DNI

R11

DNI

R9

RC0603

GND;3,4 ,5

DNI

SMA200UP

S505

0

RC060 3

GND;3,4 ,5

DNI

Ampin/

06216-057

Rev. 0 | Page 29 of 40

AD9254

C1C2C3C4C5C6C7C8C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

J503

JP3

2

13

SDIO_ODM

DUTAVDD

JP2

2

13

SCLK_DTP

JP1

2

13

CSB_DUT

SDI_CHAFIFOCLK

B1B2B3B4B5B6B7B8B9

A1A2A3A4A5A6A7A8A9

FD13

FD13

FDOR

22

23

24

O14

O15

OE4

74VCX16224

I14

I15

OE3

25

27

26

VDL

611

710

22RP502

22RP502

D13

DOR

FD12

21

GND4

U509

GND5

28

SDO_CHA

CSB1_CHA

FD11

FD12

O13

I13

22RP502

D12

SCLK_CHA

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

J503

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

J503

OUTPUT CONNECTOR

FD8

FD9

FD10

FD10

FD11

18

19

20

O11

O12

VCC2

I11

VCC3

I12

31

30

29

314

413

512

22RP502

22RP502

D11

D10

FD4

FD5

FD6

FD7

FD7

FD8

FD9

14

15

16

17

O8

O9

O10

GND3

I8

I9

GND6

I10

35

34

33

32

116

215

22RP501

22RP502

22RP502

D8D7D6D5D4D3D2

D9

FD0

FD1

FD2

FD3

FD6

13

O7

36

512

611

22RP501

FDOR

FIFOCLK

FD0

FD1

FD2

FD3

FD4

FD5

VCC1

VCC4I4I5

42

22RP501

O2

O3

I2

I3

44

43

45

116

RP5002236RP5002227RP50022

D1

45678

GND1

GND8

123

O0

O1

OE1

I0

I1

OE2

OUTPUT BUFFER

48

47

46

45

D0

DCO

9

10

11

12

O4

O5

O6

GND2

GND7I6I7

41

40

39

38

37

215

314

413

22RP501

22RP501

22RP501

DUTAVDD

2425

AVDDSENSE

SENSE

DUT

710

22RP501

TP502

D2

D3

1

2

D2

D3

DRGND

DRVDD

DUTDRVDD

RP50122

98

AD9246LFCSP

ESNESFERV_TXE

13

2

JP507

JP500

DUTAVDD

JP501

E500

RP50222

98

TP501

TP503

DUTDRVDD

17

18

19

20

21

23

22

CSB

AVDD

AGND

AGND

SCLK/DFS

DRVDD

SDIO/DCS

DOR

16

15

OR

DRGND

D12

D13

13

14

D12

D13 (MSB)

chip corn ers

VIN-

CML

AGND

AVDD

AGND

VREF

REFB

VIN+

REFT

26

27

VREF

31

29

30

28

0.1UF

C554

VIN-

VIN+

CC0402

RBIAS

PDWN

34

32

33

35

36

JP506

DNI

R503

10K

CC0603

CML

0.1UF

C556

D11

12

D11

AGND

37

RC0603

D10

11

D10

CLK+

38

CLK

D8

D9

9

10

D9

D8

EPAD

CLK-

AVDD

394041

CLK

DUTAVDD

8

DRVDD

AGND

42

JP502

DRGND

AVDD

DNI

D4

D5

D6

D7

3

4

567

D4

D5

D6

D7

U510

D0 (LSB)

DCO

D1

OEB

45

44

464748

43

D0

DCO

D1

TP500

TP504

22RP500

81

VREF

R0402

R0402

DNI

R500

DNI

DNI

DNI

R501

1.0UF

C553

CC0805

C555

0.1UF

CC0402

06216-058

Figure 54. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface

Rev. 0 | Page 30 of 40

AD9254

DNI

DNI

RC0603

R513 0

R515 0

RC0603

R525 0

R514 0

DNI

DNI

RC0603

RC0603

R516 0

R517 0

RC0603

RC0603

R527 0

DNI

R526 0

DNI

RC0603

RC0603

R520 0

R521 0

RC0603

RC0603

R531 0

DNI

R530 0

DNI

RC0603

RC0603

R519 0

R518 0

RC0603

RC0603

R529 0

R528 0

DNI

DNI

RC0603

RC0603

R524 0

RC0603

RC0603

R534 0

DNI

R533 0

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

AD9515 LOGIC SETUP

AVDD_3P3V

S1

S0

S2

S4

S3

S6

S5

S8

S7

DNI

RC0603

RC0603

R522 0

R523 0

RC0603

RC0603

DNI

R532 0

DNI

S9

S10

DNI

10K

R588

RC0402

DISABLE

2

JP508

ENABLE

DNI

153

31

DNI

10KR587

RC0402

78

OE

OE

DNI

GND

OSC50 0

VCC

VCC

OUT

10

14

12

AVDD_3P3V

0

R575

DNI

CLK

CC0402CC0402CC0402

0.1UF

C536

DNI

CLK

0.1UF

C533

RC0603

0

R506

6

T503

1

GNDOUT

CB3LV-3C

RC0603

0

R508

RC0402

OPT_CLK

0.1UF

C530

CLK

CC0402CC0402

0.1UF

C532

1

3

2

RC0603

D502

HSMS2812

0

R509

5

2

34

C511

.1UF

RC0603

RC0603

0

R512

0

R507

DNI

OPT_CLK

CC0402

CC0402

0.1UF

C531

DNI

49.9

R504

RC0603

49.9

R505

DNI

RC0603

Place C531,R505=0.

To use AD9515 (OPT _CLK), remove R507, R508, C533, C532.

AVDD_3P3V

DNI

4.12K

R586

RC0402

DNI

R580

10K

RC0402

DNI

R581

RC0402

R576

DNI

CLK

CC0402

0.1UF

C537

DNI

RC0402

DNI

100

R582

33

RC0402

31

32

DNI

21

RC0603

DNI

R510

OPT_CLK

23

OUT0

GND_PA D

GND

RSET

U500

RC0402

22

OUT0B

CLK

CLKB

235

R577

240

R583

RC0402

240

R584

RC0402

19

AD9515

AVDD_3P3V;1,4,17,20,21,24,26,29,30

SYNCB

DNI

21

RC0603

DNI

R511

OPT_CLK

E502

DNI

E503

0.1UF

C535

0.1UF

C534

DNI

RC0402

DNI

100

R585

DNI

DNI

18

OUT1

OUT1B

S10

25

S0

S9

16

S1

S8

15

S2

S7

14

S3

S6

13

S4

S5

12

S5

S4

11

S6

S3

10

S7

NC=27,28

S2

9

S8

S1

8

S9

S0

7

S10

VREF

6

E501

RC0402

R578

DNI

RC0402

R579

DNI

XFMR/AD9515

Clock Circuitry

SMAEDGE

SMAEDGE

S501

S502

GND;3,4,5

CLK

GND;3,4,5

CLK/

06216-059

Figure 55. Evaluation Board Schematic, DUT Clock Input

Rev. 0 | Page 31 of 40

AD9254

SDO_CHA

CSB1_CHA

SDI_CHA

SCLK_CHA

SDIO_ODM

R553

1K

RC0603

AVDD_3P3V

R551

1K

RC0603

DUTAVDD

6

Y1

VCC

A1

GND

U508

1K

R552

RC0603

4

Y2

NC7WZ07

A2

1325

RC0603

R550

10K

RC0603

0

R554

RC0603

0

R556

RC0603

0

R557

RC0603

0

R555

RC0603

RC0603

AVDD_3P3V

R549

10K

CSB_DUT

SCLK_DTP

6

4

Y1

Y2

VCC

U507

A1

NC7WZ16

GND

A2

1325

RC0603

R548

10K

R546

4.7K DN I

RC0603

DNI

4.7K

R545

RC0603

R547

4.7K DNI

765

GP0

GP2

GP1

VSSVDD

DNI

REMOVE WHEN USING OR PROGRAMMING PIC (U506)

DDVPMAV3P3_DDVA

U506

GP5

GP4

3

2814

SOIC8

MCLR

DNI

2

JP509

13

+5V=PROGR AMMING ONLY=A MPVDD

+3.3V=NORMAL OPERATION=AVDD_3P3V

CC0603

0.1UF

C557

DNI

R558

4.7K

RC0603

3

DNI

D505

21

PIC12F629

RC0603

Optional

R559

261

12

DNI

4

E504

PICVCC

GP1

GP0

MCLR -GP3

DNI

DNI

J504

1

34

56

78

9

2

PICVCC

GP1

GP0

MCLR -GP3

10

HEADER UP MALE

PIC-HEADER

For FIFO controlled port, populate R555, R556, R557.

When u sing P ICSPI co ntrol led po rt, p opul ate R545, R546, R547.

When u sing P ICSPI co ntrol led po rt, remo ve R555, R556, R55 7.

DNI

S1

1

SPI CIRCUITRY

2

6216-060

Figure 56. Evaluation Board Schematic, SPI Circuitry

Rev. 0 | Page 32 of 40

AD9254

AMPVDDIN

TP507

L501

10UH

LC1210

C522

1UF

4

23

1TUPTUOTUPNI

OUTPU T4

GND

1

AVDD_3.3V=3.3V

DUTDRVDD=2. 5V

DUTAVDD=1. 8V

VDL=3.3V

AMPVDD=5V

ADP3339AKC-5

U501

C523

1UF

PWR_IN

DUTAVDDIN

TP506

L504

10UH

LC1210

C518

4

23

1TUPTUOTUPNI

OUTPU T4

ADP3339AKC-1.8

U502

C519

PWR_IN

TP505

L503

1UF

GND

1

U503

1UF

AVDD_3P3V

TP513

L509

10UH

LC1210

C525

1UF

4

23

1TUPTUOTUPNI

0.1UF

C543

OUTPU T4

GND

1

ADP3339AKC-3.3

U505

C513

1UF

PWR_IN

DUTDRVDDIN

10UH

LC1210

C520

1UF

4

23

1TUPTUOTUPNI

OUTPU T4

GND

1

ADP3339AKC-2.5

C521

1UF

PWR_IN

VDLINPWR_IN

TP508

L508

10UH

LC1210

C526

1UF

4

23

1TUPTUOTUPNI

OUTPU T4

GND

1

ADP3339AKC-3.3

U504

C524

1UF

CC0402CC0402CC0402 CC0402

0.1UF

C546

0.1UF

C544

0.1UF

C545

AVDD_3P3V

0.1UF

C568

CC0603

0.1UF

C538

CC0402CC0402CC0402 CC0402

0.1UF

C542

0.1UF

C539

0.1UF

C540

AVDD_3P3V

C559

0.1UF0.1U F

C558

CC0603 CC0603

0.1UF

C565

H503

H502

H500

H501

GROUND

TEST POINTS

Connecte d to Ground

Mounting Holes

TP509

TP512

TP511

TP510

0.1UF

C574

CC0603CC0603

0.1UF

C570

CC0603

0.1UF

C566

CC0603

0.1UF

C575

0.1UF

C599C572

0.1UF

CC0603 CC0603

D503

SHOT_RECT3ADO-214AB

FER500

Power Supply Input

CHOKE_COIL

F500

6V, 2A max

0.1UF

PWR_IN

CR50 0

R589

261

21

34

D504

DO-214AA2AS2A_RECT

SMDC110F

C527

10UF

OPTIONAL POWER CONNECTION

2

3

1

CON005

7.5V POWER

P500

2.5MM JAC K

0.1UF

C514

AMPVDD

6.3V

C549

1OUF

ACASE

L507

L505

10UH

LC1210

AMPVDDIN

123456789

P1P2P3P4P5P6P7P8P9

P501

10UH

J505

GND

GND

GND

DUTDRVDDIN

DUTAVDDIN

VDL

LC1210

VDLIN

C567

CC0603

AMPVDD

DUTAVDD

0.1UF

C515

6.3V

C550

1OUF

ACASE

GND

C551

L502

10UH

LC1210

GND

AVDD_3P3VIN

10

P10

0.1UF

C564

CC0603 CC0603

VDL

DUTDRVDD

0.1UF

C516

6.3V

1OUF

ACASE

J502

C517

C552

1OUF

ACASE

L506

10UH

LC1210

0.1UF

C569

CC0603

DUTAVDD

AVDD_3P3V

0.1UF

6.3V

J501

0.1UF

C512

6.3V

C548

1OUF

ACASE

L500

10UH

LC1210

0.1UF

C573

CC0603

DUTDRVDD

Remove L501, L503,L 504,L508, L509.

To use optional power connection

06216-061

Figure 57. Evaluation Board Schematic, Power Supply Inputs

Rev. 0 | Page 33 of 40

AD9254

EVALUATION BOARD LAYOUT

Figure 58. Evaluation Board Layout, Primary Side

6216-062

Figure 59. Evaluation Board Layout, Secondary Side (Mirrored Image)

Rev. 0 | Page 34 of 40

6216-063

AD9254

Figure 60. Evaluation Board Layout, Ground Plane

6216-064

Figure 61. Evaluation Board Layout, Power Plane

Rev. 0 | Page 35 of 40

6216-065

AD9254

06216-066

Figure 62. Evaluation Board Layout, Silkscreen Primary Side

Figure 63. Evaluation Board Layout, Silkscreen Secondary Side (Mirrored Image)

Rev. 0 | Page 36 of 40

06216-067

AD9254

BILL OF MATERIALS

Table 16. Evaluation Board Bill of Materials (BOM)

Omit

Item Qty.

1 1 AD9246CE_REVA PCB PCB ADI
2

3 1 C501 Capacitor 0402 0.3 pF
4 2 C4, C5 Resistor 0402 0 Ω
5 10

6 1 C527 Capacitor 1206 10 F
7 1 C529 Capacitor 0402 20 pF
8 5 C548, C549, C550, C551, C552 Capacitor ACASE 10 F
9 1 C553 Capacitor 0805 1.0 F
10 15

24

12

(DNP)

Reference Designator Device Package Description Supplier/Part Number

C1, C2, C509, C510, C511, C512,
C514, C515, C516, C517, C528,
C530, C532, C533, C538, C539,
C540, C542, C543, C544, C545,
C546, C554, C555

C3, C500, C502, C503, C504,
C505, C531, C534, C535, C536,
C537, C557

C513, C518, C519, C520, C521,
C522, C523, C524, C525, C526

C556, C558, C559, C564, C565,
C566, C567, C568, C569, C570,
C572, C573, C574, C575, C599

Capacitor 0402 0.1 F

Capacitor 0402 1.0 F

Capacitor 0603 0.1 F

11 1 CR500 LED 0603 green

1 D502 12

13 1 D503 Diode DO-214AB 3 A, 30 V, SMC

14 1 D504 Diode DO-214AA 2 A, 50 V, SMC

15 1 D505 LED LN1461C AMB Amber LED
16 1 F500 Fuse 1210

17 1 FER500 Choke 2020

18 1 J500 Jumper Solder jumper
19 3 J501, J502, J505 Jumper Solder jumper
20 1 J503 Connector 120 pin Male header
21 1 J504 Connector 10 pin Male, 2 × 5 Samtec
22 3 JP1, JP2, JP3 Jumper 3 pin Male, straight Samtec TSW-103-07-G-S
23 4 JP500, JP501, JP502, JP506 Jumper 2 pin Male, straight Samtec TSW-102-07-G-S

25 10

26 1 OSC500 Oscillator SMT

27 1 P500 Connector PJ-102A DC power jack Digikey CP-102A-ND

2 D500, D501

1 JP507 24
2 JP508, JP509

L500, L501, L502, L503, L504,
L505, L506, L507, L508, L509

Diode SOT-23

Jumper

Ferrite Bead

3-pin
jumper

3.2 mm ×

2.5 mm ×

1.6 mm

30 V, 20 mA,
dual Schottky

6.0 V, 2.2 A
trip current
resettable fuse

Male, straight Samtec TSW-103-07-G-S

Digikey P9811CT-ND

125 MHz or
105 MHz

Panasonic
LNJ314G8TRA

HSMS2812

Micro Commercial
Components SK33­TPMSCT-ND

Micro Commercial
Components S2A­TPMSTR-ND

Tyco, Raychem
NANOSMDC110F-2

Murata
DLW5BSN191SQ2

Samtec TSW-140-08-G-T-RA

CTS Reeves CB3LV-3C

Rev. 0 | Page 37 of 40

AD9254

Omit

Item Qty.

28 1 P501 Connector 10 pin Male, straight PTMICRO10
29 6 R1, R6, R563, R565, R574, R577 Resistor 0402 DNI

5 R2, R5, R561, R562, R571 30

6 R10, R11, R12, R535, R536, R575
31 2 R3, R4 Resistor 0402 25 Ω
32 6 R7, R8, R9, R502, R510, R511 Resistor 0603 DNI
33 6

34 4 R503, R548, R549, R550 Resistor 0603 10 kΩ

1 R504 35

1 R505
36

37 4 R545, R546, R547, R558 Resistor 0603 4.7 kΩ
38 3 R551, R552, R553 Resistor 0603 1 kΩ
39 1 R559 Resistor 0603 261 Ω
40 2 R566, R567 Resistor 0402 33 Ω
41 3 R582, R585, R598 Resistor 0402 100 Ω
42 2 R583, R584 Resistor 0402 240 Ω
43 1 R586 Resistor 0402 4.12 kΩ
44 3 R580, R587, R588 Resistor 0402 10 kΩ
45 1 R589 Resistor 0603 261 Ω
46 2 R590, R591 Resistor 0402 25 Ω
47 1 R592 Resistor 0402 DNI
48 2 R593, R596 Resistor 0402 0 Ω
49 2 R594, R595 Resistor 0402 10 kΩ
50 1 R597 Resistor 0402 4.3 kΩ
51 1 RP500 Resistor RCA74204 22 Ω
52 2 RP501, RP502 Resistor RCA74208 22 Ω
53 1 S1 Switch

55 2 S504, S505 Connector SMA200UP

58 1 U500 IC

59 1 U501 IC SOT-223

9

23

2 S500, S501 54

2 S502, S503

2 T500, T501 56

1 T1

1 T503 57

1 T502

(DNP) Reference Designator Device Package Description Supplier/Part Number

Resistor 0402 0 Ω

R500, R501, R576, R578, R579,
R581

R506, R508, R509, R512, R554,
R555, R556, R557, R560

R507, R513, R514, R515, R516,
R517, R518, R519, R520, R521,
R522, R523, R524, R525, R526,
R527, R528, R529, R530, R531,
R532, R533, R534,

Resistor 0402 DNI

Resistor 0603 49.9 Ω

Resistor 0603 0 Ω

Momentary
(normally
open)

Connector SMAEDGE

Transformer SM-22 M/A-Com ETC1-1-13

Transformer CD542 Mini-Circuits ADT1-1WT

32-pin
LFCSP _VQ

SMA edge
right angle

SMA RF 5-pin
upright

Clock
distribution

Voltage
regulator

Panasonic EVQ-PLDA15

ADI AD9515BCPZ

ADI ADP3339AKCZ-5

Rev. 0 | Page 38 of 40

AD9254

Omit

Item Qty.

60 1 U502 IC SOT-223

61 1 U503 IC SOT-223

62 2 U504, U505 IC SOT-223

63 1 U506 IC 8-pin SOIC

64 1 U507 IC SC70 Dual buffer Fairchild NC7WZ16
65 1 U508 IC SC70 Dual buffer Fairchild NC7WZ07
66 1 U509 IC

67 1 U510

68 1 U511 (or Z500) IC

Total 128 107

(DNP) Reference Designator Device Package Description Supplier/Part Number

ADI ADP3339AKCZ-1.8

ADI ADP3339AKCZ-2.5

ADI ADP3339AKCZ-3.3

Microchip PIC12F629

Fairchild 74VCX162244

ADI AD8352ACPZ

DUT
(AD9254)

48-pin
TSSOP

48-pin
LFCSP_VQ

16-pin
LFCSP_VQ

Voltage
regulator

Voltage
regulator

Voltage
regulator

8-bit
microcontroller

Buffer/line
driver

ADC ADI AD9254BCPZ

Differential
amplifier

Rev. 0 | Page 39 of 40

AD9254

R

OUTLINE DIMENSIONS

0.30

0.23

0.18
PIN 1

48

INDICATO

1

BSC SQ

PIN 1
INDICATOR

7.00

0.60 MAX

37

36

0.60 MAX

1.00

0.85

0.80

12° MAX

SEATING
PLANE

TOP

VIEW

0.80 MAX

0.65 TYP

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

6.75

BSC SQ

0.20 REF

0.50

0.40

0.30

0.05 MAX

0.02 NOM
COPLANARITY

0.08

25

24

EXPOSED

PA D

(BOTTOM VIEW)

5.50
REF

13

4.25

4.10 SQ

3.95

12

0.25 MIN

Figure 64. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

7 mm × 7 mm Body, Very Thin Quad (CP-48-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9254BCPZ-150
AD9254BCPZRL7–150
AD9254-150EBZ

1

Z = Pb-free part.

2

It is required that the exposed paddle be soldered to the AGND plane to achieve the best electrical and thermal performance.

1, 2

1, 2

1

–40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-3
–40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-3
Evaluation Board

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06216-0-10/06(0)

Rev. 0 | Page 40 of 40