Analog Devices AD9254 Service Manual

14-Bit, 150 MSPS, 1.8 V

A

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply
SNR = 71.8 dBc (72.8 dBFS) to 70 MHz input
SFDR = 84 dBc to 70 MHz input
Low power: 430 mW @ 150 MSPS
Differential input with 650 MHz bandwidth
On-chip voltage reference and sample-and-hold amplifier
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary, Gray code, or twos complement data format
Clock duty cycle stabilizer
Data output clock
Serial port control

Built-in selectable digital test pattern generation
Programmable clock and data alignment

APPLICATIONS

Ultrasound equipment
IF sampling in communications receivers

CDMA2000, WCDMA, TD-SCDMA, and WiMax
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes

Macro, micro, and pico cell infrastructure

GENERAL DESCRIPTION

The AD9254 is a monolithic, single 1.8 V supply, 14-bit, 150 MSPS
analog-to-digital converter (ADC), featuring a high performance
sample-and-hold amplifier (SHA) and on-chip voltage reference.
The product uses a multistage differential pipeline architecture
with output error correction logic to provide 14-bit accuracy at
150 MSPS data rates and guarantees no missing codes over the
full operating temperature range.

The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets, including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9254 is suitable for applications in communications,
imaging, and medical ultrasound.

A differential clock input controls all internal conversion cycles.
A duty cycle stabilizer (DCS) compensates for wide variations in
the clock duty cycle while maintaining excellent overall ADC
performance.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

Analog-to-Digital Converter

AD9254

FUNCTIONAL BLOCK DIAGRAM

MODE

SELECT

DRVDD

A/D

3

VDD

AD9254

VIN+

VIN–

REFT

REFB

VREF

SENSE

SHA

REF

SELECT

MDAC1

A/D

0.5V

AGND

8-STAGE

1 1/2-BIT PIPELINE

4

CORRECTION LOGIC

OUTPUT BUFF ERS

CLOCK

DUTY CYCLE

STABILIZER

CLK+

Figure 1.

8

15

CLK– PDWN DRGND

The digital output data is presented in offset binary, Gray code, or
twos complement formats. A data output clock (DCO) is provided
to ensure proper latch timing with receiving logic.

The AD9254 is available in a 48-lead LFCSP_VQ and is specified
over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. The AD9254 operates from a single 1.8 V power supply

and features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.

2. The patented SHA input maintains excellent performance

for input frequencies up to 225 MHz.

3. The clock DCS maintains overall ADC performance over a

wide range of clock pulse widths.

4. A standard serial port interface supports various product

features and functions, such as data formatting (offset
binary, twos complement, or Gray coding), enabling the
clock DCS, power-down, and voltage reference mode.

5. The AD9254 is pin-compatible with the AD9233, allowing

a simple migration from 12 bits to 14 bits.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

OR

DCO

D13 (MSB)

D0 (LSB)

SCLK/DFS

SDIO/DCS

CSB

06216-001

AD9254

TABLE OF CONTENTS

Features.............................................................................................. 1

Timing ......................................................................................... 20

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications.............................................................. 6

Timing Diagram........................................................................... 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Serial Port Interface (SPI).............................................................. 21

Configuration Using the SPI..................................................... 21

Hardware Interface..................................................................... 21

Configuration Without the SPI................................................ 21

Memory Map .................................................................................. 22

Reading the Memory Map Register Table............................... 22

Memory Map Register Table..................................................... 23

Layout Considerations................................................................... 25

Power and Ground Recommendations................................... 25

CML ............................................................................................. 25

RBIAS........................................................................................... 25

Reference Decoupling................................................................ 25

Evaluation Board............................................................................ 26

Power Supplies............................................................................ 26

Input Signals................................................................................ 26

Equivalent Circuits........................................................................... 9

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 14

Analog Input Considerations.................................................... 14

Differential Input Configurations............................................ 15

Voltage Reference....................................................................... 16

Clock Input Considerations...................................................... 17

Jitter Considerations .................................................................. 19

Power Dissipation and Standby Mode..................................... 19

Digital Outputs ........................................................................... 20

REVISION HISTORY

10/06—Revision 0: Initial Version

Output Signals ............................................................................ 26

Default Operation and Jumper Selection Settings................. 27

Alternative Clock Configurations............................................ 27

Alternative Analog Input Drive Configuration...................... 27

Schematics................................................................................... 29

Evaluation Board Layout........................................................... 34

Bill of Materials........................................................................... 37

Outline Dimensions....................................................................... 40

Ordering Guide .......................................................................... 40

Rev. 0 | Page 2 of 40

AD9254

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.

Table 1.

AD9254BCPZ-150

Parameter Temperature

Min Typ Max

RESOLUTION Full 14 Bits
ACCURACY

No Missing Codes Full Guaranteed
Offset Error Full ±0.3 ±0.8 % FSR
Gain Error Full ±0.6 ±4.5 % FSR
Differential Nonlinearity (DNL)

1

25°C ±0.4 LSB

Full ±1.0 LSB

Integral Nonlinearity (INL)

1

25°C ±1.5 LSB
Full ±5.0 LSB
TEMPERATURE DRIFT

Offset Error Full ±15 ppm/°C
Gain Error Full ±95 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) Full ±5 ±35 mV
Load Regulation @ 1.0 mA Full 7 mV

INPUT REFERRED NOISE

VREF = 1.0 V 25°C 1.3 LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V Full 2 V p-p
Input Capacitance

2

Full 8 pF
REFERENCE INPUT RESISTANCE Full 6 kΩ
POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 2.5 3.6 V

Supply Current

1

IAVDD

Full 240 260 mA

IDRVDD1(DRVDD = 1.8 V) Full 11 mA
IDRVDD1 (DRVDD = 3.3 V) Full 23 mA

POWER CONSUMPTION

DC Input Full 430 470 mW
Sine Wave Input1 (DRVDD = 1.8 V) Full 450 mW
Sine Wave Input1 (DRVDD = 3.3 V) Full 506 mW
Standby Power
Power-Down Power Full 1.8 mW

1

Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.

3

Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).

3

Full 40 mW

Unit

Rev. 0 | Page 3 of 40

AD9254

AC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.

Table 2.

Parameter

1

Temperature

SIGNAL-TO-NOISE-RATIO (SNR)

fIN = 2.4 MHz 25°C 72.0 dBc
fIN = 70 MHz 25°C 71.8 dBc
Full 70.0 dBc
fIN = 100 MHz 25°C 71.6 dBc
fIN = 170 MHz 25°C 70.8 dBc

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 2.4 MHz 25°C 71.7 dBc
fIN = 70 MHz 25°C 71.0 dBc
Full 69.0 dBc
fIN = 100 MHz 25°C 70.6 dBc
fIN = 170 MHz 25°C

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz

25°C
25°C
25°C
25°C

WORST SECOND OR THIRD HARMONIC

fIN = 2.4 MHz
fIN = 70 MHz

fIN = 100 MHz
fIN = 170 MHz

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.4 MHz
fIN = 70 MHz

fIN = 100 MHz
fIN = 170 MHz

25°C
25°C
Full
25°C
25°C

25°C
25°C
Full
25°C
25°C

WORST OTHER (HARMONIC OR SPUR)

fIN = 2.4 MHz
fIN = 70 MHz

fIN = 100 MHz
fIN = 170 MHz

TWO-TONE SFDR

fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS )
fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS )

ANALOG INPUT BANDWIDTH

1

See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

25°C
25°C
Full
25°C
25°C

25°C
25°C
25°C

AD9254BCPZ-150

Min Typ Max

69.8

11.7

11.7

11.6

11.5

dBc

−90

−84

−74

−83

−80

90
84
74
83
80

−93

−93

−85

−90

−90

90
90
650

Unit

Bits
Bits
Bits
Bits

dBc
dBc
dBc
dBc
dBc

dBc
dBc
dBc
dBc
dBc

dBc
dBc
dBc
dBc
dBc

dBFS
dBFS
MHz

Rev. 0 | Page 4 of 40

AD9254

DIGITAL SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.

Table 3.

AD9254BCPZ-150

Parameter Temperature

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage Full 0.2 6
Input Voltage Range Full AVDD − 0.3 AVDD + 1.6
Input Common-Mode Range Full 1.1 AVDD
High Level Input Voltage (VIH) Full 1.2 3.6 V
Low Level Input Voltage (VIL) Full
High Level Input Current (IIH) Full −10 +10 µA
Low Level Input Current (IIL) Full −10 +10 µA
Input Resistance Full 8 10 12
Input Capacitance Full 4

LOGIC INPUTS (SCLK/DFS, OEB, PWDN)

High Level Input Voltage (VIH) Full 1.2 3.6 V
Low Level Input Voltage (VIL) Full 0 0.8 V
High Level Input Current (IIH) Full
Low Level Input Current (IIL) Full
Input Resistance Full 30 kΩ
Input Capacitance Full 2 pF

LOGIC INPUTS (CSB)

High Level Input Voltage (VIH) Full 1.2 3.6 V
Low Level Input Voltage (VIL) Full 0 0.8 V
High Level Input Current (IIH) Full −10 +10 µA
Low Level Input Current (IIL) Full
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF

LOGIC INPUTS (SDIO/DCS)

High Level Input Voltage (VIH) Full 1.2 DRVDD + 0.3 V
Low Level Input Voltage (VIL) Full 0 0.8 V
High Level Input Current (IIH) Full −10 +10 µA
Low Level Input Current (IIL) Full
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF

DIGITAL OUTPUTS

DRVDD = 3.3 V

High Level Output Voltage (VOH, IOH = 50 µA) Full 3.29 V
High Level Output Voltage (VOH, IOH = 0.5 mA) Full 3.25 V
Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V
Low Level Output Voltage (VOL, IOL = 50 µA) Full 0.05 V

DRVDD = 1.8 V

High Level Output Voltage (VOH, IOH = 50 µA) Full 1.79 V
High Level Output Voltage (VOH, IOH = 0.5 mA) Full 1.75 V
Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V
Low Level Output Voltage (VOL, IOL = 50 µA) Full 0.05 V

CMOS/LVDS/LVPECL
Full 1.2 V

Min Typ Max

0 0.8

−50 −75

−10 +10

+40 +135

+40 +130

Unit

V p-p
V
V

V

kΩ
pF

µA
µA

µA

µA

Rev. 0 | Page 5 of 40

AD9254

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.

Table 4.

Parameter

1

Temperature

Min Typ Max

CLOCK INPUT PARAMETERS

Conversion Rate, DCS Enabled Full 20 150 MSPS
Conversion Rate, DCS Disabled Full 10 150 MSPS
CLK Period Full 6.7 ns
CLK Pulse Width High, DCS Enabled Full 2.0 3.3 4.7 ns
CLK Pulse Width High, DCS Disabled Full 3.0 3.3 3.7 ns

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD)
DCO Propagation Delay (t

2

) Full 4.4 ns

DCO

Full 3.1 3.9 4.8 ns

Setup Time (tS) Full 1.9 2.9 ns
Hold Time (tH) Full 3.0 3.8 ns
Pipeline Delay (Latency) Full 12 Cycles
Aperture Delay (tA) Full 0.8 ns
Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms
Wake-Up Time

3

Full 350 µs
OUT-OF-RANGE RECOVERY TIME Full 3 Cycles
SERIAL PORT INTERFACE

SCLK Period (t

4

) Full 40 ns

CLK

SCLK Pulse Width High Time (tHI) Full 16 ns
SCLK Pulse Width Low Time (tLO) Full 16 ns
SDIO to SCLK Setup Time (tDS) Full 5 ns
SDIO to SCLK Hold Time (tDH) Full 2 ns
CSB to SCLK Setup Time (tS) Full 5 ns
CSB to SCLK Hold Time (tH) Full 2 ns

1

See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

3

Wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 µF capacitor across REFT and REFB.

4

See Figure 50 and the Serial Port Interface (SPI) section.

AD9254BCPZ-150

Unit

TIMING DIAGRAM

CLK+

CLK–

DATA

DCO

N – 13

N+ 2

N+ 1

N

t

A

t

CLK

t

PD

N – 12 N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4

t

S

t

H

N+ 3

t

DCO

N+ 4

N+ 5

N+ 6

t

CLK

N+ 7

Figure 2. Timing Diagram

Rev. 0 | Page 6 of 40

N+ 8

06216-002

AD9254

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

ELECTRICAL

AVDD to AGND −0.3 V to +2.0 V
DRVDD to DGND −0.3 V to +3.9 V
AGND to DGND −0.3 V to +0.3 V
AVDD to DRVDD −3.9 V to +2.0 V
D0 through D13 to DGND −0.3 V to DRVDD + 0.3 V
DCO to DGND −0.3 V to DRVDD + 0.3 V
OR to DGND −0.3 V to DRVDD + 0.3 V
CLK+ to AGND −0.3 V to +3.9 V
CLK− to AGND −0.3 V to +3.9 V
VIN+ to AGND −0.3 V to AVDD + 0.2 V
VIN− to AGND −0.3 V to AVDD + 0.2 V
VREF to AGND −0.3 V to AVDD + 0.2 V
SENSE to AGND −0.3 V to AVDD + 0.2 V
REFT to AGND −0.3 V to AVDD + 0.2 V
REFB to AGND −0.3 V to AVDD + 0.2 V
SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V
PDWN to AGND −0.3 V to +3.9 V
CSB to AGND −0.3 V to +3.9 V
SCLK/DFS to AGND −0.3 V to +3.9 V
OEB to AGND −0.3 V to +3.9 V

ENVIRONMENTAL

Storage Temperature Range –65°C to +125°C
Operating Temperature Range –40°C to +85°C
Lead Temperature

(Soldering 10 Sec)
Junction Temperature 150°C

300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

The exposed paddle must be soldered to the ground plane for
the LFCSP_VQ package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.

Table 6. Thermal Resistance

Package Type θJA θ

48-lead LFCSP_VQ (CP-48-3) 26.4 2.4 °C/W

Unit

JC

Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θ

JA

. In
addition, metal in direct contact with the package leads from
metal traces and through holes, ground, and power planes,
reduces the θ

.

JA

ESD CAUTION

Rev. 0 | Page 7 of 40

AD9254

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DRVDD

DRGNDD1D0 (LSB)

DCO

OEB

AVDD

AGND

AVDD

CLK–

CLK+

4847464544434241403938

AGND

37

AVDD

35
34
33

32
31
30
29

28
27

26
25

PDWN36

RBIAS
CML
AVDD

AGND
VIN–
VIN+
AGND

REFT
REFB

VREF
SENSE

06216-003

DRGND

DRVDD

D10

D11

D2

1

D3

2

D4

3

D5

4

D6

5

D7

6

7

8

D8

9

D9

10
11

12

PIN 1
INDICATO R

AD9254

TOP VIEW

(Not to Scale)

13141516171819

OR

D12

DRVDD

DRGND

D13 (MSB)

SDIO/DCS

2021222324

CSB

AGND

SCLK/DFS

AVDD

AGND

Figure 3. Pin Configuration

Table 7. Pin Function Description

Pin No. Mnemonic Description

0, 21, 23, 29, 32,

AGND Analog Ground. (Pin 0 is the exposed thermal pad on the bottom of the package.)

37, 41
45, 46, 1 to 6,

D0 (LSB) to D13 (MSB) Data Output Bits.

9 to 14
7, 16, 47 DRGND Digital Output Ground.
8, 17, 48 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V).
15 OR Out-of-Range Indicator.
18 SDIO/DCS

Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select
(External Pin Mode). See

Table 10.
19 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
20 CSB Serial Port Interface Chip Select (Active Low). See Tab le 10.
22, 24, 33, 40, 42 AVDD Analog Power Supply.

25 SENSE Reference Mode Selection. See Table 9.
26 VREF Voltage Reference Input/Output.
27 REFB Differential Reference (−).
28 REFT Differential Reference (+).
30 VIN+ Analog Input Pin (+).
31 VIN– Analog Input Pin (−).
34 CML Common-Mode Level Bias Output.
35 RBIAS

External Bias Resistor Connection. A 10 kΩ resistor must be connected between this pin and

analog ground (AGND).
36 PDWN Power-Down Function Select.
38 CLK+ Clock Input (+).
39 CLK– Clock Input (−).
43 OEB Output Enable (Active Low).
44 DCO Data Clock Output.

Rev. 0 | Page 8 of 40

AD9254

V

C

S

S

Ω

V

A

V

EQUIVALENT CIRCUITS

LK+

IN

06216-004

Figure 4. Equivalent Analog Input Circuit

AVDD

1.2V

10kΩ 10kΩ

Figure 5. Equivalent Clock Input Circuit

DRVDD

DIO/DCS

1kΩ

CLK–

CLK/DFS

OEB

PDWN

30kΩ

1kΩ

06216-008

Figure 8. Equivalent SCLK/DFS, OEB, PDWN Input Circuit

AVDD

26kΩ

CSB

06216-005

1kΩ

06216-009

Figure 9. Equivalent CSB Input Circuit

SENSE

1k

06216-010

06216-011

Figure 6. Equivalent SDIO/DCS Input Circuit

DRVDD

DRGND

Figure 7. Equivalent Digital Output Circuit

06216-006

06216-007

Figure 10. Equivalent Sense Circuit

DD

REF

6kΩ

Figure 11. Equivalent VREF Circuit

Rev. 0 | Page 9 of 40

AD9254

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V; DRVDD = 2.5 V; maximum sample rate, DCS enabled, 1 V internal reference; 2 V p-p differential input; AIN = −1.0 dBFS;
64k sample; T

–20

–40

= 25°C, unless otherwise noted.

A

0

150MSPS

2.3MHz @ –1dBFS
SNR = 72.0dBc (73. 0dBFS)
ENOB = 11.7 BITS
SFDR = 90.0dBc

0

150MSPS

100.3MHz @ –1dBF S
SNR = 71.6dBc (72.6dBFS)

–20

ENOB = 11.6 BI TS
SFDR = 83dBc

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

Figure 12. AD9254 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

Figure 13. AD9254 Single-Tone FFT with f

FREQUENCY (MHz )

150MSPS

30.3MHz @ –1dBFS
SNR = 71.9dBc (72. 9dBFS)
ENOB = 11.7 BITS
SFDR = 88d Bc

FREQUENCY (MHz )

= 2.3 MHz

IN

= 30.3 MHz

IN

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

06216-012

Figure 15. AD9254 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

06216-013

Figure 16. AD9254 Single-Tone FFT with f

FREQUENCY (MHz )

150MSPS

140.3MHz @ –1dBF S
SNR = 71.5dBc (72. 5dBFS)
ENOB = 11.5 BI TS
SFDR = 81dBc

FREQUENCY (MHz )

= 100.3 MHz

IN

= 140.3 MHz

IN

06216-015

06216-016

0

150MSPS

70.3MHz @ –1dBF S
SNR = 71.8dBc (72.8dBFS)

–20

ENOB = 11.7 BI TS
SFDR = 84dBc

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

Figure 14. AD9254 Single-Tone FFT with f

FREQUENCY (MHz )

= 70.3 MHz

IN

06216-014

Rev. 0 | Page 10 of 40

0

–20

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

FREQUENCY (MHz )

Figure 17. AD9254 Single-Tone FFT with f

150MSPS

170.3MHz @ –1dBF S
SNR = 70.8dBc (71. 8dBFS)
ENOB = 11.5 BI TS
SFDR = 80dBc

= 170.3 MHz

IN

06216-017

AD9254

0

150MSPS

250.3MHz @ –1dBF S
SNR = 69.3dBc (70. 3dBFS)

–20

ENOB = 11.3 BITS
SFDR = 79dBc

–40

120

100

80

SFDR (dBFS)

SNR (dBFS)

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

Figure 18. AD9254 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

Figure 19. AD9254 Two-Tone FFT with f

90

85

80

FREQUENCY (MHz )

IN

150MSPS

f

= 29.1MHz @ –7d BFS

IN1

f

= 32.1MHz @ –7d BFS

IN2

SFDR = 83.2dBc (90.2dBFS )
WoIMD3 = –83.9dBc (–90. 9dBFS)

FREQUENCY (MHz )

= 29.1 MHz, f

IN1

SFDR –40°C

= 250.3 MHz

SFDR +25°C

= 32.1 MHz

IN2

60

40

SFDR (dBc)

SNR/SFDR (dBc an d dBFS )

20

SNR (dBc)

0

–90 0–20 –10–30–40–50–60–70–80

06216-018

INPUT AMPLI TUDE (dBFS)

85dBc
REFERENCE LINE

06216-021

Figure 21. AD9254 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)

= 2.4 MHz

with f

IN

0

–20

–40

WORST I MD3 (dBc)

–60

–80

–100

SFDR/WORST IMD3 (d Bc and dBFS)

–120

–90 –78 –66 –54 –42 –30 –18 –6

06216-019

SFDR (–dBc)

SFDR (–dBFS)

WORST I MD3 (dBFS)

INPUT AMPLITUDE (dBFS)

06216-022

Figure 22. AD9254 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)

= 29.1 MHz, f

with f

IN1

90

85

80

= 32.1 MHz

IN2

SFDR +25°C

SFDR –40°C

SNR/SFDR (dBc)

75

70

65

60

0435030025020015010050

INPUT FREQUENCY (MHz)

SNR –40°C

SNR +25°C

Figure 20. AD9254 Single-Tone SNR/SFDR vs. Input Frequency (f

Temperature with 2 V p-p Full Scale

75

SFDR +85°C

SNR +85°C

00

06216-020

) and

IN

SNR/SFDR (dBc)

70

65

60

Figure 23. AD9254 Single-Tone SNR/SFDR vs. Input Frequency (f

Rev. 0 | Page 11 of 40

SNR +25°C

0435030025020015010050

INPUT FREQ UENCY (MHz)

Temperature with 1 V p-p Full Scale

SFDR +85°C

SNR –40°C

SNR +85°C

00

06216-023

) and

IN

AD9254

0

–20

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 18.75 37.50 56.25 75.00

FREQUENCY (MHz )

Figure 24. AD9254 Two-Tone FFT with f

95

90

85

80

150MSPS

f

= 169.1MHz @ –7dBF S

IN1

f

= 172.1MHz @ –7dBF S

IN2

SFDR = 83dBc (90d BFS)
WoIMD3 = –83d Bc (90dBFS)

= 169.1 MHz, f

IN1

SFDR

= 172.1 MHz

IN2

2.0

1.5

1.0

0.5

0

–0.5

INL ERROR (LSB)

–1.0

–1.5

–2.0

0 163841433612288102408192614440962048

06216-024

Figure 27. AD9254 INL with f

12000

10000

8000

6000

OUTPUT CODE

= 10.3 MHz

IN

32768 SAMPLES

1.25 LSB rms

06216-031

SNR/SFDR (dBc)

75

70

65

10 1501401301201101009080706050403020

CLOCK FREQUE NCY (MSPS)

Figure 25. AD9254 Single-Tone SNR/SFDR vs. Clock Frequency (f

0

–20

–40

WORST I MD3 (dBc)

–60

–80

–100

SFDR/WORST IMD3 (d Bc and dBFS)

–120

–90 –78 –66 –54 –42 –30 –18 –6

SFDR (–dBc)

SFDR (–dBFS)

INPUT AMPLITUDE (dBFS)

= 2.4 MHz

with f

IN

WORST I MD3 (dBFS)

SNR

CLK

Figure 26. AD9254 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)

with f

= 169.1 MHz, f

IN1

= 172.11 MHz

IN2

NUMBER OF HIT S

4000

2000

0

N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5

06216-025

)

ERROR (%FS)

06216-027

Figure 28. AD9254 Grounded Input Histogram

0

–0.5

–1.0

–1.5

–2.0

–2.5

–40–200 20406080

CODE

OFFSET ERROR

GAIN ERROR

TEMPERATURE (° C)

06216-032

06216-033

Figure 29. AD9254 Gain and Offset vs. Temperature

Rev. 0 | Page 12 of 40