Analog Devices AD9252 Service Manual

Octal, 14-Bit, 50 MSPS

S

A

V

W

Serial LVDS 1.8 V A/D Converter

AD9252

FEATURES FUNCTIONAL BLOCK DIAGRAM

8 ADCs integrated into 1 package

93.5 mW ADC power per channel at 50 MSPS SNR = 73 dB (to Nyquist) Excellent linearity

DNL = ±0.4 LSB (typical) INL = ±1.5 LSB (typical)

Serial LVDS (ANSI-644, default)

Low power reduced signal option, IEEE 1596.3 similar Data and frame clock outputs 325 MHz, full power analog bandwidth 2 V p-p input voltage range

1.8 V supply operation Serial port control

Full-chip and individual-channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

APPLICATIONS

Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam forming systems Quadrature radio receivers Diversity radio receivers Tap e dr ive s Optical networking Test equipment

GENERAL DESCRIPTION

The AD9252 is an octal, 14-bit, 50 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 50 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

DD DRVDD

AD9252

VIN+A

VIN–A

VIN+B

VIN–B

VIN+C

VIN–C

VIN+D

VIN–D

VIN+E

VIN–E

VIN+F

VIN–F

VIN+G

VIN–G

VIN+H

VIN–H

VREF

ENSE

REFT REFB

REF

SELECT

RBIAS

AGND

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI®).

The AD9252 is available in a Pb-free, 64-lead LFCSP package. It is specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Small Footprint. Eight ADCs are contained in a small, space-

saving package; low power of 93.5 mW/channel at 50 MSPS.

2. Ease of Use. A data clock output (DCO) operates up to

300 MHz and supports double data rate operation (DDR).

3. User Flexibility. Serial port interface (SPI) control offers a wide

range of flexible features to meet specific system requirements.

4. Pin-Compatible Family. This includes the AD9212 (10-bit),

and AD9222 (12-bit).

PD

0.5V

CSB

N

ADC

SERIAL PORT

INTERFA CE

SDIO/

ODM

Figure 1.

SCLK/

DTP

14

SERIAL

LVDS

14

SERIAL

LVDS

14

SERIAL

LVDS

14

SERIAL

LVDS

14

SERIAL

LVDS

14

SERIAL

LVDS

14

SERIAL

LVDS

14

SERIAL

LVDS

DATA RATE

MULTI PLI ER

CLK+

DRGND

CLK–

D+A D–A

D+B D–B

D+C D–C

D+D D–D

D+E D–E

D+F D–F

D+G D–G

D+H D–H

FCO+

FCO–

DCO+ DCO–

06296-001

AD9252

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Diagrams.............................................................................. 7

Absolute Maximum Ratings............................................................ 9

Thermal Impedance..................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Equivalent Circuits......................................................................... 12

Typical Performance Characteristics ........................................... 14

Theory of Operation ...................................................................... 17

Analog Input Considerations ................................................... 17

Clock Input Considerations...................................................... 19

Serial Port Interface (SPI).............................................................. 27

Hardware Interface..................................................................... 27

Memory Map .................................................................................. 29

Reading the Memory Map Table.............................................. 29

Reserved Locations .................................................................... 29

Default Values............................................................................. 29

Logic Levels................................................................................. 29

Evaluation Board ............................................................................ 33

Power Supplies ............................................................................ 33

Input Signals................................................................................ 33

Output Signals ............................................................................ 33

Default Operation and Jumper Selection Settings................. 34

Alternative Analog Input Drive Configuration...................... 35

Outline Dimensions ....................................................................... 52

Ordering Guide .......................................................................... 52

REVISION HISTORY

10/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 52

AD9252

SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 1.

AD9252-50 Parameter

RESOLUTION 14 Bits ACCURACY

No Missing Codes Full Guaranteed Offset Error Full ±1 ±8 mV Offset Matching Full ±3 ±8 mV Gain Error Full ±1.5 ±2.5 % FS Gain Matching Full ±0.3 ±0.7 % FS Differential Nonlinearity (DNL) Full ±0.4 ±1 LSB Integral Nonlinearity (INL) Full ±1.5 ±4 LSB

TEMPERATURE DRIFT

Offset Error Full ±2 ppm/°C Gain Error Full ±17 ppm/°C Reference Voltage (1 V Mode) Full ±21 ppm/°C

REFERENCE

Output Voltage Error (VREF = 1 V) Full ±2 ±30 mV Load Regulation @ 1.0 mA (VREF = 1 V) Full 3 mV Input Resistance Full 6 kΩ

ANALOG INPUTS

Differential Input Voltage Range (VREF = 1 V) Full 2 V p-p Common-Mode Voltage Full AVDD/2 V Differential Input Capacitance Full 7 pF Analog Bandwidth, Full Power Full 325 MHz

POWER SUPPLY

AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V IAVDD Full 360 373.4 mA IDRVDD Full 55.5 58 mA Total Power Dissipation (Including Output Drivers) Full 748 773 mW Power-Down Dissipation Full 2 11 mW

Standby Dissipation CROSSTALK Full −90 dB CROSSTALK (Overrange Condition)

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

Can be controlled via SPI.

3

Overrange condition is specific with 6 dB of the full-scale input range.

1

2

3

Temperature Min Typ Max Unit

Full 89 mW

Full −90 dB

Rev. 0 | Page 3 of 52

AD9252

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 2.

AD9252-50 Parameter

SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz Full 73.2 dB f f f SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz Full 72.5 dB f f f EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz Full 11.87 Bits f f f SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz Full 85 dBc f f f WORST HARMONIC (Second or Third) fIN = 2.4 MHz Full −85 dBc f f f WORST OTHER (Excluding Second or Third) fIN = 2.4 MHz Full −90 dBc f f f TWO-TONE INTERMODULATION DISTORTION (IMD)—

AIN1 AND AIN2 = −7.0 dBFS

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

1

Temperature Min Typ Max Unit

= 19.7 MHz Full 71 73 dB

IN

= 35 MHz Full 72.7 dB

IN

= 70 MHz Full 71 dB

IN

= 19.7 MHz Full 70.2 72.2 dB

IN

= 35 MHz Full 72 dB

IN

= 70 MHz Full 70.5 dB

IN

= 19.7 MHz Full 11.5 11.84 Bits

IN

= 35 MHz Full 11.79 Bits

IN

= 70 MHz Full 11.5 Bits

IN

= 19.7 MHz Full 73 84 dBc

IN

= 35 MHz Full 83 dBc

IN

= 70 MHz Full 79 dBc

IN

= 19.7 MHz Full −84 −73 dBc

IN

= 35 MHz Full −83 dBc

IN

= 70 MHz Full −79 dBc

IN

= 19.7 MHz Full −90 −80 dBc

IN

= 35 MHz Full −90 dBc

IN

= 70 MHz Full −89 dBc

IN

f

= 15 MHz,

IN1

= 16 MHz

f

IN2

= 70 MHz,

f

IN1

= 71 MHz

f

IN2

25°C 80.0 dBc

Rev. 0 | Page 4 of 52

AD9252

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 3.

AD9252-50 Parameter

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL

Differential Input Voltage

Input Common-Mode Voltage Full 1.2 V

Input Resistance (Differential) 25°C 20 kΩ

Input Capacitance 25°C 1.5 pF LOGIC INPUTS (PDWN, SCLK/DTP)

Logic 1 Voltage Full 1.2 3.6 V

Logic 0 Voltage Full 0.3 V

Input Resistance 25°C 30 kΩ

Input Capacitance 25°C 0.5 pF LOGIC INPUT (CSB)

Logic 1 Voltage Full 1.2 3.6 V

Logic 0 Voltage Full 0.3 V

Input Resistance 25°C 70 kΩ

Input Capacitance 25°C 0.5 pF LOGIC INPUT (SDIO/ODM)

Logic 1 Voltage Full 1.2 DRVDD + 0.3 V

Logic 0 Voltage Full 0 0.3 V

Input Resistance 25°C 30 kΩ

Input Capacitance 25°C 2 pF LOGIC OUTPUT (SDIO/ODM)

Logic 1 Voltage (IOH = 800 μA) Full 1.79 V

Logic 0 Voltage (IOL = 50 μA) Full 0.05 V DIGITAL OUTPUTS (D+, D−), (ANSI-644)

Logic Compliance LVDS

Differential Output Voltage (VOD) Full 247 454 mV

Output Offset Voltage (VOS) Full 1.125 1.375 V

Output Coding (Default) Offset binary DIGITAL OUTPUTS (D+, D−),

(Low Power, Reduced Signal Option)

Logic Compliance LVDS

Differential Output Voltage (VOD) Full 150 250 mV

Output Offset Voltage (VOS) Full 1.10 1.30 V

Output Coding (Default) Offset binary

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

This is specified for LVDS and LVPECL only.

3

This is specified for 13 SDIO pins sharing the same connection.

1

2

3

Temperature Min Typ Max Unit

Full 250 mV p-p

Rev. 0 | Page 5 of 52

AD9252

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 4.

AD9252-50

Parameter

CLOCK

OUTPUT PARAMETERS

APERTURE

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

Can be adjusted via the SPI interface.

3

Measurements were made using a part soldered to FR4 material.

4

t

SAMPLE

1

2

Temp

Min Typ Max Unit

Maximum Clock Rate Full 50 MSPS Minimum Clock Rate Full 10 MSPS Clock Pulse Width High (tEH) Full 10.0 ns Clock Pulse Width Low (tEL) Full 10.0 ns

2, 3

Propagation Delay (tPD) Full 1.5 2.3 3.1 ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps FCO Propagation Delay (t DCO Propagation Delay (t

DCO to Data Delay (t

DCO to FCO Delay (t Data to Data Skew

− t

(t

DATA-MAX

DATA-MIN

) Full 1.5 2.3 3.1 ns

FCO

4

DATA

FRAME

)

CPD

)4

Full t

Full (t

/28) − 300 (t

SAMPLE

/28) − 300 (t

SAMPLE

FCO

(t

+

SAMPLE

/28) /28) (t

/28) (t

ns

/28) + 300 ps

SAMPLE

/28) + 300 ps

SAMPLE

Full ±50 ±200 ps

) Wake-Up Time (Standby) 25°C 600 ns Wake-Up Time (Power-Down) 25°C 375 μs Pipeline Latency Full 8 CLK

cycles

Aperture Delay (tA) 25°C 750 ps Aperture Uncertainty (Jitter) 25°C <1 ps rms Out-of-Range Recovery Time 25°C 1 CLK

cycles

/28 is based on the number of bits divided by 2 because the delays are based on half duty cycles.

Rev. 0 | Page 6 of 52

AD9252

TIMING DIAGRAMS

N – 1

AIN

t

A

N

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D10

t

EL

t

DATA

D0

D1

N – 8

MSB N – 7

D12

N – 7

06296-003

t

EH

t

CPD

MSB N – 8

t

FRAME

D12

N – 8

D11

N – 8

N – 8D9N – 8D8N – 8D7N – 8D6N – 8D5N – 8D4N – 8D3N – 8D2N – 8

t

FCO

t

D–

D+

PD

Figure 2. 14-Bit Data Serial Stream (Default)

N – 1

AIN

t

A

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

N

t

EH

t

CPD

t

FCO

t

D–

D+

PD

t

FRAME

MSB

D10

N – 8

N – 8D9N – 8D8N – 8D7N – 8D6N – 8D5N – 8D4N – 8D3N – 8D2N – 8D1N – 8D0N – 8

Figure 3. 12-Bit Data Serial Stream

t

EL

t

DATA

D10

MSB

N – 7

6296-002

Rev. 0 | Page 7 of 52

AD9252

N – 1

AIN

t

A

N

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

t

EH

t

CPD

t

FCO

t

D–

D+

PD

t

FRAME

LSB

N – 8D0N – 8D1N – 8D2N – 8D3N – 8D4N – 8D5N – 8D6N – 8D7N – 8D8N – 8D9N – 8

t

EL

t

DATA

D10

D11

D12

N – 8

LSB

N – 7D0N – 7

06296-004

Figure 4. 14-Bit Data Serial Stream, LSB First

Rev. 0 | Page 8 of 52

AD9252

ABSOLUTE MAXIMUM RATINGS

Table 5.

With

Parameter

ELECTRICAL θ θ

AVDD AGND −0.3 V to +2.0 V DRVDD DRGND −0.3 V to +2.0 V AGND DRGND −0.3 V to +0.3 V AVDD DRVDD −2.0 V to +2.0 V Digital Outputs

(D+, D−, DCO+,

DCO−, FCO+, FCO−) CLK+, CLK− AGND −0.3 V to +3.9 V VIN+, VIN− AGND −0.3 V to +2.0 V SDIO/ODM AGND −0.3 V to +2.0 V PDWN, SCLK/DTP, CSB AGND −0.3 V to +3.9 V REFT, REFB, RBIAS AGND −0.3 V to +2.0 V VREF, SENSE AGND −0.3 V to +2.0 V

ENVIRONMENTAL

Operating Temperature

Range (Ambient) Maximum Junction

Temperature Lead Temperature

(Soldering, 10 sec) Storage Temperature

Range (Ambient)

Respect To

DRGND −0.3 V to +2.0 V

−40°C to +85°C

150°C

300°C

−65°C to +150°C

Rating

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL IMPEDANCE

Table 6.

Air Flow Velocity (m/s)

0.0 17.7°C/W

1.0 15.5°C/W 8.7°C/W 0.6°C/W

2.5 13.9°C/W

1

θ

for a 4-layer PCB with solid ground plane (simulated). Exposed pad

JA

soldered to PCB.

1

θ

JA

JB JC

ESD CAUTION

Rev. 0 | Page 9 of 52

AD9252

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VIN+F

VIN–F

AVD D

VIN–E

VIN+E

AVD D

REFT

REFB

VREF

SENSE

RBIAS

VIN+D

VIN–D

AVD D

VIN–C

VIN+C

49

48

AVD D

47

VIN+B

46

VIN–B

45

AVD D

44

VIN–A

43

VIN+A

42

AVD D

41

PDWN

40

CSB

39

SDIO/ODM

38

SCLK/DTP

37

AVD D

36

DRGND

35

DRVDD

34

D+A

33

D–A

AVD D VIN+G VIN–G

AVD D VIN–H VIN+H

AVD D

CLK–

CLK+

AVD D

DRGND

DRVDD

D–H D+H

646362616059585756555453525150

PIN 1 INDICATOR

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

EXPOSED PADDLE, PIN 0 (BOTTO M OF PACKAGE)

AD9252

TOP VIEW

(Not to Scale)

171819202122232425262728293031

D–F

D+F

D–E

D–G

D+E

D+G

D–D

FCO–

FCO+

DCO–

DCO+

32

D–C

D–B

D+D

D+C

D+B

Figure 5. 64-Lead LFCSP Top View

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

0 AGND Analog Ground (Exposed Paddle) 1, 4, 7, 8, 11,

AVDD 1.8 V Analog Supply 12, 37, 42, 45, 48, 51, 59, 62

13, 36 DRGND Digital Output Driver Ground 14, 35 DRVDD 1.8 V Digital Output Driver Supply 2 VIN+G ADC G Analog Input—True 3 VIN−G ADC G Analog Input—Complement 5 VIN−H ADC H Analog Input—Complement 6 VIN+H ADC H Analog Input—True 9 CLK− Input Clock—Complement 10 CLK+ Input Clock—True 15 D−H ADC H Digital Output—Complement 16 D+H ADC H True Digital Output—True 17 D−G ADC G Digital Output—Complement 18 D+G ADC G True Digital Output—True 19 D−F ADC F Digital Output—Complement 20 D+F ADC F True Digital Output—True 21 D−E ADC E Digital Output—Complement 22 D+E ADC E True Digital Output—True 23 DCO− Data Clock Digital Output—Complement 24 DCO+ Data Clock Digital Output—True 25 FCO− Frame Clock Digital Output—Complement 26 FCO+ Frame Clock Digital Output—True 27 D−D ADC D Digital Output—Complement 28 D+D ADC D True Digital Output—True 29 D−C ADC C Digital Output—Complement 30 D+C ADC C True Digital Output—True 31 D−B ADC B Digital Output—Complement 32 D+B ADC B True Digital Output—True

06296-005

Rev. 0 | Page 10 of 52

AD9252

Pin No. Mnemonic Description

33 D−A ADC A Digital Output—Complement 34 D+A ADC A True Digital Output—True 38 SCLK/DTP Serial Clock/Digital Test Pattern 39 SDIO/ODM Serial Data Input-Output/Output Driver Mode 40 CSB Chip Select Bar 41 PDWN Power Down 43 VIN+A ADC A Analog Input—True 44 VIN−A ADC A Analog Input—Complement 46 VIN−B ADC B Analog Input—Complement 47 VIN+B ADC B Analog Input—True 49 VIN+C ADC C Analog Input—True 50 VIN−C ADC C Analog Input—Complement 52 VIN−D ADC D Analog Input—Complement 53 VIN+D ADC D Analog Input—True 54 RBIAS External Resistor to Set the Internal ADC Core Bias Current 55 SENSE Reference Mode Selection 56 VREF Voltage Reference Input/Output 57 REFB Differential Reference (Negative) 58 REFT Differential Reference (Positive) 60 VIN+E ADC E Analog Input—True 61 VIN−E ADC E Analog Input—Complement 63 VIN−F ADC F Analog Input—Complement 64 VIN+F ADC F Analog Input—True

Rev. 0 | Page 11 of 52

AD9252

S

EQUIVALENT CIRCUITS

DRVDD

VIN

Figure 6. Equivalent Analog Input Circuit

CLK

10

10k

1.25V

10k

10

V

D– D+

V

06296-006

DRGND

V

6296-009

Figure 9. Equivalent Digital Output Circuit

SCLK/DTP OR PDWN

1k

30k

Figure 7. Equivalent Clock Input Circuit

DIO/ODM

350

30k

Figure 8. Equivalent SDIO/ODM Input Circuit

06296-007

06296-010

Figure 10. Equivalent SCLK/DTP or PDWN Input Circuit

RBIAS

06296-008

100

06296-011

Figure 11. Equivalent RBIAS Circuit

Rev. 0 | Page 12 of 52

AD9252

A

V

DD

70k

CSB

Figure 12. Equivalent CSB Input Circuit

1k

VREF

6k

06296-012

6296-014

Figure 14. Equivalent VREF Circuit

SENSE

1k

06296-013

Figure 13. Equivalent SENSE Circuit

Rev. 0 | Page 13 of 52

AD9252

TYPICAL PERFORMANCE CHARACTERISTICS

0

AIN = –0.5dBF S SNR = 71.16dB ENOB = 11.53 BITS

–20

SFDR = 72.92dBc

–20

0

AIN = –0.5dBFS SNR = 73.71dB ENOB = 11.95 BITS SFDR = 85.86dBc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

02

Figure 15. Single-Tone 32k FFT with f Figure 18. Single-Tone 32k FFT with f

0

AIN = –0.5dBF S SNR = 72.98dB ENOB = 11.83 BITS

–20

SFDR = 83.8dBc

–40

–60

–80

AMPLITUDE (dBFS)

5 101520

FREQUENCY (MHz)

= 2.3 MHz, f

IN

SAMPLE

= 50 MSPS

5

06296-048

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

025

90

85

80

75

SNR/SFDR (dB)

70

5 101520

FREQUENCY (MHz)

SFDR

SNR

= 120 MHz, f = 50 MSPS

IN

SAMPLE

06296-051

–100

–120

02

Figure 16. Single-Tone 32k FFT with f

0

AIN = –0.5dBFS SNR = 72.36dB ENOB = 11.73 BITS

–20

SFDR = 86.21dBc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

02

Figure 17. Single-Tone 32k FFT with f

5 101520

FREQUENCY (MHz)

= 35 MHz, f

IN

5 101520

FREQUENCY (MHz)

= 70 MHz, f

IN

SAMPLE

5

06296-049

= 50 MSPS

5

06296-050

= 50 MSPS

65

60

10 15 20 25 30 35 40 45 50

Figure 19. SNR/SFDR vs. f

90

85

80

75

SNR/SFDR (dB)

70

65

60

10 15 20 25 30 35 40 45 50

Figure 20. SNR/SFDR vs. f

ENCODE (MSPS)

SAMPLE

SFDR

SNR

ENCODE (MSPS)

SAMPLE

, fIN = 10.3 MHz, f = 50 MSPS

, fIN = 19.7 MHz, f = 50 MSPS

SAMPLE

06296-039

06296-040

Rev. 0 | Page 14 of 52

AD9252

90

80

SFDR

70

60

0

AIN1 AND AIN2 = –7dBFS SFDR = 83.64d B IMD2 = 95.57d Bc IMD3 = 84.26d Bc

–20

–40

50

40

SNR/SFDR (dB)

30

20

10

–60 –50 –40 –30 –20 –10 0

SNR

ANALOG INPUT LEVEL (dBFS)

Figure 21. SNR/SFDR vs. Analog Input Level, f Figure 24. Two-Tone 32k FFT with f

90

80

70

60

50

40

SNR/SFDR (dB)

30

20

SFDR

SNR

80dB REFERENCE

= 10.3 MHz, f

IN

80dB REFERENCE

SAMPLE

06296-041

= 50 MSPS

–60

AMPLITUDE (dBFS)

–80

–100

–120

0 5 10 15 20 25

90

85

80

75

SNR/SFDR (dB)

70

65

FREQUENCY ( MHz)

= 71 MHz, f

f

IN2 SAMPLE

SFDR

SNR

= 50 MSPS

= 70 MHz and

IN1

06296-044

10

–60 –50 –40 –30 –20 –10 0

Figure 22. SNR/SFDR vs. Analog Input Level, f

0

AIN1 AND AIN2 = –7dBFS SFDR = 86.27d B IMD2 = 97.82d Bc IMD3 = 86.13d Bc

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 5 10 15 20 25

Figure 23. Two-Tone 32k FFT with f

ANALOG INPUT LEVEL (dBFS)

IN

FREQUE NCY (MHz)

= 16 MHz, f

f

IN2

SAMPLE

= 50 MSPS

= 19.7 MHz, f

IN1

SAMPLE

= 15 MHz and

06296-042

= 50 MSPS

06296-043

60

1 10 100 1000

90

85

80

75

SINAD/SFDR ( dB)

70

65

60

–40–200 20406080

Figure 26. SINAD/SFDR vs. Temperature, f

ANALOG INPUT FREQUENCY ( MHz)

Figure 25. SNR/SFDR vs. f

TEMPERATURE (°C)

, f

IN

SAMPLE

SFDR

SINAD

= 19.7 MHz, f

IN

= 50 MSPS

SAMPLE

06296-045

06296-046

= 50 MSPS

Rev. 0 | Page 15 of 52

AD9252

–

2.0

1.5

1.0

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

–2.0

0 16000

2000 4000 6000 8000 10000 12000 14000

CODE

Figure 27. INL, f

= 2.3 MHz, f

IN

SAMPLE

= 50 MSPS

06296-053

1.8

1.6

1.4

1.2

1.0

0.8

0.6

NUMBER OF HITS (Millions)

0.4

0.2

0

N – 3 N – 2 N – 1 N N+ 1 N + 2 N + 3

CODE

Figure 30. Input-Referred Noise Histogram, f

1.047LSB rms

= 50 MSPS

SAMPLE

06296-054

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

2000 4000 6000 8000 10000 12000 14000

0 16000

CODE

Figure 28. DNL, f

30

–35

–40

–45

–50

CMRR (dB)

–55

–60

–65

–70

0 5 10 15 20 25 30 35 40

Figure 29. CMRR vs. Frequency, f

= 2.3 MHz, f

IN

FREQUENCY (MHz)

SAMPLE

= 50 MSPS

SAMPLE

= 50 MSPS

06296-052

06296-055

0

NPR = 62.5dB NOTCH = 18.0MHz NOTCH WIDT H = 2.3MHz

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

0

Figure 31. Noise Power Ratio (NPR), f

0

–1

–2

–3

–4

–5

–6

–7

AMPLITUDE ( dBFS)

–8

–9

–10

–11

0 50045040035030025020015010050

5101520 25

FREQUENCY (MHz)

SAMPLE

–3dB BANDWIDTH = 325MHz

FREQUENCY (MHz)

Figure 32. Full Power Bandwidth vs. Frequency, f

= 50 MSPS

SAMPLE

06296-038

06296-037

Rev. 0 | Page 16 of 52