Analog Devices AD9246 Service Manual

14-Bit, 80 MSPS/105 MSPS/125 MSPS,

A

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply
SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input
SFDR = 85 dBc to 70 MHz input
Low power: 395 mW @ 125 MSPS
Differential input with 650 MHz bandwidth
On-chip voltage reference and sample-and-hold amplifier
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary, Gray code, or twos complement data format
Clock duty cycle stabilizer
Data output clock
Serial port control

Built-in selectable digital test pattern generation
Programmable clock and data alignment

APPLICATIONS

Ultrasound equipment
IF sampling in communications receivers

IS-95, CDMA-One, IMT-2000
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes

GENERAL DESCRIPTION

The AD9246 is a monolithic, single 1.8 V supply, 14-bit, 80 MSPS/
105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring
a high performance sample-and-hold amplifier (SHA) and on-chip
voltage reference. The product uses a multistage differential
pipeline architecture with output error correction logic to
provide 14-bit accuracy at 125 MSPS data rates and guarantees
no missing codes over the full operating temperature range.

The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets, including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9246 is suitable for applications in communications,
imaging, and medical ultrasound.

A differential clock input controls all internal conversion cycles.
A duty cycle stabilizer (DCS) compensates for wide variations in
the clock duty cycle while maintaining excellent overall ADC
performance.

1.8 V Analog-to-Digital Converter
AD9246

FUNCTIONAL BLOCK DIAGRAM

MODE

SELECT

DRVDD

A/D

3

OR

DCO

D13 (MSB)

D0 (LSB)

SCLK/DFS

SDIO/DCS

CSB

VDD

AD9246

VIN+

VIN–

REFT

REFB

VREF

SENSE

SHA

REF

SELECT

MDAC1

A/D

0.5V

AGND

8-STAGE

1 1/2-BIT PIPELINE

4

CORRECTION LOGIC

OUTPUT BUF FERS

CLOCK

DUTY CYCLE

STABILIZER

CLK+

Figure 1.

8

15

CLK– PDWN DRGND

The digital output data is presented in offset binary, Gray code, or
twos complement formats. A data output clock (DCO) is provided
to ensure proper latch timing with receiving logic.

The AD9246 is available in a 48-lead LFCSP_VQ and is specified
over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. The AD9246 operates from a single 1.8 V power supply

and features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.

2. The patented SHA input maintains excellent performance

for input frequencies up to 225 MHz.

3. The clock DCS maintains overall ADC performance over a

wide range of clock pulse widths.

4. A standard serial port interface supports various product

features and functions, such as data formatting (offset
binary, twos complement, or Gray coding), enabling the
clock DCS, power-down, and voltage reference mode.

5. The AD9246 is pin-compatible with the AD9233, allowing

a simple migration from 12 bits to 14 bits.

05491-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD9246

TABLE OF CONTENTS

Features.............................................................................................. 1

Timing ......................................................................................... 22

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

AC Specifications.......................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications.............................................................. 7

Timing Diagram........................................................................... 7

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Serial Port Interface (SPI).............................................................. 23

Configuration Using the SPI..................................................... 23

Hardware Interface..................................................................... 23

Configuration Without the SPI................................................ 23

Memory Map .................................................................................. 24

Reading the Memory Map Register Table............................... 24

Memory Map Register Table..................................................... 25

Layout Considerations................................................................... 27

Power and Ground Recommendations................................... 27

CML ............................................................................................. 27

RBIAS........................................................................................... 27

Reference Decoupling................................................................ 27

Evaluation Board............................................................................ 28

Power Supplies............................................................................ 28

Input Signals................................................................................ 28

Equivalent Circuits......................................................................... 10

Typical Performance Characteristics ........................................... 11

Theory of Operation ...................................................................... 15

Analog Input Considerations.................................................... 15

Voltage Reference....................................................................... 17

Clock Input Considerations...................................................... 18

Jitter Considerations .................................................................. 20

Power Dissipation and Standby Mode..................................... 20

Digital Outputs ........................................................................... 21

Output Signals ............................................................................ 28

Default Operation and Jumper Selection Settings................. 29

Alternative Clock Configurations............................................ 29

Alternative Analog Input Drive Configuration...................... 29

Schematics................................................................................... 31

Evaluation Board Layouts ......................................................... 36

Bill of Materials........................................................................... 39

Outline Dimensions....................................................................... 42

Ordering Guide .......................................................................... 42

Rev. A | Page 2 of 44

AD9246

REVISION HISTORY

8/06—Rev. 0 to Rev. A

Added 80 MSPS.................................................................. Universal

Changes to Features..........................................................................1

Deleted Figures 19, 20, 22, 23 ........................................................11

Deleted Figures 24, 25, 27 to 29.....................................................12

Deleted Figures 31, 34.....................................................................13

Deleted Figures 37, 38, 40, 41 ........................................................14

Deleted Figure 46 ............................................................................15

Deleted Figure 52 ............................................................................16

Changes to Figure 41 ......................................................................17

Changes to Figure 46 ......................................................................19

Inserted Figure 54 ...........................................................................21

Added Data Clock Output (DCO) Section .................................22

Changes to Table 15........................................................................25

Changes to Table 16........................................................................39

Changes to the Ordering Guide....................................................42

4/06—Revision 0: Initial Version

Rev. A | Page 3 of 44

AD9246

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS
enabled, unless otherwise noted.

Table 1.

AD9246BCPZ-80 AD9246BCPZ-105 AD9246BCPZ-125

Parameter Temp

RESOLUTION Full 14 14 14 Bits
ACCURACY

No Missing Codes Full Guaranteed Guaranteed Guaranteed
Offset Error Full ±0.3 ±0.5 ±0.3 ±0.8 ±0.3 ±0.8 % FSR
Gain Error Full ±0.6 ±4.7 ±0.6 ±5.0 ±0.6 ±4.2 % FSR
Differential Nonlinearity (DNL)

1

Full ±1.0 ±1.0 ±1.0 LSB

25°C ±0.4 ±0.4 ±0.4 LSB

Integral Nonlinearity (INL)

1

Full ±5.0 ±5.0 ±5.0 LSB
25°C ±1.5 ±1.3 ±1.5 LSB
TEMPERATURE DRIFT

Offset Error Full ±15 ±15 ±15 ppm/°C
Gain Error Full ±95 ±95 ±95 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) Full ±5 ±20 ±5 ±35 ±5 ±35 mV
Load Regulation @ 1.0 mA Full 7 7 7 mV

INPUT REFERRED NOISE

VREF = 1.0 V 25°C 1.3 1.3 1.3 LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V Full
Input Capacitance

2

Full
REFERENCE INPUT RESISTANCE Full
POWER SUPPLIES

Supply Voltage

AVDD Full
DRVDD Full

Supply Current

1

IAVDD

Full

IDRVDD1 (DRVDD = 1.8 V) Full
IDRVDD1 (DRVDD = 3.3 V) Full

POWER CONSUMPTION

DC Input Full
Sine Wave Input1 (DRVDD = 1.8 V) Full
Sine Wave Input1 (DRVDD = 3.3 V) Full
Standby Power

3

Full

Power-Down Power Full

1

Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.

3

Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).

Min Typ Max Min Typ Max Min Typ Max Unit

2 2
8 8
6 6

1.7 1.8 1.9 1.7 1.8 1.9

1.7 2.5 3.6 1.7 2.5 3.6

138 155 178 194
7 9
12 16

248 279 320 350
261 337
288 373
40 40

1.8 1.8

2 V p-p
8 pF
6 kΩ

1.7 1.8 1.9 V

1.7 2.5 3.6 V

220 236 mA
11 mA
19 mA

395 425 mW
415 mW
458 mW
40 mW

1.8 mW

Rev. A | Page 4 of 44

AD9246

AC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference;AIN = −1.0 dBFS, DCS
enabled, unless otherwise noted.

Table 2.

Parameter

1

Temp

SIGNAL-TO-NOISE-RATIO (SNR)

fIN = 2.4 MHz 25°C 71.9 71.9 71.9 dBc
fIN = 70 MHz 25°C 71.9 71.9 71.7 dBc
Full 70.8 69.5 69.5 dBc
fIN = 100 MHz 25°C 71.6 71.6 71.6 dBc
fIN = 170 MHz 25°C 70.9 70.9 70.8 dBc

SIGNAL-TO-NOISE AND DISTORTION
(SINAD)

fIN = 2.4 MHz 25°C 71.1 71.1 71.1 dBc
fIN = 70 MHz 25°C 71.5 70.8 70.6 dBc
Full 70.4 68.5 68.5 dBc
fIN = 100 MHz 25°C 70.6 70.6 70.6 dBc
fIN = 170 MHz 25°C

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz

25°C 11.7 11.7
25°C 11.6 11.6
25°C 11.6 11.6
25°C 11.5 11.5

WORST SECOND OR THIRD HARMONIC

fIN = 2.4 MHz
fIN = 70 MHz

fIN = 100 MHz
fIN = 170 MHz

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.4 MHz
fIN = 70 MHz

fIN = 100 MHz
fIN = 170 MHz

25°C
25°C
Full
25°C
25°C

25°C
25°C
Full
25°C
25°C

WORST OTHER HARMONIC OR SPUR

fIN = 2.4 MHz
fIN = 70 MHz

fIN = 100 MHz
fIN = 170 MHz

TWO-TONE SFDR

fIN = 29 MHz (−7 dBFS), 32 MHz

25°C
25°C
Full
25°C
25°C

25°C 87 87

(−7 dBFS)
fIN = 169 MHz (−7 dBFS), 172 MHz

25°C 83 83

(−7 dBFS)

ANALOG INPUT BANDWIDTH

1

See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

25°C

AD9246BCPZ-80 AD9246BCPZ-105 AD9246BCPZ-125

Min Typ Max Min Typ Max Min Typ Max Unit

69.9

69.9

−90 −90 −90

−85 −85 −85

−76

−73

−73

−85 −85 −85

−83.5 −83.5 −83

90 90 90
85 85 85
76

73

73

85 85 85

83.5 83.5 83

−90 −90 −90

−90 −90 −90

−85

−80

−80

−90 −90 −90

−90 −90 −90

85

84

650

650

650

69.8

11.7

11.6

11.6

11.5

dBc

Bits
Bits
Bits
Bits

dBc
dBc
dBc
dBc
dBc

dBc
dBc
dBc
dBc
dBc

dBc
dBc
dBc
dBc
dBc

dBc

dBc

MHz

Rev. A | Page 5 of 44

AD9246

DIGITAL SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS
enabled, unless otherwise noted.

Table 3.

AD9246BCPZ-80/105/125

Parameter Temp

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage Full 0.2 6
Input Voltage Range Full AVDD − 0.3 AVDD + 1.6
Input Common-Mode Range Full 1.1 AVDD
High Level Input Voltage (VIH) Full 1.2 3.6 V
Low Level Input Voltage (VIL) Full
High Level Input Current (IIH) Full −10 +10 µA
Low Level Input Current (IIL) Full −10 +10 µA
Input Resistance Full 8 10 12
Input Capacitance Full 4

LOGIC INPUTS (SCLK/DFS, OEB, PWDN)

High Level Input Voltage (VIH) Full 1.2 3.6 V
Low Level Input Voltage (VIL) Full 0 0.8 V
High Level Input Current (IIH) Full
Low Level Input Current (IIL) Full
Input Resistance Full 30 kΩ
Input Capacitance Full 2 pF

LOGIC INPUTS (CSB)

High Level Input Voltage (VIH) Full 1.2 3.6 V
Low Level Input Voltage (VIL) Full 0 0.8 V
High Level Input Current (IIH) Full −10 +10 µA
Low Level Input Current (IIL) Full
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF

LOGIC INPUTS (SDIO/DCS)

High Level Input Voltage (VIH) Full 1.2 DRVDD + 0.3 V
Low Level Input Voltage (VIL) Full 0 0.8 V
High Level Input Current (IIH) Full −10 +10 µA
Low Level Input Current (IIL) Full
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF

DIGITAL OUTPUTS

DRVDD = 3.3 V

High Level Output Voltage (VOH, IOH = 50 µA) Full 3.29 V
High Level Output Voltage (VOH , IOH = 0.5 mA) Full 3.25 V
Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V
Low Level Output Voltage (VOL, IOL = 50 µA) Full 0.05 V

DRVDD = 1.8 V

High Level Output Voltage (VOH, IOH = 50 µA) Full 1.79 V
High Level Output Voltage (VOH, IOH = 0.5 mA) Full 1.75 V
Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V
Low Level Output Voltage (VOL, IOL = 50 µA) Full 0.05 V

CMOS/LVDS/LVPECL
Full 1.2 V

Min Typ Max

0 0.8

−50 −75

−10 +10

+40 +135

+40 +130

Unit

V p-p
V
V

V

kΩ
pF

µA
µA

µA

µA

Rev. A | Page 6 of 44

AD9246

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.

Table 4.

Parameter

1

Temp

CLOCK INPUT PARAMETERS

Conversion Rate, DCS Enabled Full 20 80 20 105 20 125 MSPS
Conversion Rate, DCS Disabled Full 10 80 10 105 10 125 MSPS
CLK Period Full 12.5 9.5 8 ns
CLK Pulse Width High, DCS Enabled Full 3.75 6.25 8.75 2.85 4.75 6.65 2.4 4 5.6 ns
CLK Pulse Width High, DCS Disabled Full 5.63 6.25 6.88 4.28 4.75 5.23 3.6 4 4.4 ns

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD)
DCO Propagation Delay (t

2

) Full 4.4 4.4 4.4 ns

DCO

Full 3.1 3.9 4.8 3.1 3.9 4.8 3.1 3.9 4.8 ns

Setup Time (tS) Full 4.9 5.7 3.4 4.3 2.6 3.5 ns
Hold Time (tH) Full 5.9 6.8 4.4 5.3 3.7 4.5 ns
Pipeline Delay (Latency) Full 12 12 12 cycles
Aperture Delay (tA) Full 0.8 0.8 0.8 ns
Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms
Wake-Up Time

3

Full 350 350 350 s
OUT-OF-RANGE RECOVERY TIME Full 2 2 3 Cycles
SERIAL PORT INTERFACE

SCLK Period (t

4

) Full 40 40 40 ns

CLK

SCLK Pulse Width High Time (tHI) Full 16 16 16 ns
SCLK Pulse Width Low Time (tLO) Full 16 16 16 ns
SDIO to SCLK Setup Time (tDS) Full 5 5 5 ns
SDIO to SCLK Hold Time (tDH) Full 2 2 2 ns
CSB to SCLK Setup Time (tS) Full 5 5 5 ns
CSB to SCLK Hold Time (tH) Full 2 2 2 ns

1

See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

3

Wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 µF capacitor across REFT and REFB.

4

See Figure 57 and the Serial Port Interface (SPI) section.

AD9246BCPZ-80 AD9246BCPZ-105 AD9246BCPZ-125

Min Typ Max Min Typ Max Min Typ Max

Unit

TIMING DIAGRAM

CLK+

CLK–

DATA

DCO

N+2

N+ 1

N

t

A

t

CLK

t

PD

N – 13

N – 12 N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4

t

S

t

H

N+ 3

t

DCO

N+ 4

N+ 5

t

CLK

N+ 6

N+ 7

Figure 2. Timing Diagram

Rev. A | Page 7 of 44

N+ 8

05491-002

AD9246

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

ELECTRICAL

AVDD to AGND −0.3 V to +2.0 V
DRVDD to DGND −0.3 V to +3.9 V
AGND to DGND −0.3 V to +0.3 V
AVDD to DRVDD −3.9 V to +2.0 V
D0 through D13 to DGND −0.3 V to DRVDD + 0.3 V
DCO to DGND −0.3 V to DRVDD + 0.3 V
OR to DGND −0.3 V to DRVDD + 0.3 V
CLK+ to AGND −0.3 V to +3.9 V
CLK− to AGND −0.3 V to +3.9 V
VIN+ to AGND −0.3 V to AVDD + 0.2 V
VIN− to AGND −0.3 V to AVDD + 0.2 V
VREF to AGND −0.3 V to AVDD + 0.2 V
SENSE to AGND −0.3 V to AVDD + 0.2 V
REFT to AGND −0.3 V to AVDD + 0.2 V
REFB to AGND −0.3 V to AVDD + 0.2 V
SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V
PDWN to AGND −0.3 V to +3.9 V
CSB to AGND −0.3 V to +3.9 V
SCLK/DFS to AGND −0.3 V to +3.9 V
OEB to AGND −0.3 V to +3.9 V

ENVIRONMENTAL

Storage Temperature Range –65°C to +125°C
Operating Temperature Range –40°C to +85°C
Lead Temperature

(Soldering 10 Sec)
Junction Temperature +150°C

+300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

The exposed paddle must be soldered to the ground plane for
the LFCSP_VQ package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.

Table 6. Thermal Resistance

Package Type θJA θ

48-lead LFCSP_VQ (CP-48-3) 26.4 2.4 °C/W

Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation effectively reducing θ
addition, metal in direct contact with the package leads from
metal traces, and through holes, ground, and power planes,
reduces the θ

.

JA

Unit

JC

. In

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 8 of 44

AD9246

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DRVDD

DRGNDD1D0 (LSB)

DCO

OEB

AVDD

AGND

AVDD

CLK–

CLK+

4847464544434241403938

AGND

37

AVDD

35
34
33

32

31
30

29

28
27

26
25

PDWN36

RBIAS
CML
AVDD

AGND

VIN–
VIN+

AGND

REFT
REFB

VREF
SENSE

05491-003

DRGND

DRVDD

D10

D11

D2

1

D3

2

D4

3

D5

4

D6

5

D7

6

7

8

D8

9

D9

10
11

12

PIN 1
INDICATO R

AD9246

TOP VIEW

(Not to Scale)

13141516171819

OR

D12

DRVDD

DRGND

D13 (MSB)

SDIO/DCS

2021222324

CSB

AGND

SCLK/DFS

AVDD

AGND

Figure 3. Pin Configuration

Table 7. Pin Function Description

Pin No. Mnemonic Description

0, 21, 23, 29, 32,

AGND Analog Ground. (Pin 0 is the exposed thermal pad on the bottom of the package.)

37, 41
45, 46, 1 to 6,

D0 (LSB) to D13 (MSB) Data Output Bits.

9 to 14
7, 16, 47 DRGND Digital Output Ground.
8, 17, 48 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V ).
15 OR Out-of-Range Indicator.
18 SDIO/DCS

Serial Port Interface (SPI)® Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select
(External Pin Mode). See

Table 10.
19 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
20 CSB Serial Port Interface Chip Select (Active Low). See Tabl e 10.
22, 24, 33, 40, 42 AVDD Analog Power Supply.

25 SENSE Reference Mode Selection. See Table 9 .
26 VREF Voltage Reference Input/Output.
27 REFB Differential Reference (−).
28 REFT Differential Reference (+).
30 VIN+ Analog Input Pin (+).
31 VIN– Analog Input Pin (−).
34 CML Common-Mode Level Bias Output.
35 RBIAS

External Bias Resistor Connection. A 10 kΩ resistor must be connected between this pin and

analog ground (AGND).
36 PDWN Power-Down Function Select.
38 CLK+ Clock Input (+).
39 CLK– Clock Input (−).
43 OEB Output Enable (Active Low).
44 DCO Data Clock Output.

Rev. A | Page 9 of 44

AD9246

V

C

S

S

A

V

A

V

EQUIVALENT CIRCUITS

LK+

IN

05491-004

Figure 4. Equivalent Analog Input Circuit

AVDD

1.2V

10kΩ 10kΩ

Figure 5. Equivalent Clock Input Circuit

DRVDD

DIO/DCS

1kΩ

CLK–

CLK/DFS

OEB

PDWN

30kΩ

1kΩ

05491-008

Figure 8. Equivalent SCLK/DFS, OEB, PDWN Input Circuit

VDD

26kΩ

CSB

05491-005

1kΩ

05491-010

Figure 9. Equivalent CSB Input Circuit

SENSE

1kΩ

05491-011

05491-012

Figure 6. Equivalent SDIO/DCS Input Circuit

DRVDD

DRGND

Figure 7. Equivalent Digital Output Circuit

05491-006

05491-007

Figure 10. Equivalent Sense Circuit

DD

REF

6kΩ

Figure 11. Equivalent VREF Circuit

Rev. A | Page 10 of 44

AD9246

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V; DRVDD = 2.5 V; maximum sample rate, DCS enabled, 1 V internal reference; 2 V p-p differential input;
AIN = −1.0 dBFS; 64k sample; T

0

–20

–40

= 25°C, unless otherwise noted. All figures show typical performance for all speed grades.

A

–20

–40

0

125MSPS

100.3MHz @ –1dBF S
SNR = 71.6dBc (72.6dBFS)
ENOB = 11.5 BI TS
SFDR = 85dBc

125MSPS

2.3MHz @ –1dBF S
SNR = 71.9dB (72. 9dBFS)
ENOB = 11.7 BI TS
SFDR = 90dBc

–60

–80

AMPLI TUDE (d BFS)

–100

–120

–140

0 62.500

Figure 12. AD9246-125 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0 62.500

Figure 13. AD9246-125 Single-Tone FFT with f

0

–20

–40

15.625 31.25 0 46.875

FREQUENCY (MHz)

15.625 31.250 46.875

FREQUENCY (MHz)

125MSPS

70.3MHz @ –1dBFS
SNR = 71.7dB (72.7d BFS)
ENOB = 11.5 BITS
SFDR = 85dBc

= 2.3 MHz

IN

125MSPS

30.3MHz @ –1dBFS
SNR = 71.9dBc (72.9dBFS)
ENOB = 11.6 BI TS
SFDR = 88.8d Bc

= 30.3 MHz

IN

–60

–80

AMPLI TUDE (d BFS)

–100

–120

–140

0 62.500

05491-013

Figure 15. AD9246-125 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0 62.500

05491-014

Figure 16. AD9246-125 Single-Tone FFT with f

0

–20

–40

15.625 31. 250 46.875

FREQUENCY (MHz)

15.625 31. 250 46.875

FREQUENCY (MHz)

125MSPS

170.3MHz @ –1dBF S
SNR = 70.8dB (71.8d BFS)
ENOB = 11.4 BITS
SFDR = 83.4dBc

= 100.3 MHz

IN

125MSPS

140.3MHz @ –1dBF S
SNR = 71dB (72dBF S)
ENOB = 11.4 BI TS
SFDR = 85dBc

= 140.3 MHz

IN

05491-016

05491-017

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0 62.500

Figure 14. AD9246-125 Single-Tone FFT with f

15.625 31. 250 46. 875

FREQUENCY (MHz)

= 70.3 MHz

IN

05491-015

Rev. A | Page 11 of 44

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0 62.500

Figure 17. AD9246-125 Single-Tone FFT with f

15.625 31. 250 46.875

FREQUENCY (MHz)

IN

= 170.3 MHz

05491-018

AD9246

AMPLITUDE ( dBFS)

–100

–20

–40

–60

–80

0

125MSPS

225.3MHz @ –1dBF S
SNR = 70.3dB (71.3dBFS)
ENOB = 11.3 BI TS
SFDR = 80.4dBc

SNR/SFDR (dBc)

95

90

85

80

SNR = +85°C

75

SFDR = +25°C

SFDR = +85°C

SNR = +25°C

SFDR = –40°C

SNR = –40°C

–120

–140

0 62.500

Figure 18. AD9246-125 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0 62.500

Figure 19. AD9246-125 Single-Tone FFT with f

120

100

80

15.625 31. 250 46.875

FREQUENCY (MHz)

125MSPS

300.3MHz @ –1dBF S
SNR = 69.3dB (70.3d BFS)
ENOB = 11 BIT S
SFDR = 77.5dBc

15.625 31.250 46. 875

FREQUENCY (MHz)

SFDR (dBFS)

SNR (dBFS)

= 225.3 MHz

IN

= 300.3 MHz

IN

70

65

0 250

05491-019

Figure 21. AD9246 Single-Tone SNR/SFDR vs. Input Frequency (f

50 100 150 200

INPUT FREQ UENCY (MHz)

) and

IN

05491-022

Temperature with 2 V p-p Full Scale

95

90

85

80

SNR/SFDR (dBc)

75

SNR = +85°C

70

65

0 250

05491-020

Figure 22. AD9246 Single-Tone SNR/SFDR vs. Input Frequency (f

SFDR = +85°C

SFDR = –40°C

SFDR = +25°C

SNR = +25°C

50 100 150 200

INPUT FREQ UENCY (MHz)

SNR = –40°C

) and

IN

05491-023

Temperature with 1 V p-p Full Scale

0

–0.25

OFFSET ERROR

60

SFDR (dBc)

40

SNR/SFDR (dBc and dBFS)

20

SNR (dBc)

0

–90 0

–80 –70 –60 –50 –40 –30 –20 –10

INPUT AMPLI TUDE (dBFS)

85dB REF ERENCE L INE

Figure 20. AD9246 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)

= 2.4 MHz

with f

IN

05491-040

Rev. A | Page 12 of 44

–0.50

–0.75

GAIN/OFFSET ERROR (%FSR)

–1.00

–20 0 204060

–40 80

GAIN ERROR

TEMPERATURE (° C)

Figure 23. AD9246 Gain and Offset vs. Temperature

05491-035

AD9246

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0 62.500

15.625 31.250 46.875

FREQUENCY (MHz)

Figure 24. AD9246-125 Two-Tone FFT with f

0

125MSPS

169.1MHz @ –7dBF S

172.1MHz @ –7dBF S

–20

SFDR = 84dBc (91dBF S)

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0 62.500

15.625 31.250 46.875

FREQUENCY (MHz)

Figure 25. AD9246-125 Two-Tone FFT with f

0

–20

125MSPS

29.1MHz @ –7dBF S

32.1MHz @ –7dBF S
SFDR = 85dBc (92d BFS)

= 29.1 MHz, f

IN1

= 169.1 MHz, f

IN1

IN2

IN2

05491-025

= 32.1 MHz

05491-026

= 172.1 MHz

0

–20

–40

–60

–80

SFDR/IMD3 (dBc and dBFS)

–100

–120

–90 –6

SFDR (dBc)

IMD3 (dBc)

SFDR (dBFS)

IMD3 (dBFS )

–78 –66 –54 –42 –30 –18

INPUT AMPLI TUDE (dBFS)

Figure 27. AD9246 Two-Tone SFDR/IMD vs. Input Amplitude (AIN)

= 29.1 MHz, F

with F

IN1

0

–20

–40

IMD3 (dBFS )

–60

–80

SFDR/IMD3 (dBc and dBFS)

–100

–120

–90 –6

SFDR (dBFS)

–78 –66 –54 –42 –30 –18

INPUT AMPLI TUDE (dBFS)

= 32.1 MHz

IN2

SFDR (dBc)

IMD3 (dBc)

Figure 28. AD9246 Two-Tone SFDR/IMD vs. Input Amplitude (AIN)

–20

= 169.1 MHz, F

with F

IN1

0

= 172.11 MHz

IN2

NPR = 62.9dBc
NOTCH @ 18.5MHz
NOTCH WIDTH = 3MHz

05491-028

05491-029

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 15.36 30.72 46.08 61. 44

FREQUENCY (MHz)

Figure 26. AD9246-125 Two 64k WCDMA Carriers

= 215.04 MHz, fS = 122.88 MSPS

with f

IN

05491-085

Rev. A | Page 13 of 44

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 62.500

15.625 31.250 46.875

FREQUENCY (MHz)

Figure 29. AD9246 Noise Power Ratio (NPR)

05491-089

AD9246

SNR/SFDR (dBc)

100

95

90

85

80

75

SFDR

SNR

10

8

6

4

NUMBER OF HIT S (1M)

2

1.3 LSB rms

70

5 125

25 45 65 85 105

CLOCK FREQUE NCY (MSPS)

Figure 30. AD9246 Single-Tone SNR/SFDR vs. Clock Frequency (f

= 2.4 MHz

with f

IN

100

SFDR DCS ON

95

90

85

80

75

SNR/SFDR (dBc)

70

65

60

Figure 31. AD9246 SNR/SFDR vs. Duty Cycle with f

90

85

80

SNR/SFDR (dBc)

75

70

SFDR DCS OFF

SNR DCS ON

SNR DCS OFF

20 80

SFDR

0.5 1.3

0.6 0.7 0. 8 0.9 1. 0 1.1 1.2

40 60

DUTY CYCLE (%)

SNR

INPUT COMMON-MODE VOLTAGE (V)

= 10.3 MHz

IN

Figure 32. AD9246 SNR/SFDR vs. Input Common Mode (VCM)

= 30 MHz

with f

IN

0

N – 4

N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4

05491-030

)

S

INL ERROR (LSB)

05491-027

DNL ERROR (LSB)

05491-031

Figure 33. AD9246 Grounded Input Histogram

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0 16384

2048 4096 6144 8192 10240 12288 14336

Figure 34. AD9246 INL with f

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

0 16384

2048 4096 6144 8192 10240 12288 14336

Figure 35. AD9246 DNL with f

OUTPUT CODE

OUTPUT CODE

OUTPUT CODE

= 10.3 MHz

IN

= 10.3 MHz

IN

05491-084

05491-024

05491-021

Rev. A | Page 14 of 44

AD9246

THEORY OF OPERATION

The AD9246 architecture consists of a front-end sample-and­hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 14-bit result in the digital correction logic. The pipeline
architecture permits the first stage to operate on a new input
sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.

The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The output
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power down, the output buffers
go into a high impedance state.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9246 is a differential switched
capacitor SHA that has been designed for optimum
performance while processing a differential input signal.

The clock signal alternately switches the SHA between sample
mode and hold mode (see
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source.

A shunt capacitor can be placed across the inputs to provide
dynamic charging currents. This passive network creates a low­pass filter at the ADC input; therefore, the precise values are
dependent on the application.

In IF undersampling applications, any shunt capacitors should
be reduced. In combination with the driving source impedance,
these capacitors would limit the input bandwidth.

Figure 36). When the SHA is

For more information, see Application Notes

Domain Response of Switched-Capacitor ADCs; and
A Resonant Approach to Interfacing Amplifiers to Switched­Capacitor ADCs, and the Analog Dialogue article,

Coupled Front-End for Wideband A/D Converters.”

VIN+

VIN–

S

C

PIN, PAR

C

PIN, PAR

S

Figure 36. Switched Capacitor SHA Input

C

S

H

C

S

For best dynamic performance, the source impedances driving
VIN+ and VIN− should match such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.

An internal differential reference buffer creates two reference
voltages used to define the input span of the ADC core. The
span of the ADC core is set by the buffer to be 2 × VREF. The
reference voltages are not available to the user. Two bypass
points, REFT and REFB, are brought out for decoupling to
reduce the noise contributed by the internal reference buffer.
It is recommended that REFT be decoupled to REFB by a 0.1 F
capacitor, as described in the

Layout Considerations section.

Input Common Mode

The analog inputs of the AD9246 are not internally dc-biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device such that V
recommended for optimum performance; however, the device
functions over a wider range with reasonable performance (see
Figure 32). An on-board, common-mode voltage reference is
included in the design and is available from the CML pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the CML pin voltage
(typically 0.55 × AVDD). The CML pin must be decoupled to
ground by a 0.1 F capacitor, as described in the
Considerations

section.

AN-742, Frequency

AN-827,

“Transformer-

S

C

H

C

H

S

= 0.55 × AVDD is

CM

Layout

05491-037

Rev. A | Page 15 of 44

AD9246

A

V

DIFFERENTIAL INPUT CONFIGURATIONS

Optimum performance is achieved by driving the AD9246 in
a differential input configuration. For baseband applications,
the AD8138 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the AD8138 is easily set with the CML pin of the
AD9246 (see Figure 37), and the driver can be configured in
a Sallen-Key filter topology to provide band limiting of the
input signal.

1V p-p

For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration (see Figure 38). The CML voltage can be
connected to the center tap of the secondary winding of the
transformer to bias the analog input.

The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can cause core
saturation, which leads to distortion.

49.9Ω

0.1µF

499Ω

523Ω

499Ω

AD8138

499Ω

R

C

R

Figure 37. Differential Input Configuration Using the AD8138

R

2V p-p

49.9Ω

0.1µF

C

R

Figure 38. Differential Transformer-Coupled Configuration

VIN+

VIN–

VIN+

AD9246

VIN–

AVDD

AD9246

CML

CML

05491-038

05491-039

At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9246. For applications where
SNR is a key parameter, transformer coupling is the recom­mended input.

For applications where SFDR is a key parameter, differential
double balun coupling is the recommended input configuration
(see Figure 40).

As an alternative to using a transformer-coupled input at
frequencies in the second Nyquist zone, the AD8352 differential
driver can be used (see Figure 41).

In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and source impedance and
may need to be reduced or removed. Table 8 displays recom­mended values to set the RC network. However, these values are
dependent on the input signal and should only be used as a
starting guide.

Table 8. RC Network Recommended Values

Frequency Range (MHz) R Series (Ω) C Differential (pF)

0 to 70 33 15
70 to 200 33 5
200 to 300 15 5
>300 15 Open

Single-Ended Input Configuration

Although not recommended, it is possible to operate the
AD9246 in a single-ended input configuration, as long as the
input voltage swing is within the AVDD supply. Single-ended
operation can provide adequate performance in cost-sensitive
applications.

In this configuration, SFDR and distortion performance
degrade due to the large input common-mode swing. If the
source impedances on each input are matched, there should be
little effect on SNR performance. Figure 39 details a typical
single-ended input configuration.

10µF

1V p-p

49.9Ω

10µF

0.1µF

0.1µF

Figure 39. Single-Ended Input Configuration

DD

1kΩ

R

1kΩ

AVD D

Rev. A | Page 16 of 44

1kΩ

1kΩ

C

R

VIN+

AD9246

VIN–

05491-042

AD9246

V

A

A

2V p-p

0.1µF

S

SP

A

Figure 40. Differential Double Balun Input Configuration

0.1µF

25Ω

P

0.1µF

CC

25Ω

0.1µF

R

C

R

VIN+

AD9246

VIN–

CML

05491-080

NALOG INPUT

NALOG INPUT

0.1µF

C

D

0.1µF

0Ω

16

1

2

R

R

D

G

3

4

5

0Ω

8, 13

AD8352

14

0.1µF

0.1µF

11

10

0.1µF

0.1µF

200Ω

200Ω

R

R

0.1µF

VIN+

C

AD9246

VIN–

CML

05491-081

Figure 41. Differential Input Configuration Using the AD8352

Table 9. Reference Configuration Summary

Resulting Differential

Selected Mode SENSE Voltage Resulting VREF (V)

Span (V p-p)

External Reference AVDD N/A 2 × External Reference
Internal Fixed Reference VREF 0.5 1.0
Programmable Reference 0.2 V to VREF

R2

⎛
⎜
⎝

⎞

+×

15.0

(see Figure 43)

⎟

R1

⎠

2 × VREF

Internal Fixed Reference AGND to 0.2 V 1.0 2.0

VOLTAGE REFERENCE

A stable and accurate voltage reference is built into the AD9246.
The input range is adjustable by varying the reference voltage
applied to the AD9246, using either the internal reference or an
externally applied reference voltage. The input span of the ADC
tracks reference voltage changes linearly. The various reference
modes are summarized in the following sections. The
Decoupling

section describes the best practices and require-

ments for PCB layout of the reference.

Reference

If a resistor divider is connected external to the chip as shown

Figure 43, the switch sets to the SENSE pin. This puts the

in
reference amplifier in a noninverting mode with the VREF
output defined as

VREF 15.0

⎛
⎜
⎝

+=

⎟

R1

⎠

R2

⎞

If the SENSE pin is connected to AVDD, the reference amplifier
is disabled, and an external reference voltage can be applied to
the VREF pin (see the

External Reference Operation section).

Internal Reference Connection

A comparator within the AD9246 detects the potential at the
SENSE pin and configures the reference into four possible
states, as summarized in

Tabl e 9. If SENSE is grounded, the

The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.

reference amplifier switch is connected to the internal resistor
divider (see

Figure 42), setting VREF to 1 V.

Connecting the SENSE pin to VREF switches the reference
amplifier input to the SENSE pin, completing the loop and
providing a 0.5 V reference output.

Rev. A | Page 17 of 44

AD9246

External Reference Operation

The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac­teristics.

Figure 45 shows the typical drift characteristics of the

internal reference in both 1 V and 0.5 V modes.

10

8

6

0.1µF0.1µF

SENSE

VIN+

VIN–

VREF

SELECT

LOGIC

ADC

CORE

––

REFT

0.1µF

REFB

0.5V

VREF = 1V

VREF = 0.5V

AD9246

05491-043

Figure 42. Internal Reference Configuration

VIN+

VIN–

VREF

0.1µF0.1µF

R2

SENSE

R1

SELECT

LOGIC

CORE

ADC

0.5V

AD9246

––

REFT

0.1µF

REFB

05491-044

Figure 43. Programmable Reference Configuration

If the internal reference of the AD9246 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered.

Figure 44 depicts

how the internal reference voltage is affected by loading.

0

VREF = 0.5V

–0.25

VREF = 1V

–0.50

4

2

REFERENCE VOL TAGE ERROR (mV)

0

–40

–20

0 204060

TEMPERATURE ( °C)

80

05491-036

Figure 45. Typical VREF Drift

When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
resistor divider loads the external reference with an equivalent
6 kΩ load (see

Figure 11). In addition, an internal buffer
generates the positive and negative full-scale references for the
ADC core. Therefore, the external reference must be limited to
a maximum of 1 V.

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9246 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ pin and the
CLK− pin via a transformer or capacitors. These pins are biased
internally (see

Clock Input Options

The AD9246 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal used, the jitter of the clock
source is of the most concern (see the
section).

Figure 5) and require no external bias.

Jitter Considerations

–0.75

–1.00

REFERENCE VOL TAGE ERROR ( %)

–1.25

0

0.5 1.0 1.5

LOAD CURRENT (mA)

Figure 44. VREF Accuracy vs. Load

Figure 46 shows one preferred method for clocking the
AD9246. A low jitter clock source is converted from single­ended to a differential signal using an RF transformer. The
back-to-back Schottky diodes across the transformer secondary
limit clock excursions into the AD9246 to approximately

0.8 V p-p differential. This helps prevent the large voltage

2.0

05491-033

swings of the clock from feeding through to other portions of
the AD9246, while preserving the fast rise and fall times of the
signal, which are critical to a low jitter performance.

Rev. A | Page 18 of 44

AD9246

MIN-CIRCUITS

CLOCK

INPUT

50Ω

ADT1–1WT, 1:1Z

100Ω

XFMR

0.1µF

0.1µF0.1µF

0.1µF

SCHOTTKY

DIODES:

HSMS2812

CLK+

ADC

AD9246

CLK–

Figure 46. Transformer Coupled Differential Clock

If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins, as shown in

AD9513/AD9514/AD9515

Figure 47. The AD9510/AD9511/AD9512/

family of clock drivers offers excel-

lent jitter performance.

CLOCK

INPUT

CLOCK

INPUT

1

50Ω

1

50Ω RESIST ORS ARE OPTIONAL

0.1µF

CLK

AD951x

PECL DRIV ER

0.1µF

CLK

1

50Ω

Figure 47. Differential PECL Sample Clock

0.1µF

CLK+

100Ω

0.1µF

240Ω240Ω

ADC

AD9246

CLK–

A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in
AD9511/AD9512/AD9513/AD9514/AD9515

Figure 48. The AD9510/

family of clock

drivers offers excellent jitter performance.

CLOCK

INPUT

CLOCK

INPUT

50Ω

1

50Ω RESISTO RS ARE OPTIONAL

0.1µF

0.1µF

1

50Ω

Figure 48. Differential LVDS Sample Clock

CLK

AD951x

LVDS DRIV ER

CLK

1

0.1µF

100Ω

0.1µF

CLK+

ADC

AD9246

CLK–

In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
directly drive CLK+ from a CMOS gate, while bypassing the
CLK− pin to ground using a 0.1 F capacitor in parallel with a
39 kΩ resistor (see

Figure 49). CLK+ may be directly driven
from a CMOS gate. This input is designed to withstand input
voltages up to 3.6 V, making the selection of the drive logic
voltage very flexible. When driving CLK+ with a 1.8 V CMOS
signal, biasing the CLK− pin with a 0.1 F capacitor in parallel
with a 39 kΩ resistor (see

Figure 49) is required. The 39 kΩ
resistor is not required when driving CLK+ with a 3.3 V CMOS
signal (see

Figure 50).

CLOCK

INPUT

05491-048

CLOCK

INPUT

1

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may

05491-049

be sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.

The AD9246 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling, or falling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9246. Noise and distortion performance are nearly flat
for a wide range of duty cycles when the DCS is on, as shown in
Figure 31.

Jitter in the rising edge of the input is still of paramount
concern and is not reduced by the internal stabilization circuit.
The duty cycle control loop does not function for clock rates

05491-050

less than 20 MHz nominally. The loop has a time constant
associated with it that needs to be considered in applications
where the clock rate can change dynamically. This requires a
wait time of 1.5 s to 5 s after a dynamic clock frequency
increase (or decrease) before the DCS loop is relocked to the
input signal. During the time period the loop is not locked, the
DCS loop is bypassed, and the internal device timing is
dependent on the duty cycle of the input clock signal. In such
an application, it may be appropriate to disable the duty cycle
stabilizer. In all other applications, enabling the DCS circuit is
recommended to maximize ac performance.

VCC

0.1µF

1kΩ

AD951x

1

50Ω

1

50Ω RESISTOR IS OPTIONAL

CMOS DRIVER

1kΩ

0.1µF

OPTIONAL

100Ω

39kΩ

Figure 49. Single-Ended 1.8 V CMOS Sample Clock

VCC

0.1µF

1kΩ

AD951x

1

50Ω

50Ω RESISTOR I S OPTI ONAL

CMOS DRIVER

1kΩ

OPTIONAL

100Ω

Figure 50. Single-Ended 3.3 V CMOS Sample Clock

0.1µF

0.1µF

0.1µF

CLK+

ADC

AD9246

CLK–

CLK+

ADC

AD9246

CLK–

05491-051

05491-052

Rev. A | Page 19 of 44

AD9246

The DCS can be enabled or disabled by setting the SDIO/DCS
pin when operating in the external pin mode (see
via the SPI, as described in

Tabl e 13.

Table 1 0), or

Table 10. Mode Selection (External Pin Mode)

Voltage at Pin SCLK/DFS SDIO/DCS

AGND Binary (default) DCS disabled
AVDD Twos complement

DCS enabled
(default)

JITTER CONSIDERATIONS

High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (f

SNR = −20 log (2π × f

In the equation, the rms aperture jitter represents the root mean
square of all jitter sources, which include the clock input, analog
input signal, and ADC aperture jitter specification. IF under­sampling applications are particularly sensitive to jitter, as
illustrated in

SNR (dBc)

Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9246. Power supplies
for clock drivers should be separated from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
The power supplies should also not be shared with analog input
circuits, such as buffers, to avoid the clock modulating onto the
input signal or vice versa. Low jitter, crystal-controlled oscillators
make the best clock sources. If the clock is generated from
another type of source (by gating, dividing, or other methods),
it should be retimed by the original clock at the last step.

Refer to Application Notes

ADC System Performance, and
the Effects of Clock Phase Noise and Jitter, for more in-depth

information about jitter performance as it relates to ADCs.

) due to jitter (tJ) is calculated as follows:

IN

× tJ)

IN

Figure 51.

75

70

MEASURED

PERFORMANCE

65

60

55

50

45

40

1 10 100 1000

INPUT FREQUENCY (MHz)

0.05ps

0.20ps

0.5ps

1.0ps

1.50ps

2.00ps

2.50ps

3.00ps

Figure 51. SNR vs. Input Frequency and Jitter

AN-501, Aperture Uncertainty and

AN-756, Sampled Systems and

05491-083

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 52 and Figure 53, the power dissipated by
the AD9246 is proportional to its sample rate. The digital power
dissipation is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current (I

where N is the number of output bits, 14 in the case of the
AD9246.

This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency, f
established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal. Reducing the capacitive load
presented to the output drivers can minimize digital power
consumption. The data in
under the same operating conditions as the data for the
Performance Characteristics
output driver.

475

450

425

400

POWER (mW)

375

350

325

Figure 52. AD9246-125 Power and Current vs. Clock Frequency f

410

390

370

350

330

310

POWER (mW)

290

270

250

Figure 53. AD9246-105 Power and Current vs. Clock Frequency f

) can be calculated as:

DRVDD

DRVDDDRVDD

IAVDD

TOTAL POWER

01

0

25 50 75 100

IAVDD

25 50 75 100

f

CVI

LOAD

/2. In practice, the DRVDD current is

CLK

CLK

N

×××=

2

Figure 52 and Figure 53 was taken

section, with a 5 pF load on each

IDRVDD

CLOCK FREQUE NCY (MSPS)

TOTAL POWER

IDRVDD

CLOCK FREQUE NCY (MSPS)

Ty pi ca l

250

200

150

100

CURRENT (mA)

50

0

25

05491-034

200

180

160

140

120

100

80

60

40

20

0

CURRENT (mA)

05491-068

= 30 MHz

IN

= 30 MHz

IN

Rev. A | Page 20 of 44

AD9246

290

275

260

245

POWER (mW)

230

215

0

IAVDD

TOTAL POWER

IDRVDD

20 40 60

CLOCK FREQUE NCY (MSPS)

Figure 54. AD9246-80 Power and Current vs. Clock Frequency f

Power-Down Mode

By asserting the PDWN pin high, the AD9246 is placed in
power-down mode. In this state, the ADC typically dissipates

1.8 mW. During power-down, the output drivers are placed in
a high impedance state. Reasserting the PDWN pin low returns
the AD9246 to its normal operational mode. This pin is both

1.8 V and 3.3 V tolerant.

Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and then must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in power-down mode;
and shorter power-down cycles result in proportionally shorter
wake-up times. With the recommended 0.1 µF decoupling
capacitors on REFT and REFB, it takes approximately 0.25 ms
to fully discharge the reference buffer decoupling capacitors and

0.35 ms to restore full operation.

Standby Mode

When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required (see the

Memory Map section).

DIGITAL OUTPUTS

The AD9246 output drivers can be configured to interface with

1.8 V to 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.

150

120

90

60

30

0

80

= 30 MHz

IN

As detailed in the

Manual

, the data format can be selected for either offset binary,

Interfacing to High Speed ADCs via SPI User

twos complement, or Gray code when using the SPI control.

Out-of-Range (OR) Condition

An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR is a digital output
that is updated along with the data output corresponding to the

CURRENT (mA)

particular sampled input voltage. Thus, OR has the same pipeline
latency as the digital data.

OR DATA OUTPUTS

1

1111

1111

11

0

1111

1111

11

0

1111

1111

11

05491-091

0

0000

00
0
1

0000

0000

00

0000

0000

00

0000

1111
1111
1110

0001
0000
0000

OR

–FS + 1/2 L SB

–FS – 1/2 LSB

Figure 55. OR Relation to Input Voltage and Output Data

+FS – 1 LS B

+FS–FS

+FS – 1/2 L SB

05491-088

OR is low when the analog input voltage is within the analog
input range and high when the analog input voltage exceeds the
input range, as shown in

Figure 55. OR remains high until the
analog input returns to within the input range, and another conver­sion is completed. By logically AND’ing the OR bit with the MSB
and its complement, overrange high or underrange low conditions
can be detected.
underrange circuit in

MSB

OR

MSB

Tabl e 1 1 is a truth table for the overrange/

Figure 56, which uses NAND gates.

OVER = 1

UNDER = 1

Figure 56. Overrange/Underrange Logic

05491-087

Table 11. Overrange/Underrange Truth Table

OR MSB Analog Input Is:

0 0 Within range
0 1 Within range
1 0 Underrange
1 1 Overrange

Digital Output Enable Function (OEB)

The AD9246 has three-state ability. If the OEB pin is low, the
output data drivers are enabled. If the OEB pin is high, the
output data drivers are placed in a high impedance state. This is
not intended for rapid access to the data bus. Note that OEB is
referenced to the digital supplies (DRVDD) and should not
exceed that supply voltage.

The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when operat­ing in the external pin mode (see

Table 1 0).

Rev. A | Page 21 of 44

AD9246

TIMING

The lowest typical conversion rate of the AD9246 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.

The AD9246 provides latched data outputs with a pipeline delay
of 12 clock cycles. Data outputs are available one propagation
delay (t

The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9246. These transients can degrade the dynamic performance
of the converter.

Table 12. Output Data Format

Input (V) Condition (V) Binary Output Mode Twos Complement Mode

VIN+ – VIN– < –VREF – 0.5 LSB 00 0000 0000 0000 10 0000 0000 0000 11 0000 0000 0000 1
VIN+ – VIN– = –VREF 00 0000 0000 0000 10 0000 0000 0000 11 0000 0000 0000 0
VIN+ – VIN– = 0 10 0000 0000 0000 00 0000 0000 0000 00 0000 0000 0000 0
VIN+ – VIN– = +VREF – 1.0 LSB 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000 0
VIN+ – VIN– > +VREF – 0.5 LSB 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000 1

) after the rising edge of the clock signal.

PD

Data Clock Output (DCO)

The AD9246 provides a data clock output (DCO) intended for
capturing the data in an external register. The data outputs are valid
on the rising edge of DCO, unless the DCO clock polarity has
been changed via the SPI. See

Figure 2 for a graphical timing

description.

Gray Code Mode
(SPI accessible)

OR

Rev. A | Page 22 of 44

AD9246

SERIAL PORT INTERFACE (SPI)

The AD9246 serial port interface (SPI) allows the user to
configure the converter for specific functions or operations
through a structured register space provided inside the ADC.
This provides the user added flexibility and customization,
depending on the application. Addresses are accessed via the
serial port and can be written to or read from via the port.
Memory is organized into bytes that are further divided into
fields, as documented in the
operational information, see the

via SPI User Manual

.

Memory Map section. For detailed

Interfacing to High Speed ADCs

CONFIGURATION USING THE SPI

As summarized in Tabl e 13 , three pins define the SPI of this ADC.
The SCLK/DFS pin synchronizes the read and write data
presented to the ADC. The SDIO/DCS dual purpose pin allows
data to be sent and read from the internal ADC memory map
registers. The CSB pin is an active low control that enables or
disables the read and write cycles.

Table 13. Serial Port Interface Pins

Pin Name Function

SCLK/DFS

SDIO/DCS

CSB

The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing.
Tabl e 1 4 provide examples of the serial timing and its definitions.

Other modes involving the CSB are available. The CSB can be
held low indefinitely to permanently enable the device (this is
called streaming). The CSB can stall high between bytes to allow
for additional external timing. When CSB is tied high, SPI
functions are placed in a high impedance mode. This mode
turns on any SPI pin secondary functions.

During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and the length is determined
by the W0 bit and the W1 bit. All data is composed of 8-bit
words. The first bit of each individual byte of serial data
indicates whether a read or write command is issued. This
allows the serial data input/output (SDIO) pin to change
direction from an input to an output.

SCLK (serial clock) is the serial shift clock in. SCLK
synchronizes serial interface reads and writes.
SDIO (serial data input/output) is a dual purpose
pin. The typical role for this pin is an input and
output, depending on the instruction being sent
and the relative position in the timing frame.
CSB (chip select bar) is an active low control that
gates the read and write cycles.

Figure 57 and

In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip as well as read the
contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an
output at the appropriate point in the serial frame.

Data can be sent in MSB- or in LSB-first mode. MSB first is the
default on power up and can be changed via the configuration
register. For more information, see the
ADCs via SPI User Manual

Table 14. SPI Timing Diagram Specifications

Name Description

tDS Setup time between data and rising edge of SCLK
tDH Hold time between data and rising edge of SCLK
t

Period of the clock

CLK

tS Setup time between CSB and SCLK
tH Hold time between CSB and SCLK
tHI

tLO

Minimum period that SCLK should be in a logic
high state

Minimum period that SCLK should be in a logic
low state

.

Interfacing to High Speed

HARDWARE INTERFACE

The pins described in Ta b l e 13 comprise the physical interface
between the user’s programming device and the serial port of
the AD9246. The SCLK and CSB pins function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.

The SPI interface is flexible enough to be controlled by either
PROM or PIC microcontrollers. This provides the user with the
ability to use an alternate method to program the ADC. One
method is described in detail in the Application Note
Microcontroller-based Serial Port Interface Boot Circuit.

When the SPI interface is not used, some pins serve a dual
function. When strapped to AVDD or ground during device
power-on, the pins are associated with a specific function.

AN-812,

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers,
the SDIO/DCS and SCLK/DFS pins serve as stand-alone
CMOS-compatible control pins. When the device is powered
up, it is assumed that the user intends to use the pins as static
control lines for the output data format and duty cycle stabilizer
(see

Tabl e 10 ). In this mode, the CSB chip select should be
connected to AVDD, which disables the serial port interface.
For more information, see the
via SPI User Manual

.

Interfacing to High Speed ADCs

Rev. A | Page 23 of 44

AD9246

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight address
locations. The memory map is roughly divided into three
sections: the chip configuration registers map (Address 0x00 to
Address 0x02), the device index and transfer registers map
(Address 0xFF), and the ADC functions map (Address 0x08 to
Address 0x18).

Default Values

Coming out of reset, critical registers are loaded with default
values. The default values for the registers are shown in

Logic Levels

An explanation of two registers follows:

• “Bit is set” is synonymous with “Bit is set to Logic 1” or

“Writing Logic 1 for the bit.”

Tabl e 15 .

Tabl e 1 5 displays the register address number in hexadecimal in
the first column. The last column displays the default value for
each hexadecimal address. The Bit 7 (MSB) column is the start
of the default hexadecimal value given. For example, Hexadecimal
Address 0x14, output_phase, has a hexadecimal default value of
0x00. This means Bit 3 = 0, Bit 2 = 0, Bit 1 = 1, and Bit 0 = 1 or
0011 in binary. This setting is the default output clock or DCO
phase adjust option. The default value adjusts the DCO phase
90° relative to the nominal DCO edge and 180° relative to the
data edge. For more information on this function, consult the

Interfacing to High Speed ADCs via SPI User Manual.

Open Locations

Locations marked as open are currently not supported for this
device. When required, these locations should be written with
0s. Writing to these locations is required only when part of an
address location is open (for example, Address 0x14). If the
entire address location is open (Address 0x13), then the address
location does not need to be written.

• “Clear a bit” is synonymous with “Bit is set to Logic 0” or

“Writing Logic 0 for the bit.”

SPI-Accessible Features

A list of features accessible via the SPI and a brief description of
what the user can do with these features follow. These features
are described in detail in the
SPI User Manua l

.

Interfacing to High Speed ADCs via

• Modes: Set either power-down or standby mode.

• Clock: Access the DCS via the SPI.

• Offset: Digitally adjust the converter offset.

• Tes t I/ O: Set test modes to have known data on output bits.

• Output Mode: Set up outputs; vary the strength of the

output drivers.

• Output Phase: Set the output clock polarity.

• VREF: Set the reference voltage.

CSB

SCLK

SDIO

DON’T CARE

t

DS

t

S

R/W W1 W0 A12 A11 A10 A9 A8 A7

t

DH

t

HI

Figure 57. Serial Port Interface Timing Diagram

t

CLK

t

LO

Rev. A | Page 24 of 44

D5 D4 D3 D2 D1 D0

t

H

DON’T CARE

DON’T CAREDON’T CARE

05491-056

AD9246

MEMORY MAP REGISTER TABLE

Table 15. Memory Map Register

Default
Addr.
(Hex)

Chip Configuration Registers

00 chip_port_config 0 LSB first

01 chip_id 8-bit Chip ID Bits 7:0

02 chip_grade Open Open Open Open Child ID

Device Index and Transfer Registers

FF device_update Open Open Open Open Open Open Open SW transfer 0x00 Synchronously

Global ADC Functions

08 modes Open Open PDWN

09 clock Open Open Open Open Open Open Open Duty cycle

Parameter Name

Bit 7
(MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

0 = Off
(Default)
1 = On

Soft reset
0 = Off

(Default)
1 = On

0—full
(Default)

1—standby

1 1 Soft reset

0 = Off
(Default)
1 = On

(AD9246 = 0x00), (default)

Open Open Open Read
0 = 125
MSPS,
1 = 105
MSPS

Open Open Internal power-down mode

000—normal (power-up, Default)

001—full power-down

010—standby

011—normal (power-up)

Note: External PDWN pin overrides

this setting.

LSB first
0 = Off

(Default)
1 = On

Bit 0
(LSB)

0 0x18 The nibbles

stabilizer
0—disabled
1— enabled
(Default)

Value
(Hex)

Read
only

only

0x00 Determines

Default Notes/
Comments

should be
mirrored. See the

Interfacing to
High Speed ADCs
via SPI User

.

Manual

Default is unique
chip ID, different
for each device.

Child ID used to
differentiate
speed grades.

transfers data
from the master
shift register to
the slave.

various generic
modes of chip
operation. See
the

Power
Dissipation
and Standby
Mode

section

SPI-

and the

Accessible

0x01

Features

section.

See the

Duty Cycle

section and the

Clock

SPI-Accessible
Features

section.

Rev. A | Page 25 of 44

AD9246

Addr.
(Hex)

Flexible ADC Functions

10 offset

0D test_io PN23

14 output_mode Output Driver

16 output_phase Output Clock

18 VREF Internal Reference

1

Parameter Name

External output enable (OEB) pin must be high.

Bit 7
(MSB)

Configuration
00 for DRVDD = 2.5 V to

3.3 V (Default)
10 for DRVDD = 1.8 V

Polarity
1 = inverted
0 = normal
(Default)

Resistor Divider
00—VREF = 1.25 V

01—VREF = 1.5 V
10—VREF = 1.75 V
11—VREF = 2.00 V
(Default)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Open Open Open Open Open Open Open 0x00

Digital Offset Adjust<5:0>
011111
011110
011101
…
000010
000001
000000
111111
111110
111101
...
100001
100000

PN9
0 =
normal
(Default)
1 = reset

Open Output

Open Open Open Open Open Open 0xC0

0 =

normal

(Default)

1 =

reset

Disable

1—

disabled

0—

enabled

Global Output Test Options

Open Output

1

Offset in LSBs

+31
+30
+29

+2
+1
0 (Default)
1

−2

−3

−31

−32

000—off (Default)
001—midscale short

010—+FS short
011—−FS short

100—checker board output
101—PN 23 sequence
110—PN 9
111—one/zero word toggle

Data
Invert
1 =
invert

Bit 0
(LSB)

Data Format Select
00—offset binary
(default)
01—twos
complement
10—Gray Code

Default
Value
(Hex)

0x00 Adjustable for

Default Notes/
Comments

offset inherent
in the converter.
See the

SPI­Accessible
Features

section.

0x00 See the

Interfacing to
High Speed
ADCs via SPI

User Manual

0x00 Configures the

outputs and
the format of
the data.

See the

.

SPI­Accessible
Features

section.

See the

SPI­Accessible
Features

section.

Rev. A | Page 26 of 44

AD9246

LAYOUT CONSIDERATIONS

POWER AND GROUND RECOMMENDATIONS

When connecting power to the AD9246, it is recommended
that two separate supplies be used: one for analog (AVDD, 1.8 V
nominal) and one for digital (DRVDD, 1.8 V to 3.3 V nominal).
If only a single 1.8 V supply is available, it is routed to AVDD
first, then tapped off and isolated with a ferrite bead or filter
choke with decoupling capacitors proceeding connection to
DRVDD. The user can employ several different decoupling
capacitors to cover both high and low frequencies. These should
be located close to the point of entry at the PC board level and
close to the parts with minimal trace length.

A single PC board ground plane is sufficient when using the
AD9246. With proper decoupling and smart partitioning of
analog, digital, and clock sections of the PC board, optimum
performance is easily achieved.

Exposed Paddle Thermal Heat Slug Recommendations

It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9246. An
exposed, continuous copper plane on the PCB should mate to
the AD9246 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.

To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous plane by overlaying a silkscreen
on the PCB into several uniform sections. This provides several
tie points between the two during the reflow process. Using one
continuous plane with no partitions guarantees only one tie
point between the ADC and PCB. See
example. For detailed information on packaging and the PCB
layout of chip scale packages, see

A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package.

Figure 58 for a PCB layout

Application Note AN-772,

CML

The CML pin should be decoupled to ground with a 0.1 F
capacitor, as shown in

RBIAS

The AD9246 requires the user to place a 10 kΩ resistor between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.

REFERENCE DECOUPLING

The VREF pin should be externally decoupled to ground with
a low ESR 1.0 F capacitor in parallel with a 0.1 F ceramic low
ESR capacitor. In all reference configurations, REFT and REFB
are bypass points provided for reducing the noise contributed
by the internal reference buffer. It is recommended that an external

0.1 F ceramic capacitor be placed across REFT/REFB. While
placement of this 0.1 F capacitor is not required, the SNR
performance degrades by approximately 0.1 dB without it. All
reference decoupling capacitors should be placed as close to the
ADC as possible with minimal trace lengths.

SILKSCREEN PARTITION

PIN 1 INDICATOR

Figure 58. Typical PCB Layout

Figure 38.

05491-057

Rev. A | Page 27 of 44

AD9246

EVALUATION BOARD

The AD9246 evaluation board provides all of the support
circuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially through
a double balun configuration (default) or through the

AD8352
differential driver. The ADC can also be driven in a single-ended
fashion. Separate power pins are provided to isolate the DUT
from the

AD8352 drive circuitry. Each input configuration can

be selected by proper connection of various components (see
Figure 60 to Figure 70). Figure 59 shows the typical bench
characterization setup used to evaluate the ac performance of
the AD9246.

It is critical that the signal sources used for the analog input and
clock have very low phase noise (<1 ps rms jitter) to realize the
optimum performance of the converter. Proper filtering of the
analog input signal to remove harmonics and lower the integrated
or broadband noise at the input is also necessary to achieve the
specified noise performance.

Figure 60 to Figure 64 for the complete schematics and

See
layout diagrams that demonstrate the routing and grounding
techniques that should be applied at the system level.

POWER SUPPLIES

This evaluation board comes with a wall-mountable switching
power supply that provides a 6 V, 2 A maximum output. Connect
the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz
to 63 Hz. The other end is a 2.1 mm inner diameter jack that
connects to the PCB at P500. Once on the PC board, the 6 V
supply is fused and conditioned before connecting to five low
dropout linear regulators that supply the proper bias to each of
the various sections on the board.

When operating the evaluation board in a nondefault condition,
L501, L503, L504, L508, and L509 can be removed to disconnect
the switching power supply. This enables the user to individually
bias each section of the board. Use P501 to connect a different
supply for each section. At least one 1.8 V supply is needed with
a 1 A current capability for AVDD_DUT and DRVDD_DUT;
however, it is recommended that separate supplies be used for
analog and digital. To operate the evaluation board using the
AD8352 option, a separate 5.0 V supply (AMP_VDD) with a
1 A current capability is needed. To operate the evaluation board
using the alternate SPI options, a separate 3.3 V analog supply
is needed, in addition to the other supplies. The 3.3 V supply
(AVDD_3.3V) should have a 1 A current capability, as well.
Solder Jumpers J501, J502, and J505 allow the user to combine
these supplies (see

INPUT SIGNALS

When connecting the clock and analog source, use clean signal
generators with low phase noise, such as Rohde & Schwarz SMHU
or Agilent HP8644 signal generators or the equivalent. Use
1-meter long, shielded, RG-58, 50 Ω coaxial cable for making
connections to the evaluation board. Enter the desired frequency
and amplitude for the ADC. Typically, most evaluation boards
from Analog Devices, Inc. can accept a ~2.8 V p-p or 13 dBm
sine wave input for the clock. When connecting the analog
input source, it is recommended to use a multipole, narrow­band, band-pass filter with 50 Ω terminations. Analog Devices
uses TTE®, Allen Avionics, and K&L® types of band-pass filters.
Connect the filter directly to the evaluation board, if possible.

OUTPUT SIGNALS

The parallel CMOS outputs interface directly with the Analog
Devices standard single-channel FIFO data capture board
(HSC-ADC-EVALB-SC). For more information on the FIFO
boards and their optional settings, visit

Figure 64 for more details).

www.analog.com/FIFO.

WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz

6V DC

SWITCHING

POWER
SUPPLY

ROHDE & SCHWARZ,

SMHU,

2V p-p SIGNAL

SYNTHESIZ ER

ROHDE & SCHWARZ,

SMHU,
2V p-p SIGNAL
SYNTHESIZER

2A MAX

BAND-PASS

FILTER

AIN

CLK

5.0V

–+

GND

AMP_VDD

1.8V

GND

2.5V

–+–+

GND

AVDD_DUT

AD9246

EVALUATION BOARD

–+

DRVDD_DUT

3.3V

GND

–+

VDL

PARALLEL

3.3V

GND

AVD D_3. 3V

14-BIT

CMOS

SPI SPISPI

3.3V

–+

VCC

GND

HSC-ADC-EVALB-SC

FIFO DATA

CAPTURE

BOARD

USB

CONNECTION

PC

RUNNING

ADC

ANALYZER

AND SPI

USER

SOFTWARE

05491-082

Figure 59. Evaluation Board Connection

Rev. A | Page 28 of 44

AD9246

DEFAULT OPERATION AND JUMPER SELECTION SETTINGS

The following is a list of the default and optional settings or
modes allowed on the AD9246 Rev. A evaluation board.

POWER

Connect the switching power supply that is supplied in the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P500.

VIN

The evaluation board is set up for a double balun configuration
analog input with optimum 50 Ω impedance matching out to
70 MHz. For more bandwidth response, the differential
capacitor across the analog inputs can be changed or removed
(see

Tabl e 8). The common mode of the analog inputs is
developed from the center tap of the transformer via the CML
pin of the ADC (see the

VREF

VREF is set to 1.0 V by tying the SENSE pin to ground via
JP507 (Pin 1 and Pin 2). This causes the ADC to operate in

2.0 V p-p full-scale range. A separate external reference option
is also included on the evaluation board. Connect JP507
between Pin 2 and Pin 3, connect JP501, and provide an
external reference at E500. Proper use of the VREF options is
detailed in the

RBIAS

RBIAS requires a 10 kΩ resistor (R503) to ground and is used to
set the ADC core bias current.

Volt a ge R e fe r enc e section.

CLOCK

The default clock input circuitry is derived from a simple
transformer-coupled circuit using a high bandwidth 1:1 impedance
ratio transformer (T503) that adds a very low amount of jitter to
the clock path. The clock input is 50 Ω terminated and ac-coupled
to handle single-ended sine wave inputs. The transformer converts
the single-ended input to a differential signal that is clipped
before entering the ADC clock inputs.

Analog Input Considerations section).

SCLK/DFS

If the SPI port is in external pin mode, the SCLK/DFS pin sets the
data format of the outputs. If the pin is left floating, the pin is
internally pulled down, setting the default condition to binary.
Connecting JP2 Pin 2 and Pin 3 sets the format to twos comple­ment. If the SPI port is in serial pin mode, connecting JP2 Pin 1
and Pin 2 connects the SCLK pin to the on-board SPI circuitry
(see the

Serial Port Interface (SPI) section).

SDIO/DCS

If the SPI port is in external pin mode, the SDIO/DCS pin acts
to set the duty cycle stabilizer. If the pin is left floating, the pin is
internally pulled up, setting the default condition to DCS enabled.
To disable the DCS, connect JP3 Pin 2 and Pin 3. If the SPI port
is in serial pin mode, connecting JP3 Pin 1 and Pin 2 connects the
SDIO pin to the on-board SPI circuitry (see the
Interface (SPI)

section).

Serial Port

ALTERNATIVE CLOCK CONFIGURATIONS

A differential LVPECL clock can also be used to clock the ADC
input using the
the components listed in
Consult the

To configure the analog input to drive the
the default transformer option, the following components need
to be added, removed, and/or changed.

1. Remove R507, R508, C532, and C533 in the default

clock path.

2. Populate R505 with a 0 Ω resistor and C531 in the default

clock path.

3. Populate R511, R512, R513, R515 to R524, U500, R580,

R582, R583, R584, C536, C537, and R586.

If using an oscillator, two oscillator footprint options are also
available (OSC500) to check the performance of the ADC.
JP508 gives the user flexibility in using the enable pin, which is
common on most oscillators. Populate OSC500, R575, R587,
and R588 to use this option.

AD9515 (U500). When using this drive option,

Table 1 6 need to be populated.

AD9515 data sheet for more information.

AD9515 instead of

PDWN

To enable the power-down feature, connect JP506, shorting the
PDWN pin to AVDD.

CSB

The CSB pin is internally pulled up, setting the chip into
external pin mode, to ignore the SDIO and SCLK information.
To connect the control of the CSB pin to the SPI circuitry on the
evaluation board, connect JP1 Pin 1 and Pin 2. To set the chip
into serial pin mode and enable the SPI information on the
SDIO and SCLK pins, tie JP1 low (connect Pin 2 and Pin 3) in
the always enabled mode.

Rev. A | Page 29 of 44

ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION

This section provides a brief description of the alternative
analog input drive configuration using the
using this particular drive option, some components need to be
populated, as listed in
differential driver, including how it works and its optional pin
settings, consult the

To configure the analog input to drive the
the default transformer option, the following components need
to be added, removed and/or changed.

Tabl e 1 6 . For more details on the AD8352

AD8352 data sheet.

AD8352. When

AD8352 instead of

AD9246

1. Remove C1 and C2 in the default analog input path.

2. Populate R3 and R4 with 200 Ω resistors in the analog

input path.

3. Populate the optional amplifier input path with all

components except R594, R595, and C502. Note that
to terminate the input path, only one of the following
components should be populated: R9, R592, or the
combination of R590 and R591.

4. Populate C529 with a 5 pF capacitor in the analog input path.

Currently, R561 and R562 are populated with 0 Ω resistors to
allow signal connection. This area allows the user to design a
filter, if additional requirements are necessary.

Rev. A | Page 30 of 44

AD9246

SCHEMATICS

2

DUTAVDD

D501

DNI

1

3

HSMS2812

2

DUTAVDD

D500

DNI

1

3

HSMS2812

DNI

.1UF

C502

DNI

R595

10K

AMPVDD

31

disable

R594

10K

DNI

J500

OPTIONAL AMP INPUT

AMPVDD

AMPOUT+

.1UF

C504

DNI

DNI

RC0402

0R535

12

11

GND

VCC

13

VCM

15

ENB

2

16 14

VIP

enable

0

R593

C500

DNI

.1UF

RDP

2

DNI

AMPOUT-

C505

DNI

.1UF

DNI

RC0402

R536 0

9

10

GND

VON

VOP

U511

RGP

R598

100

0.3PF

C501

4.3K

R597

DNI

R592

8

VCC

GND

67

5

VIN

AMPVDD

0

DNI

R596

.1UF

DNI

C503

AD8352

DNI

SIGNAL=GND;17

RGN

RDN

413

DNI DNI DNI

C529

CC0402

DNI

DNI

CML

RC0402

DNI

20PF

RC0402RC0402

213

VIN-

VIN-

RC0402

33

R567

RC0402

0

R562

.1UF

C510

25

R4

VIN+

AMPOUT-

C2

.1UF

4

When using R1, remove R3, R4,R6.

Replace C1, C2 w ith 0 oh m resistors.

ETC1-1-13

Replace R5 wi th 0.1UF cap

0

R5

RC0402

VIN+

R563

RC0402

RC0402

R566

33

R574

RC0402

RC0402

R561

0

0

R571

25

R3

AMPOUT+

RC0402

R565

C1

.1UF

5

T501

SP

05491-072

DNI

R590

DNI

R1

RC0402

CML

1234

SP

T500

ETC1-1-13

5

RC0402

0

R2

DOUBLE BALUN / XFMR INPUT

CC0402

0.1UF

C528

RC0603

R560

0

12

DNI

50

R502

GND;3 ,4,5

SMAEDGE

S500

Ain

6

T502

DNI

1

34

25

C509

.1UF

R6

DNI

RC0402

CML

CC0402

DNI

C3

RC0603

R7

DNI

12

RC0603

SMAEDGE

S503

When usi ng T502, remove T500, T501.

Repalce C1, C2 wi th 0 ohm resist ors.

Remove R3, R4. Place R6 , R502,.

R8

DNI

RC0603

GND;3 ,4,5

Ain/

DNI

0

C4

21

DNI

R10

0

SMA200UP

S504

25

R591

CC0402

RC0603

DNI

R9

GND;3,4,5

DNI

Ampin

25

DNI

2

1

SP

T1

DNI

5

43

C5

R12

RC0603

S505

DNI

CC0402

0

RC0603

DNI

0

12

R11

GND;3,4,5

SMA200UP

DNI

Ampin/

R590/R591,R9,R592 O nly one sh ould be install ed at a time.

Install all optional Amp input components.

Remove C1, C2.

Set R3=R4=200 OHM.

For ampl ifier (AD8352) :

DNI

0

RC0603

Figure 60. Evaluation Board Schematic, DUT Analog Inputs

Rev. A | Page 31 of 44

AD9246

JP3

2

13

SDIO_ODM

DUTAVDD

JP2

2

13

SCLK_DTP

JP1

2

13

CSB_DUT

C1C2C3C4C5C6C7C8C9

SDI_CHAFIFOCLK

B1B2B3B4B5B6B7B8B9

A1A2A3A4A5A6A7A8A9

FD13

FD13

FDOR

22

23

24

O14

O15

OE4

74VCX16224

I14

OE3

I15

25

27

26

VDL

710

611

22RP502

22RP502

D13

DOR

FD12

21

GND4

U509

GND5

28

CSB1_CHA

FD11

FD12

O13

I13

22RP502

D12

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

J503

SDO_CHA

SCLK_CHA

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

J503

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

J503

OUTPUT CONNECTOR

FD8

FD9

FD10

FD10

FD11

18

19

20

O11

O12

VCC2

VCC3

I11

I12

31

30

29

512

413

314

22RP502

22RP502

D11

D10

FD6

FD7

FD9

16

17

O10

GND3

GND6

I10

33

32

215

22RP502

D9

FD4

FD5

FD7

FD8

14

15

O8

O9

I9

I8

35

34

116

611

22RP502

22RP501

D8D7D6D5D4

FD0

FD1

FD2

FD3

FD6

13

O7

I7

36

512

22RP501

FDOR

FIFOCLK

FD0

FD1

FD2

FD3

FD4

FD5

VCC1

VCC4

42

22RP501

O2

O3

I2

I3

44

43

116

45

RP5002236RP5002227RP50022

D1

D2

GND1

GND8

45678

123

O0

O1

OE1

OE2

I0

I1

48

47

46

45

D0

DCO

9

10

11

12

O4

O5

O6

GND2

I5

I4

GND7

I6

41

40

39

38

37

413

314

215

22RP501

22RP501

22RP501

D3

05491-073

OUTPUT BUFFER

DUTAVDD

2425

AVDDSENSE

SENSE

DUT

23

AGND

VREF

26

VREF

710

22RP501

TP502

D3

D2

1

2

D2

D3

DRGND

DRVDD

DUTDRVDD

RP501 22

98

AD9246LFCSP

ESNESFERV_TXE

13

2

JP507

JP500

DUTAVDD

JP501

E500

RP502 22

98

TP503

TP501

D4

D5

D6

9

D8

D8

AVDD

DUTAVDD

8

DRVDD

AGND

42

JP502

D7

3

4

567

D4

D5

D6

D7

DRGND

U510

DCO

D1

OEB

AVDD

D0 (LSB)

45

44

464748

43

D0

DCO

DNI

D1

TP500

TP504

DUTDRVDD

17

18

19

20

21

22

CSB

AVDD

AGND

REFT

REFB

27

28

0.1UF

C554

CC0402

AGND

29

30

DRVDD

SDIO/DCS

SCLK/DFS

VIN+

VIN-

AGND

31

32

VIN-

VIN+

D12

D13

DOR

13

16

15

14

OR

D12

DRGND

D13 (MSB)

PDWN

CML

AVDD

RBIAS

34

33

35

36

R503

10K

CML

0.1UF

C556

D9

D10

D11

11

12

10

D9

D10

D11

EPAD

chip corn ers

CLK+

AGND

CLK-

394041

38

37

JP506

DNI

CLK

CLK

RC0603

CC0603

22RP500

81

VREF

R0402

R0402

DNI

DNI

R501

R500

DNI

DNI

1.0UF

C553

CC0805

C555

0.1UF

CC0402

Figure 61. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface

Rev. A | Page 32 of 44

AD9246

DNI

DNI

RC0603

R513 0

R515 0

RC0603

R525 0

R514 0

DNI

DNI

RC0603

RC0603

R516 0

R517 0

RC0603

RC0603

R527 0

DNI

R526 0

DNI

RC0603

RC0603

R520 0

R521 0

RC0603

RC0603

R531 0

DNI

R530 0

DNI

RC0603

RC0603

R519 0

R518 0

RC0603

RC0603

R529 0

R528 0

DNI

DNI

RC0603

RC0603

R524 0

RC0603

RC0603

R534 0

DNI

R533 0

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

RC0603

RC0603

R522 0

R523 0

RC0603

RC0603

DNI

R532 0

DNI

05491-071

AD9515 LOGIC SETUP

AVDD_3P3V

S1

S0

S3

S2

S5

S4

S7

S6

CLK

CC0402CC0402CC0402

0.1UF

C537

RC0402

DNI

100

R582

0.1UF

C533

CLK

CC0402CC0402

C532

0.1UF

C536

DNI

CLK

0.1UF

S9

S8

CLK

CC0402

DNI

R583

RC0402

R584

RC0402

S10

E502

240

DNI

240

DNI

E503

0.1UF

C535

0.1UF

C534

DNI

RC0402

DNI

100

R585

DNI

DNI

10K

R588

RC0402

DISABLE

2

JP508

ENABLE

DNI

153

31

OE

OE

DNI

DNI

10KR587

RC0402

GND

OSC500

VCC

VCC

OUT

10

14

12

AVDD_3P3V

0

R575

DNI

1

3

2

RC0603

0

R506

6

RC0603

D502

HSMS2812

0

R509

5

To use AD9515 (OPT _CLK), remove R507, R508, C533, C532.

Place C531,R505=0.

R586

RC0402

T503

R580

10K

1

2

34

C511

.1UF

78

GNDOUT

CB3LV-3C

RC0603

0

R507

0

R508

RC0402

OPT_CLK

0.1UF

C530

DNI

OPT_CLK

CC0402

0.1UF

C531

DNI

RC0603

RC0603

0

R512

CC0402

49.9

R504

RC0603

49.9

R505

DNI

RC0603

RC0402

AVDD_3P3V

DNI

R581

RC0402

R576

DNI

23

OUT0

DNI

33

RC0402

GND_PA D

31

4.12K

GND

32

RSET

U500

DNI

235

DNI

RC0402

21

RC0603

DNI

R510

OPT_CLK

18

19

22

OUT1

OUT0B

OUT1B

S10

25

S0

S9

16

S1

S8

15

S2

S7

14

S3

S6

13

S4

S5

12

S5

S4

11

S6

S3

10

S7

NC=27,28

S2

AD9515

9

S8

S1

8

S9

S0

7

S10

VREF

6

AVDD_3P3V;1,4,17,20,21,24,26,29,30

CLK

CLKB

SYNCB

E501

DNI

R577

RC0402

R578

DNI

RC0402

21

RC0603

R579

DNI

DNI

R511

OPT_CLK

XFMR/AD9515

Clock Circuitry

SMAEDGE

S501

SMAEDGE

S502

CLK/

GND;3,4 ,5

GND;3,4,5

CLK

Figure 62. Evaluation Board Schematic, DUT Clock Input

Rev. A | Page 33 of 44

AD9246

SDO_CHA

CSB1_CHA

SDI_CHA

SCLK_CHA

SDIO_ODM

R553

1K

RC0603

AVDD_3P3V

R551

1K

RC0603

DUTAVDD

6

Y1

VCC

A1

GND

U508

1K

R552

RC0603

4

Y2

NC7WZ07

A2

1325

RC0603

R550

10K

RC0603

0

R554

RC0603

0

R556

RC0603

0

R557

RC0603

0

R555

RC0603

AVDD_3P3V

R549

10K

CSB_DUT

SCLK_DTP

6

4

Y1

Y2

VCC

NC7WZ16

A1

GND

A2

U507

1325

RC0603

R548

10K

05491-070

RC0603

R546

4.7K DNI

RC0603

DNI

4.7K

R545

RC0603

R547

4.7K DNI

765

GP0

GP2

GP1

VSSVDD

DNI

REMOVE WHEN USING OR PROGRAMMING PIC (U506)

DDVPMAV3P3_DDVA

U506

GP5

GP4

3

2814

SOIC8

MCLR

DNI

2

JP509

13

+5V=PROGRAMMING ONLY=AMPVDD

+3.3V=NORMAL OPERATION=AVDD_3P3V

DNI

CC0603

0.1UF

C557

R558

4.7K

RC060 3

3

DNI

D505

21

PIC12F629

RC0603

Optional

R559

261

DNI

12

DNI

4

E504

1

PICVCC

34

GP1

56

GP0

78

MCL R-GP3

9

J504

DNI

2

PICVCC

GP1

GP0

MCL R-GP3

10

HEADER UP MALE

PIC-HEADER

For FIFO controlled port, populate R555, R556, R557.

When using PICSPI controlled port, populate R545, R546, R547.

When using PICSPI controlled port, remove R555, R556, R557.

DNI

S1

1

SPI CIRCUITRY

2

Figure 63. Evaluation Board Schematic, SPI Circuitry

Rev. A | Page 34 of 44

AD9246

AMPVDDIN

TP507

L501

10UH

LC1210

C522

1UF

4

23

1TUPTUOTUPNI

OUTPU T4

GND

1

AVDD_3.3V=3.3V

DUTDRVDD=2.5V

DUTAVDD=1.8V

VDL=3.3V

AMPVDD=5V

ADP3339AKC-5

U501

C523

1UF

PWR_IN

DUTAVDDIN

TP506

L504

10UH

LC1210

C518

4

23

1TUPTUOTUPNI

TP505

L503

10UH

1UF

AVDD_3P3V

TP513

L509

10UH

LC1210

C525

1UF

4

23

1TUPTUOTUPNI

0.1UF

C543

OUTPU T4

GND

1

ADP3339AKC-3.3

U505

C513

1UF

PWR_IN

DUTDRVDDIN

LC1210

C520

1UF

4

23

1TUPTUOTUPNI

VDLINPWR_IN

TP508

L508

10UH

LC1210

C526

1UF

4

23

1TUPTUOTUPNI

CC0402CC0402C C0402 CC0402

0.1UF

C546

0.1UF

C544

0.1UF

C545

AVDD_3P3V

0.1UF

C538

CC0402CC0402CC0402

0.1UF

C542

CC0402

0.1UF

C539

0.1UF

C540

AVDD_3P3V

H503

H502

H500

H501

GROUND

TEST POINTS

Connected to Ground

Mounting Hole s

TP509

TP512

TP511

TP510

0.1UF

C574

CC0603CC0603

05491-069

D503

Power Supply Input

U502

SHOT_RECT3ADO-214AB

FER500

CHOKE_COIL

F500

6V, 2A max

0.1UF

OUTPUT4

GND

1

ADP3339AKC-1.8

C519

1UF

PWR_IN

PWR_IN

CR50 0

21

34

D504

DO-214AA2AS2A_RECT

SMDC110F

C527

10UF

2

3

1

P500

OUTPUT4

GND

1

ADP3339AKC-2.5

U503

C521

1UF

PWR_IN

R589

261

CON005

7.5V POWER

2.5MM JAC K

OUTPUT4

GND

1

ADP3339AKC-3.3

U504

C524

1UF

0.1UF

C514

AMPVDD

6.3V

C549

1OUF

ACASE

L505

10UH

LC1210

OPTIONAL POWER CONNECTION

AMPVDDIN

123456789

P1P2P3P4P5P6P7P8P9

P501

L507

J505

GND

GND

DUTDRVDDIN

DUTAVDDIN

C559

0.1UF0.1UF

C558

0.1UF

C568

CC0603

0.1UF

C567

CC0603

AMPVDD

DUTAVDD

0.1UF

C515

VDL

6.3V

C550

1OUF

ACASE

L502

10UH

LC1210

GND

10UH

LC1210

GND

GND

VDLIN

AVDD_3P3VIN

10

P10

CC0603 CC0603

0.1UF

C565

0.1UF

C564

CC0603 CC0603

VDL

DUTDRVDD

0.1UF

C516

L506

C552

10UH

LC1210

6.3V

C551

1OUF

ACASE

J502

C570

CC0603

0.1UF

C566

CC0603

0.1UF

C575

0.1UF

C569

CC0603

DUTAVDD

AVDD_3P3V

0.1UF

C517

6.3V

1OUF

ACASE

J501

L500

0.1UF

C512

6.3V

C548

1OUF

ACASE

10UH

LC1210

0.1UF

C599C572

0.1UF

CC0603 CC0603

0.1UF

C573

CC0603

DUTDRVDD

Remove L501,L503, L504,L508,L 509.

To use optional power connection

Figure 64. Evaluation Board Schematic, Power Supply Inputs

Rev. A | Page 35 of 44

AD9246

EVALUATION BOARD LAYOUTS

Figure 65. Evaluation Board Layout, Primary Side

05491-077

Figure 66. Evaluation Board Layout, Secondary Side (Mirrored Image)

Rev. A | Page 36 of 44

5491-076

AD9246

Figure 67. Evaluation Board Layout, Ground Plane

05491-079

Figure 68. Evaluation Board Layout, Power Plane

Rev. A | Page 37 of 44

5491-078

AD9246

Figure 69. Evaluation Board Layout, Silkscreen Primary Side

05491-075

Figure 70. Evaluation Board Layout, Silkscreen Secondary Side (Mirrored Image)

Rev. A | Page 38 of 44

05491-074

AD9246

BILL OF MATERIALS

Table 16. Evaluation Board Bill of Materials (BOM)

Omit

Item Qty.

1 1 AD9246CE_REVA PCB PCB ADI
2

3 1 C501 Capacitor 0402 0.3 pF
4 2 C4, C5 Resistor 0402 0 Ω
5 10

6 1 C527 Capacitor 1206 10 F
7 1 C529 Capacitor 0402 20 pF
8 5 C548, C549, C550, C551, C552 Capacitor ACASE 10 F
9 1 C553 Capacitor 0805 1.0 F
10 15

24

12

(DNP)

Reference Designator Device Package Description Supplier/Part Number

C1, C2, C509, C510, C511, C512,
C514, C515, C516, C517, C528,
C530, C532, C533, C538, C539,
C540, C542, C543, C544, C545,
C546, C554, C555

C3, C500, C502, C503, C504,
C505, C531, C534, C535, C536,
C537, C557

C513, C518, C519, C520, C521,
C522, C523, C524, C525, C526

C556, C558, C559, C564, C565,
C566, C567, C568, C569, C570,
C572, C573, C574, C575, C599

Capacitor 0402 0.1 F

Capacitor 0402 1.0 F

Capacitor 0603 0.1 F

11 1 CR500 LED 0603 green

1 D502 12

13 1 D503 Diode DO-214AB 3 A, 30 V, SMC

14 1 D504 Diode DO-214AA 2 A, 50 V, SMC

15 1 D505 LED LN1461C AMB Amber LED
16 1 F500 Fuse 1210

17 1 FER500 Choke 2020

18 1 J500 Jumper Solder jumper
19 3 J501, J502, J505 Jumper Solder jumper
20 1 J503 Connector 120 pin Male header
21 1 J504 Connector 10 pin Male, 2 × 5 Samtec
22 3 JP1, JP2, JP3 Jumper 3 pin Male, straight Samtec TSW-103-07-G-S
23 4 JP500, JP501, JP502, JP506 Jumper 2 pin Male, straight Samtec TSW-102-07-G-S

25 10

26 1 OSC500 Oscillator SMT

27 1 P500 Connector PJ-102A DC power jack Digikey CP-102A-ND
28 1 P501 Connector 10 pin Male, straight PTMICRO10

2 D500, D501

1 JP507 24
2 JP508, JP509

L500, L501, L502, L503, L504,
L505, L506, L507, L508, L509

Diode SOT-23

Jumper

Ferrite Bead

3-pin
jumper

3.2 mm ×

2.5 mm ×

1.6 mm

30 V, 20 mA,
dual Schottky

6.0 V, 2.2 A
trip current
resettable fuse

Male, straight Samtec TSW-103-07-G-S

Digikey P9811CT-ND

125 MHz or
105 MHz

Panasonic
LNJ314G8TRA

HSMS2812

Micro Commercial
Group SK33-TPMSCT-ND

Micro Commercial
Group S2A-TPMSTR-ND

Tyco, Raychem
NANOSMDC110F-2

Murata
DLW5BSN191SQ2

Samtec TSW-140-08-G-T-RA

CTS Reeves CB3LV-3C

Rev. A | Page 39 of 44

AD9246

Omit

Item Qty.

29 6 R1, R6, R563, R565, R574, R577 Resistor 0402 DNI

5 R2, R5, R561, R562, R571 30

6 R10, R11, R12, R535, R536, R575
31 2 R3, R4 Resistor 0402 25 Ω
32 6 R7, R8, R9, R502, R510, R511 Resistor 0603 DNI
33 6

34 4 R503, R548, R549, R550 Resistor 0603 10 kΩ

1 R504 35

1 R505
36

37 4 R545, R546, R547, R558 Resistor 0603 4.7 kΩ
38 3 R551, R552, R553 Resistor 0603 1 kΩ
39 1 R559 Resistor 0603 261 Ω
40 2 R566, R567 Resistor 0402 33 Ω
41 3 R582, R585, R598 Resistor 0402 100 Ω
42 2 R583, R584 Resistor 0402 240 Ω
43 1 R586 Resistor 0402 4.12 kΩ
44 3 R580, R587, R588 Resistor 0402 10 kΩ
45 1 R589 Resistor 0603 261 Ω
46 2 R590, R591 Resistor 0402 25 Ω
47 1 R592 Resistor 0402 DNI
48 2 R593, R596 Resistor 0402 0 Ω
49 2 R594, R595 Resistor 0402 10 kΩ
50 1 R597 Resistor 0402 4.3 kΩ
51 1 RP500 Resistor RCA74204 22 Ω
52 2 RP501, RP502 Resistor RCA74208 22 Ω
53 1 S1 Switch

55 2 S504, S505 Connector SMA200UP

58 1 U500 IC

59 1 U501 IC SOT-223

60 1 U502 IC SOT-223

9

23

2 S500, S501 54

2 S502, S503

2 T500, T501 56

1 T1

1 T503 57

1 T502

(DNP) Reference Designator Device Package Description Supplier/Part Number

Resistor 0402 0 Ω

R500, R501, R576, R578, R579,
R581

R506, R508, R509, R512, R554,
R555, R556, R557, R560

R507, R514, R513, R515, R516,
R517, R518, R519, R520, R521,
R522, R523, R524, R525, R526,
R527, R528, R529, R530, R531,
R532, R533, R534,

Resistor 0402 DNI

Resistor 0603 49.9 Ω

Resistor 0603 0 Ω

Momentary
(normally open)

Connector SMAEDGE

Transformer SM-22 M/A-Com ETC1-1-13

Transformer CD542 Mini-Circuits ADT1-1WT

32-pin
LFCSP

SMA edge
right angle

SMA RF 5-pin
upright

Clock
distribution

Voltage
regulator

Voltage
regulator

Panasonic EVQ-PLDA15

ADI AD9515BCPZ

ADP3339AKCZ-5

ADI

ADP3339AKCZ-1.8

ADI

Rev. A | Page 40 of 44

AD9246

Omit

Item Qty.

61 1 U503 IC SOT-223

62 2 U504, U505 IC SOT-223

63 1 U506 IC 8-pin SOIC

64 1 U507 IC SC70 Dual buffer Fairchild NC7WZ16
65 1 U508 IC SC70 Dual buffer Fairchild NC7WZ07
66 1 U509 IC

67 1 U510

68 1 U511 (or Z500) IC

To ta l

128 107

(DNP) Reference Designator Device Package Description Supplier/Part Number

ADP3339AKCZ-2.5

ADI

ADP3339AKCZ-3.3

ADI

Microchip PIC12F629

Fairchild 74VCX162244

AD8352ACPZ

ADI

DUT
(AD9246)

48-pin
TSSOP

48-pin
LFCSP_VQ

16-pin
LFCSP_VQ

Voltage
regulator

Voltage
regulator

8-bit
microcontroller

Buffer/line
driver

ADC ADI AD9246BCPZ

Differential
amplifier

Rev. A | Page 41 of 44

AD9246

OUTLINE DIMENSIONS

BSC SQ

PIN 1
INDICATOR

7.00

0.60 MAX

37

36

0.60 MAX

0.30

0.23

0.18
PIN 1

INDICATO

48

1

R

1.00

0.85

0.80

12° MAX

SEATING
PLANE

TOP

VIEW

0.80 MAX

0.65 TYP

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

6.75

BSC SQ

0.20 REF

0.50

0.40

0.30

0.05 MAX

0.02 NOM
COPLANARITY

0.08

25

24

EXPOSED

PA D

(BOTTOM VIEW)

5.50
REF

4.25

4.10 SQ

3.95

12

13

0.25 MIN

Figure 71. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

7 mm × 7 mm Body, Very Thin Quad (CP-48-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9246BCPZ-1252 –40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-3
AD9246BCPZRL7-125
AD9246BCPZ-1052 –40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-3
AD9246BCPZRL7-105
AD9246BCPZ-80
AD9246BCPZRL7-80
AD9246-125EB Evaluation Board
AD9246-105EB Evaluation Board
AD9246-80EB Evaluation Board

1

It is required that the exposed paddle be soldered to the AGND plane to achieve the best electrical and thermal performance.

2

Z = Pb-free part.

2

2

2

2

–40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-3

–40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-3
–40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-3
–40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-3

1

Rev. A | Page 42 of 44

AD9246

NOTES

Rev. A | Page 43 of 44

AD9246

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05491-0-8/06(A)

Rev. A | Page 44 of 44