Analog Devices AD9246 Service Manual

14-Bit, 80 MSPS/105 MSPS/125 MSPS,

A

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Clock duty cycle stabilizer Data output clock Serial port control

Built-in selectable digital test pattern generation Programmable clock and data alignment

APPLICATIONS

Ultrasound equipment IF sampling in communications receivers

IS-95, CDMA-One, IMT-2000 Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes

GENERAL DESCRIPTION

The AD9246 is a monolithic, single 1.8 V supply, 14-bit, 80 MSPS/ 105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring a high performance sample-and-hold amplifier (SHA) and on-chip voltage reference. The product uses a multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range.

The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and offsets, including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9246 is suitable for applications in communications, imaging, and medical ultrasound.

A differential clock input controls all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.

1.8 V Analog-to-Digital Converter AD9246

FUNCTIONAL BLOCK DIAGRAM

MODE

SELECT

DRVDD

A/D

3

OR

DCO

D13 (MSB)

D0 (LSB)

SCLK/DFS

SDIO/DCS

CSB

VDD

AD9246

VIN+

VIN–

REFT

REFB

VREF

SENSE

SHA

REF

SELECT

MDAC1

A/D

0.5V

AGND

8-STAGE

1 1/2-BIT PIPELINE

4

CORRECTION LOGIC

OUTPUT BUF FERS

CLOCK

DUTY CYCLE

STABILIZER

CLK+

Figure 1.

8

15

CLK– PDWN DRGND

The digital output data is presented in offset binary, Gray code, or twos complement formats. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic.

The AD9246 is available in a 48-lead LFCSP_VQ and is specified over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. The AD9246 operates from a single 1.8 V power supply

and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.

2. The patented SHA input maintains excellent performance

for input frequencies up to 225 MHz.

3. The clock DCS maintains overall ADC performance over a

wide range of clock pulse widths.

4. A standard serial port interface supports various product

features and functions, such as data formatting (offset binary, twos complement, or Gray coding), enabling the clock DCS, power-down, and voltage reference mode.

5. The AD9246 is pin-compatible with the AD9233, allowing

a simple migration from 12 bits to 14 bits.

05491-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9246

REVISION HISTORY

8/06—Rev. 0 to Rev. A

Added 80 MSPS.................................................................. Universal

Changes to Features..........................................................................1

Deleted Figures 19, 20, 22, 23 ........................................................11

Deleted Figures 24, 25, 27 to 29.....................................................12

Deleted Figures 31, 34.....................................................................13

Deleted Figures 37, 38, 40, 41 ........................................................14

Deleted Figure 46 ............................................................................15

Deleted Figure 52 ............................................................................16

Changes to Figure 41 ......................................................................17

Changes to Figure 46 ......................................................................19

Inserted Figure 54 ...........................................................................21

Added Data Clock Output (DCO) Section .................................22

Changes to Table 15........................................................................25

Changes to Table 16........................................................................39

Changes to the Ordering Guide....................................................42

4/06—Revision 0: Initial Version

Rev. A | Page 3 of 44

AD9246

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled, unless otherwise noted.

Table 1.

AD9246BCPZ-80 AD9246BCPZ-105 AD9246BCPZ-125

Parameter Temp

RESOLUTION Full 14 14 14 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.3 ±0.5 ±0.3 ±0.8 ±0.3 ±0.8 % FSR Gain Error Full ±0.6 ±4.7 ±0.6 ±5.0 ±0.6 ±4.2 % FSR Differential Nonlinearity (DNL)

1

Full ±1.0 ±1.0 ±1.0 LSB

25°C ±0.4 ±0.4 ±0.4 LSB

Integral Nonlinearity (INL)

1

Full ±5.0 ±5.0 ±5.0 LSB 25°C ±1.5 ±1.3 ±1.5 LSB TEMPERATURE DRIFT

Offset Error Full ±15 ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ±95 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) Full ±5 ±20 ±5 ±35 ±5 ±35 mV Load Regulation @ 1.0 mA Full 7 7 7 mV

INPUT REFERRED NOISE

VREF = 1.0 V 25°C 1.3 1.3 1.3 LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V Full Input Capacitance

2

Full REFERENCE INPUT RESISTANCE Full POWER SUPPLIES

Supply Voltage

AVDD Full DRVDD Full

Supply Current

1

IAVDD

Full

IDRVDD1 (DRVDD = 1.8 V) Full IDRVDD1 (DRVDD = 3.3 V) Full

POWER CONSUMPTION

DC Input Full Sine Wave Input1 (DRVDD = 1.8 V) Full Sine Wave Input1 (DRVDD = 3.3 V) Full Standby Power

3

Full

Power-Down Power Full

1

Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.

3

Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).

Min Typ Max Min Typ Max Min Typ Max Unit

2 2 8 8 6 6

1.7 1.8 1.9 1.7 1.8 1.9

1.7 2.5 3.6 1.7 2.5 3.6

138 155 178 194 7 9 12 16

248 279 320 350 261 337 288 373 40 40

1.8 1.8

2 V p-p 8 pF 6 kΩ

1.7 1.8 1.9 V

1.7 2.5 3.6 V

220 236 mA 11 mA 19 mA

395 425 mW 415 mW 458 mW 40 mW

1.8 mW

Rev. A | Page 4 of 44

AD9246

AC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference;AIN = −1.0 dBFS, DCS enabled, unless otherwise noted.

Table 2.

Parameter

1

Temp

SIGNAL-TO-NOISE-RATIO (SNR)

fIN = 2.4 MHz 25°C 71.9 71.9 71.9 dBc fIN = 70 MHz 25°C 71.9 71.9 71.7 dBc Full 70.8 69.5 69.5 dBc fIN = 100 MHz 25°C 71.6 71.6 71.6 dBc fIN = 170 MHz 25°C 70.9 70.9 70.8 dBc

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 2.4 MHz 25°C 71.1 71.1 71.1 dBc fIN = 70 MHz 25°C 71.5 70.8 70.6 dBc Full 70.4 68.5 68.5 dBc fIN = 100 MHz 25°C 70.6 70.6 70.6 dBc fIN = 170 MHz 25°C

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.4 MHz fIN = 70 MHz fIN = 100 MHz fIN = 170 MHz

25°C 11.7 11.7 25°C 11.6 11.6 25°C 11.6 11.6 25°C 11.5 11.5

WORST SECOND OR THIRD HARMONIC

fIN = 2.4 MHz fIN = 70 MHz

fIN = 100 MHz fIN = 170 MHz

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.4 MHz fIN = 70 MHz

fIN = 100 MHz fIN = 170 MHz

25°C 25°C Full 25°C 25°C

WORST OTHER HARMONIC OR SPUR

fIN = 2.4 MHz fIN = 70 MHz

fIN = 100 MHz fIN = 170 MHz

TWO-TONE SFDR

fIN = 29 MHz (−7 dBFS), 32 MHz

25°C 25°C Full 25°C 25°C

25°C 87 87

(−7 dBFS) fIN = 169 MHz (−7 dBFS), 172 MHz

25°C 83 83

(−7 dBFS)

ANALOG INPUT BANDWIDTH

1

See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

25°C

AD9246BCPZ-80 AD9246BCPZ-105 AD9246BCPZ-125

Min Typ Max Min Typ Max Min Typ Max Unit

69.9

−90 −90 −90

−85 −85 −85

−76

−73

−85 −85 −85

−83.5 −83.5 −83

90 90 90 85 85 85 76

73

85 85 85

83.5 83.5 83

−90 −90 −90

−85

−80

−90 −90 −90

85

84

650

69.8

11.7

11.6

11.5

dBc

Bits Bits Bits Bits

dBc dBc dBc dBc dBc

dBc

MHz

Rev. A | Page 5 of 44

AD9246

DIGITAL SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled, unless otherwise noted.

Table 3.

AD9246BCPZ-80/105/125

Parameter Temp

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance Internal Common-Mode Bias Differential Input Voltage Full 0.2 6 Input Voltage Range Full AVDD − 0.3 AVDD + 1.6 Input Common-Mode Range Full 1.1 AVDD High Level Input Voltage (VIH) Full 1.2 3.6 V Low Level Input Voltage (VIL) Full High Level Input Current (IIH) Full −10 +10 µA Low Level Input Current (IIL) Full −10 +10 µA Input Resistance Full 8 10 12 Input Capacitance Full 4

LOGIC INPUTS (SCLK/DFS, OEB, PWDN)

High Level Input Voltage (VIH) Full 1.2 3.6 V Low Level Input Voltage (VIL) Full 0 0.8 V High Level Input Current (IIH) Full Low Level Input Current (IIL) Full Input Resistance Full 30 kΩ Input Capacitance Full 2 pF

LOGIC INPUTS (CSB)

High Level Input Voltage (VIH) Full 1.2 3.6 V Low Level Input Voltage (VIL) Full 0 0.8 V High Level Input Current (IIH) Full −10 +10 µA Low Level Input Current (IIL) Full Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUTS (SDIO/DCS)

High Level Input Voltage (VIH) Full 1.2 DRVDD + 0.3 V Low Level Input Voltage (VIL) Full 0 0.8 V High Level Input Current (IIH) Full −10 +10 µA Low Level Input Current (IIL) Full Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

DIGITAL OUTPUTS

DRVDD = 3.3 V

High Level Output Voltage (VOH, IOH = 50 µA) Full 3.29 V High Level Output Voltage (VOH , IOH = 0.5 mA) Full 3.25 V Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (VOL, IOL = 50 µA) Full 0.05 V

DRVDD = 1.8 V

High Level Output Voltage (VOH, IOH = 50 µA) Full 1.79 V High Level Output Voltage (VOH, IOH = 0.5 mA) Full 1.75 V Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (VOL, IOL = 50 µA) Full 0.05 V

CMOS/LVDS/LVPECL Full 1.2 V

Min Typ Max

0 0.8

−50 −75

−10 +10

+40 +135

+40 +130

Unit

V p-p V V

V

kΩ pF

µA µA

µA

Rev. A | Page 6 of 44

AD9246

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.

Table 4.

Parameter

1

Temp

CLOCK INPUT PARAMETERS

Conversion Rate, DCS Enabled Full 20 80 20 105 20 125 MSPS Conversion Rate, DCS Disabled Full 10 80 10 105 10 125 MSPS CLK Period Full 12.5 9.5 8 ns CLK Pulse Width High, DCS Enabled Full 3.75 6.25 8.75 2.85 4.75 6.65 2.4 4 5.6 ns CLK Pulse Width High, DCS Disabled Full 5.63 6.25 6.88 4.28 4.75 5.23 3.6 4 4.4 ns

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD) DCO Propagation Delay (t

2

) Full 4.4 4.4 4.4 ns

DCO

Full 3.1 3.9 4.8 3.1 3.9 4.8 3.1 3.9 4.8 ns

Setup Time (tS) Full 4.9 5.7 3.4 4.3 2.6 3.5 ns Hold Time (tH) Full 5.9 6.8 4.4 5.3 3.7 4.5 ns Pipeline Delay (Latency) Full 12 12 12 cycles Aperture Delay (tA) Full 0.8 0.8 0.8 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms Wake-Up Time

3

Full 350 350 350 s OUT-OF-RANGE RECOVERY TIME Full 2 2 3 Cycles SERIAL PORT INTERFACE

SCLK Period (t

4

) Full 40 40 40 ns

CLK

SCLK Pulse Width High Time (tHI) Full 16 16 16 ns SCLK Pulse Width Low Time (tLO) Full 16 16 16 ns SDIO to SCLK Setup Time (tDS) Full 5 5 5 ns SDIO to SCLK Hold Time (tDH) Full 2 2 2 ns CSB to SCLK Setup Time (tS) Full 5 5 5 ns CSB to SCLK Hold Time (tH) Full 2 2 2 ns

1

See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

3

Wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 µF capacitor across REFT and REFB.

4

See Figure 57 and the Serial Port Interface (SPI) section.

AD9246BCPZ-80 AD9246BCPZ-105 AD9246BCPZ-125

Min Typ Max Min Typ Max Min Typ Max

Unit

TIMING DIAGRAM

CLK+

CLK–

DATA

DCO

N+2

N+ 1

N

t

A

t

CLK

t

PD

N – 13

N – 12 N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4

t

S

t

H

N+ 3

t

DCO

N+ 4

N+ 5

t

CLK

N+ 6

N+ 7

Figure 2. Timing Diagram

Rev. A | Page 7 of 44

N+ 8

05491-002

AD9246

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

ELECTRICAL

AVDD to AGND −0.3 V to +2.0 V DRVDD to DGND −0.3 V to +3.9 V AGND to DGND −0.3 V to +0.3 V AVDD to DRVDD −3.9 V to +2.0 V D0 through D13 to DGND −0.3 V to DRVDD + 0.3 V DCO to DGND −0.3 V to DRVDD + 0.3 V OR to DGND −0.3 V to DRVDD + 0.3 V CLK+ to AGND −0.3 V to +3.9 V CLK− to AGND −0.3 V to +3.9 V VIN+ to AGND −0.3 V to AVDD + 0.2 V VIN− to AGND −0.3 V to AVDD + 0.2 V VREF to AGND −0.3 V to AVDD + 0.2 V SENSE to AGND −0.3 V to AVDD + 0.2 V REFT to AGND −0.3 V to AVDD + 0.2 V REFB to AGND −0.3 V to AVDD + 0.2 V SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V PDWN to AGND −0.3 V to +3.9 V CSB to AGND −0.3 V to +3.9 V SCLK/DFS to AGND −0.3 V to +3.9 V OEB to AGND −0.3 V to +3.9 V

ENVIRONMENTAL

Storage Temperature Range –65°C to +125°C Operating Temperature Range –40°C to +85°C Lead Temperature

(Soldering 10 Sec) Junction Temperature +150°C

+300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

The exposed paddle must be soldered to the ground plane for the LFCSP_VQ package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package.

Table 6. Thermal Resistance

Package Type θJA θ

48-lead LFCSP_VQ (CP-48-3) 26.4 2.4 °C/W

Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation effectively reducing θ addition, metal in direct contact with the package leads from metal traces, and through holes, ground, and power planes, reduces the θ

.

JA

Unit

JC

. In

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 8 of 44

AD9246

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DRVDD

DRGNDD1D0 (LSB)

DCO

OEB

AVDD

AGND

AVDD

CLK–

CLK+

4847464544434241403938

AGND

37

AVDD

35 34 33

32

31 30

29

28 27

26 25

PDWN36

RBIAS CML AVDD

AGND

VIN– VIN+

AGND

REFT REFB

VREF SENSE

05491-003

DRGND

DRVDD

D10

D11

D2

1

D3

2

D4

3

D5

4

D6

5

D7

6

7

8

D8

9

D9

10 11

12

PIN 1 INDICATO R

AD9246

TOP VIEW

(Not to Scale)

13141516171819

OR

D12

DRVDD

DRGND

D13 (MSB)

SDIO/DCS

2021222324

CSB

AGND

SCLK/DFS

AVDD

AGND

Figure 3. Pin Configuration

Table 7. Pin Function Description

Pin No. Mnemonic Description

0, 21, 23, 29, 32,

AGND Analog Ground. (Pin 0 is the exposed thermal pad on the bottom of the package.)

37, 41 45, 46, 1 to 6,

D0 (LSB) to D13 (MSB) Data Output Bits.

9 to 14 7, 16, 47 DRGND Digital Output Ground. 8, 17, 48 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V ). 15 OR Out-of-Range Indicator. 18 SDIO/DCS

Serial Port Interface (SPI)® Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select (External Pin Mode). See

Table 10. 19 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). 20 CSB Serial Port Interface Chip Select (Active Low). See Tabl e 10. 22, 24, 33, 40, 42 AVDD Analog Power Supply.

25 SENSE Reference Mode Selection. See Table 9 . 26 VREF Voltage Reference Input/Output. 27 REFB Differential Reference (−). 28 REFT Differential Reference (+). 30 VIN+ Analog Input Pin (+). 31 VIN– Analog Input Pin (−). 34 CML Common-Mode Level Bias Output. 35 RBIAS

External Bias Resistor Connection. A 10 kΩ resistor must be connected between this pin and

analog ground (AGND). 36 PDWN Power-Down Function Select. 38 CLK+ Clock Input (+). 39 CLK– Clock Input (−). 43 OEB Output Enable (Active Low). 44 DCO Data Clock Output.

Rev. A | Page 9 of 44

AD9246

V

C

S

A

V

A

V

EQUIVALENT CIRCUITS

LK+

IN

05491-004

Figure 4. Equivalent Analog Input Circuit

AVDD

1.2V

10kΩ 10kΩ

Figure 5. Equivalent Clock Input Circuit

DRVDD

DIO/DCS

1kΩ

CLK–

CLK/DFS

OEB

PDWN

30kΩ

1kΩ

05491-008

Figure 8. Equivalent SCLK/DFS, OEB, PDWN Input Circuit

VDD

26kΩ

CSB

05491-005

1kΩ

05491-010

Figure 9. Equivalent CSB Input Circuit

SENSE

1kΩ

05491-011

05491-012

Figure 6. Equivalent SDIO/DCS Input Circuit

DRVDD

DRGND

Figure 7. Equivalent Digital Output Circuit

05491-006

05491-007

Figure 10. Equivalent Sense Circuit

DD

REF

6kΩ

Figure 11. Equivalent VREF Circuit

Rev. A | Page 10 of 44

AD9246

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V; DRVDD = 2.5 V; maximum sample rate, DCS enabled, 1 V internal reference; 2 V p-p differential input; AIN = −1.0 dBFS; 64k sample; T

0

–20

–40

= 25°C, unless otherwise noted. All figures show typical performance for all speed grades.

A

–20

–40

0

125MSPS

100.3MHz @ –1dBF S SNR = 71.6dBc (72.6dBFS) ENOB = 11.5 BI TS SFDR = 85dBc

125MSPS

2.3MHz @ –1dBF S SNR = 71.9dB (72. 9dBFS) ENOB = 11.7 BI TS SFDR = 90dBc

–60

–80

AMPLI TUDE (d BFS)

–100

–120

–140

0 62.500

Figure 12. AD9246-125 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0 62.500

Figure 13. AD9246-125 Single-Tone FFT with f

0

–20

–40

15.625 31.25 0 46.875

FREQUENCY (MHz)

15.625 31.250 46.875

FREQUENCY (MHz)

125MSPS

70.3MHz @ –1dBFS SNR = 71.7dB (72.7d BFS) ENOB = 11.5 BITS SFDR = 85dBc

= 2.3 MHz

IN

125MSPS

30.3MHz @ –1dBFS SNR = 71.9dBc (72.9dBFS) ENOB = 11.6 BI TS SFDR = 88.8d Bc

= 30.3 MHz

IN

–60

–80

AMPLI TUDE (d BFS)

–100

–120

–140

0 62.500

05491-013

Figure 15. AD9246-125 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0 62.500

05491-014

Figure 16. AD9246-125 Single-Tone FFT with f

0

–20

–40

15.625 31. 250 46.875

FREQUENCY (MHz)

15.625 31. 250 46.875

FREQUENCY (MHz)

125MSPS

170.3MHz @ –1dBF S SNR = 70.8dB (71.8d BFS) ENOB = 11.4 BITS SFDR = 83.4dBc

= 100.3 MHz

IN

125MSPS

140.3MHz @ –1dBF S SNR = 71dB (72dBF S) ENOB = 11.4 BI TS SFDR = 85dBc

= 140.3 MHz

IN

05491-016

05491-017

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0 62.500

Figure 14. AD9246-125 Single-Tone FFT with f

15.625 31. 250 46. 875

FREQUENCY (MHz)

= 70.3 MHz

IN

05491-015

Rev. A | Page 11 of 44

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0 62.500

Figure 17. AD9246-125 Single-Tone FFT with f

15.625 31. 250 46.875

FREQUENCY (MHz)

IN

= 170.3 MHz

05491-018

AD9246

AMPLITUDE ( dBFS)

–100

–20

–40

–60

–80

0

125MSPS

225.3MHz @ –1dBF S SNR = 70.3dB (71.3dBFS) ENOB = 11.3 BI TS SFDR = 80.4dBc

SNR/SFDR (dBc)

95

90

85

80

SNR = +85°C

75

SFDR = +25°C

SFDR = +85°C

SNR = +25°C

SFDR = –40°C

SNR = –40°C

–120

–140

0 62.500

Figure 18. AD9246-125 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0 62.500

Figure 19. AD9246-125 Single-Tone FFT with f

120

100

80

15.625 31. 250 46.875

FREQUENCY (MHz)

125MSPS

300.3MHz @ –1dBF S SNR = 69.3dB (70.3d BFS) ENOB = 11 BIT S SFDR = 77.5dBc

15.625 31.250 46. 875

FREQUENCY (MHz)

SFDR (dBFS)

SNR (dBFS)

= 225.3 MHz

IN

= 300.3 MHz

IN

70

65

0 250

05491-019

Figure 21. AD9246 Single-Tone SNR/SFDR vs. Input Frequency (f

50 100 150 200

INPUT FREQ UENCY (MHz)

) and

IN

05491-022

Temperature with 2 V p-p Full Scale

95

90

85

80

SNR/SFDR (dBc)

75

SNR = +85°C

70

65

0 250

05491-020

Figure 22. AD9246 Single-Tone SNR/SFDR vs. Input Frequency (f

SFDR = +85°C

SFDR = –40°C

SFDR = +25°C

SNR = +25°C

50 100 150 200

INPUT FREQ UENCY (MHz)

SNR = –40°C

) and

IN

05491-023

Temperature with 1 V p-p Full Scale

0

–0.25

OFFSET ERROR

60

SFDR (dBc)

40

SNR/SFDR (dBc and dBFS)

20

SNR (dBc)

0

–90 0

–80 –70 –60 –50 –40 –30 –20 –10

INPUT AMPLI TUDE (dBFS)

85dB REF ERENCE L INE

Figure 20. AD9246 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)

= 2.4 MHz

with f

IN

05491-040

Rev. A | Page 12 of 44

–0.50

–0.75

GAIN/OFFSET ERROR (%FSR)

–1.00

–20 0 204060

–40 80

GAIN ERROR

TEMPERATURE (° C)

Figure 23. AD9246 Gain and Offset vs. Temperature

05491-035

AD9246

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0 62.500

15.625 31.250 46.875

FREQUENCY (MHz)

Figure 24. AD9246-125 Two-Tone FFT with f

0

125MSPS

169.1MHz @ –7dBF S

172.1MHz @ –7dBF S

–20

SFDR = 84dBc (91dBF S)

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0 62.500

15.625 31.250 46.875

FREQUENCY (MHz)

Figure 25. AD9246-125 Two-Tone FFT with f

0

–20

125MSPS

29.1MHz @ –7dBF S

32.1MHz @ –7dBF S SFDR = 85dBc (92d BFS)

= 29.1 MHz, f

IN1

= 169.1 MHz, f

IN1

IN2

05491-025

= 32.1 MHz

05491-026

= 172.1 MHz

0

–20

–40

–60

–80

SFDR/IMD3 (dBc and dBFS)

–100

–120

–90 –6

SFDR (dBc)

IMD3 (dBc)

SFDR (dBFS)

IMD3 (dBFS )

–78 –66 –54 –42 –30 –18

INPUT AMPLI TUDE (dBFS)

Figure 27. AD9246 Two-Tone SFDR/IMD vs. Input Amplitude (AIN)

= 29.1 MHz, F

with F

IN1

0

–20

–40

IMD3 (dBFS )

–60

–80

SFDR/IMD3 (dBc and dBFS)

–100

–120

–90 –6

SFDR (dBFS)

–78 –66 –54 –42 –30 –18

INPUT AMPLI TUDE (dBFS)

= 32.1 MHz

IN2

SFDR (dBc)

IMD3 (dBc)

Figure 28. AD9246 Two-Tone SFDR/IMD vs. Input Amplitude (AIN)

–20

= 169.1 MHz, F

with F

IN1

0

= 172.11 MHz

IN2

NPR = 62.9dBc NOTCH @ 18.5MHz NOTCH WIDTH = 3MHz

05491-028

05491-029

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 15.36 30.72 46.08 61. 44

FREQUENCY (MHz)

Figure 26. AD9246-125 Two 64k WCDMA Carriers

= 215.04 MHz, fS = 122.88 MSPS

with f

IN

05491-085

Rev. A | Page 13 of 44

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

0 62.500

15.625 31.250 46.875

FREQUENCY (MHz)

Figure 29. AD9246 Noise Power Ratio (NPR)

05491-089

AD9246

SNR/SFDR (dBc)

100

95

90

85

80

75

SFDR

SNR

10

8

6

4

NUMBER OF HIT S (1M)

2

1.3 LSB rms

70

5 125

25 45 65 85 105

CLOCK FREQUE NCY (MSPS)

Figure 30. AD9246 Single-Tone SNR/SFDR vs. Clock Frequency (f

= 2.4 MHz

with f

IN

100

SFDR DCS ON

95

90

85

80

75

SNR/SFDR (dBc)

70

65

60

Figure 31. AD9246 SNR/SFDR vs. Duty Cycle with f

90

85

80

SNR/SFDR (dBc)

75

70

SFDR DCS OFF

SNR DCS ON

SNR DCS OFF

20 80

SFDR

0.5 1.3

0.6 0.7 0. 8 0.9 1. 0 1.1 1.2

40 60

DUTY CYCLE (%)

SNR

INPUT COMMON-MODE VOLTAGE (V)

= 10.3 MHz

IN

Figure 32. AD9246 SNR/SFDR vs. Input Common Mode (VCM)

= 30 MHz

with f

IN

0

N – 4

N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4

05491-030

)

S

INL ERROR (LSB)

05491-027

DNL ERROR (LSB)

05491-031

Figure 33. AD9246 Grounded Input Histogram

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0 16384

2048 4096 6144 8192 10240 12288 14336

Figure 34. AD9246 INL with f

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

0 16384

2048 4096 6144 8192 10240 12288 14336

Figure 35. AD9246 DNL with f

OUTPUT CODE

= 10.3 MHz

IN

= 10.3 MHz

IN

05491-084

05491-024

05491-021

Rev. A | Page 14 of 44

Analog Devices AD9246 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING DIAGRAM

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

EQUIVALENT CIRCUITS

TYPICAL PERFORMANCE CHARACTERISTICS