Analog Devices AD9245 b Datasheet
FEATURES
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 72.7 dBc to Nyquist
SFDR = 87.6 dBc to Nyquist
Low power: 366 mW
Differential input with 500 MHz bandwidth
On-chip reference and sample-and-hold
DNL = ± 0.5 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
APPLICATIONS
High end medical imaging equipment
IF sampling in communications receivers:
WCDMA, CDMA-One, CDMA-2000, TDS-CDMA
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
Power sensitive military applications
GENERAL DESCRIPTION
The AD9245 is a monolithic, single 3 V supply, 14-bit, 80 MSPS
analog-to-digital converter featuring a high performance
sample-and-hold amplifier (SHA) and voltage reference. The
AD9245 uses a multistage differential pipelined architecture
with output error correction logic to provide 14-bit accuracy at
80 MSPS and guarantee no missing codes over the full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and common modes, including
single-ended applications. It is suitable for multiplexed systems
that switch full-scale voltage levels in successive channels, and
for sampling single-channel inputs at frequencies well beyond
the Nyquist rate. Combined with power and cost savings over
previously available analog-to-digital converters, the AD9245 is
suitable for applications in communications, imaging, and
medical ultrasound.
A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for
wide variations in the clock duty cycle while maintaining
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
14-Bit, 80 MSPS, 3 V A/D Converter
AD9245
FUNCTIONAL BLOCK DIAGRAM
DRVDDAVDD
AD9245
VIN+
VIN–
REFT
REFB
VREF
SENSE
SHA
REF
SELECT
MDAC1
4 16
A/D
0.5V
AGND
Figure 1. Functional Block Diagram
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow. Fabricated on an advanced CMOS process, the
AD9245 is available in a 32-lead LFCSP and is specified over
the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9245 operates from a single 3 V power supply and
features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families.
2. Operating at 80 MSPS, the AD9245 consumes a low 366 mW.
3. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz, and can be configured for
single-ended or differential operation.
4. The AD9245 is pin compatible with the AD9215, AD9235,
and AD9236. This allows a simplified migration from 10 bits
to 14 bits and 20 MSPS to 80 MSPS.
5. The clock DCS maintains overall ADC performance over a
wide range of clock pulsewidths.
6. The OTR output bit indicates when the signal is beyond the
selected input range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
8-STAGE
1 1/2-BIT PIPELINE
CORRECTION LOGIC
14
OUTPUT BUFFERS
CLOCK
DUTY CYCLE
STABILIZER
CLK PDWN MODE DGND
MODE
SELECT
A/D
03583-B-001
3
OTR
D13 (MSB)
D0 (LSB)
AD9245
TABLE OF CONTENTS
AD9245–DC Specifications ............................................................ 3
Analog Input and Reference Overview ................................... 14
AD9245–AC Specifications............................................................. 4
AD9245–Digital Specifications....................................................... 5
AD9245–Switching Specifications ................................................. 6
Explanation of Test Levels........................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Definitions of Specifications ........................................................... 8
Pin Configuration and Functional Descriptions.......................... 9
Equivalent Circuits......................................................................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 14
REVISION HISTORY
Revision B
Clock Input Considerations...................................................... 15
Jitter Considerations .................................................................. 16
Power Dissipation and Standby Mode .................................... 16
Digital Outputs........................................................................... 16
Timing ......................................................................................... 17
Voltage Reference....................................................................... 17
Internal Reference Connection ................................................ 17
External Reference Operation .................................................. 18
Operational Mode Selection ..................................................... 18
Evaluation Board........................................................................ 18
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
10/03—Data Sheet Changed from REV. A to REV. B
Changes to Figure 33 ..................................................................... 17
5/03—Data Sheet Changed from REV. 0 to REV. A
Changes to Figure 30 .................................................................... 15
Changes to Figure 37 ..................................................................... 19
Changes to Figure 38..................................................................... 20
Changes to Figure 39...................................................................... 21
Changes to Table 10 ....................................................................... 24
Changes to the ORDERING GUIDE........................................... 25
Rev. B | Page 2 of 28
AD9245
AD9245–DC SPECIFICATIONS
Table 1. AVDD = 3 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, 2 V p-p Differential Input, 1.0 V External Reference, unless
otherwise noted
Parameter
Temp
Test Level
Min Typ Max
RESOLUTION Full VI 14 Bits
ACCURACY
No Missing Codes Full VI Guaranteed
Offset Error1 Full VI ±0.30 ±1.2 % FSR
Gain Error 25°C V ±0.28 % FSR
Gain Error1 Full VI ±0.70 ±4.16 % FSR
Differential Nonlinearity (DNL)2 Full VI ±0.5 ±1.0 LSB
Integral Nonlinearity (INL)2 Full VI ±1.4 ±5.15 LSB
TEMPERATURE DRIFT
Offset Error1 Full V ±10 ppm/°C
Gain Error Full V ±12 ppm/°C
Gain Error1 Full V ±17 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) Full VI ±3 ±34 mV
Load Regulation @ 1.0 mA 25°C V ±2 mV
Output Voltage Error (0.5 V Mode) 25°C V ±6 mV
Load Regulation @ 0.5 mA 25°C V ±1 mV
INPUT REFERRED NOISE
VREF = 0.5 V 25°C V 1.86 LSB rms
VREF = 1.0 V 25°C V 1.17 LSB rms
ANALOG INPUT
Input Span, VREF = 0.5 V Full IV 1 V p-p
Input Span, VREF = 1.0 V Full IV 2 V p-p
Input Capacitance3 Full V 7 pF
REFERENCE INPUT RESISTANCE Full V 7 kΩ
POWER SUPPLIES
Supply Voltage
AVDD Full IV 2.7 3.0 3.6 V
DRVDD Full IV 2.25 2.5 3.6 V
Supply Current
IAVDD2 Full VI 122 138 mA
IDRVDD2 25°C V 9 mA
PSRR 25°C V ±0.01 % FSR
POWER CONSUMPTION
Low Frequency Input4 25°C V 366 mW
Standby Power5 25°C V 1.0 mW
AD9245BCP
Unit
1
With a 1.0 V internal reference.
2
Measured at the maximum clock rate, f
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to for the equivalent analog input structure. Figure 4
4
Measured at AC Specification conditions without output drivers.
5
Standby power is measured with a dc input, CLK pin inactive (i.e., set to AVDD or AGND).
= 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
IN
Rev. B | Page 3 of 28
AD9245
AD9245–AC SPECIFICATIONS
Table 2. AVDD = 3 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, 2 V p-p Differential Input, 1.0 V External Reference,
AIN = –0.5 dBFS, DCS Off, unless otherwise noted
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz Full VI 71.1 dB
25°C V 73.3 dB
fIN = 40 MHz 25°C V 72.7 dB
fIN = 70 MHz Full IV 70.5 dB
25°C V 71.7 dB
fIN = 100 MHz 25°C V 70.2 dB
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.4 MHz Full VI 70.7 dB
25°C V 73.2 dB
fIN = 40 MHz 25°C V 72.5 dB
fIN = 70 MHz Full IV 69.9 dB
25°C V 71.2 dB
fIN = 100 MHz 25°C V 69.6 dB
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz Full VI 11.5 Bits
25°C V 11.9 Bits
fIN = 40 MHz 25°C V 11.8 Bits
fIN = 70 MHz Full IV 11.3 Bits
25°C V 11.5 Bits
fIN = 100 MHz 25°C V 11.3 Bits
WORST SECOND OR THIRD
fIN = 2.4 MHz Full VI –76.5 dBc
25°C V –92.8 dBc
fIN = 40 MHz 25°C V –87.6 dBc
fIN = 70 MHz Full IV –75.7 dBc
25°C V –81.6 dBc
fIN = 100 MHz 25°C V –79.0 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz Full VI 76.5 dBc
25°C V 92.8 dBc
fIN = 40 MHz 25°C V 87.6 dBc
fIN = 70 MHz Full IV 75.7 dBc
25°C V 81.6 dBc
fIN = 100 MHz 25°C V 79.0 dBc
Temp
Test Level
Min Typ Max
AD9245BCP
Unit
Rev. B | Page 4 of 28
AD9245
AD9245–DIGITAL SPECIFICATIONS
Table 3. AVDD = 3 V, DRVDD = 2.5 V, 1.0 V External Reference, unless otherwise noted
Parameter
LOGIC INPUTS (CLK, PDWN)
High Level Input Voltage Full IV 2.0 V
Low Level Input Voltage Full IV 0.8 V
High Level Input Current Full IV –10 +10 µA
Low Level Input Current Full IV –10 +10 µA
Input Capacitance Full V 2 pF
DIGITAL OUTPUT BITS (D0–D13, OTR)1
DRVDD = 3.3 V
High Level Output Voltage (IOH = 50 µA) Full IV 3.29 V
High Level Output Voltage (IOH = 0.5 mA) Full IV 3.25 V
Low Level Output Voltage (IOH = 1.6 mA) Full IV 0.2 V
Low Level Output Voltage (IOH = 50 µA) Full IV 0.05 V
DRVDD = 2.5 V
High Level Output Voltage (IOH = 50 µA) Full IV 2.49 V
High Level Output Voltage (IOH = 0.5 mA) Full IV 2.45 V
Low Level Output Voltage (IOH = 1.6 mA) Full IV 0.2 V
Low Level Output Voltage (IOH = 50 µA) Full IV 0.05 V
Temp
Test Level
1
Output voltage levels measured with 5 pF load on each output.
AD9245BCP
Min Typ Max
Unit
Rev. B | Page 5 of 28
AD9245
AD9245–SWITCHING SPECIFICATIONS
Table 4. AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted
AD9245BCP
Unit
Parameter
Temp
Test Level
Min Typ Max
CLOCK INPUT PARAMETERS
Maximum Conversion Rate Full VI 80 MSPS
Minimum Conversion Rate Full V 1 MSPS
CLK Period Full V 12.5 ns
CLK Pulsewidth High1 Full V 4.6 ns
CLK Pulsewidth Low1 Full V 4.6 ns
DATA OUTPUT PARAMETERS
Output Propagation Delay (tPD)2 Full V 4.2 ns
Pipeline Delay (Latency) Full V 7 Cycles
Aperture Delay (tA) Full V 1 ns
Aperture Uncertainty (Jitter, tJ) Full V 0.3 ps rms
Wake-Up Time3 Full V 7 ms
OUT-OF-RANGE RECOVERY TIME Full V 2 Cycles
1
With duty cycle stabilizer (DCS) enabled.
2
Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
3
Wake-up time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
N+1
ANALOG
INPUT
CLK
DATA
OUT
N
N–1
N–9N–8N–7N–6N–5N–4N–3N–2N–1 N
t
N+2
A
Figure 2. Timing Diagram
N+3
N+4
N+5
t
= 6.0ns MAX
PD
2.0ns MIN
N+6
N+7
N+8
03583-B-002
EXPLANATION OF TEST LEVELS
Test Level Definitions
I 100% production tested.
II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
Rev. B | Page 6 of 28
AD9245
ABSOLUTE MAXIMUM RATINGS
Table 5. AD9245 Absolute Maximum Ratings
Parameter With Respect to Min Max Unit
ELECTRICAL
AVDD AGND –0.3 +3.9 V
DRVDD DGND –0.3 +3.9 V
AGND DGND –0.3 +0.3 V
AVDD DRVDD –3.9 +3.9 V
D0–D13 DGND –0.3 DRVDD + 0.3 V
CLK, MODE AGND –0.3 AVDD + 0.3 V
VIN+, VIN– AGND –0.3 AVDD + 0.3 V
VREF AGND –0.3 AVDD + 0.3 V
SENSE AGND –0.3 AVDD + 0.3 V
REFT, REFB AGND –0.3 AVDD + 0.3 V
PDWN AGND –0.3 AVDD + 0.3 V
ENVIRONMENTAL
Storage Temperature –65 +125 °C
Operating Temperature Range –40 +85 °C
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature 150 °C
300
°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions on a 4-layer board
in still air, in accordance with EIA/JESD51-1.
Table 6. Thermal Resistance
Package Type
CP-32 32.5 32.71 °C/W
θJC
θ
JA
Airflow increases heat dissipation, effectively reducing θ
Also, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θ
. It is recommended that the exposed paddle be
JA
soldered to the ground plane for the LFCSP package. There is an
increased reliability of the solder joints, and maximum thermal
capability of the package is achieved with the exposed paddle
soldered to the customer board.
Unit
JA
.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 7 of 28
AD9245
(
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth (Full Power Bandwidth)—The analog
input frequency at which the spectral power of the fundamental
frequency (as determined by the FFT analysis) is reduced by 3 dB.
Aperture Delay (t
rising edge of the clock and the instant at which the analog
input is sampled.
Aperture Uncertainty (Jitter, t
tion in aperture delay.
Integral Nonlinearity (INL)—The deviation of each individual
code from a line drawn from negative full scale through positive
full scale. The point used as negative full scale occurs ½ LSB
before the first code transition. Positive full scale is defined as a
level 1½ LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
Differential Nonlinearity (DNL, No Missing Codes)—An
ideal ADC exhibits code transitions that are exactly 1 LSB apart.
DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16384 codes
must be present over all operating ranges.
Offset Error—The major carry transition should occur for an
analog value ½ LSB below VIN+ = VIN–. Offset error is
defined as the deviation of the actual transition from that point.
)—The delay between the 50% point of the
A
)—The sample-to-sample varia-
J
Effective Number of Bits (ENOB)—The effective number of
bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following
formula:
)
=
ENOB
Signal-to-Noise Ratio (SNR)
SINAD
1
—The ratio of the rms input
76.1−
02.6
signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the
first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
1
—The difference in dB
between the rms input signal amplitude and the peak spurious
signal. The peak spurious component may or may not be a
harmonic.
1
Two -Ton e SFDR
—The ratio of the rms value of either input
tone to the rms value of the peak spurious component. The
peak spurious component may or may not be an IMD product.
Clock Pulsewidth and Duty Cycle—Pulsewidth high is the
minimum amount of time that the clock pulse should be left in
the Logic 1 state to achieve rated performance. Pulsewidth low
is the minimum time the clock pulse should be left in the
Logic 0 state. At a given clock rate, these specifications define an
acceptable clock duty cycle.
Gain Error—The first code transition should occur at an
analog value ½ LSB above negative full scale. The last transition
should occur at an analog value 1½ LSB below the positive
full scale. Gain error is the deviation of the actual difference
between first and last code transitions and the ideal difference
between first and last code transitions.
Temperature Drift—The temperature drift for offset error and
gain error specifies the maximum change from the initial
(25°C) value to the value at T
MIN
or T
MAX
.
Power Supply Rejection Ratio—The change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
1
Total Harmonic Distortion (THD)
—The ratio of the rms
input signal amplitude to the rms value of the sum of the first
six harmonic components.
1
Signal-to-Noise and Distortion (SINAD)
—The ratio of the
rms input signal amplitude to the rms value of the sum of all
other spectral components below the Nyquist frequency, including harmonics but excluding dc.
Minimum Conversion Rate—The clock rate at which the SNR
of the lowest analog signal frequency drops by no more than
3 dB below the guaranteed limit.
Maximum Conversion Rate—The clock rate at which parametric testing is performed.
Output Propagation Delay (t
)—The delay between the clock
PD
rising edge and the time when all bits are within valid logic
levels.
Out-of-Range Recovery Time—The time it takes for the ADC
to reacquire the analog input after a transition from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
1
AC specifications may be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
Rev. B | Page 8 of 28
AD9245
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
32 AVDD
31 AGND
30 VIN–
29 VIN+
28 AGND
27 AVDD
26 REFT
25 REFB
DNC 1
CLK 2
DNC 3
PDWN 4
(LSB) D0 5
D1 6
D2 7
D3 8
(Not to Scale)
D4 9
D5 10
AD9245
CSP
TOP VIEW
D6 11
D7 12
D8 13
D9 14
Figure 3. 32-Lead LFCSP
Table 7. Pin Function Descriptions—32-Lead LFCSP (CP Package)
Pin No. Mnemonic Description
1, 3 DNC Do Not Connect
2 CLK Clock Input Pin
4 PDWN Power-Down Function Select
5 to 14, 17 to 20 D0 (LSB) to D13 (MSB) Data Output Bits
15 DGND Digital Output Ground
16 DRVDD Digital Output Driver Supply
21 OTR Out-of-Range Indicator
22 MODE Data Format Select and DCS Mode Selection (see )
23 SENSE Reference Mode Selection (see Table 8)
24 VREF Voltage Reference Input/Output
25 REFB Differential Reference (–)
26 REFT Differential Reference (+)
27, 32 AVDD Analog Power Supply
28, 31 AGND Analog Ground
29 VIN+ Analog Input Pin (+)
30 VIN– Analog Input Pin (–)
DGND 15
24 VREF
23 SENSE
22 MODE
21 OTR
20 D13 (MSB)
19 D12
18 D11
17 D10
DRVDD 16
03583-B-022
Table 9
Rev. B | Page 9 of 28
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