Analog Devices AD9245 Service Manual
14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
FEATURES
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 72.7 dBc to Nyquist
SFDR = 83.0 dBc to Nyquist
Low power
366 mW at 80 MSPS
300 mW at 65 MSPS
165 mW at 40 MSPS
90 mW at 20 MSPS
Differential input with 500 MHz bandwidth
On-chip reference and sample-and-hold
DNL = ±0.5 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty-cycle stabilizer
APPLICATIONS
Medical imaging equipment
IF sampling in communications receivers
WCDMA, CDMA-One, CDMA-2000, and TDS-CDMA
Battery-powered instruments
Hand-held scopemeters
Spectrum analyzers
Power-sensitive military applications
GENERAL DESCRIPTION
The AD9245 is a monolithic, single 3 V supply, 14-bit,
20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital
converter (ADC) featuring a high performance sample-andhold amplifier (SHA) and voltage reference. The AD9245 uses a
multistage differential pipelined architecture with output error
correction logic to provide 14-bit accuracy and guarantee no
missing codes over the full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and common modes, including
single-ended applications. It is suitable for multiplexed systems
that switch full-scale voltage levels in successive channels and
for sampling single-channel inputs at frequencies well beyond
the Nyquist rate. Combined with power and cost savings over
previously available analog-to-digital converters, the AD9245 is
suitable for applications in communications, imaging, and
medical ultrasound.
3 V A/D Converte
AD9245
FUNCTIONAL BLOCK DIAGRAM
DRVDDAVDD
AD9245
VIN+
VIN–
REFT
REFB
VREF
SENSE
SHA
REF
SELECT
A/D
AGND
MDAC1
4
0.5V
A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for
wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow. Fabricated on an advanced CMOS process, the
AD9245 is available in a 32-lead LFCSP and is specified over
the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9245 operates from a single 3 V power supply and
features a separate digital output driver supply to
accommodate 2.5 V and 3.3 V logic families.
2. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz and can be configured for
single-ended or differential operation.
3. The AD9245 is pin-compatible with the AD9215, AD9235,
and AD9236. This allows a simplified migration from 10 bits
to 14 bits and 20 MSPS to 80 MSPS.
4. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
5. The OTR output bit indicates when the signal is beyond the
selected input range.
8-STAGE
1 1/2-BIT PIPELINE
16
CORRECTION LOGIC
14
OUTPUT BUFFERS
CLOCK
DUTY CYCLE
STABILIZER
CLK PDWN MODE DGND
Figure 1.
MODE
SELECT
A/D
3
OTR
D13 (MSB)
D0 (LSB)
03583-001
r
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved.
AD9245
TABLE OF CONTENTS
Features.............................................................................................. 1
Typical Performance Characteristics........................................... 13
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 7
Switching Specifications.............................................................. 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Terminology .................................................................................... 10
Pin Configuration and Function Descriptions........................... 11
Theory of Operation ...................................................................... 18
Analog Input and Reference Overview ................................... 18
Clock Input Considerations...................................................... 19
Jitter Considerations .................................................................. 20
Power Dissipation and Standby Mode .................................... 20
Digital Outputs........................................................................... 20
Timing ......................................................................................... 21
Voltage Reference....................................................................... 21
Internal Reference Connection ................................................ 21
External Reference Operation .................................................. 22
Operational Mode Selection ..................................................... 22
Evaluation Board........................................................................ 22
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 29
Equivalent Circuits......................................................................... 12
REVISION HISTORY
1/06—Rev. C to Rev. D
Changes to Differential Input Configurations Section and
Figure 40 ..........................................................................................19
Changes to Internal Reference Connection Section ..................21
Changes to Figure 49...................................................................... 23
Changes to Figure 50...................................................................... 24
Changes to Table 12........................................................................ 28
Updated Outline Dimensions....................................................... 29
Changes to Ordering Guide.......................................................... 29
8/05—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Features, Applications, General Description, and
Product Highlights ........................................................................... 1
Added Table 1; Renumbered Sequentially .................................... 3
Changes to Table 2............................................................................ 4
Added Table 3; Renumbered Sequentially .................................... 5
Changes to Table 4............................................................................ 6
Changes to Table 5............................................................................ 7
Changes to Table 6............................................................................ 8
Deleted Explanation of Test Levels Table...................................... 8
Added Figure 26 to Figure 31; Renumbered Sequentially ........ 16
Added Figure 32 to Figure 37; Renumbered Sequentially ........ 17
Changes to Figure 39...................................................................... 18
Changes to Clock Input Consideration Section......................... 19
Changes to Figure 44...................................................................... 20
Changes to Table 10 ....................................................................... 21
Changes to Figure 51...................................................................... 25
Changes to Table 12 ....................................................................... 28
Changes to Ordering Guide.......................................................... 29
Updated Outline Dimensions....................................................... 29
10/03—Rev. A to Rev. B
Changes to Figure 33...................................................................... 17
5/03—Rev. 0 to Rev. A
Changes to Figure 30...................................................................... 15
Changes to Figure 37...................................................................... 19
Changes to Figure 38...................................................................... 20
Changes to Figure 39...................................................................... 21
Changes to Table 10 ....................................................................... 24
Changes to the Ordering Guide ................................................... 25
Rev. D | Page 2 of 32
AD9245
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise noted.
Table 1.
AD9245BCP-20 AD9245BCP-40 AD9245BCP-65
Parameter
Min Typ Max Min Typ Max Min Typ Max
RESOLUTION 14 14 14 Bits
ACCURACY
No Missing Codes Guaranteed 14 14 14 Bits
Offset Error ±0.30 ±1.60 ±0.50 ±1.75 ±0.50 ±1.75 % FSR
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
1
2
2
1
±0.30 ±3.25 ±0.50 ±3.25 ±0.50 ±6.90 % FSR
±0.50 ±1.00 ±0.50 ±1.00 ±0.50 ±1.00 LSB
±1.20 ±3.10 ±1.40 ±3.40 ±1.60 ±5.55 LSB
Offset Error ±2 ±2 ±3 ppm/°C
Gain Error ±12 ±12 ±12 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) ±5 ±35 ±5 ±35 ±5 ±35 mV
Load Regulation @ 1.0 mA 0.8 0.8 0.8 mV
Output Voltage Error (0.5 V Mode) ±2.5 ±2.5 ±2.5 mV
Load Regulation @ 0.5 mA 0.1 0.1 0.1 mV
INPUT REFERRED NOISE
VREF = 0.5 V 2.28 2.28 2.28 LSB rms
VREF = 1.0 V 1.08 1.08 1.08 LSB rms
ANALOG INPUT
Input Span, VREF = 0.5 V 1 1 1 V p-p
Input Span, VREF = 1.0 V 2 2 2 V p-p
Input Capacitance
3
7 7 7 pF
REFERENCE INPUT RESISTANCE 7 7 7 kΩ
POWER SUPPLIES
Supply Voltages
AVDD 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V
DRVDD 2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 V
Supply Current
2
IAVDD
IDRVDD
2
30 55 100 mA
2 5 7 mA
PSRR ±0.01 ±0.01 ±0.01 % FSR
POWER CONSUMPTION
DC Input
Sine Wave Input
Standby Power
1
Gain errors and gain temperature coefficients are based on the ADC only (with a fixed 1.0 V external reference).
2
Measured at maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4
Measured with dc input at maximum clock rate.
5
Standby power is measured with a dc input, the CLK pin inactive (that is, set to AVDD or AGND).
4
2
5
90 165 300 mW
95 120 180 220 320 375 mW
1.0 1.0 1.0 mW
Unit
Rev. D | Page 3 of 32
AD9245
AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, unless otherwise noted.
Table 2.
AD9245BCP-80
Parameter Min Typ Max Unit
RESOLUTION 14 Bits
ACCURACY
No Missing Codes Guaranteed
Offset Error
Gain Error ±0.28 % FSR
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error ±12 ppm/°C
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) ±3 ±34 mV
Load Regulation @ 1.0 mA ±2 mV
Output Voltage Error (0.5 V Mode) ±6 mV
Load Regulation @ 0.5 mA ±1 mV
INPUT REFERRED NOISE
VREF = 0.5 V 1.86 LSB rms
VREF = 1.0 V 1.17 LSB rms
ANALOG INPUT
Input Span, VREF = 0.5 V 1 V p-p
Input Span, VREF = 1.0 V 2 V p-p
Input Capacitance
REFERENCE INPUT RESISTANCE 7 kΩ
POWER SUPPLIES
Supply Voltage
AVDD 2.7 3.0 3.6 V
DRVDD 2.25 2.5 3.6 V
Supply Current
IAVDD
IDRVDD
PSRR ±0.01 % FSR
POWER CONSUMPTION
Low Frequency Input
Standby Power
1
With a 1.0 V internal reference.
2
Measured at the maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 4 for the equivalent analog input structure.
4
Measured at ac specification conditions without output drivers.
5
Standby power is measured with a dc input, CLK pin inactive (that is, set to AVDD or AGND).
1
1
2
2
1
1
3
2
2
4
5
±0.30 ±1.2 % FSR
±0.70 ±4.16 % FSR
±0.5 ±1.0 LSB
±1.4 ±5.15 LSB
±10 ppm/°C
±17 ppm/°C
7 pF
122 138 mA
9 mA
366 mW
1.0 mW
Rev. D | Page 4 of 32
AD9245
AC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, DCS off,
unless otherwise noted.
Table 3.
AD9245BCP-20 AD9245BCP-40 AD9245BCP-65
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
f
= 2.4 MHz 73.5 73.5 73.1 dBc
INPUT
f
= 9.7 MHz 70.6 73.3 dBc
INPUT
f
= 19.6 MHz 70.5 73.4 dBc
INPUT
f
= 32.5 MHz 70.3 72.7 dBc
INPUT
f
= 100 MHz 70.8 71.3 70.2 dBc
INPUT
SIGNAL-TO-NOISE RATIO AND DISTORTION (SINAD)
f
= 2.4 MHz 73.4 73.4 73.0 dBc
INPUT
f
= 9.7 MHz 69.4 73.2 dBc
INPUT
f
= 19.6 MHz 70.0 73.2 dBc
INPUT
f
= 32.5 MHz 68.4 72.6 dBc
INPUT
f
= 100 MHz 69.5 69.1 67.9 dBc
INPUT
EFFECTIVE NUMBER OF BITS (ENOB)
f
= 9.7 MHz 11.9 Bits
INPUT
f
= 19.6 MHz 11.8 Bits
INPUT
f
= 32.5 MHz 11.7 Bits
INPUT
WORST HARMONIC (SECOND OR THIRD)
f
= 9.7 MHz –89 –80 dBc
INPUT
f
= 19.6 MHz –89 –80 dBc
INPUT
f
= 32.5 MHz –83 –74 dBc
INPUT
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
= 2.4 MHz 92.0 92.0 92.0 dBc
INPUT
f
= 9.7 MHz 80.0 89.0 dBc
INPUT
f
= 19.6 MHz 80.0 89.0 dBc
INPUT
f
= 32.5 MHz 74.0 83.0 dBc
INPUT
f
= 100 MHz 84.0 85.0 80.5 dBc
INPUT
Rev. D | Page 5 of 32
AD9245
AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, AIN = –0.5 dBFS, DCS off,
unless otherwise noted.
Table 4.
AD9245BCP-80
Parameter Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz 71.1 73.3 dB
fIN = 40 MHz 72.7 dB
fIN = 70 MHz 70.5 71.7 dB
fIN = 100 MHz 70.2 dB
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.4 MHz 70.7 73.2 dB
fIN = 40 MHz 72.5 dB
fIN = 70 MHz 69.9 71.2 dB
fIN = 100 MHz 69.6 dB
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz 11.5 11.9 Bits
fIN = 40 MHz 11.8 Bits
fIN = 70 MHz 11.3 11.5 Bits
fIN = 100 MHz 11.3 Bits
WORST HARMONIC (SECOND OR THIRD)
fIN = 2.4 MHz −92.8 –76.5 dBc
fIN = 40 MHz –87.6 dBc
fIN = 70 MHz −81.6 –75.7 dBc
fIN = 100 MHz –79.0 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz 76.5 92.8 dBc
fIN = 40 MHz 87.6 dBc
fIN = 70 MHz 75.7 81.6 dBc
fIN = 100 MHz 79.0 dBc
Rev. D | Page 6 of 32
AD9245
DIGITAL SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, 1.0 V internal reference, unless otherwise noted.
Table 5.
AD9245BCP-20/AD9245BCP-40/AD9245BCP-65/AD9245BCP-80
Parameter Min Typ Max Unit
LOGIC INPUTS (CLK, PDWN)
High Level Input Voltage 2.0 V
Low Level Input Voltage 0.8 V
High Level Input Current –10 +10 μA
Low Level Input Current –10 +10 μA
Input Capacitance 2 pF
DIGITAL OUTPUT BITS (D0 to D13, OTR)
2
DRVDD = 3.3 V
High Level Output Voltage (IOH = 50 μA) 3.29 V
High Level Output Voltage (IOH = 0.5 mA) 3.25 V
Low Level Output Voltage (IOH = 1.6 mA) 0.2 V
Low Level Output Voltage (IOH = 50 μA) 0.05 V
DRVDD = 2.5 V
High Level Output Voltage (IOH = 50 μA) 2.49 V
High Level Output Voltage (IOH = 0.5 mA) 2.45 V
Low Level Output Voltage (IOH = 1.6 mA) 0.2 V
Low Level Output Voltage (IOH = 50 μA) 0.05 V
1
AD9245BCP-80 performance measured with 1.0 V external reference.
2
Output voltage levels measured with 5 pF load on each output.
1
Rev. D | Page 7 of 32
AD9245
SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted.
Table 6.
AD9245BCP-20 AD9245BCP-40 AD9245BCP-65 AD9245BCP-80 Unit
Parameter
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
CLOCK INPUT PARAMETERS
Maximum Conversion Rate 20 40 65 80 MSPS
Minimum Conversion Rate 1 1 1 1 MSPS
CLK Period 50.0 25.0 15.4 12.5 ns
CLK Pulse Width High
CLK Pulse Width Low
1
1
15.0 8.8 6.2 4.6 ns
15.0 8.8 6.2 4.6 ns
DATA OUTPUT PARAMETERS
Output Delay2 (tPD) 3.5 3.5 3.5 4.2 ns
Pipeline Delay (Latency) 7 7 7 7 Cycles
Aperture Delay (tA) 1.0 1.0 1.0 1.0 ns
Aperture Uncertainty Jitter (tJ) 0.5 0.5 0.5 0.3 ps rms
Wake-Up Time
3
3.0 3.0 3.0 7.0 ms
OUT-OF-RANGE RECOVERY TIME 1 1 2 2 Cycles
1
For the AD9245BCP-65 and AD9245BCP-80 models only, with duty cycle stabilizer enabled. DCS function not applicable for AD9245BCP-20 and AD9245BCP-40
models.
2
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
3
Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
N+1
ANALOG
INPUT
CLK
DATA
OUT
N
N–1
N–9N–8N–7N–6N–5N–4N–3N–2N–1 N
t
A
N+2
N+3
N+4
N+5
t
= 6.0ns MAX
PD
2.0ns MIN
N+6
N+7
N+8
03583-002
Figure 2. Timing Diagram
Rev. D | Page 8 of 32
AD9245
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter With Respect to Min Max Unit
ELECTRICAL
AVDD AGND –0.3 +3.9 V
DRVDD DGND –0.3 +3.9 V
AGND DGND –0.3 +0.3 V
AVDD DRVDD –3.9 +3.9 V
D0 to D13 DGND –0.3 DRVDD + 0.3 V
CLK, MODE AGND –0.3 AVDD + 0.3 V
VIN+, VIN– AGND –0.3 AVDD + 0.3 V
VREF AGND –0.3 AVDD + 0.3 V
SENSE AGND –0.3 AVDD + 0.3 V
REFT, REFB AGND –0.3 AVDD + 0.3 V
PDWN AGND –0.3 AVDD + 0.3 V
ENVIRONMENTAL
Storage Temperature Range –65 +125 °C
Operating Temperature Range –40 +85 °C
Lead Temperature
(Soldering 10 sec)
Junction Temperature 150 °C
300 °C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions on a 4-layer board
in still air, in accordance with EIA/JESD51-1.
Table 8. Thermal Resistance
Package Type
32-Lead LFCSP 32.5 32.71 °C/W
θJC
θ
JA
Airflow increases heat dissipation, effectively reducing θJA.
In addition, more metal directly in contact with the package
leads from metal traces, through holes, ground, and power
planes reduces the θ
. It is recommended that the exposed
JA
paddle be soldered to the ground plane for the LFCSP package.
There is an increased reliability of the solder joints, and
maximum thermal capability of the package is achieved with
the exposed paddle soldered to the customer board.
Unit
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 9 of 32
AD9245
(
−
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.
1
Aperture Delay (t
)
A
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter, t
)
J
The sample-to-sample variation in aperture delay.
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16,384
codes must be present over all operating ranges.
Offset Error
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN–. Offset error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value ½ LSB
above negative full scale. The last transition should occur at an
analog value 1½ LSB below the positive full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
Tem p er at u re Dr i ft
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at T
MIN
or T
MAX
.
Power Supply Rejection Ratio
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at its maximum limit.
1
Total Harmonic Distortion (THD)
The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.
Effective Number of Bits (ENOB)
The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured
SINAD using the following formula:
)
SINAD
=
ENOB
Signal-to-Noise Ratio (SNR)
1.76
6.02
1
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
1
The difference in dB between the rms input signal amplitude
and the peak spurious signal. The peak spurious component
may or may not be a harmonic.
Two -Tone SFDR
1
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the Logic 0 state. At a given clock rate,
these specifications define an acceptable clock duty cycle.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Output Propagation Delay (t
)
PD
The delay between the clock rising edge and the time when all
bits are within valid logic levels.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
1
AC specifications may be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
Rev. D | Page 10 of 32
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