Analog Devices AD9245 Service Manual

14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,

FEATURES

Single 3 V supply operation (2.7 V to 3.6 V) SNR = 72.7 dBc to Nyquist SFDR = 83.0 dBc to Nyquist Low power

366 mW at 80 MSPS 300 mW at 65 MSPS 165 mW at 40 MSPS

90 mW at 20 MSPS Differential input with 500 MHz bandwidth On-chip reference and sample-and-hold DNL = ±0.5 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary or twos complement data format Clock duty-cycle stabilizer

APPLICATIONS

Medical imaging equipment IF sampling in communications receivers

WCDMA, CDMA-One, CDMA-2000, and TDS-CDMA Battery-powered instruments Hand-held scopemeters Spectrum analyzers Power-sensitive military applications

GENERAL DESCRIPTION

The AD9245 is a monolithic, single 3 V supply, 14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC) featuring a high performance sample-andhold amplifier (SHA) and voltage reference. The AD9245 uses a multistage differential pipelined architecture with output error correction logic to provide 14-bit accuracy and guarantee no missing codes over the full operating temperature range.

The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and common modes, including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available analog-to-digital converters, the AD9245 is suitable for applications in communications, imaging, and medical ultrasound.

3 V A/D Converte

AD9245

FUNCTIONAL BLOCK DIAGRAM

DRVDDAVDD

AD9245

VIN+ VIN–

REFT REFB

VREF

SENSE

SHA

REF

SELECT

A/D

AGND

MDAC1

4

0.5V

A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in straight binary or twos complement formats. An out-of-range (OTR) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow. Fabricated on an advanced CMOS process, the AD9245 is available in a 32-lead LFCSP and is specified over the industrial temperature range (–40°C to +85°C).

PRODUCT HIGHLIGHTS

1. The AD9245 operates from a single 3 V power supply and

features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families.

2. The patented SHA input maintains excellent performance for

input frequencies up to 100 MHz and can be configured for single-ended or differential operation.

3. The AD9245 is pin-compatible with the AD9215, AD9235,

and AD9236. This allows a simplified migration from 10 bits to 14 bits and 20 MSPS to 80 MSPS.

4. The clock DCS maintains overall ADC performance over a

wide range of clock pulse widths.

5. The OTR output bit indicates when the signal is beyond the

selected input range.

8-STAGE

1 1/2-BIT PIPELINE

16

CORRECTION LOGIC

14

OUTPUT BUFFERS

CLOCK

DUTY CYCLE

STABILIZER

CLK PDWN MODE DGND

Figure 1.

MODE

SELECT

A/D

3

OTR

D13 (MSB) D0 (LSB)

03583-001

r

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9245

REVISION HISTORY

1/06—Rev. C to Rev. D Changes to Differential Input Configurations Section and

Figure 40 ..........................................................................................19

Changes to Internal Reference Connection Section ..................21

Changes to Figure 49...................................................................... 23

Changes to Figure 50...................................................................... 24

Changes to Table 12........................................................................ 28

Updated Outline Dimensions....................................................... 29

Changes to Ordering Guide.......................................................... 29

8/05—Rev. B to Rev. C

Updated Format..................................................................Universal

Changes to Features, Applications, General Description, and

Product Highlights ........................................................................... 1

Added Table 1; Renumbered Sequentially .................................... 3

Changes to Table 2............................................................................ 4

Added Table 3; Renumbered Sequentially .................................... 5

Changes to Table 4............................................................................ 6

Changes to Table 5............................................................................ 7

Changes to Table 6............................................................................ 8

Deleted Explanation of Test Levels Table...................................... 8

Added Figure 26 to Figure 31; Renumbered Sequentially ........ 16

Added Figure 32 to Figure 37; Renumbered Sequentially ........ 17

Changes to Figure 39...................................................................... 18

Changes to Clock Input Consideration Section......................... 19

Changes to Figure 44...................................................................... 20

Changes to Table 10 ....................................................................... 21

Changes to Figure 51...................................................................... 25

Changes to Table 12 ....................................................................... 28

Changes to Ordering Guide.......................................................... 29

Updated Outline Dimensions....................................................... 29

10/03—Rev. A to Rev. B

Changes to Figure 33...................................................................... 17

5/03—Rev. 0 to Rev. A

Changes to Figure 30...................................................................... 15

Changes to Figure 37...................................................................... 19

Changes to Figure 38...................................................................... 20

Changes to Figure 39...................................................................... 21

Changes to Table 10 ....................................................................... 24

Changes to the Ordering Guide ................................................... 25

Rev. D | Page 2 of 32

AD9245

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise noted.

Table 1.

AD9245BCP-20 AD9245BCP-40 AD9245BCP-65

Parameter

Min Typ Max Min Typ Max Min Typ Max

RESOLUTION 14 14 14 Bits ACCURACY

No Missing Codes Guaranteed 14 14 14 Bits Offset Error ±0.30 ±1.60 ±0.50 ±1.75 ±0.50 ±1.75 % FSR Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL)

TEMPERATURE DRIFT

1

2

1

±0.30 ±3.25 ±0.50 ±3.25 ±0.50 ±6.90 % FSR ±0.50 ±1.00 ±0.50 ±1.00 ±0.50 ±1.00 LSB ±1.20 ±3.10 ±1.40 ±3.40 ±1.60 ±5.55 LSB

Offset Error ±2 ±2 ±3 ppm/°C Gain Error ±12 ±12 ±12 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) ±5 ±35 ±5 ±35 ±5 ±35 mV Load Regulation @ 1.0 mA 0.8 0.8 0.8 mV Output Voltage Error (0.5 V Mode) ±2.5 ±2.5 ±2.5 mV Load Regulation @ 0.5 mA 0.1 0.1 0.1 mV

INPUT REFERRED NOISE

VREF = 0.5 V 2.28 2.28 2.28 LSB rms VREF = 1.0 V 1.08 1.08 1.08 LSB rms

ANALOG INPUT

Input Span, VREF = 0.5 V 1 1 1 V p-p Input Span, VREF = 1.0 V 2 2 2 V p-p Input Capacitance

3

7 7 7 pF REFERENCE INPUT RESISTANCE 7 7 7 kΩ POWER SUPPLIES

Supply Voltages

AVDD 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V DRVDD 2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 V

Supply Current

2

IAVDD IDRVDD

2

30 55 100 mA

2 5 7 mA

PSRR ±0.01 ±0.01 ±0.01 % FSR

POWER CONSUMPTION

DC Input Sine Wave Input Standby Power

1

Gain errors and gain temperature coefficients are based on the ADC only (with a fixed 1.0 V external reference).

2

Measured at maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

3

Input capacitance refers to the effective capacitance between one differential input pin and AGND.

4

Measured with dc input at maximum clock rate.

5

Standby power is measured with a dc input, the CLK pin inactive (that is, set to AVDD or AGND).

4

2

5

90 165 300 mW

95 120 180 220 320 375 mW

1.0 1.0 1.0 mW

Unit

Rev. D | Page 3 of 32

AD9245

AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, unless otherwise noted.

Table 2.

AD9245BCP-80 Parameter Min Typ Max Unit

RESOLUTION 14 Bits ACCURACY

No Missing Codes Guaranteed Offset Error Gain Error ±0.28 % FSR Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL)

TEMPERATURE DRIFT

Offset Error Gain Error ±12 ppm/°C Gain Error

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) ±3 ±34 mV Load Regulation @ 1.0 mA ±2 mV Output Voltage Error (0.5 V Mode) ±6 mV Load Regulation @ 0.5 mA ±1 mV

INPUT REFERRED NOISE

VREF = 0.5 V 1.86 LSB rms VREF = 1.0 V 1.17 LSB rms

ANALOG INPUT

Input Span, VREF = 0.5 V 1 V p-p Input Span, VREF = 1.0 V 2 V p-p

Input Capacitance REFERENCE INPUT RESISTANCE 7 kΩ POWER SUPPLIES

Supply Voltage

AVDD 2.7 3.0 3.6 V DRVDD 2.25 2.5 3.6 V

Supply Current

IAVDD IDRVDD

PSRR ±0.01 % FSR POWER CONSUMPTION

Low Frequency Input

Standby Power

1

With a 1.0 V internal reference.

2

Measured at the maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

3

Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 4 for the equivalent analog input structure.

4

Measured at ac specification conditions without output drivers.

5

Standby power is measured with a dc input, CLK pin inactive (that is, set to AVDD or AGND).

1

2

1

3

2

4

5

±0.30 ±1.2 % FSR

±0.70 ±4.16 % FSR ±0.5 ±1.0 LSB ±1.4 ±5.15 LSB

±10 ppm/°C

±17 ppm/°C

7 pF

122 138 mA 9 mA

366 mW

1.0 mW

Rev. D | Page 4 of 32

AD9245

AC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, DCS off, unless otherwise noted.

Table 3.

AD9245BCP-20 AD9245BCP-40 AD9245BCP-65 Parameter Min Typ Max Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

f

= 2.4 MHz 73.5 73.5 73.1 dBc

INPUT

f

= 9.7 MHz 70.6 73.3 dBc

INPUT

f

= 19.6 MHz 70.5 73.4 dBc

INPUT

f

= 32.5 MHz 70.3 72.7 dBc

INPUT

f

= 100 MHz 70.8 71.3 70.2 dBc

INPUT

SIGNAL-TO-NOISE RATIO AND DISTORTION (SINAD)

f

= 2.4 MHz 73.4 73.4 73.0 dBc

INPUT

f

= 9.7 MHz 69.4 73.2 dBc

INPUT

f

= 19.6 MHz 70.0 73.2 dBc

INPUT

f

= 32.5 MHz 68.4 72.6 dBc

INPUT

f

= 100 MHz 69.5 69.1 67.9 dBc

INPUT

EFFECTIVE NUMBER OF BITS (ENOB)

f

= 9.7 MHz 11.9 Bits

INPUT

f

= 19.6 MHz 11.8 Bits

INPUT

f

= 32.5 MHz 11.7 Bits

INPUT

WORST HARMONIC (SECOND OR THIRD)

f

= 9.7 MHz –89 –80 dBc

INPUT

f

= 19.6 MHz –89 –80 dBc

INPUT

f

= 32.5 MHz –83 –74 dBc

INPUT

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f

= 2.4 MHz 92.0 92.0 92.0 dBc

INPUT

f

= 9.7 MHz 80.0 89.0 dBc

INPUT

f

= 19.6 MHz 80.0 89.0 dBc

INPUT

f

= 32.5 MHz 74.0 83.0 dBc

INPUT

f

= 100 MHz 84.0 85.0 80.5 dBc

INPUT

Rev. D | Page 5 of 32

AD9245

AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, AIN = –0.5 dBFS, DCS off, unless otherwise noted.

Table 4.

AD9245BCP-80 Parameter Min Typ Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 2.4 MHz 71.1 73.3 dB

fIN = 40 MHz 72.7 dB

fIN = 70 MHz 70.5 71.7 dB

fIN = 100 MHz 70.2 dB SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 2.4 MHz 70.7 73.2 dB

fIN = 40 MHz 72.5 dB

fIN = 70 MHz 69.9 71.2 dB

fIN = 100 MHz 69.6 dB EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.4 MHz 11.5 11.9 Bits

fIN = 40 MHz 11.8 Bits

fIN = 70 MHz 11.3 11.5 Bits

fIN = 100 MHz 11.3 Bits WORST HARMONIC (SECOND OR THIRD)

fIN = 2.4 MHz −92.8 –76.5 dBc

fIN = 40 MHz –87.6 dBc

fIN = 70 MHz −81.6 –75.7 dBc

fIN = 100 MHz –79.0 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.4 MHz 76.5 92.8 dBc

fIN = 40 MHz 87.6 dBc

fIN = 70 MHz 75.7 81.6 dBc

fIN = 100 MHz 79.0 dBc

Rev. D | Page 6 of 32

AD9245

DIGITAL SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, 1.0 V internal reference, unless otherwise noted.

Table 5.

AD9245BCP-20/AD9245BCP-40/AD9245BCP-65/AD9245BCP-80 Parameter Min Typ Max Unit

LOGIC INPUTS (CLK, PDWN)

High Level Input Voltage 2.0 V Low Level Input Voltage 0.8 V High Level Input Current –10 +10 μA Low Level Input Current –10 +10 μA Input Capacitance 2 pF

DIGITAL OUTPUT BITS (D0 to D13, OTR)

2

DRVDD = 3.3 V

High Level Output Voltage (IOH = 50 μA) 3.29 V High Level Output Voltage (IOH = 0.5 mA) 3.25 V Low Level Output Voltage (IOH = 1.6 mA) 0.2 V Low Level Output Voltage (IOH = 50 μA) 0.05 V

DRVDD = 2.5 V

High Level Output Voltage (IOH = 50 μA) 2.49 V High Level Output Voltage (IOH = 0.5 mA) 2.45 V Low Level Output Voltage (IOH = 1.6 mA) 0.2 V Low Level Output Voltage (IOH = 50 μA) 0.05 V

1

AD9245BCP-80 performance measured with 1.0 V external reference.

2

Output voltage levels measured with 5 pF load on each output.

1

Rev. D | Page 7 of 32

AD9245

SWITCHING SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted.

Table 6.

AD9245BCP-20 AD9245BCP-40 AD9245BCP-65 AD9245BCP-80 Unit

Parameter

Min Typ Max Min Typ Max Min Typ Max Min Typ Max

CLOCK INPUT PARAMETERS

Maximum Conversion Rate 20 40 65 80 MSPS

Minimum Conversion Rate 1 1 1 1 MSPS

CLK Period 50.0 25.0 15.4 12.5 ns

CLK Pulse Width High

CLK Pulse Width Low

1

15.0 8.8 6.2 4.6 ns

DATA OUTPUT PARAMETERS

Output Delay2 (tPD) 3.5 3.5 3.5 4.2 ns

Pipeline Delay (Latency) 7 7 7 7 Cycles

Aperture Delay (tA) 1.0 1.0 1.0 1.0 ns

Aperture Uncertainty Jitter (tJ) 0.5 0.5 0.5 0.3 ps rms

Wake-Up Time

3

3.0 3.0 3.0 7.0 ms

OUT-OF-RANGE RECOVERY TIME 1 1 2 2 Cycles

1

For the AD9245BCP-65 and AD9245BCP-80 models only, with duty cycle stabilizer enabled. DCS function not applicable for AD9245BCP-20 and AD9245BCP-40

models.

2

Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.

3

Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.

N+1

ANALOG

INPUT

CLK

DATA

OUT

N

N–1

N–9N–8N–7N–6N–5N–4N–3N–2N–1 N

t

A

N+2

N+3

N+4

N+5

t

= 6.0ns MAX

PD

2.0ns MIN

N+6

N+7

N+8

03583-002

Figure 2. Timing Diagram

Rev. D | Page 8 of 32

AD9245

ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter With Respect to Min Max Unit ELECTRICAL

AVDD AGND –0.3 +3.9 V DRVDD DGND –0.3 +3.9 V AGND DGND –0.3 +0.3 V AVDD DRVDD –3.9 +3.9 V D0 to D13 DGND –0.3 DRVDD + 0.3 V CLK, MODE AGND –0.3 AVDD + 0.3 V VIN+, VIN– AGND –0.3 AVDD + 0.3 V VREF AGND –0.3 AVDD + 0.3 V SENSE AGND –0.3 AVDD + 0.3 V REFT, REFB AGND –0.3 AVDD + 0.3 V PDWN AGND –0.3 AVDD + 0.3 V

ENVIRONMENTAL

Storage Temperature Range –65 +125 °C Operating Temperature Range –40 +85 °C Lead Temperature

(Soldering 10 sec) Junction Temperature 150 °C

300 °C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions on a 4-layer board in still air, in accordance with EIA/JESD51-1.

Table 8. Thermal Resistance

Package Type

32-Lead LFCSP 32.5 32.71 °C/W

θJC

θ

JA

Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the θ

. It is recommended that the exposed

JA

paddle be soldered to the ground plane for the LFCSP package. There is an increased reliability of the solder joints, and maximum thermal capability of the package is achieved with the exposed paddle soldered to the customer board.

Unit

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. D | Page 9 of 32

AD9245

(

−

TERMINOLOGY

Analog Bandwidth (Full Power Bandwidth)

The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.

Signal-to-Noise and Distortion (SINAD)

The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc.

1

Aperture Delay (t

)

A

The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter, t

)

J

The sample-to-sample variation in aperture delay.

Integral Nonlinearity (INL)

The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16,384 codes must be present over all operating ranges.

Offset Error

The major carry transition should occur for an analog value ½ LSB below VIN+ = VIN–. Offset error is defined as the deviation of the actual transition from that point.

Gain Error

The first code transition should occur at an analog value ½ LSB above negative full scale. The last transition should occur at an analog value 1½ LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.

Tem p er at u re Dr i ft

The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at T

MIN

or T

MAX

.

Power Supply Rejection Ratio

The change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit.

1

Total Harmonic Distortion (THD)

The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components.

Effective Number of Bits (ENOB)

The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula:

)

SINAD

=

ENOB

Signal-to-Noise Ratio (SNR)

1.76

6.02

1

The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

1

The difference in dB between the rms input signal amplitude and the peak spurious signal. The peak spurious component may or may not be a harmonic.

Two -Tone SFDR

1

The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product.

Clock Pulse Width and Duty Cycle

Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the Logic 0 state. At a given clock rate, these specifications define an acceptable clock duty cycle.

Minimum Conversion Rate

The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The clock rate at which parametric testing is performed.

Output Propagation Delay (t

)

PD

The delay between the clock rising edge and the time when all bits are within valid logic levels.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.

1

AC specifications may be reported in dBc (degrades as signal levels are

lowered) or in dBFS (always related back to converter full scale).

Rev. D | Page 10 of 32

AD9245

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

32 AVDD

31 AGND

30 VIN–

29 VIN+

28 AGND

27 AVDD

26 REFT

25 REFB

DNC 1

CLK 2

DNC 3

PDWN 4

(LSB) D0 5

D1 6 D2 7 D3 8

AD9245

CSP

TOP VIEW

(Not to Scale)

D4 9

D5 10

D6 11

D7 12

D8 13

D9 14

Figure 3. LFCSP Pin Configuration

DGND 15

DRVDD 16

24 VREF 23 SENSE 22 MODE 21 OTR 20 D13 (MSB) 19 D12 18 D11 17 D10

03583-022

Table 9. Pin Function Descriptions

Pin No. Mnemonic Description

1, 3 DNC Do Not Connect 2 CLK Clock Input Pin 4 PDWN Power-Down Function Select 5 to 14, 17 to 20 D0 (LSB) to D13 (MSB) Data Output Bits 15 DGND Digital Output Ground 16 DRVDD Digital Output Driver Supply 21 OTR Out-of-Range Indicator 22 MODE Data Format Select and DCS Mode Selection (See Table 11) 23 SENSE Reference Mode Selection (See Table 10) 24 VREF Voltage Reference Input/Output 25 REFB Differential Reference (–) 26 REFT Differential Reference (+) 27, 32 AVDD Analog Power Supply 28, 31 AGND Analog Ground 29 VIN+ Analog Input Pin (+) 30 VIN– Analog Input Pin (–)

Rev. D | Page 11 of 32

AD9245

EQUIVALENT CIRCUITS

AVDD

VIN+, VIN–

003

03583-

Figure 4. Equivalent Analog Input Circuit

AVDD

MODE

20kΩ

-004

03583

Figure 5. Equivalent MODE Input Circuit

DRVDD

Figure 6. Equivalent Digital Output Circuit

AVDD

CLK,

PDWN

Figure 7. Equivalent Digital Input Circuit

D13-D0, OTR

006

03583-

-005

03583

Rev. D | Page 12 of 32

AD9245

TYPICAL PERFORMANCE CHARACTERISTICS

DUT = AD9245-80, AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, DCS disabled, TA = 25°C, 2 V p-p differential input, AIN = −0.5 dBFS, VREF = 1.0 V external, unless otherwise noted.

0 –10 –20 –30 –40 –50 –60 –70 –80

AMPLITUDE (dBFS)

–90

–100 –110 –120

0 5 10 15 20 25 30 35

FREQUENCY (MHz)

Figure 8. Single Tone 8K FFT @ 2.5 MHz

AIN = –0.5dBFS SNR = 73.2dBc ENOB = 11.8 BITS SFDR = 92.8dBc

03583-032

40

100

90

80

70

60

SNR/SFDR (dBc AND dBFS)

50

40

–30 –25 –20 –15 –10 –5

SFDR (dBc)

SFDR = 90dBc REFERENCE LINE

SNR (dBc)

INPUT AMPLITUDE (dBFS)

SFDR (dBFS)

SNR (dBFS)

Figure 11. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 2.5 MHz

03583-033

0

AIN = –0.5dBFS SNR = 72.7dBc

–10

ENOB = 11.8 BITS SFDR = 87.6dBc

–20 –30 –40 –50 –60 –70 –80

AMPLITUDE (dBFS)

–90

–100 –110 –120

0 5 10 15 20 25 30 35

FREQUENCY (MHz)

Figure 9. Single Tone 8K FFT @ 39 MHz

0 –10 –20 –30 –40 –50 –60 –70 –80

AMPLITUDE (dBFS)

–90

–100 –110 –120

0 5 10 15 20 25 30 35

AIN = –0.5dBFS SNR = 71.7dBc ENOB = 11.5 BITS SFDR = 81.6dBc

FREQUENCY (MHz)

Figure 10. Single Tone 8K FFT @ 70 MHz

100

90

80

70

60

SNR/SFDR (dBc AND dBFS)

50

03583-023

40

–30 –25 –20 –15 –10 –5

SFDR (dBc)

SFDR = 90dBc REFERENCE LINE

SNR (dBc)

INPUT AMPLITUDE (dBFS)

SFDR (dBFS)

SNR (dBFS)

03583-034

0

Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 39 MHz

100

SFDR (DIFF)

90

SFDR (SE)

80

70

SNR/SFDR (dBc)

60

03583-024

40

50

0 20406080

SAMPLE RATE (MSPS)

SNR (DIFF)

SNR (SE)

100

03583-025

Figure 13. SNR/SFDR vs. Sample Rate @ 40 MHz

Rev. D | Page 13 of 32

AD9245

0

AIN = –6.5dBFS

–10

SNR = 73.4dBFS SFDR = 86.0dBFS

–20 –30 –40 –50 –60 –70 –80

AMPLITUDE (dBFS)

–90 –100 –110 –120

0 5 10 15 20 25 30 35

FREQUENCY (MHz)

Figure 14. Two-Tone 8K FFT @ 30 MHz and 31 MHz

03583-029

40

100

90

80

70

60

SNR/SFDR (dBc AND dBFS)

50

40

–30 –27 –24 –21 –18 –15 –12 –9

SFDR = 90dBc REFERENCE LINE

SFDR (dBc)

INPUT AMPLITUDE (dBFS)

SFDR (dBFS)

SNR (dBFS)

SNR (dBc)

–6

Figure 17. Two-Tone SNR/SFDR vs. Input Amplitude @ 30 MHz and 31 MHz

03583-031

0 –10 –20 –30 –40 –50 –60 –70 –80

AMPLITUDE (dBFS)

–90

–100 –110 –120

0 5 10 15 20 25 30 35

FREQUENCY (MHz)

Figure 15. Two-Tone 8K FFT @ 69 MHz and 70 MHz

1.5

1.0

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

0 2048 4096 6144 8192 10240 12288 14336

CODE

Figure 16. Typical INL

AIN = –6.5dBFS SNR = 72.7dBFS SFDR = 78.8dBFS

40

16384

03583-030

03583-026

100

90

80

70

60

SNR/SFDR (dBc AND dBFS)

50

40

–30 –27 –24 –21 –18 –15 –12 –9

SFDR = 90dBc REFERENCE LINE

INPUT AMPLITUDE (dBFS)

SFDR (dBFS)

SFDR (dBc)

SNR (dBFS)

SNR (dBc)

03583-027

–6

Figure 18. Two-Tone SNR/SFDR vs. Input Amplitude @ 69 MHz and 70 MHz

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL (LSB)

–0.4

–0.6

–0.8

–1.0

0 2048 4096 6144 8192 10240 12288 14336

CODE

16384

03583-028

Figure 19. Typical DNL

Rev. D | Page 14 of 32

AD9245

75

74

73

72

71

70

69

SNR (dBc)

68

67

66

65

0 25 50 75 100

–40°C

+25°C

+85°C

INPUT FREQUENCY (MHz)

Figure 20. SNR vs. Input Frequency

03583-036

125

100

95

90

85

SFDR (dBc)

80

75

70

0 25 50 75 100

INPUT FREQUENCY (MHz)

Figure 23. SFDR vs. Input Frequency

–40°C

+25°C

+85°C

125

03583-038

90

SFDR (DCS ON)

88

86

84

82

80

78

SNR/SFDR (dBc)

76

74

72

70

30 35 40 45 50 55 60 65

SFDR (DCS OFF)

SNR (DCS OFF)

SNR (DCS ON)

DUTY CYCLE (%)

Figure 21. SNR/SFDR vs. Clock Duty Cycle

0 –10 –20 –30 –40 –50 –60 –70 –80

AMPLITUDE (dBFS)

–90

–100

–110

–120

0 9.6 19.2 28.8 38.4

FREQUENCY (MHz)

Figure 22. 32K FFT WCDMA Carrier @ F

= 96 MHz; Sample Rate = 76.8 MSPS

IN

70

03583-037

03583-059

0 –10 –20 –30 –40 –50 –60 –70 –80

AMPLITUDE (dBFS)

–90

–100 –110 –120

0 9.6 19.2 28.8 38.4

FREQUENCY (MHz)

Figure 24. Two 32K FFT CDMA-2000 Carriers @

= 46.08 MHz; Sample Rate = 61.44 MSPS

F

IN

0 –10 –20 –30 –40 –50 –60 –70 –80

AMPLITUDE (dBFS)

–90

–100

–110

–120

0 9.6 19.2 28.8 38.4

FREQUENCY (MHz)

Figure 25. Two 32K FFT WCDMA Carriers @

= 76.8 MHz; Sample Rate = 61.44 MSPS

F

IN

03583-060

03583-061

Rev. D | Page 15 of 32

AD9245

0

–20

–40

AIN = –0.5dBFS SNR = 72.7dBc ENOB = 11.7 BITS SFDR = 81.3dBc

0

–20

–40

AIN = –0.5dBFS SNR = 73.4dBc ENOB = 11.9 BITS SFDR = 88.3dBc

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 5 10 15 20 25 30

FREQUENCY (MHz)

Figure 26. AD9245-65 Single Tone 16K FFT @ 35 MHz

2.0

1.5

1.0

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

–2.0

0 2048 4096 6144 8192 10240 12288 14336 16384

CODE

Figure 27. AD9245-65 Typical INL

2.0

1.5

1.0

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

–2.0

0 2048 4096 6144 8192 10240 12288 14336 16384

CODE

Figure 28. AD9245-40 Typical INL

03583-062

03583-063

03583-064

–60

–80

AMPLITUDE (dBFS)

–100

–120

02468101214161820

FREQUENCY (MHz)

Figure 29. AD9245-40 Single Tone 16K FFT @ 19.7 MHz

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 2048 4096 6144 8192 10240 12288 14336 16384

CODE

Figure 30. AD9245-65 Typical DNL

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 2048 4096 6144 8192 10240 12288 14336 16384

CODE

Figure 31. AD9245-40 Typical DNL

03583-065

03583-066

03583-067

Rev. D | Page 16 of 32

AD9245

2.0

1.5

1.0

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

–2.0

0 2048 4096 6144 8192 10240 12288 14336 16384

CODE

Figure 32. AD9245-20 Typical INL

0

AIN = –0.5dBFS SNR = 73.4dBc

–20

ENOB = 11.9 BITS SFDR = 95.0dBc

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 2048 4096 6144 8192 10240 12288 14336 16384

CODE

Figure 35. AD9245-20 Typical DNL

0

AIN = –0.5dBFS SNR = 73.3dBc

–20

ENOB = 11.9 BITS SFDR = 92.6dBc

03583-071

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

012345678910

FREQUENCY (MHz)

Figure 33. AD9245-20 Single Tone 16K FFT @ 5 MHz

75

–0.5dBFS

70

–6dBFS

65

60

SINAD (dBc)

55

–20dBFS

50

1 10 100

INPUT FREQUENCY (MHz)

Figure 34. AD9245-20 SINAD vs. Input Frequency

03583-069

03583-070

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

012345678910

FREQUENCY (MHz)

Figure 36. AD9245-20 Single Tone 16K FFT @ 9.7 MHz

10004707

7281624

HITS

1755666

253625

N–3 N–2 N–1 N N+1 N+2 N+3

7996189

3167101

547498

CODE

Figure 37. AD9245-20 Grounded-Input Histogram

03583-072

03583-073

Rev. D | Page 17 of 32

AD9245

THEORY OF OPERATION

The AD9245 architecture consists of a front-end sample-andhold amplifier (SHA) followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections consisting of a 4-bit first stage followed by eight 1.5-bit stages, and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.

The input stage contains a differential SHA that can be ac-coupled or dc-coupled in differential or single-ended modes. The output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state.

ANALOG INPUT AND REFERENCE OVERVIEW

The analog input to the AD9245 is a differential switchedcapacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input can support a wide common-mode range (VCM) and maintain excellent performance, as shown in common-mode voltage of midsupply minimizes signaldependent errors and provides optimum performance.

100

95

90

85

80

75

70

SNR/SFDR (dBc)

65

60

55

50

0.5 1.0 1.5 2.0 2.5

Figure 38. AD9245-80 SNR/SFDR vs. Common-Mode Level

SFDR (2.5MHz)

SFDR (39MHz)

COMMON-MODE LEVEL (V)

Figure 38. An input

SNR (2.5MHz)

SNR (39MHz)

03583-039

3.0

Referring to Figure 39, the clock signal alternately switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. In addition, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC’s input; therefore, the precise values are dependent upon the application. In IF undersampling applications, any shunt capacitors should be reduced or removed. In combination with the driving source impedance, they would limit the input bandwidth.

H

VIN+

VIN–

T

C

PAR

T

C

PAR

Figure 39. Switched-Capacitor SHA Input

5pF

T

012

H

03583-

For best dynamic performance, the source impedances driving VIN+ and VIN– should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC.

An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as:

REFT = ½ (AVDD + VREF)

REFB = ½ (AVDD − VREF)

Span = 2 × (REFT − REFB) = 2 × VREF

The previous equations show that the REFT and REFB voltages are symmetrical about the midsupply voltage, and, by definition, the input span is twice the value of the VREF voltage.

The internal voltage reference can be pin strapped to fixed values of 0.5 V or 1.0 V, or adjusted within the same range as discussed in the

Internal Reference Connection section. Maximum SNR performance is achieved with the AD9245 set to the largest input span of 2 V p-p. The relative SNR degradation is 3 dB when changing from 2 V p-p mode to 1 V p-p mode.

Rev. D | Page 18 of 32

AD9245

2

The SHA can be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as

VCM

VREF

=

MIN

MAX

2

()

=

VREFAVDD

+

2

The minimum common-mode input level allows the AD9245 to accommodate ground referenced inputs.

Although optimum performance is achieved with a differential input, a single-ended source can be applied to VIN+ or VIN–. In this configuration, one input accepts the signal, while the opposite input is set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal can be applied to VIN+ while a 1 V reference is applied to VIN–. The AD9245 then accepts an input signal varying between 2 V and 0 V. In the single-ended configuration, distortion performance can degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies.

Differential Input Configurations

As previously detailed, optimum performance is achieved while driving the AD9245 in a differential input configuration. For baseband applications, the AD8351 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8351 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.

1kΩ

0.1μF

33Ω

20pF

33Ω

AVDD

VIN+

AD9245

VIN–

AGND

1.2kΩ

0.1μF

2V p-p

50Ω

Figure 40. Differential Input Configuration Using the AD8351

25Ω

0.1μF

AD8351

At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9245. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration. The value of the shunt capacitor is dependent on the input frequency and source impedance and should be reduced or removed. An example is shown in

Figure 41.

33Ω

V p-p

49.9Ω

0.1μF

Figure 41. Differential Transformer-Coupled Configuration

20pF

33Ω

1kΩ

The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion.

Single-Ended Input Configuration

A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, there is a degradation in SFDR and distortion performance due to the large input common-mode swing (see

Figure 13). However, if the source impedances on each input are matched, there should be little effect on SNR performance.

Figure 42 details a typical

single-ended input configuration.

Ω

V p-p

1k

49.9

0.33μF

Ω

+

10μF 0.1μF

Figure 42. Single-Ended Input Configuration

1k

Ω

33

Ω

20pF

1k

Ω

33

Ω

1k

Ω

CLOCK INPUT CONSIDERATIONS

03583-013

Typical high speed ADCs use both clock edges to generate a variety of internal timing signals, and as a result can be sensitive to clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9245-80 and AD9245-65 contain a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9245. As shown in

Figure 21, noise and distortion performance is nearly flat for a 30% to 70% duty cycle with the DCS on.

The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 100 clock cycles to allow the DLL to acquire and lock to the new rate.

AVDD

VIN+

AD9245

VIN–

AGND

AVDD

VIN+

AD9245

VIN–

AGND

014

03583-

015

03583-

Rev. D | Page 19 of 32

AD9245

JITTER CONSIDERATIONS

High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (f calculated with the following equation:

SNR = −20log

) due only to aperture jitter (tJ) can be

INPUT

10

[2π f

INPUT

× tj]

which is determined by the sample rate and the characteristics of the analog input signal.

450

400

AD9245-80

350

In the equation, the rms aperture jitter represents the rootmean square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter (see

Figure 43).

The clock input should be treated as an analog signal in cases where aperture jitter can affect the dynamic range of the AD9245. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.

75

70

65

60

55

SNR (dBc)

50

45

40

1

INPUT FREQUENCY (MHz)

Figure 43. SNR vs. Input Frequency and Jitter

0.2ps

MEASURED SNR

0.5ps

1.0ps

1.5ps

2.0ps

2.5ps

3.0ps

100010010

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 44, the power dissipated by the AD9245 is proportional to its sample rate. The digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current (I

) can be calculated as

DRVDD

NfCVI

×××=

DRVDDDRVDD

CLKLOAD

where N is the number of output bits, 14 in the case of the AD9245. This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency, f

/2. In practice, the DRVDD current

CLK

is established by the average number of output bits switching,

300

250

200

TOTAL POWER (mW)

150

AD9245-20

100

50

0 1020304050607080

Figure 44. AD9245 Power vs. Sample Rate @ 2.5 MHz

AD9245-40

AD9245-65

SAMPLE RATE (MSPS)

03583-074

Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in

Figure 44 was taken with the same operating conditions as those reported in the

Typical Perf o r mance Chara c teristi c s section, and with a

5 pF load on each output driver.

By asserting the PDWN pin high, the AD9245 is placed in standby mode. In this state, the ADC typically dissipates 1 mW if the CLK and analog inputs are static. During standby, the output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the AD9245 to its normal operational mode.

Low power dissipation in standby mode is achieved by shutting down the reference, reference buffer, and biasing networks. The

03583-041

decoupling capacitors on REFT and REFB are discharged when entering standby mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in standby mode, and shorter standby cycles result in proportionally shorter wake-up times. With the recommended 0.1 μF and 10 μF decoupling capacitors on REFT and REFB, it takes approximately 1 second to fully discharge the reference buffer decoupling capacitors and 7 ms to restore full operation.

DIGITAL OUTPUTS

The AD9245 output drivers can be configured to interface with

2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies, which can affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts can require external buffers or latches.

Rev. D | Page 20 of 32

AD9245

As detailed in Tab l e 1 1 , the data format can be selected for either offset binary or twos complement.

TIMING

The AD9245 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (t

) after the rising edge of the clock signal. Refer to

PD

Figure 2 for a detailed timing diagram.

The length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD9245. These transients can degrade the converter’s dynamic performance.

The lowest typical conversion rate of the AD9245 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance can degrade.

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into the AD9245. The input range can be adjusted by varying the reference voltage applied to the AD9245 using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in and described in the following sections.

If the ADC is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage).

Tabl e 10

In all reference configurations, REFT and REFB drive the A/D conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.

VIN+

10μF+0.1μF

VIN–

ADC

CORE

VREF

SELECT

LOGIC

SENSE

0.5V

AD9245

Figure 45. Internal Reference Configuration

REFT

0.1μF

0.1μF 10μF

REFB

0.1μF

03583-017

+

If the internal reference of the AD9245 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered.

Figure 46 depicts how the internal reference voltage is affected by loading. A 2 mA load is the maximum recommended load.

INTERNAL REFERENCE CONNECTION

0.05

A comparator within the AD9245 detects the potential at the SENSE pin and configures the reference into one of four possible states, which are summarized in

Tabl e 10 . If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see

Figure 45), setting VREF to 1 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected as shown in

Figure 47, the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as

R2

⎞

⎛

VREF 15.0

+×=

⎟

⎜

R1

⎠

⎝

0

–0.05

–0.10

ERROR (%)

–0.15

–0.20

–0.25

0 0.5 1.0 1.5 2.0 2.5 3.0

1.0V ERROR (%)

LOAD (mA)

Figure 46. VREF Accuracy vs. Load

0.5V ERROR (%)

Table 10. Reference Configuration Summary

Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p)

External Reference AVDD N/A 2 × External Reference Internal Fixed Reference VREF 0.5 1.0 Programmable Reference 0.2 V to VREF

R2

⎞

⎛ ⎜ ⎝

10.5

+×

R1

(See Figure 47)

⎟ ⎠

2 × VREF

Internal Fixed Reference AGND to 0.2 V 1.0 2.0

3-019

0358

Rev. D | Page 21 of 32

AD9245

OPERATIONAL MODE SELECTION

VIN+

10μF+0.1μF

VIN–

ADC

CORE

VREF

R2 SENSE

R1

Figure 47. Programmable Reference Configuration

SELECT

LOGIC

0.5V

AD9245

REFT

0.1μF

0.1μF 10μF

REFB

0.1μF

03583-018

+

EXTERNAL REFERENCE OPERATION

The use of an external reference can be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) can be necessary to reduce gain matching errors to an acceptable level. the typical drift characteristics of the internal reference in both

1.0 V and 0.5 V modes.

When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 kΩ load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1.0 V.

1.0

0.9

0.8

0.7

0.6

0.5

0.4

VREF ERROR (%)

0.3

0.2

0.1

0

–40

Figure 48. Typical VREF Drift

VREF = 1.0V

VREF = 0.5V

TEMPERATURE (°C)

Figure 48 shows

80706050403020100–10–20–30

03583-040

As discussed earlier, the AD9245 can output data in either offset binary or twos complement format. There is also a provision for enabling or disabling the clock DCS. The MODE pin is a multilevel input that controls the data format and DCS state. The input threshold values and corresponding mode selections are outlined in

Tabl e 1 1 .

Table 11. Mode Selection

MODE Voltage Data Format Duty Cycle Stabilizer

AVDD Twos Complement Disabled 2/3 AVDD Twos Complement Enabled 1/3 AVDD Offset Binary Enabled AGND (Default) Offset Binary Disabled

EVALUATION BOARD

The AD9245 evaluation board provides the support circuitry required to operate the ADC in its various modes and configurations. Complete schematics and layout plots follow and demonstrate the proper routing and grounding techniques that should be applied at the system level.

It is critical that signal sources with very low phase noise (<1 ps rms jitter) be used to realize the ultimate performance of the converter. Proper filtering of the input signal, to remove harmonics and lower the integrated noise at the input, is also necessary to achieve the specified noise performance.

The AD9245 can be driven single-ended or differentially through a transformer. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics).

An alternative differential analog input path using an AD8351 op amp is included in the layout but is not populated in production. Designers interested in evaluating the op amp with the ADC should remove C15, R12, and R3 and populate the op amp circuit. The passive network between the AD8351 outputs and the AD9245 allows the user to optimize the frequency response of the op amp for the application.

Rev. D | Page 22 of 32

AD9245

X

6

1 H

D N G

E L O H T

2

M

H

1

P6

AVDD

EXTREF

1V MAX E1

6 E L O H T M

6 E L O H T

3

H

M

P2

6

45

123

Ω

5

k

R

1

P11

AVDD

P8 P9

GND

R1

4 H

MODE

C22

C13

10kΩ

6 E L O H T M

5.0V

VAMP

VDL

2.5V

GND

2.5V

DRVDD

GND

3.0V

AVDD

P5

2

P1

10μF

0.10μF

D C

E

B A

P7

7 R

GND

Ω

k 1

3

P10

IT B

E G N A R R E V O

C8

0.1μF GND

C12

10kΩ

4

Ω

6

k

R

1

C9

0.10μF

GND GND

P3

0.1μF

R9

Ω

0 2

2 2 P R

P4

GND

0.1μF

C29

X

X R D

6 1

1

) B S

(M

C11

10μF

GND

X

0

9

1

D

2

1

0

1

5

6

7

D10 D11 D12 D13

OTR

MODE

SENSE

VREF

GND

7 2

C

2

D

4

N

R

, A 7 1

, C 5 1

, C 2 1

, R 3

R E V O M E R

X

7

8

D

9

8

D D V R D

D D V D

REFB

25262728293031

D N G

D D V A

E B

D L U O H

7 1

S E

, C

N

2 4

O Y

, R

L

2

N

1

O

R

Ω

0

F

μ

6

.1

C

0

1

3

2

1

D

5

4

3

1

2

3

4

17 18 19 20 21 22 23 24

C7

0.1μF

. 8 1

C D N

T

, A

U

6

P

, C

IN

2 4

D E

, R

D

9

N

1

E

, R

E

8

L

1

G

R

IN

E

S

C

R

A L

O F

P

6 1

E IM

T A

D R A O

B N O

D N G

5 1

D N G D

T F E R

6 2 R

6 3 R

4 1

9 D

U4

AD9245

D

N

D V

G

A

D

N

V

G

A

Ω

k 1

Ω

k 1

2 1 R

IN P M A

X

6

5

4

D

5

4

6

1

2

3

1

3

2

1

8

7

6

5

D

+

–

N G

IN

A

V

+

–

D

IN

N

V

G

1 2 C

Ω

4

3

R

3

Ω

0

OUT

X

3

2

1

0

D

Ω

0 2

2

:

1

R

P

E

R

P M U J E

L B A R E D L O

S IN P

E S N E S

R

D

E

N

T

G

IL F R O

F

1

Ω

1

6

R

3

D N G

OPTIONAL XFR

T2

R E

ID IV D

E G A T L O V L A N R E T X E :

A O T E

B

OUT

X

) T L U A F E

(D E C N E R E F E

R V 1 L A N R E T

IN : B O T

E

F

3

p

2

0

C

1

FT C1–1–13

F F

N

E C

:

O

N

S

F

R

E

N

F

E

C

R

P

D

O

/

/D

N

E

M

T

S

E

F E

R E

R

F

V

E

.5 0

L R

L

A

N

R

E

T

X E

IN

:

C

D

O

T

E

Ω

8

k

R

1

K L C

3

Ω

R

0

T

OUT

C

X

2

5

1

IN R F X

S

U

N

C

E

J

/D

E

M

Y

L

E

R

B

L

A

P

IN

R

M

E

O

B

D

T

C

L

E

S

O

S

O

F

S

F

W

IN

T

O

:

P E

1

2

3

4

D

O

T

M

5

D N G

P13

P14

D D V A

D N G

5

Ω

2

k

R

1

3

Ω

1

k

R

1

D D V A

5

Ω

1

3

R

3

F

μ

0

8 1

.1

C

0

R SINGLE ENDED

D N

B IN

P M A

B

OUT

X

C

4

E S I R

3

P

D N G

G

R18

25Ω

R3, R16, C18

ONLY ONE SHOULD BE

ON BOARD AT A TIME

03583-050

3

2

1

0

1

9

4

5

6

7

8

) B S

(L

0 1

9 4

32

T 1

D D V A

F

p 0 1

D D V A

1 L

D

0 1 R

ADT1–1WT

H n 0 1

1 J

D N G

6 2 C

Ω

6

5

3

4 E

6

1

XFRIN1

9 1 C

F 0p

2

2 R

D

N

G

F p 0 1

6 1 C

CT

2

5

34

NC

D N G

F

μ

15

.1

C

0

P M A

D3

8 7

D2

D1

6

D0

5

PDWN

4

DNC

3

CLK

2

DNC

1

1 L R O

P N D

5 C

F

μ

.1 0

C E S

I R P

D N G

F

μ

.1 0

Figure 49. LFCSP Evaluation Board Schematic—Analog Inputs and DUT

Rev. D | Page 23 of 32

AD9245

D N G

9

7

5

1

3

1

3

1

2 1 P

4

2

4

2

D N

R

G

D

Y R D

D

N

G

3

4

2

4 7 3 2 6 1

1

H

U

T V

L 4 7

2OE

2CLK

C A D

/ T A K L C

2Q7

2QB

GND

2DB

2D7

GND

6

5

7

2

DRX

GND

D13X

B S M

1

9

7

5

6

1 2

8 2

5

6

D N G

B S M

2Q6

2D6

D12X

1 1

9

7

2

0

1

8

2

0

1

8

D D V R D

9

0

8

1

2

1

CC

2Q4

V

2Q5

CC

2D4

V

2D5

0

9

1

3

2

3

D11X

D10X

DRVDD

1

4 1

7 1

2 3

3 1

4 1

2Q3

2D3

D9X

9

7

5

1

0

8

6

2

1

0

8

6

2

1

D N G

5

6

4

1

2Q2

2Q1

GND

2D2

2D1

GND

4

3

5

3

D8X

D7X

GND

7

5

3

1

2

5

3

1

2

6

4

2

6

4

2

D N G

1

2

3

1

D N

1Q7

1Q8

G

1D8

1D7

GND

8

7

6

3

D6X

D5X

GND

3

1

7

9

2

3

1

7

9

3

2

8

0

3

2

3

2

8

0

3

2

3

D D V R D

0

8

9

1

CC

1Q6

V

1Q5

CC

V

1D6

1D5

1

0

9

4

3

D4X

D3X

DRVDD

9

5

3

9

7

5

3

4

0

8

6

3

4

3

4

6

0

8

3

4

3

D

Y R D

D N G

7

5

6

3

4

D

Q

N

1

G

1D4

1D3

GND

4

3

2

4

D1X

GND

D2X

N G

D

N

G

D N G

9

Ω

3

k 1

R

8

Ω

3

k 1

R

P M A V

D N G

1

3

4

2

T U

6 4

1Q1

1D1

O

1OE

1

N

I

1CLK

8

7

4

C A D

/ T A L K L C

1Q2

1D2

5 4

D0X

B S L

G

F

4

μ

2

0 1

C

P M A V

F

μ

5

1

4

. 0

C

F

μ

4

1

4

. 0

C

D N G

S T N E N

O

R

P

E

I

M

F

I

O

L

C

P

L

M

L

A

E

S

C

U

A L

O T

P

1 4

N

R

W

R

O D

O 0

R

4

E

R

W

E

O

S

P

U

U3

, 2 4 R ,

)

8

.

T

1

H

4

R

.

G

,

I

R

8

3

R

1

R

(

R

C

,

O

E

2

D

0

R

1

4

N

E

R

A

H

,

E

T

5

N

V

P

1

O

W

E

C

O

M

C

,

E

6

H

X

S

E

R

C

Ω

0

k

4

0 1

R

D N G

Ω

1

k

4

0 1

R

P M

A V

4

Ω

1

5 2

R

M

S

C

O

P

V

0

9

1

AD8351

1

2

N

1

D

P

W

G

P

R

8 2 C

N

I P M

A

B

N

I

P

M

A

F

μ

7

7 2 C

6 1 R

I H P O

8

3 I H N

I

F

μ

1

. 0

P M A

1

.

0

C

0

7 1

Ω

0

R

D N G

M

O

M

L P

O

C

7

6

Ω

k

4

2

3

. 1

R

5

4

2

O

G

L

P

N

I

R

3

Ω

3

5 2

R

F

μ

0

5

1

3

. 0

C

5

Ω

3

5 2

R

D

D N

N G

G

D N

9 1 R

G

Ω

0 5

03583-051

Figure 50. LFCSP Evaluation Board Schematic—Digital Path

Rev. D | Page 24 of 32

AD9245

C40

0.001μF

C46

C37

0.1μF

10μF

VDL

DRVDD

C20

10μF

GND

C49

0.001μF

C48

0.001μF

C47

0.1μF

C1

0.1μF

C39

0.001μF

C38

0.001μF

C36

0.1μF

C34

0.1μF

C31

0.1μF

C30

0.001μF

C2

10μF

GND

C41

0.1μF

VAMP

LATCH BYPASSING

GND

R22

0Ω

DR

Rx

DNP

0Ω

R37

CLKLAT/DAC

SCHEMATIC SHOWS TWO GATE DELAY SETUP.

FOR ONE DELAY, REMOVE R22 AND R37 AND

ATTACH Rx (Rx = 0Ω).

0Ω

R23

VDL

367

1Y

B

A

1

245

GND

8

11

14

GND

PWR

2Y

A 2

R32

1kΩ

4Y

3Y

B

A

2

3

9

B 3

10

GND

U5

B

A

4

12

13

R20

1kΩ

GND

ENCX

74VCX86

R21

1kΩ

GND

R24

1kΩ

GND

E51

AVDD

DRVDD AVDD

VDL

C14

0.001μF

C33

0.1μF

C32

0.001μF

C25

10μF

C4

ANALOG BYPASSING DIGITAL BYPASSING LATCH BYPASSING

GND

C3

10μF

GND

10μF

C10

10μF

DUT BYPASSING

CLOCK TIMING ADJUSTMENTS

FOR A DIRECT ENCODE USE R27

FOR A BUFFERED ENCODE USE R28

ENC

0Ω

ENCX

ENC

E50

R27

0Ω

CLK

R28

VDL

E52 E53

VDL

R31

C43

1kΩ

0.1μF

ENCODE

J2

VDL

E31 E35

R30

R29

E43 E44

1kΩ

GND

50Ω

GND

VDL

03583-052

Figure 51. LFCSP Evaluation Board Schematic—Clock Input

Rev. D | Page 25 of 32

AD9245

Figure 52. LFCSP Evaluation Board Layout, Primary Side

03583-055

03583-053

Figure 54. LFCSP Evaluation Board Layout, Ground Plane

Figure 53. LFCSP Evaluation Board Layout, Secondary Side

03583-054

Rev. D | Page 26 of 32

Figure 55. LFCSP Evaluation Board Layout, Power Plane

03583-056

AD9245

Figure 56. LFCSP Evaluation Board Layout, Primary Silkscreen

03583-057

Figure 57. LFCSP Evaluation Board Layout, Secondary Silkscreen

03583-058

Rev. D | Page 27 of 32

AD9245

Table 12. LFCSP Evaluation Board Bill of Materials

Recommended

Item Qty. Omit1Reference Designator Device Package Value

18

1

C1, C5, C7, C8, C9, C11, C12,

Chip Capacitors 0603 0.1 μF

Vendor/Part No.

C13, C15, C16, C31, C33, C34, C36, C37, C41, C43, C47

8

C6, C17, C18, C27, C28, C35, C45, C44

8

2

C2, C3, C4, C10, C20,

Tantalum Capacitors TAJC 10 μF

C22, C25, C29

2 C24, C46

3 8

C14, C30, C32, C38,

Chip Capacitors 0603 0.001 μF

C39, C40, C48, C49

4 1 C19 Chip Capacitors 0603 20 pF

1 C26 5

Chip Capacitors 0603 10 pF

2 C21, C23 9

6

E31, E35, E43, E44,

Headers EHOLE Jumper Blocks

E50, E51, E52, E53

2 E1, E45

7 2 J1, J2 SMA Connectors/50 Ω SMA 8 1 L1 Inductor 0603 10 nH

Coilcraft/ 0603CS-10NXGBU

9 1 P2 Terminal Block TB6

Wieland/25.602.2653.0, z5-530-0625-0

10 1 P12 Header Dual 20-Pin RT Angle HEADER40 Digi-Key S2131-20-ND

5 R3, R12, R23, R28, Rx 11

Chip Resistors 0603 0 Ω

6 R16, R17, R22, R27, R42, R37 12 2 R4, R15 Chip Resistors 0603 33 Ω

13 14

R5, R6, R7, R8, R13, R20, R21,

Chip Resistors 0603 1 kΩ

R24, R25, R26, R30, R31, R32, R36

14 2 R10, R11 Chip Resistors 0603 36 Ω

1 R29 15

Chip Resistors 0603 50 Ω

1 R19 16 2 RP1, RP2 Resistor Packs R_742 220 Ω

Digi-Key

CTS/742C163221JTR 17 1 T1 ADT1-1WT AWT1-1T Mini-Circuits

18 1 U1 74LVTH162374 CMOS Register TSSOP-48

19 1 U4 AD9245BCP ADC (DUT) LFCSP-32 Analog Devices, Inc. X

20 1 U5 74VCX86M SOIC-14 Fairchild

21 1 PCB AD92XXBCP/PCB PCB Analog Devices, Inc. X

22 1 U3 AD8351 Op Amp MSOP-8 Analog Devices, Inc. X

23 1 T2 M/A-COM Transformer ETC1-1-13 1-1 TX M/A-COM/ETC1-1-13

24 5 R1, R2, R9, R38, R39 Chip Resistors 0603 SELECT

25 3 R14, R18, R35 Chip Resistors 0603 25 Ω

26 2 R40, R41 Chip Resistors 0603 10 kΩ

27 1 R34 Chip Resistor 1.2 kΩ

28 1 R33 Chip Resistor 25 Ω

81 35

To ta l

1

These items are included in the PCB design, but are omitted at assembly.

Supplied by ADI

Rev. D | Page 28 of 32

AD9245

OUTLINE DIMENSIONS

0.08

0.60 MAX

25

24

EXPOSED

PAD

(BOTTOM VIEW)

17

16

32

1

8

9

3.50 REF

PIN 1 INDICATOR

3.25

3.10 SQ

2.95

0.25 MIN

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING PLANE

5.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

4.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

Figure 58. 32-Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description

AD9245BCP-80 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD9245BCPRL7–80 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD9245BCPZ-80 AD9245BCPZRL7-80 AD9245BCPZ-65 AD9245BCPZRL7-65 AD9245BCPZ-40 AD9245BCPZRL7-40 AD9245BCPZ-20 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD9245BCPZRL7-20 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2

2

–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2

2

–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2

2

–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2

2

–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2

2

AD9245BCP-80EB Evaluation Board AD9245BCP-65EB Evaluation Board AD9245BCP-40EB Evaluation Board AD9245BCP-20EB Evaluation Board

1

It is recommended that the exposed paddle be soldered to the ground plane for the LFCSP package. There is an increased reliability of the solder joints, and the

maximum thermal capability of the package is achieved with the exposed paddle soldered to the customer board.

2

Z = Pb-free part.

1

Package Option

Rev. D | Page 29 of 32

AD9245

NOTES

Rev. D | Page 30 of 32

AD9245

NOTES

Rev. D | Page 31 of 32

AD9245

NOTES

Rev. D | Page 32 of 32

Analog Devices AD9245 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

TERMINOLOGY

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

EQUIVALENT CIRCUITS

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

ANALOG INPUT AND REFERENCE OVERVIEW

Differential Input Configurations

Single-Ended Input Configuration

CLOCK INPUT CONSIDERATIONS

JITTER CONSIDERATIONS

POWER DISSIPATION AND STANDBY MODE

DIGITAL OUTPUTS

TIMING

VOLTAGE REFERENCE

INTERNAL REFERENCE CONNECTION

OPERATIONAL MODE SELECTION

EXTERNAL REFERENCE OPERATION

EVALUATION BOARD

OUTLINE DIMENSIONS

ORDERING GUIDE