Analog Devices AD9238 Service Manual

12-Bit, 20 MSPS/40 MSPS/65 MSPS

FEATURES

Integrated dual 12-bit ADC Single 3 V supply operation (2.7 V to 3.6 V) SNR = 70 dB (to Nyquist, AD9238-65) SFDR = 80.5 dBc (to Nyquist, AD9238-65) Low power: 300 mW/channel at 65 MSPS Differential input with 500 MHz, 3 dB bandwidth Exceptional crosstalk immunity > 85 dB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary or twos complement data format Clock duty cycle stabilizer Output datamux option

APPLICATIONS

Ultrasound equipment Direct conversion or IF sampling receivers

WB-CDMA, CDMA2000, WiMAX Battery-powered instruments Hand-held scopemeters Low cost, digital oscilloscopes

GENERAL DESCRIPTION

The AD9238 is a dual, 3 V, 12-bit, 20 MSPS/40 MSPS/65 MSPS analog-to-digital converter (ADC). It features dual high performance sample-and-hold amplifiers (SHAs) and an integrated voltage reference. The AD9238 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy and to guarantee no missing codes over the full operating temperature range at up to 65 MSPS data rates. The wide bandwidth, differential SHA allows for a variety of user-selectable input ranges and offsets, including single-ended applications. It is suitable for various applications, including multiplexed systems that switch fullscale voltage levels in successive channels and for sampling inputs at frequencies well beyond the Nyquist rate.

Dual single-ended clock inputs are used to control all internal conversion cycles. A duty cycle stabilizer is available and can compensate for wide variations in the clock duty cycle, allowing the converter to maintain excellent performance. The digital output data is presented in either straight binary or twos complement format. Out-of-range signals indicate an overflow condition, which can be used with the most significant bit to determine low or high overflow.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Dual A/D Converter

AD9238

FUNCTIONAL BLOCK DIAGRAM

AVDD

AGND

VIN+_A VIN–_A

REFT_A

REFB_A

VREF

SENSE

AGND

REFT_B

REFB_B

VIN+_B VIN–_B

SHA

0.5V

SHA

AD9238

ADC

DRVDD

Figure 1.

12

OUTPUT

BUFFERS

CLOCK

DUTY CYCLE

STABILIZER

CONTROL

12

OUTPUT

BUFFERS

DRGND

Fabricated on an advanced CMOS process, the AD9238 is available in a Pb-free, space saving, 64-lead LQFP or LFCSP and is specified over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. Pin-compatible with the AD9248, 14-bit 20MSPS/

40 MSPS/65 MSPS ADC.

2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS

allow flexibility between power, cost, and performance to suit an application.

3. Low power consumption:

• AD9238-65: 65 MSPS = 600 mW

• AD9238-40: 40 MSPS = 330 mW

• AD9238-20: 20 MSPS = 180 mW

4. Typical channel isolation of 85 dB @ f

5. The clock duty cycle stabilizer (AD9238-20/AD9238-40/

AD9238-65) maintains performance over a wide range of clock duty cycles.

6. Multiplexed data output option enables single-port operation

from either Data Port A or Data Port B.

www.analog.com

MUX/

MODE

MUX/

= 10 MHz.

IN

12

OTR_A D11_A TO D0_A

OEB_A

MUX_SELECT CLK_A CLK_B DCS

SHARED_REF PWDN_A PWDN_B DFS

OTR_B D11_B TO D0_B

OEB_B

02640-001

AD9238

REVISION HISTORY

4/05—Rev. A to Rev. B

Changes to Format and Layout........................................ Universal

Added LFCSP..................................................................... Universal

Changes to Features and Applications...........................................1

Changes to General Description and Product Highlights ..........1

Changes to Figure 1..........................................................................1

Changes to Table 1............................................................................3

Changes to Table 2............................................................................5

Added Digital Specifications...........................................................6

Moved Switching Specifications to.................................................6

LFCSP PCB Schematics............................................................. 36

LFCSP PCB Layers..................................................................... 39

Thermal Considerations............................................................ 44

Outline Dimensions....................................................................... 45

Ordering Guide .......................................................................... 46

Changes to Pin Function Descriptions..........................................8

Changes to Terminology Section .................................................10

Changes to Figure 29......................................................................15

Changes to Clock Input and Considerations Section................17

Changes to Figure 33......................................................................18

Changes to Data Format Section..................................................19

Added AD9238 LQFP Evaluation Board Section ......................21

Added Dual ADC LFCSP PCB Section.......................................34

Added Thermal Considerations Section.....................................44

Updated Outline Dimensions.......................................................45

Changes to Ordering Guide.......................................................... 46

Rev. B | Page 2 of 48

AD9238

9/03—Rev. 0 to Rev. A

Changes to DC Specifications ........................................................2

Changes to Switching Specifications .............................................3

Changes to AC Specifications......................................................... 4

Changes to Figure 1..........................................................................4

Changes to Ordering Guide............................................................ 5

Changes to TPCs 2, 3, and 6 ........................................................... 8

Changes to Clock Input and Considerations Section................ 13

Added Text to Data Format Section ............................................15

Changes to Figure 9........................................................................16

Added Evaluation Board Diagrams Section............................... 17

Update Outline Dimensions ......................................................... 24

2/03—Revision 0: Initial Version

Rev. B | Page 3 of 48

AD9238

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 1.

Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full VI 12 12 12 Bits ACCURACY

No Missing Codes Guaranteed Full VI 12 12 12 Bits Offset Error Full VI ±0.30 ±1.2 ±0.50 ±1.1 ±0.50 ±1.1 % FSR Gain Error1 Full IV ±0.30 ±2.2 ±0.50 ±2.4 ±0.50 ±2.5 % FSR Differential Nonlinearity (DNL)2 Full V ±0.35 ±0.35 ±0.35 LSB 25°C I ±0.35 ±0.9 ±0.35 ±0.8 ±0.35 ±1.0 LSB Integral Nonlinearity (INL)2 Full V ±0.45 ±0.60 ±0.70 LSB

25°C I ±0.40 ±1.4 ±0.50 ±1.4 ±0.55 ±1.75 LSB TEMPERATURE DRIFT

Offset Error Full V ±4 ±4 ±6 µV/°C Gain Error Full V ±12 ±12 ±12 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) Full VI ±5 ±35 ±5 ±35 ±5 ±35 mV Load Regulation @ 1.0 mA Full V 0.8 0.8 0.8 mV Output Voltage Error (0.5 V Mode) Full V ±2.5 ±2.5 ±2.5 mV Load Regulation @ 0.5 mA Full V 0.1 0.1 0.1 mV

INPUT REFERRED NOISE

Input Span = 1 V 25°C V 0.54 0.54 0.54 LSB Input Span = 2.0 V 25°C V 0.27 0.27 0.27 LSB

ANALOG INPUT

Input Span = 1.0 V Full IV 1 1 1 V p-p Input Span = 2.0 V Full IV 2 2 2 V p-p Input Capacitance3 Full V 7 7 7 pF

REFERENCE INPUT RESISTANCE Full V 7 7 7 kΩ POWER SUPPLIES

Supply Voltages

Supply Current

PSRR Full V ±0.01 ±0.01 ±0.01 % FSR

POWER CONSUMPTION

DC Input4 Full V 180 330 600 mW Sine Wave Input2 Full VI 190 212 360 397 640 698 mW Standby Power5 Full V 2.0 2.0 2.0 mW

MATCHING CHARACTERISTICS

Offset Error 25°C V ±0.1 ±0.1 ±0.1 % FSR Gain Error 25°C V ±0.05 ±0.05 ±0.05 % FSR

1

Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).

2

Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.

3

Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure for the equivalent analog input structure. 28

4

Measured with dc input at maximum clock rate.

5

Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).

, DCS enabled, unless otherwise noted.

MAX

Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65

rms

AVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V DRVDD Full IV 2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 V

IAVDD2 Full V 60 110 200 mA IDRVDD2 Full V 4 10 14 mA

Rev. B | Page 4 of 48

AD9238

AC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 2.

Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR)

f

INPUT

f

INPUT

25°C IV 69.7 70.4 dB f

INPUT

25°C IV 69.7 70.3 dB f

INPUT

25°C IV 68.7 70.0 dB f

INPUT

SIGNAL-TO-NOISE AND DISTORTION

RATIO (SINAD) f

INPUT

f

INPUT

25°C IV 69.3 70.2 dB f

INPUT

25°C IV 69.4 70.1 dB f

INPUT

25°C IV 68.1 69.1 dB f

INPUT

EFFECTIVE NUMBER OF BITS (ENOB)

f

INPUT

f

INPUT

25°C IV 11.3 11.5 Bits f

INPUT

25°C IV 11.3 11.4 Bits f

INPUT

25°C IV 11.1 11.3 Bits f

INPUT

WORST HARMONIC (SECOND or THIRD)

f

INPUT

f

INPUT

f

INPUT

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f

INPUT

f

INPUT

25°C I 76.1 86.0 dBc f

INPUT

25°C I 76.7 86.0 dBc f

INPUT

25°C I 72.5 80.5 dBc f

INPUT

CROSSTALK Full V −85.0 −85.0 −85.0 dB

, DCS enabled, unless otherwise noted.

MAX

Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65

= 2.4 MHz 25°C V 70.4 70.4 70.3 dB = 9.7 MHz Full V 70.2 dB

= 19.6 MHz Full V 70.1 dB

= 32.5 MHz Full V 69.3 dB

= 100 MHz 25°C V 68.7 68.3 67.6 dB

= 2.4 MHz 25°C V 70.2 70.2 70.1 dB = 9.7 MHz Full V 70.1 dB

= 19.6 MHz Full V 69.9 dB

= 32.5 MHz Full V 68.9 dB

= 100 MHz 25°C V 67.9 67.9 66.6 dB

= 2.4 MHz 25°C V 11.5 11.5 11.4 Bits = 9.7 MHz Full V 11.4 Bits

= 19.6 MHz Full V 11.4 Bits

= 32.5 MHz Full V 11.2 Bits

= 100 MHz 25°C V 11.1 11.1 10.9 Bits

= 9.7 MHz Full V −84.0 dBc = 19.6 MHz Full V −85.0 dBc = 35 MHz Full V −80.0 dBc

= 2.4 MHz 25°C V 86.0 86.0 86.0 dBc = 9.7 MHz Full V 84.0 dBc

= 19.6 MHz Full V 85.0 dBc

= 32.5 MHz Full V 80.0 dBc

= 100 MHz 25°C V 75.0 dBc

Rev. B | Page 5 of 48

AD9238

DIGITAL SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 3.

Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit LOGIC INPUTS

High Level Input Voltage Full IV 2.0 2.0 2.0 V Low Level Input Voltage Full IV 0.8 0.8 0.8 V High Level Input Current Full IV −10 +10 −10 +10 −10 +10 µA Low Level Input Current Full IV −10 +10 −10 +10 −10 +10 µA Input Capacitance Full IV 2 2 2 pF

LOGIC OUTPUTS1

High Level Output Voltage Full IV

Low Level Output Voltage Full IV 0.05 0.05 0.05 V

1

Output voltage levels measured with capacitive load only on each output.

SWITCHING SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 4.

Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit SWITCHING PERFORMANCE

Maximum Conversion Rate Full VI 20 40 65 MSPS Minimum Conversion Rate Full V 1 1 1 MSPS CLK Period Full V 50.0 25.0 15.4 ns CLK Pulse-Width High1 Full V 15.0 8.8 6.2 ns CLK Pulse-Width Low1 Full V 15.0 8.8 6.2 ns

DATA OUTPUT PARAMETER

Output Delay2 (tPD) Full VI 2 3.5 6 2 3.5 6 2 3.5 6 ns Pipeline Delay (Latency) Full V 7 7 7 Cycles Aperture Delay (tA) Full V 1.0 1.0 1.0 ns Aperture Uncertainty (tJ) Full V 0.5 0.5 0.5 pS rms Wake-Up Time3 Full V 2.5 2.5 2.5 ms

OUT-OF-RANGE RECOVERY TIME Full V 2 2 2 Cycles

1

The AD9238-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 23).

2

Output delay is measured from clock 50% transition to data 50% transition, with a 5 pF load on each output.

3

Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.

, DCS enabled, unless otherwise noted.

MAX

, DCS enabled, unless otherwise noted.

MAX

N

ANALOG

INPUT

N–1

Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65

DRVDD −

0.05

DRVDD −

0.05

DRVDD −

0.05

V

Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65

N+1

N+2

N+3

N+4

N+5

N+6

N+7

N+8

CLOCK

DATA

OUT

N–9 N–8

N–7

N–6

N–5

N–4

N–3

N–2

N–1

N

t

PD

MIN 2.0ns,

=

MAX 6.0ns

02640-002

Figure 2. Timing Diagram

Rev. B | Page 6 of 48

AD9238

ABSOLUTE MAXIMUM RATINGS1

Table 5.

Parameter Rating Pin Name With Respect To Min Max Unit

ELECTRICAL

AVDD AGND −0.3 +3.9 V DRVDD DRGND −0.3 +3.9 V AGND DRGND −0.3 +0.3 V AVDD DRVDD −3.9 +3.9 V Digital Outputs CLK, DCS, MUX_SELECT, SHARED_REF DRGND −0.3 DRVDD + 0.3 V OEB, DFS AGND −0.3 AVDD + 0.3 V VINA, VINB AGND −0.3 AVDD + 0.3 V VREF AGND −0.3 AVDD + 0.3 V SENSE AGND −0.3 AVDD + 0.3 V REFB, REFT AGND −0.3 AVDD + 0.3 V PDWN AGND −0.3 AVDD + 0.3 V

ENVIRONMENTAL2

Operating Temperature −45 +85 °C Junction Temperature 150 °C Lead Temperature (10 sec) 300 °C Storage Temperature −65 +150 °C

1

Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is

not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.

2

Typical thermal impedances: 64-lead LQFP, θJA = 54°C/W; 64-lead LFCSP, θJA = 26.4°C/W with heat slug soldered to ground plane. These measurements were taken on a

4-layer board in still air, in accordance with EIA/JESD51-7.

EXPLANATION OF TEST LEVELS

I 100% production tested. II 100% production tested at 25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI

100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. B | Page 7 of 48

AD9238

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK_A

AGND VIN+_A VIN–_A

AGND

AVDD

REFT_A

REFB_A

VREF

SENSE

REFB_B

REFT_B

AVDD

AGND VIN–_B

VIN+_B

AGND

AVDD

SHARED_REF

64 63 62 61 60 55 54 53 52 51 50 4959 58 57 56

1

PIN 1

2

IDENTIFIER

3 4 5 6 7 8

9 10 11 12 13 14 15 16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

MUX_SELECT

OTR_A

OEB_A

PDWN_A

AD9238

64-LEAD LQFP

TOP VIEW

(Not to Scale)

D9_A

D8_A

D11_A (MSB)

D10_A

DRVDD

DRGND

D7_A

D6_A

D5_A

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

D4_A D3_A

D2_A D1_A D0_A (LSB) DNC DNC DRVDD DRGND OTR_B D11_B (MSB) D10_B D9_B

D8_B D7_B D6_B

DFS

DCS

AVDD

CLK_B

PDWN_B

OEB_B

DNC = DO NOT CONNECT

Figure 3. 64-Lead LQFP and LFCSP Pin Configuration

DNC

D1_B

D2_B

D0_B (LSB)

DRVDD

DRGND

D3_B

D4_B

D5_B

02640-003

Rev. B | Page 8 of 48

AD9238

Table 6. Pin Function Descriptions (64-Lead LQFP and 64-Lead LFCSP)

Pin No. Mnemonic Description

1, 4, 13, 16 AGND Analog Ground. 2 VIN+_A Analog Input Pin (+) for Channel A. 3 VIN–_A Analog Input Pin (−) for Channel A. 5, 12, 17, 64 AVDD Analog Power Supply. 6 REFT_A Differential Reference (+) for Channel A. 7 REFB_A Differential Reference (−) for Channel A. 8 VREF Voltage Reference Input/Output. 9 SENSE Reference Mode Selection. 10 REFB_B Differential Reference (−) for Channel B. 11 REFT_B Differential Reference (+) for Channel B. 14 VIN−_B Analog Input Pin (−) for Channel B. 15 VIN+_B Analog Input Pin (+) for Channel B. 18 CLK_B Clock Input Pin for Channel B. 19 DCS Enable Duty Cycle Stabilizer (DCS) Mode (Tie High to Enable). 20 DFS Data Output Format Select Bit (Low for Offset Binary, High for Twos Complement). 21 PDWN_B Power-Down Function Selection for Channel B:

Logic 0 enables Channel B.

Logic 1 powers down Channel B. (Outputs static, not High-Z.)

22 OEB_B Output Enable Bit for Channel B:

Logic 0 enables Data Bus B.

Logic 1 sets outputs to High-Z. 23, 24, 42, 43 DNC Do Not Connect Pins. Should be left floating. 25 to 27,

30 to 38 28, 40, 53 DRGND Digital Output Ground. 29, 41, 52 DRVDD

39 OTR_B Out-of-Range Indicator for Channel B. 44 to 51,

54 to 57 58 OTR_A Out-of-Range Indicator for Channel A. 59 OEB_A Output Enable Bit for Channel A:

60 PDWN_A Power-Down Function Selection for Channel A:

61 MUX_SELECT Data Multiplexed Mode.

62 SHARED_REF Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared Reference Mode). 63 CLK_A Clock Input Pin for Channel A.

D0_B (LSB) to D11_B (MSB)

D0_A (LSB) to D11_A (MSB)

Channel B Data Output Bits.

Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor. Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF.

Channel A Data Output Bits.

Logic 0 enables Data Bus A.

Logic 1 sets outputs to High-Z.

Logic 0 enables Channel A.

Logic 1 powers down Channel A. (Outputs static, not High-Z.)

(See Data Format section for how to enable; high setting disables output data multiplexed mode).

Rev. B | Page 9 of 48

AD9238

TERMINOLOGY

Aperture Delay

SHA performance measured from the rising edge of the clock input to when the input signal is held for conversion.

Aperture Jitter

The variation in aperture delay for successive samples, which is manifested as noise on the input to the ADC.

Integral Nonlinearity (INL)

Deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.

frequency, including harmonics but excluding dc. The value for SINAD is expressed in dB.

Effective Number of Bits (ENOB)

Using the following formula

ENOB = (SINAD − 1.76)/6.02

ENOB for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.

Signal-to-Noise Ratio (SNR)

The ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in dB.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4,096 codes must be present over all operating ranges.

Offset Error

The major carry transition should occur for an analog value ½ LSB below VIN+ = VIN−. Offset error is defined as the deviation of the actual transition from that point.

Gain Error

The first code transition should occur at an analog value ½ LSB above negative full scale. The last transition should occur at an analog value 1½ LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.

Temp er at u re D ri ft

The temperature drift for zero error and gain error specifies the maximum change from the initial (25°C) value to the value at

or T

T

MIN

MAX

.

Power Supply Rejection The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit.

Total Harmonic Distortion (THD) The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal, expressed as a percentage or in decibels relative to the peak carrier signal (dBc).

Signal-to-Noise and Distortion (SINAD) Ratio

The ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist

Spurious-Free Dynamic Range (SFDR) The difference in dB between the rms amplitude of the input signal and the peak spurious signal, which may or may not be a harmonic.

Nyquist Sampling When the frequency components of the analog input are below the Nyquist frequency (f

/2), this is often referred to as

CLOCK

Nyquist sampling.

IF Sampling Due to the effects of aliasing, an ADC is not limited to Nyquist sampling. Higher sampled frequencies are aliased down into the first Nyquist zone (DC − f

/2) on the output of the ADC.

CLOCK

The bandwidth of the sampled signal should not overlap Nyquist zones and alias onto itself. Nyquist sampling performance is limited by the bandwidth of the input SHA and clock jitter (jitter adds more noise at higher input frequencies).

Two -Tone SFDR

The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.

Crosstalk

Coupling onto one channel being driven by a (−0.5 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Measurement includes all spurs resulting from both direct coupling and mixing components.

Rev. B | Page 10 of 48

AD9238

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD, DRVDD = 3.0 V, T = 25°C, AIN differential drive, full scale = 2 V, unless otherwise noted.

0

–20

–40

MAGNITUDE (dBFS)

–60

–80

–100

–120

CROSSTALK

10 15 20 25 30

50

FREQUENCY (MHz)

SECOND HARMONIC

Figure 4. Single-Tone FFT of Channel A Digitizing f

While Channel B Is Digitizing f

0

–20

–40

dB

–60

–80

–100

–120

SECOND HARMONIC

10

CROSSTALK

15 20 25 3050

FREQUENCY (MHz)

Figure 5. Single-Tone FFT of Channel A Digitizing f

While Channel B Is Digitizing f

0

–20

–40

dB

CROSSTALK

–60

–80

–100

–120

SECOND HARMONIC

15 20 25 3050

10

FREQUENCY (MHz)

Figure 6. Single-Tone FFT of Channel A Digitizing f

While Channel B is Digitizing f

IN

THIRD HARMONIC

= 10 MHz

IN

= 76 MHz

IN

= 126 MHz

= 12.5 MHz

IN

= 70 MHz

IN

= 120 MHz

IN

02640-004

02640-005

02640-006

100

95

90

85

80

75

70

SFDR/SNR (dBc)

65

60 55 50

40

45 50 55 60 65

ADC SAMPLE RATE (MSPS)

SNR

SFDR

Figure 7. AD9238-65 Single-Tone SNR/SFDR vs. FS with f

100

95

90

85

80

75

70

SFDR/SNR (dBc)

65

60 55 50

ADC SAMPLE RATE (MSPS)

SFDR

SNR

35302520

Figure 8. AD9238-40 Single-Tone SNR/SFDR vs. FS with f

100

95

90

85

80

75

70

SFDR/SNR (dBc)

65

60 55 50

0

5101520

ADC SAMPLE RATE (MSPS)

SFDR

SNR

Figure 9. AD9238-20 Single-Tone SNR/SFDR vs. FS with f

= 32.5 MHz

IN

40

= 20 MHz

IN

= 10 MHz

IN

02640-007

02640-008

02640-009

Rev. B | Page 11 of 48

AD9238

100

95

90

80

70

SFDR/SNR (dBc)

60

50

40

–30 –25 –20 –15 –10 –5

–35

INPUT AMPLITUDE (dBFS)

SFDR

SNR

Figure 10. AD9238-65 Single-Tone SNR/SFDR vs. AIN with f

100

90

80

70

SFDR/SNR (dBc)

60

SNR

SFDR

SNR

0

= 32.5 MHz

IN

02640-010

90

85

80

SFDR/SNR (dBc)

75

70

65

20 40 60 80 100 120

0

Figure 13. AD9238-65 Single-Tone SNR/SFDR vs. f

SNR

SFDR

SNR

INPUT FREQUENCY (MHz)

02640-013

140

IN

95

90

85

80

SFDR/SNR (dBc)

75

SNR

SFDR

50

40

–30 –25 –20 –15 –10 –5

–35

INPUT AMPLITUDE (dBFS)

Figure 11. AD9238-40 Single-Tone SNR/SFDR vs. AIN with f

100

90

SNR

SFDR

80

70

SNR

SFDR/SNR (dBc)

60

50

40

–30 –25 –20 –15 –10 –5

–35

INPUT AMPLITUDE (dBFS)

SNR

Figure 12. AD9238-20 Single-Tone SNR/SFDR vs. AIN with f

0

= 20 MHz

IN

0

= 10 MHz

IN

02640-011

02640-012

SNR

70

65

20 40 60 80 100 120

0

Figure 14. AD9238-40 Single-Tone SNR/SFDR vs. f

SNR

INPUT FREQUENCY (MHz)

02640-014

140

IN

95

90

SFDR

85

80

SFDR/SNR (dBc)

75

70

65

20 40 60 80 100 120

0

Figure 15. AD9238-20 Single-Tone SNR/SFDR vs. f

SNR

INPUT FREQUENCY (MHz)

02640-015

140

IN

Rev. B | Page 12 of 48

AD9238

0

–20

–40

100

SNR

95

90

85

SFDR

–60

–80

MAGNITUDE (dBFS)

–100

–120

10

Figure 16. Dual-Tone FFT with f

0

–20

–40

–60

–80

MAGNITUDE (dBFS)

–100

–120

10 15 20 25 3050

Figure 17. Dual-Tone FFT with f

0

15 20 25 3050

FREQUENCY (MHz)

1 = 45 MHz and fIN2 = 46 MHz

IN

FREQUENCY (MHz)

1 = 70 MHz and fIN2 = 71 MHz

IN

02640-016

02640-017

80

75

SFDR/SNR (dBFS)

70

65

60

–24

SNR

–21 –18 –15 –12 –9 –6

INPUT AMPLITUDE (dBFS)

Figure 19. Dual-Tone SNR/SFDR vs. AIN with f

100

SNR

95

90

85

80

75

SFDR/SNR (dBFS)

70

65

60

–24

SFDR

SNR

–21 –18 –15 –12 –9 –6

INPUT AMPLITUDE (dBFS)

Figure 20. Dual-Tone SNR/SFDR vs. AIN with f

100

1 = 45 MHz and fIN2 = 46 MHz

IN

1 = 70 MHz and fIN2 = 71 MHz

IN

02640-019

02640-020

–20

–40

–60

–80

MAGNITUDE (dBFS)

–100

–120

10 15 20 25 3050

Figure 18. Dual-Tone FFT with f

FREQUENCY (MHz)

1 = 200 MHz and fIN2 = 201 MHz

IN

02640-018

Rev. B | Page 13 of 48

95

90

85

80

75

SFDR/SNR (dBFS)

70

65

60

–24

SNR

SFDR

SNR

–21 –18 –15 –12 –9 –6

INPUT AMPLITUDE (dBFS)

02640-021

Figure 21. Dual-Tone SNR/SFDR vs.

AIN with f

1 = 200 MHz and fIN2 = 201 MHz

IN

AD9238

74

12.0

600

–65

72

SINAD (dBc)

SINAD –20

70

SINAD –40

68

0

20 40 60

CLOCK FREQUENCY

Figure 22. SINAD vs. FS with Nyquist Input

95

90

85

80

75

70

65

SINAD/SFDR (dBc)

60

55

50

30

DCS OFF (SFDR)

35

40 45 50 55 60 65

DCS ON (SFDR)

DUTY CYCLE (%)

Figure 23. SINAD/SFDR vs. Clock Duty Cycle

84

82

80

78

76

74

72

SINAD/SFDR (dB)

70

68

66

–50

SFDR

SINAD

0 50 100

TEMPERATURE (°C)

Figure 24. SINAD/SFDR vs. Temperature with f

DCS ON (SINAD)

DCS OFF (SINAD)

IN

SINAD –65

= 32.5 MHz

11.5

11.0

02640-022

02640-023

02640-024

500

400

300

AVDD POWER (mW)

200

100

0102030405060

–40

–20

SAMPLE RATE (MSPS)

02640-025

Figure 25. Analog Power Consumption vs. FS

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2 –0.4

–0.6 –0.8 –1.0

150010005000 2000 2500 3000 3500 4000

CODE

02640-026

Figure 26. AD9238-65 Typical INL

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2 –0.4

–0.6 –0.8 –1.0

150010005000 2000 2500 3000 3500 4000

CODE

02640-027

Figure 27. AD9238-65 Typical DNL

Rev. B | Page 14 of 48

AD9238

V

EQUIVALENT CIRCUITS

AVDD

Figure 30. Equivalent Digital Input Circuit

IN+_A, VIN–_A, IN+_B, VIN–_B

AVDD

Figure 28. Equivalent Analog Input Circuit

02640-062

CLK_A, CLK_B

DCS, DFS,

MUX_SELECT,

SHARED_REF

02640-064

DRVDD

02640-063

Figure 29. Equivalent Digital Output Circuit

Rev. B | Page 15 of 48

AD9238

V

THEORY OF OPERATION

The AD9238 consists of two high performance ADCs that are based on the AD9235 converter core. The dual ADC paths are independent, except for a shared internal band gap reference source, VREF. Each of the ADC paths consists of a proprietary front end SHA followed by a pipelined switched-capacitor ADC. The pipelined ADC is divided into three sections, consisting of a 4-bit first stage, followed by eight 1.5-bit stages, and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined through the digital correction logic block into a final 12-bit result. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the respective clock.

Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC and a residual multiplier to drive the next stage of the pipeline. The residual multiplier uses the flash ADC output to control a switched-capacitor digital-to-analog converter (DAC) of the same resolution. The DAC output is subtracted from the stage’s input signal and the residual is amplified (multiplied) to drive the next pipeline stage. The residual multiplier stage is also called a multiplying DAC (MDAC). One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.

The input stage contains a differential SHA that can be configured as ac- or dc-coupled in differential or single-ended modes. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing.

In IF undersampling applications, any shunt capacitors should be removed. In combination with the driving source impedance, they limit the input bandwidth. For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC.

H

T

H

02640-065

VIN+

IN–

T

C

PAR

T

C

PAR

Figure 31. Switched-Capacitor Input

5pF

An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as:

REFT = ½(AV D D + VREF)

REFB = ½ (AV D D + VREF)

Span = 2 × (REFT − REFB) = 2 × VREF

ANALOG INPUT

The analog input to the AD9238 is a differential, switchedcapacitor, SHA that has been designed for optimum performance while processing a differential input signal. The SHA input accepts inputs over a wide common-mode range. An input common-mode voltage of midsupply is recommended to maintain optimal performance.

The SHA input is a differential, switched-capacitor circuit. In Figure 31, the clock signal alternatively switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents.

The equations above show that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage.

The internal voltage reference can be pin-strapped to fixed values of 0.5 V or 1.0 V or adjusted within the same range as discussed in the Internal Reference Connection section. Maximum SNR performance is achieved with the AD9238 set to the largest input span of 2 V p-p. The relative SNR degradation is 3 dB when changing from 2 V p-p mode to 1 V p-p mode.

The SHA may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as:

VCM

= VREF/2

MIN

This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependant on the application.

Rev. B | Page 16 of 48

VCM

= (AV D D + VREF)/2

MAX

AD9238

2

The minimum common-mode input level allows the AD9238 to accommodate ground-referenced inputs. Although optimum performance is achieved with a differential input, a singleended source may be driven into VIN+ or VIN−. In this configuration, one input accepts the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal may be applied to VIN+, while a 1 V reference is applied to VIN−. The AD9238 then accepts an input signal varying between 2 V and 0 V. In the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies and in the lower speed grade models (AD9238-40 and AD9238-20).

Differential Input Configurations

As previously detailed, optimum performance is achieved while driving the AD9238 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.

At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9238. This is especially true in IF under-sampling applications where frequencies in the 70 MHz to 200 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration, as shown in Figure 32.

CLOCK INPUT AND CONSIDERATIONS

Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics.

The AD9238 provides separate clock inputs for each channel. The optimum performance is achieved with the clocks operated at the same frequency and phase. Clocking the channels asynchronously may degrade performance significantly. In some applications, it is desirable to skew the clock timing of adjacent channels. The AD9238’s separate clock inputs allow for clock timing skew (typically ±1 ns) between the channels without significant performance degradation.

The AD9238 contains two clock duty cycle stabilizers, one for each converter, that retime the nonsampling edge, providing an internal clock with a nominal 50% duty cycle. When proper track-and-hold times for the converter are required to maintain high performance, maintaining a 50% duty cycle clock is particularly important in high speed applications. It may be difficult to maintain a tightly controlled duty cycle on the input clock on the PCB (see Figure 23). DCS can be enabled by tying the DCS pin high.

The duty cycle stabilizer uses a delay-locked loop to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 2 µs to 3 µs to allow the DLL to acquire and settle to the new rate.

AVDD

VINA

AD9238

VINB

AGND

02640-032

V p-p

49.9Ω

0.1µF

Figure 32. Differential Transformer Coupling

50Ω

10pF

50Ω

10pF

1kΩ

The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion.

Single-Ended Input Configuration

A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there is a degradation in SFDR and distortion performance due to the large input common-mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance.

High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (f

) due only to aperture jitter (tJ) can be

INPUT

calculated as

SNR

⎡

×=

log20

⎢

()

⎢

⎣

1

π2

INPUT

In the equation, the rms aperture jitter, t

⎤ ⎥

×××

tf

⎥

j

⎦

, represents the root-

J

sum square of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter.

For optimal performance, especially in cases where aperture jitter may affect the dynamic range of the AD9238, it is important to minimize input clock jitter. The clock input circuitry should use stable references; for example, use analog power and ground planes to generate the valid high and low digital levels for the AD9238 clock input. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source

Rev. B | Page 17 of 48

AD9238

(by gating, dividing, or other methods), it should be retimed by the original clock at the last step.

POWER DISSIPATION AND STANDBY MODE

The power dissipated by the AD9238 is proportional to its sampling rates. The digital (DRVDD) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The digital drive current can be calculated by

discharged 0.1 µF and 10 µF decoupling capacitors on REFT and REFB.

A single channel can be powered down for moderate power savings. The powered-down channel shuts down internal circuits, but both the reference buffers and shared reference remain powered on. Because the buffer and voltage reference remain powered on, the wake-up time is reduced to several clock cycles.

= V

I

DRVDD

where N is the number of bits changing, and C

DRVDD

× C

LOAD

× f

CLOCK

× N

is the average

LOAD

load on the digital pins that changed.

The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increases with clock frequency.

Either channel of the AD9238 can be placed into standby mode independently by asserting the PDWN_A or PDWN_B pins.

It is recommended that the input clock(s) and analog input(s) remain static during either independent or total standby, which results in a typical power consumption of 1 mW for the ADC. Note that if DCS is enabled, it is mandatory to disable the clock of an independently powered-down channel. Otherwise, significant distortion results on the active channel. If the clock inputs remain active while in total standby mode, typical power dissipation of 12 mW results.

The minimum standby power is achieved when both channels are placed into full power-down mode (PDWN_A = PDWN_B = HI). Under this condition, the internal references are powered down. When either or both of the channel paths are enabled after a power-down, the wake-up time is directly related to the recharging of the REFT and REFB decoupling capacitors and to the duration of the power-down. Typically, it takes approximately 5 ms to restore full operation with fully

A

–1

0

A

1

A

2

A

3

DIGITAL OUTPUTS

The AD9238 output drivers can be configured to interface with

2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches.

The data format can be selected for either offset binary or twos complement. See the Data Format section for more information.

TIMING

The AD9238 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (t to Figure 2 for a detailed timing diagram.

The internal duty cycle stabilizer can be enabled on the AD9238 using the DCS pin. This provides a stable 50% duty cycle to internal circuits.

The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9238. These transients can detract from the converter’s dynamic performance. The lowest typical conversion rate of the AD9238 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance may degrade.

A

4

A

5

) after the rising edge of the clock signal. Refer

PD

8

ANALOG INPUT ADC A

A

6

7

A

B

–1

0

B

–8

t

PD

Figure 33. Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT

B

1

A

B

–7

B

2

A

B–6A–5B–5A

–6

B

3

t

PD

B

4

B

–4

B

5

A

B

–3

B

6

A

–2

A

B

–2

7

B

–1

B

8

ANALOG INPUT ADC B

CLK_A = CLK_B = MUX_SELECT

A

B

0

A

0

1

D0_A TO D11_A

02640-066

Rev. B | Page 18 of 48

AD9238

DATA FORMAT

The AD9238 data output format can be configured for either twos complement or offset binary. This is controlled by the data format select pin (DFS). Connecting DFS to AGND produces offset binary output data. Conversely, connecting DFS to AVDD formats the output data as twos complement.

The output data from the dual ADCs can be multiplexed onto a single 12-bit output bus. The multiplexing is accomplished by toggling the MUX_SELECT bit, which directs channel data to the same or opposite channel data port. When MUX_SELECT is logic high, the Channel A data is directed to the Channel A output bus, and the Channel B data is directed to the Channel B output bus. When MUX_SELECT is logic low, the channel data is reversed, that is the Channel A data is directed to the Channel B output bus, and the Channel B data is directed to the Channel A output bus. By toggling the MUX_SELECT bit, multiplexed data is available on either of the output data ports.

If the ADCs run with synchronized timing, this same clock can be applied to the MUX_SELECT pin. Any skew between CLK_A, CLK_B, and MUX_SELECT can degrade ac performance. It is recommended to keep the clock skew <100 pS. After the MUX_SELECT rising edge, either data port has the data for its respective channel; after the falling edge, the alternate channel’s data is placed on the bus. Typically, the other unused bus would be disabled by setting the appropriate OEB high to reduce power consumption and noise. Figure 33 shows an example of multiplex mode. When multiplexing data, the data rate is two times the sample rate. Note that both channels must remain active in this mode and that each channel’s powerdown pin must remain low.

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into the AD9238. The input range can be adjusted by varying the reference voltage applied to the AD9238, using either the internal reference with different external resistor configurations or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. If the ADC is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage).

gain and offset matching performance. If the ADCs are to function independently, the reference decoupling can be treated independently and can provide superior isolation between the dual channels. To enable shared reference mode, the SHARED_REF pin must be tied high and the external differential references must be externally shorted. (REFT_A must be externally shorted to REFT_B, and REFB_A must be shorted to REFB_B.)

Internal Reference Connection

A comparator within the AD9238 detects the potential at the SENSE pin and configures the reference into four possible states, which are summarized in Table 7. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 34), setting VREF to 1 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected, as shown in Figure 35, the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as

VREF = 0.5 × (1 + R2/R1)

In all reference configurations, REFT and REFB drive the ADC core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.

VIN+

VIN–

REFT

0.1µF

10µF

VREF

0.1µF

SENSE

SELECT

LOGIC

ADC

CORE

0.5V

REFB

0.1µF

10µF

The shared reference mode allows the user to connect the references from the dual ADCs together externally for superior

Figure 34. Internal Reference Configuration

AD9238

Table 7. Reference Configuration Summary

Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p)

External Reference AVDD N/A 2 × External Reference Internal Fixed Reference VREF 0.5 1.0 Programmable Reference 0.2 V to VREF 0.5 × (1 + R2/R1) 2 × VREF (See Figure 35) Internal Fixed Reference AGND to 0.2 V 1.0 2.0

Rev. B | Page 19 of 48

02640-034

AD9238

External Reference Operation

The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. A high precision external reference may also be selected to provide lower gain and offset temperature drift. Figure 36 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 kΩ load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 V. If the internal reference of the AD9238 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 37 depicts how the internal reference voltage is affected by loading.

VIN+

VIN–

REFT

0.1µF

ADC

CORE

REFB

0.1µF

10µF

1.2

1.0

0.8

0.6

VREF ERROR (%)

0.4

0.2

0

–40

0.05

0

–0.05

–0.10

ERROR (%)

–0.15

–0.20

–0.25

0

–30

–20

–10010

20

TEMPERATURE (°C)

Figure 36. Typical VREF Drift

1V ERROR

0.5

1.0

1.5

LOAD (mA)

Figure 37. VREF Accuracy vs. Load

30

VREF = 0.5V

50

40

0.5V ERROR

2.0

VREF = 1V

70

60

2.5

02640-067

80

02640-068

3.0

10µF

SENSE

VREF

R2

R1

SELECT

LOGIC

0.5V

AD9238

02640-035

Figure 35. Programmable Reference Configuration

Rev. B | Page 20 of 48

AD9238

AD9238 LQFP EVALUATION BOARD

The evaluation board supports both the AD9238 and AD9248 and has five main sections: clock circuitry, inputs, reference circuitry, digital control logic, and outputs. A description of each section follows. Table 8 shows the jumper settings and notes assumptions in the comment column.

Four supply connections to TB1 are necessary for the evaluation board: the analog supply of the DUT, the on-board analog circuitry supply, the digital driver DUT supply, and the onboard digital circuitry supply. Separate analog and digital supplies are recommended, and on each supply 3 V is nominal. Each supply is decoupled on-board, and each IC, including the DUT, is decoupled locally. All grounds should be tied together.

CLOCK CIRCUITRY

The clock circuitry is designed for a low jitter sine wave source to be ac-coupled and level shifted before driving the 74VHC04 hex inverter chips (U8 and U9) whose output provides the clock to the part. The POT (R32 and R31) on the level shifting circuitry allows the user to vary the duty cycle if desired. The amplitude of the sine wave must be large enough for the trip points of the hex inverter and within the supplies to avoid noise from clipping. To ensure a 50% duty cycle internal to the part, the AD9238-65 has an on-chip duty cycle stabilizer circuit that is enabled by putting in Jumper JP11. The duty cycle stabilizer circuitry should only be used at clock rates above 40 MSPS.

Each channel has its own clock circuitry, but normally both clock pins are driven by a single 74VHC04, and the solder Jumper JP24 is used to tie the clock pins together. When the clock pins are tied together and only one 74VHC04 is being used, the series termination resistor for the other channel must be removed (either R54 or R55, depending on which inverter is being used).

A data capture clock for each channel is created and sent to the output buffers in order to be used in the data capture system if needed. Jumpers JP25 and JP26 are used to invert the data clock if necessary and can be used to debug data capture timing problems.

ANALOG INPUTS

The AD9238 achieves the best performance with a differential input. The evaluation board has two input options for each channel, a transformer (XFMR) and an AD8138, both of which perform single-ended-to-differential conversions. The XFMR allows for the best high frequency performance, and the AD8138 is ideal for dc evaluation, low frequency inputs, and driving an ADC differentially without loading the single-ended signal.

The common-mode level for both input options is set to midsupply by a resistor divider off the AVDD supply but can also be overdriven with an external supply using the (test points) TP12, TP13 for the AD8138s and TP14, TP15 for the XFMRs. For low distortion of full-scale input signals when using an AD8138, put JP17 and JP22 in Position B and put an external negative supply on TP10 and TP11.

For best performance, use low jitter input sources and a high performance band-pass filter after the signal source, before the evaluation board (see Figure 38). For XFMR inputs, use solder Jumpers JP13, JP14 for Channel A and JP20, JP21 for Channel B. For AD8138 inputs, use solder Jumpers JP15, JP16 for Channel A and JP18, JP19 for Channel B. Remove all solder from the jumpers not being used.

REFERENCE CIRCUITRY

The evaluation board circuitry allows the user to select a reference mode through a series of jumpers and provides an external reference if necessary. Refer to Table 9 to find the jumper settings for each reference mode. The external reference on the board is a simple resistor divider/zener diode circuit buffered by an AD822 (U4). The POT (R4) can be used to change the level of the external reference to fine adjust the ADC full scale.

DIGITAL CONTROL LOGIC

The digital control logic on the evaluation board is a series of jumpers and pull-down resistors used as digital inputs for the following pins on the AD9238: the power-down and output enable bar for each channel, the duty cycle restore circuitry, the twos complement output mode, the shared reference mode, and the MUX_SELECT pin. Refer to Table 8 for normal operating jumper positions.

OUTPUTS

The outputs of the AD9238 (and the data clock discussed earlier) are buffered by 74VHC541s (U2, U3, U7, U10) to ensure the correct load on the outputs of the DUT, as well as the extra drive capability to the next part of the system. The 74VHC541s are latches, but on this evaluation board, they are wired and function as buffers. JP30 can be used to tie the data clocks together if desired. If the data clocks are tied, R39 or R40 must be removed, depending on which clock circuitry is being used.

Rev. B | Page 21 of 48

AD9238

Table 8. PCB Jumpers

Normal

JP Description

1 Reference Out 1 V Reference Mode 2 Reference In 1 V Reference Mode 3 Reference Out 1 V Reference Mode 4 Reference Out 1 V Reference Mode 5 Reference Out 1 V Reference Mode 6 Shared Reference Out 7 Shared Reference Out 8 PDWN B Out 9 PDWN A Out 10 Shared Reference Out 11 Duty Cycle In Duty Cycle Restore On 12 Twos Complement Out 13 Input In Using XFMR Input 14 Input In Using XFMR Input 15 Input Out Using XFMR Input 16 Input Out Using XFMR Input 17 AD8138 Supply A Using XFMR Input 18 Input Out Using XFMR Input 19 Input Out 20 Input In 21 Input In 22 AD8138 Supply A 23 Mux Select Out 24 Tie Clocks In Using One Signal for Clock 25 Data Clock A 26 Data Clock Out Using One Signal for Clock 27 Mux Select In 28 OEB_A Out 29 Mux Select Out 30 Data Clock Out 35 OEB_B Out

Setting Comment

Table 9. Reference Jumpers

Reference Mode JP1 JP2 JP3 JP4 JP5

1 V Internal Out In Out Out Out

0.5 V Internal Out Out In Out Out External In Out Out Out In

SINE SOURCE

LOW JITTER

SINE SOURCES

LOW JITTER

(HP8644)

BAND-PASS

FILTERS

AD9238

EVALUATION BOARD

INPUT

CIRCUITRY

Figure 38. PCB Test Setup

(HP8644)

CLOCK

CIRCUITRY

AD9238

REFERENCE MODE SELECTION/EXTERNAL REFERENCE/CONTROL

LOGIC

OUTPUT

BUFFERS

02640-060

Rev. B | Page 22 of 48

AD9238

LQFP EVALUATION BOARD BILL OF MATERIALS (BOM)

Table 10.

No. Quantity Reference Designator Device Package Value

1 18 C1, C2, C11, C12, C27, C28, C33, C34, C50, C51, C73 to C76, C87 to C90 Capacitors ACASE 10 µF 2 23 C3 to C10, C29 to C31, C56, C61 to C65, C77, C79, C80, C84 to C86 Capacitors 0805 0.1 µF 3 7 C13, C15, C18, C19, C21, C23, C25 Capacitors 0603 0.001 µF 4 15 C6, C14, C16, C17, C20, C22, C24, C26, C32, C35 to C40 Capacitors 0603 0.1 µF 5 4 C41 to C44 Capacitors DCASE 22 µF 6 4 C45 to C48 Capacitors 1206 0.1 µF 7 2 C49, C53 Capacitors ACASE 6.3 V 8 2 C52, C57 Capacitors 0201 0.01 µF 9 4 C54, C55, C68, C69 Capacitors 0805 10 4 C58, C59, C70, C71 Capacitors 0603 DNP 11 2 C60, C72 Capacitors 0603 20 pF 12 1 D1 AD1580 SOT-23CAN 1.2 V 13 1 J1 SAM080UPM 14 14 JP1 to JP5, JP8 to JP12, JP23, JP28, JP29, JP35 JPRBLK02 15 13 JP6, JP7, JP13, JP14 to JP16, JP18 to JP21, JP24, JP27, JP30 JPRSLD02 16 4 JP17, JP22, JP25, JP26 JPRBLK03 17 4 L1 to L4 IND1210 LC1210 10 µH 18 6 R1, R2, R13, R14, R23, R27 Resistors 1206 33 Ω 19 1 R3 Resistor 1206 5.49 kΩ 20 1 R4 Resistor RV3299UP 10 kΩ 21 7 R5, R6, R38, R41, R43, R44, R51 Resistors 0805 5 kΩ 22 6 R7, R8, R19, R20, R52, R53 Resistors 1206 49.9 Ω 23 8 R9, R18, R29, R30, R47 to R50 Resistors 0805 1 kΩ 24 6 R10, R12, R15, R24, R25, R28 Resistors 1206 499 Ω 25 2 R11, R26 Resistors 1206 523 Ω 26 4 R16, R17, R21, R22 Resistors 1206 40 Ω 27 2 R31, R32 Resistors RV3299W 10 kΩ 28 4 R33 to R35, R42 Resistors 0805 500 Ω 29 2 R36, R37 Resistors 1206 10 kΩ 30 2 R39, R40 Resistors 0805 22 Ω 31 2 R54, R55 Resistors 1206 0 Ω 32 16 RP1 to RP16 Resistor Pack RCA74204 22 Ω 33 6 S1 to S6 SMA200UP 34 2 T1, T2 DIP06RCUP T1-1T 35 1 TB1 TBLK06REM 36 4 TP1, TP3, TP5, TP7 LOOPTP RED 37 4 TP2, TP4, TP6, TP8 LOOPTP BLK 38 7 TP9, TP12 to TP17 LOOPMINI WHT 39 2 TP10, TP11 LOOPMINI RED 40 1 U1 64LQFP7X7 AD9238 41 4 U2, U3, U7, U10 SOL20 74VHC541 42 1 U4 SOIC-8 AD822 43 2 U5, U6 SO8NC7 AD8138 44 2 U8, U9 TSSOP-14 74VHC04

Rev. B | Page 23 of 48

AD9238

LQFP EVALUATION BOARD SCHEMATICS

BLK

AVDD

L2

10µH

1

AVDDIN

TB1

DUTCLKA

12

74VHC04

13

C46

C42

CLKAO

TP2

RED

TP3

L1

0.1µF 10µH

25V

22µF

DUTAVDDIN

JP24

10

AGND;7

AVDD;14

U9

11

JP25

74VHC04

RED

TP1

0Ω

R54

TP17

WHT

8

AGND;7

74VHC04

AVDD;14

U9

AGND;7

AVDD;14

U9

9

DUTAVDD

2

TB1

R1

13

A B

BLK

TP4

C45

0.1µF

C41

22µF

33Ω

2

25V

DATACLKA

AGND

3

TB1

R2

RED

TP5

10µHL4

DRVDDIN

DATACLKB

33Ω

2

DUTDRVDD

5

TB1

1

A

B

3

C44

JP26

C48

AGND;7

TP6

0.1µF

22µF

AVDD;14

BLK

25V

U8

AGND

10

11

TP7

4

TB1

AGND;7

74VHC04

DVDD

RED

L3

10µH

6

TB1

DVDDIN

0Ω

R55

12

AVDD;14

U8

13

BLK

TP8

C47

0.1µF

C43

22µF

F25V

DUTCLKB

WHT

TP16

AGND;7

74VHC04

AVDD;14

U8

8

74VHC04

9

74VHC04

R32

10kΩ

CLKA

S6

AGND;7

C84

4

AVDD;14

74VHC04

U9

3

R42

500Ω

0.1µF

R53

49.9Ω

6

AGND;7

AVDD;14

U9

5

AGND;7

74VHC04

R33

500Ω

2

AVDD;14

U9

1

AVDD

CW

AGND;7

R35

AVDD;14

U8

500Ω

43

CW

AVDD

AGND;7

74VHC04

R31

10kΩ

CLKB

S5

C77

AVDD;14

U8

0.1µF

2

1

AGND;7

74VHC04

R34

R52

49.9Ω

AVDD;14

U8

500Ω

6

5

74VHC04

AVDD

C73

C80

C74

C79

10µF

0.1µF

10µF

0.1µF

6.3V

02640-038

Figure 39. Evaluation Board Schematic

Rev. B | Page 24 of 48

AD9238

JP15

VIN+_A

C59

DNP

R13

33Ω

JP14

C68

VAL

SHEET 3

C60

20pF

R14

33Ω

JP13

C69

VIN–_A

JP16

VAL

C89

C58

DNP

WHT

TP14

T1–1T

XFMR INPUT A

C87

6.3V

10µF

6.3V

10µF

1

S

NC = 5 P

6

S2

C85

C64

2

O

R19

49.9Ω

0.1µF R50

1kΩ

R47

0.1µF

3

T1

4

1kΩ

R30

1kΩ

AVDD

VIN–_B

C71

DNP

R27

33Ω

JP19

JP20

C55

VAL

SHEET 3

C72

20PF

VIN+_B

C65

C90

6.3V

DNP

C88

JP18

10µF

TP15

T1–1T

6.3V

10µF

WHT

1 SP

NC = 5

6

C63

C70

R23

33Ω

JP21

C54

VAL

0.1µF

R48

1kΩ

R49

1kΩ

AVDD

3

2

O

T2

O

4

R7

49.9Ω

XFMR INPUT B

S4

0.1µF R9

1kΩ

TP10

RED

JP17

R29

WHT

TP13

AVDD

1kΩ

AVDD

10V

C49

6.3V

02640-B-039

R18

WHT

TP12

AVDD

1kΩ

AVDD

R25

499Ω

RED

TP11

3

V

5

3

0

. 6

JP22

B

2

A

13

C62

0.1µF

C50

6.3V

10µF

1

C

R17

40Ω

R16

40Ω

2

R15

5

4

R12

499Ω

3

B

2

A

1

C56

0.1µF

C51

6.3V

10µF

AD8138

6

VEE

VOC

VO–

VO+

–IN

+IN

1

8

U5

R11

523Ω

AMP INPUT A

499Ω

VCC 3

C86

0.1µF

R10

499Ω

R20

49.9Ω

S1

R22

40Ω

AD8138

6

VEE

499

R28

S3

AMP INPUT B

R21

40Ω

2

R24

4

5

VOC

VO+

VO–

–IN

+IN

8

1

U6

R26

523Ω

R8

499Ω

VCC

3

C61

0.1µF

49.9Ω

Figure 40. Evaluation Board Schematic (Continued)

Rev. B | Page 25 of 48

AD9238

DUTAVDD

AVDD

6.3V

C2

10µF

C21

0.001µF

C22

0.1µF

C19

0.001µF

C20

0.1µF

C17

0.1µF

C18

0.001µF

646362616059585756555453525150

JP10

DUTCLKA

AVDD1

CLK_A

JP9

JP28

OEB_A

PDWN_A

SHAREDREF

MUXSELECT

OTRA

DA13

OTR_A

(MSB)D11_A

R6

R43

R38

DA12

D10_A

5kΩ

DA11

D9_A

DA10

D8_A

DRVSS3

DRVDD3

DA9

D7_A

JP27

DA8

49

D6_A

CLKAO

DA7

DA6

D4_A

D5_A

47

JP29

DA5

46

D3_A

AVDD

DA4

D2_A

45

DA3

D1_A

JP23

DA2

44

D0_A

43

DA1

DNC

42

DA0

DNC

41

DRVDD2

40

39

DRVSS2

OTRB

DB13

38

OTR_B

(MSB)D11_B

37

DB12

36

D10_B

DB11

D9_B

DUTDRVDD

6.3V

C11

10µF

C14

0.1µF

DB10

DB9

DB8

C13

0.001µF

33

34

35

C26

0.1µF

D8_B

D6_B

D7_B

C25

U1

0.001µF

AD9238

C24

C16

0.1µF

VIN+_A

VIN–_A

AVSS2

AVDD2

REFT_A

REFB_A

VREF

SENSE

REFB_B

REFT_B

AVDD3

AVSS3

VIN–_B

VIN+_B

AVSS4

AVDD4

AVSS1

C15

0.001µF

1

5

4

3

2

9

8

7

6

11

10

15

14

13

12

CLK_B

19

18

17

16

OEB_B

DUTYEN

DFS

PDWN_B

DNC

D0_B

D1_B

D2_B

DRVSS1

DRVDD1

D3_B

D4_B

D5_B

32

31

30

29

28

27

26

254824

23

22

21

20

0.1µF

C23

0.001µF

AVDD

VIN–_A

VIN+_A

C52

C40

JP6

C39

0.01µF

0.1µF

AGND;4

AVDD;8

+IN

576

AVDD

JP7

U4 OUT

R3

–IN

5.49kΩ

AD822

CW

TP9

WHT

R4

1.2V 1

C35

0.1µF

C33

6.3V

10µF

C36

0.1µF

C38

0.1µF

C34

6.3V

10µF

C37

0.1µF

6.3V

C1

10µF

C30

0.1µF

1

AGND;4

AVDD;8

+IN 3

10kΩ

D1

2

C57

C32

OUT U4

C29

VIN–_B

0.01µF

0.1µF

–IN

2

0.1µF

VIN+_B

JP5

AD822

DUTCLKB

C12

JP2

JP3

DB0

R44

5kΩ

R5

5kΩ

JP8

JP35

6.3V

10µF

AVDD

R51

5kΩ

R41

AVDD

5kΩ

02640-040

JP1

JP4

JP12

JP11

DUTAVDD

C31

0.1µF

R36

10kΩ

R37

10kΩ

DB7

DB6

DB5

DB4

DB3

DB2

DB1

Figure 41. Evaluation Board Schematic (Continued)

Rev. B | Page 26 of 48

AD9238

OTRA

DA13 DA12 DA11 DA10

DA9 DA8

DA7 DA6 DA5 DA4 DA3 DA2

DA1

DA0

C75 10µF

6.3V

DATACLKA RP9

1

RP9

2 3

RP9 RP94 RP10 RP102 RP10

3

RP10

4

RP11 RP11

2

RP11 RP11

4

RP12 RP12

2

RP12 RP12

4

C3

0.1µF

22Ω

22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω

22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω

C10

0.1

0.1µF

8 7

6 5 81 7 6 5

81 7 63 5 81 7 63 5

µF

1

G1

19

G2 GND

74VHC541

A1 Y1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

1

G1

19

G2 GND

74VHC541

2

A1 Y1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

U10

0.1µF

U7

VCC

10µF

6.3V DVDD

20 10

182 17

Y2

16

Y3

15

Y4

14

Y5

13

Y6

12

Y7

11

Y8

20 10

18

17

Y2

16

Y3

15

Y4

14

Y5

13

Y6

12

Y7

11

Y8

R40 22Ω

RP1 22Ω

RP1

2

RP1 RP14 RP2 RP22 RP2

4

RP2 RP3 81

2

RP3 RP3

4

RP3 RP4 RP42 RP4

4

RP4

81

22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω

2

7 63 5 81 7 63 5

4 6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

SAM080UPM

JP30

J1

11 13 15 17 19 21 23 25

HEADER UP MALE NO SHROUD

27 29 31 33 35 37 39

1 3 5 7 9

C28

C8

C9

C4

0.1µF

VCC GND

VCC

C27 10µF

6.3V

20 10

18 17

Y2

16

Y3

15

Y4

14

Y5

13

Y6

12

Y7

11

Y8

20 10

18 17

Y2

16

Y3

15

Y4

14

Y5

13

Y6

12

Y7

11

Y8

DVDD

R39 22Ω

1 2 3 4 1 2

4

1

2

4 1 2 3

RP5 RP5 RP5 RP5 RP6 RP6 RP6 RP6 RP7 RP7 RP763 RP7 RP8 RP8 RP8

RP8 22Ω

22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω

HEADER UP MALE NO SHROUD

J1

41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79

02640-041

42

8 7 6 5 8 7 63 5 8 7

5 8 7 6

54

44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80

SAM080UPM

OTRB

DA13 DA12

DA11

DA10

DA9

DA8

DA7

DA6 DA5 DA4 DA3 DA2 DA1 DA0

C76 10µF

6.3V

RP13

1

2

RP13

3

RP13

4

RP13 RP14

2

RP14 RP14

3 4

RP14

1

RP15

2

RP15

3

RP15

4 1

RP16 RP16

2 3

RP16 RP16

4

DATACLKB

C7

0.1µF

22Ω

22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω

22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω

C6

C5

0.1µF

1

G1

8

7 6 5 81 7 6 5 8

7 6 5 8 7 6 5

19

1

19

U2

G2

74VHC541

2

A1 Y1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

G1

U3

G2 GND

74VHC541

2

A1 Y1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

Figure 42. Evaluation Board Schematic (Continued)

Rev. B | Page 27 of 48

AD9238

LQFP PCB LAYERS

Figure 43. PCB Top Side Silkscreen

02640-046

Rev. B | Page 28 of 48

AD9238

Figure 44. PCB Top Layer

02640-042

Rev. B | Page 29 of 48

AD9238

Figure 45. PCB Ground Plane

02640-044

Rev. B | Page 30 of 48

AD9238

Figure 46. PCB Split Power Plane

02640-045

Rev. B | Page 31 of 48

AD9238

Figure 47. PCB Bottom Layer

02640-043

Rev. B | Page 32 of 48

AD9238

Figure 48. PCB Bottom Silkscreen

2640-047

Rev. B | Page 33 of 48

AD9238

DUAL ADC LFCSP PCB1

The PCB requires a low jitter clock source, analog sources, and power supplies. The PCB interfaces directly with ADI’s standard dual-channel data capture board (HSC-ADC-EVAL-DC), which together with ADI’s ADC Analyzer™ software allows for quick ADC evaluation.

POWER CONNECTOR

Power is supplied to the board via three detachable 4-lead power strips.

Table 11. Power Connector

Terminal Comments

VCC1 3.0 V Analog supply for ADC VDD1 3.0 V Output supply for ADC VDL1 3.0 V Supply circuitry VREF Optional external VREF +5 V Optional op amp supply

−5 V Optional op amp supply

1

VCC, VDD, and VDL are the minimum required power connections.

ANALOG INPUTS

The evaluation board accepts a 2 V p-p analog input signal centered at ground at two SMB connectors, Input A and Input B. These signals are terminated at their respective transformer primary side. T1 and T2 are wideband RF transformers that provide the single-ended-to-differential conversion, allowing the ADC to be driven differentially, minimizing even-order harmonics. The analog signals can be low-pass filtered at the transformer secondary to reduce high frequency aliasing.

OPTIONAL OPERATIONAL AMPLIFIER

The PCB has been designed to accommodate an optional AD8139 op amp that can serve as a convenient solution for dc-coupled applications. To use the AD8139 op amp, remove C14, R4, R5, C13, R37, and R36. Place R22, R23, R30, and R24.

CLOCK

The clock inputs are buffered on the board at U5 and U6. These gates provide buffered clocks to the on-board latches, U2 and U4, ADC input clocks, and DRA and DRB that are available at the output Connector P3, P8. The clocks can be inverted at the timing jumpers labeled with the respective clocks. The clock paths also provide for various termination options. The ADC input clocks can be set to bypass the buffers at P2 to P9 and P10, P12. An optional clock buffer U3, U7 can also be placed. The clock inputs can be bridged at TIEA, TIEB (R20, R40) to allow one to clock both channels from one clock source; however, optimal performance is obtained by driving J2 and J3.

Table 12. Jumpers

Terminal Comments

OEB A Output Enable for A Side PDWN A Power-Down A MUX Mux Input SHARED REF Shared Reference Input DR A Invert DR A LATA Invert A Latch Clock ENC A Invert Encode A OEB B Output Enable for B Side PDWN B Power-Down B DFS Data Format Select SHARED REF Shared Reference Input DR B Invert DR B LATB Invert B Latch Clock ENC B Invert Encode B

VOLTAGE REFERENCE

The ADC SENSE pin is brought out to E41, and the internal reference mode is selected by placing a jumper from E41 to ground (E27). External reference mode is selected by placing a jumper from E41 to E25 and E30 to E2. R56 and R45 allow for programmable reference mode selection.

1

The LFCSP PCB is in development.

DATA OUTPUTS

The ADC outputs are latched on the PCB at U2 and U4. The ADC outputs have the recommended series resistors in line to limit switching transient effects on ADC performance.

Rev. B | Page 34 of 48

AD9238

LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM)

Table 13.

No. Quantity Reference Designator Device Package Value

1 2 C1, C3 Capacitors 0201 20 pF 2 7 C2, C5, C7, C9, C10, C22, C36 Capacitors 0805 10 µF 3 44

C4, C6, C8, C11 to C15, C20, C21,

C24 to C27, C29 to C35, C39 to C61 4 6 C16 to C19, C37, C38 Capacitors TAJD 10 µF 5 2 C23, C28 Capacitors 0201 0.1 µF 6 6 J1 to J6 SMBs 7 3 P1, P4, P11 Power Connector Posts Z5.531.3425.0 Wieland 8 3 P1, P4, P11 Detachable Connectors 25.602.5453.0 Wieland 9 2 P31, P8 Connectors 10 4 R1, R2, R32, R34 Resistors 0402 36 Ω 11 6 R3, R7, R11, R14, R51, R61 Resistors 0402 50 Ω 12 4 R4, R5, R36, R37 Resistors 0402 33 Ω 13 9 R9, R10, R12, R13, R20, R35, R38, R40, R43 Resistors 0402 0 Ω 14 6 R15, R16, R18, R26, R29, R31 Resistors 0402 499 Ω 15 2 R17, R25 Resistors 0402 525 Ω 16 27

R19, R21, R27, R28, R39, R41, R44,

R46 to R49, R52, R54, R55, R57 to R60, R62 to R70 17 4 R22 to R24, R30 Resistors 0402 40 Ω 18 2 R45, R56 Resistors 0402 10 kΩ 19 1 R50 Resistor 0402 22 Ω 20 8 RZ1 to RZ6, RZ9, RZ10 Resistor Pack 220 Ω 21 2 T1, T2 Transformers AWT-1WT Mini-Circuits® 22 1 U1 AD9238 LFCSP-64 23 2 U2, U4 SN74LVCH16373A TSSOP-48 24 2 U32, U7 SN74LVC1G04 SOT-70 25 2 U5, U6 SN74VCX86 SO-14 26 2 U11, U12 AD8139 SO-8/EP 27 4 R6, R8, R33, R42 Resistors 0402 100 Ω

1

P3 and P8 implemented as one 80-pin connector SAMTEC TSW-140-08-L-D-RA.

2

U3 and U7 not placed.

Capacitors 0402 0.1 µF

Resistors 0402 1 kΩ

Rev. B| Page 35 of 48

AD9238

LFCSP PCB SCHEMATICS

VD

C25

0.1µF

ENCA

14

Ω

R42

100

Ω

0

R43

4

Y

GND

3

VCC

74LCX86

1A

1234567

U7

P12 P10

VD

R39

J6

Ω

R61

50

Ω

E10

R63

1k

VD

E17

VD

E6

R65

1kΩ

E5

VD

–5V

+5V

EXT_VREFVDLVDD

4123 4123 4123

VD

C58

0.1µF

C36

DUT CLOCK SELECTABLE

TO BE DIRECT OR BUFFERED

VD

Ω

R33

100

VD

10µF

5

VCC

A

NC

SN74LVC1G04

2

1

F

µ

C56

0.1

MUX

E9

E7

Ω

R64

1k

P1

P4

P11

VD

E15

Ω

E14

E13 E12

R46

1k

DRA

Ω

0

R10

124Y113B103A9

4B134A

1B1Y2A2B2Y

E4VD

1kΩ

C40

0.1µF

TIEA

J3

ENCODE A

C8

0.1µF

VDD

Ω

E20

R62

1k

E18

ENCA

Ω

R66

1k

VD

EXT_VREF

C19

C18

VDD VDL

C17

+ + + ++

VD

C16

+5V

C38

–5V

C37

VDL

VD

VDD

P5

P7

P6

H1

H3

C45

C44

C43

C39

VD

Ω

R47

1k

Ω

0

8

R9

3Y

CLKLATA

MUX

Ω

0

R35

Ω

0

R38

U6

GND

P14

R44

1kΩ

E3

R41

1kΩ

R11

50Ω

D9A

D10A

D13A OTRA

VD

1µF

.

0

1µF

.

0 1µF

.

0

0.1µF

10µF

+

10µF

H4

H2

TO TIE CLOCKS TOGETHER

D3A

45

D6_A D6A48D5_A D5A47D4_A D4A46D3_A

D7_A D7A

49

D8_A D8A

50

D9_A

51

DRVDD2

52

DRGND2

53

D10_A

54

D11_A D11A

55

D12_A D12A

56

D13_A

57

OTR_A

58

OEB_A

59

PDWN_A

60 61 62 63 64

65

MUX_SEL

SH_REF CLK_A AVDD5

EPAD

AGND2VIN_A3VIN_AB4AGND1

1

C23

C1

20pF

C24

AMPOUTA

Ω

R4

33

T2

F

µ

C14

0.1

Ω

R3

50

AMPINA

J4

AIN A

C4

D2A

42

44

D2_A

D1_A D1A43D0_A D0A

AVDD16REFT_A

5

7

VD

0.1µF C55

C5

0.1µF

C26

Ω

R5

33

CTAPA

6

5

4

3

1

2

CTAPA

F

µ

C31

0.1

Ω

0

F

µ

0.1

REFB_A

0.1µF

10µF

0.1µF

AMPOUTAB

C9

41

8

R58

TIEA

J5

DRVDD1

VREF

PADS TO SHORT

F

µ

10

R20

R14

VDD

40

DRGND1

U1

SENSE

9

SENSE

SEE

BELOW

C29

0.1µF

REFTA

REFERENCES TOGETHER

Ω

1k

R57

TIEB

Ω

0

R40

Ω

50

OTRB

39

D13_B D13B38D12_B D12B37D11_B D11B36D10_B

OTR_B

REFB_B11REFT_B

10

12

VD

REFT_B

REFB_B

C54

0.1µF

C7

10µF

C27

0.1µF

REFTB

REFBA

REFBB

P15

P16

P18

VD

R60

E42

E43

Ω

R59

1k

BUFFERED

TO BE DIRECT OR

DUT CLOCK SELECTABLE

C57

0.1µF

C22

10µF

D9B

D10B

34

35

D9_B

AGND214VIN_BB15VIN_B16AGND3

AVDD2

13

C28

0.1µF

AMPOUTBB

R37

P17

CTAPB

6

5

1

2

Ω

1k

CTAPB

F

µ

C12

C10

10

0.1

C3

VD

SN74LVC1G04

Ω

33

5

1

33

D8_B D8B

20pF

4

3

AMPINB

AIN B

Ω

R6

100

VD

Ω

22

4

VCC

NC

A

3

2

D7_B

32

D6_B

31

D5_B

30

DRVDD

29

DRGND

28

D4_B

27

D3_B

26

D2_B

25

D1_B

24

D0_B

23

OEB_B

22

PDWN_B

21

DFS

20

DCS

19

CLK_B

18

AVDD3

17

R36

T1

J1

ENCB

Y

GND

Ω

33

C13

R7

Ω

R8

100

R50

U3

VD

D7B D6B D5B

D4B D3B D2B D1B D0B

AMPOUTB

F

µ

0.1

Ω

50

E34 E16

CLKLATB

Ω

0

R12

7

62B5

2Y

GND

U5

3Y3A3B4Y4A4BVCC

8

9

1011121314

P9

P13

E36VD

P2

R52

1kΩ

C42

0.1µF

TIEB

F

µ

J2

0.1 C6

VDD

ENCB

VD

F

µ

C11

0.1

R56

VREF AND SENSE CIRCUIT

VD

Ω

R48

1k

Ω

0

41Y31B21A1

2A

R49

E35

R54

1kΩ

R51

50Ω

ENCODE B

SENSE

Ω

10k

E41

E25

VD

E37E38

DRB

1kΩ



R70

C30

R45

E27

VD

Ω

R55

1k

R13

74LCX86

F

µ

C41

0.1

VD

E31E33

Ω

R69

1k

VD

E26

Ω

1k

Ω

R68

1k

F

µ

0.1

VD

E29

E21

VD

E40

E22

VD

Ω

R67

1k

E24

F

VREF

µ

C2

10

Ω

10k

E30

E2

EXT_VREF

MTHOLE6

02640-069

Figure 49. PCB Schematic (1 of 3)

Rev. B | Page 36 of 48

AD9238

D9Q

D8Q

D7Q

D6Q

D5Q

D4Q

D3Q

D2Q

DRA

GND

D13P

D12P

D11P

D10P

D9P

D8P

D7P

D6P

D5P

D4P

D3P

D2P

D1P

D0P

DORP

DRB

GND

D13Q

D12Q

D11Q

D10Q

D1Q

D0Q

DORQ

DORP

D13P

16151413121110

220

RSO16ISO

24

2Q8

OE2

D = INPUT

Q = OUTPUT

2D8

LE2

25

R3R1R2 312

23

2Q7

2D7

26

RZ5

D12P

R4

4

22

21

GND GND

27

28

39

D11P

R5

20

2Q6

2D6

29

39

40

D10P

R6

19

2Q5

2D5

30

40

D9P

VDL

18

VCC

31

37

R7 765

2Q4

2D4

17

32

D8P

2Q3

2D3

333537

9

R8 8

16

33

P3

D7P

GND

15

34

14

2Q2

2D2

35

220

RZ6

RSO16ISO

12

13

1Q8

2Q1

1D8

2D1

37

36

1113151719212325272931

D6P

D5P

D4P

D3P

16151413121110

R5

R4

R3R1R2

5

4

312

VDL

5

6

8

9

11

10

7

1Q3

1Q4

1Q5

1Q6

1Q7

VCC

GND

VCC

1D3

1D4

1D5

1D6

1D7

GND

38

39

44

43

41

40

42

11131517192123252729313335

D2P

GND

101214161820222426283032343638

4

45

R6 6

1Q2

1D2

101214161820222426283032343638

D1P

3

46

8

R7 7

1Q1

1D1

D0P

2

OE1

LE1

47

13579

HEADER40

246

9

220

R8

RZ10

RSO16ISO

8

1

U2

SN74LVCH16373A

48

D13Q

D11Q

D10Q

D12Q

DORQ

16151413121110

R6

R5

R4

R3R1R2

5

4

312

VDL

19

20

22

23

21

24

2Q8

2Q5

2Q6

2Q7

OE2

D = INPUT

Q = OUTPUT

LE2

2D8

25

26

2D7

VCC

2D5

2D6

GND GND

30

29

27

28

D9Q

18

2Q4

2D4

31

R7

D8Q

17

32

2Q3

2D3

9

R8 876

16

33

39

D7Q

15

GND

34

39

2Q2

2D2

14

35

37

2Q1

2D1

37

220

RZ9

13

1Q8

1D8

36

35

363840

RSO16ISO

12

1Q7

1D7

37

P8

9

40

D5Q

8

1Q5

1D5

41

D4Q

R3R1R2 312

VDL

VCC

7

42

R4

4

1Q4

1D4

D3Q

6

1Q3

1D3

43

D2Q

R5 5

5

GND

44

D6Q

16151413121110

11

10

1Q6

GND

1D6

GND

38

39

4

45

171921232527293133

182022242628303234

R6 6

1Q2

1D2

D1Q

3

1Q1

1D1

46

16

D0Q

R7 7

2

OE1

LE1

47

11131517192123252729313335

111315

8

101214

8

10

121416182022242628303234363840

9

R8 8

1

U4

SN74LVCH16373A

48

13579

246

HEADER40



C50

0.1µF

C51

0.1µF

C52

0.1µF

C53

0.1µF

C46

0.1µF

C47

0.1µF

C48

0.1µF

C49

0.1µF

CLKLATA

16151413121110

220

RZ3

RSO16ISO

D13A

OTRA

R3R1R2 312

R4

4

D12A

R5

D11A

VDL

R6

D10A

D9A

R7 765

D8A

9

R8 8

D7A

VDL

16151413121110

220

RZ4

RSO16ISO

D6A

D5A

R3R1R2

312

R4

D4A

4

D3A

CLKLATA

9

R8

R7

R6

R5

8

7

6

5

D2A

D0A

D1A

CLKLATB

16151413121110

220

RZ1

RSO16ISO

OTRB

Figure 50. PCB Schematic (2 of 3)

Rev. B | Page 37 of 48

R3R1R2 312

D13B

R4

4

D12B

R5

5

D11B

VDL

R6

D10B

R7

D9B

D8B

9

R8 876

D7B

16151413121110

220

RZ2

RSO16ISO

D5B

D6B

R3R1R2

VDL

312

D4B

R4

4

D3B

R5

5

D2B

R6

6

D1B

R7

7

D0B

CLKLATB

9

R8 8

VDL

02640-070

AD9238

OP AMP INPUT OFF PIN 1 OF TRANSFORMER

AMPINA

R16

R17

C59

R18

0.1µF

1kΩ

1

–IN

EPAD

+IN

8

2

VOCM

NC

7

C33

499Ω

C32

0.1µF

+5V

R22

40Ω

4

36

V+

U11

+OUT

AD8139

V–

–OUT

5

0.1µF

–5V

R23

40Ω

AMPOUTAB AMPOUTA

C21

R19

1kΩ

VD

499Ω

525Ω

R21

9

C60

AMPINB

R26

499Ω

C20

R28

1kΩ

VD

R25

525Ω

9

R29

499Ω

Figure 51. PCB Schematic (3 of 3)

C15

R27

C34

C61

R31

0.1µF

1kΩ

1

–IN

EPAD

+IN

8

0.1µF

499Ω

2

VOCM

NC

7

36

R15

V+

V–

499Ω

+5V

4

+OUT

–OUT

5

–5V

C35

0.1µF

AD8139

U12

R30

R24

40Ω

AMPOUTB AMPOUTBB

02640-071

Rev. B | Page 38 of 48

AD9238

LFCSP PCB LAYERS

Figure 52. PCB Top-Side Silkscreen

Rev. B | Page 39 of 48

02640-072

AD9238

Figure 53. PCB Top-Side Copper Routing

02640-073

Rev. B | Page 40 of 48

AD9238

Figure 54. PCB Ground Layer

02640-074

Rev. B | Page 41 of 48

AD9238

Figure 55. PCB Split Power Plane

02640-075

Rev. B | Page 42 of 48

AD9238

Figure 56. PCB Bottom-Side Copper Routing

02640-076

Rev. B | Page 43 of 48

AD9238

Figure 57. PCB Bottom-Side Silkscreen

THERMAL CONSIDERATIONS

The AD9238 LFCSP has an integrated heat slug that improves the thermal and electrical properties of the package when locally attached to a ground plane at the PCB. A thermal (filled) via array to a ground plane beneath the part provides a path for heat to escape the package, lowering junction temperature. Improved electrical performance also results from the reduction in package parasitics due to proximity of the ground plane. Recommended array is 0.3 mm vias on 1.2 mm pitch. θ

26.4°C/W with this recommended configuration. Soldering the slug to the PCB is a requirement for this package.

=

JA

Rev. B | Page 44 of 48

02640-077

02640-078

Figure 58. Thermal Via Array

AD9238

Q

OUTLINE DIMENSIONS

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

9.00

BSC SQ

PIN 1 INDICATOR

0.75

0.60

0.45

0.20

0.09 7°

3.5° 0°

0.10 MAX COPLANARITY

COMPLIANT TO JEDEC STANDARDS MS-026-BBD

1.60 MAX

16

VIEW A

1

17

LEAD PITCH

PIN 1

0.40

BSC

Figure 59. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-1)

Dimensions shown in millimeters

49

48

0.60 MAX

9.00

BSC SQ

TOP VIEW

(PINS DOWN)

0.23

0.18

0.13

0.30

0.25

0.18

4964

48

7.00

BSC S

33

32

PIN 1

64

1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING PLANE

TOP

VIEW

0.80 MAX

0.65 TYP

0.50 BSC

*

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD EXCEPT FOR EXPOSED PAD DIMENSION

8.75

BSC SQ

0.20 REF

0.45

0.40

0.35

0.05 MAX

0.02 NOM

33

32

Figure 60. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-1)

Dimensions shown in millimeters

EXPOSED PAD

(BOTTOM VIEW)

7.50 REF

*

4.85

4.70 SQ

4.55

16

17

Rev. B | Page 45 of 48

AD9238

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9238BST-20 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9238BSTRL-20 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9238BSTZ-201 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9238BSTZRL-201 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9238BSTZ-20EB1 Evaluation Board with AD9238BSTZ-20 AD9238BST-40 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9238BSTRL-40 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9238BSTZ-401 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9238BSTZRL-401 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9238BSTZ-40EB1 Evaluation Board with AD9238BSTZ-40 AD9238BST-65 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9238BSTRL-65 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9238BSTZ-651 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9238BSTZRL-651 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9238BSTZ-65EB1 Evaluation Board with AD9238BSTZ-65 AD9238BCPZ-201 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD9238BCPZRL-201 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD9238BCPZ-20EB1 Evaluation Board with AD9238BCPZ-20 AD9238BCPZ-401 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD9238BCPZRL-401 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD9238BCPZ-40EB1 Evaluation Board with AD9238BCPZ-40 AD9238BCPZ-651 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD9238BCPZRL-651 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD9238BCPZ-65EB1 Evaluation Board with AD9238BCPZ-65

1

Z = Pb-free part.

Rev. B | Page 46 of 48

AD9238

NOTES

Rev. B | Page 47 of 48

AD9238

NOTES

C02640–0–4/05(B)

Rev. B | Page 48 of 48

Analog Devices AD9238 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

EXPLANATION OF TEST LEVELS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

EQUIVALENT CIRCUITS

THEORY OF OPERATION

ANALOG INPUT

Differential Input Configurations

CLOCK INPUT AND CONSIDERATIONS

Single-Ended Input Configuration

POWER DISSIPATION AND STANDBY MODE

DIGITAL OUTPUTS

TIMING

DATA FORMAT

VOLTAGE REFERENCE

Internal Reference Connection

External Reference Operation

AD9238 LQFP EVALUATION BOARD

CLOCK CIRCUITRY

ANALOG INPUTS

REFERENCE CIRCUITRY

DIGITAL CONTROL LOGIC

OUTPUTS

LQFP EVALUATION BOARD BILL OF MATERIALS (BOM)

LQFP EVALUATION BOARD SCHEMATICS

LQFP PCB LAYERS

POWER CONNECTOR

ANALOG INPUTS

OPTIONAL OPERATIONAL AMPLIFIER

CLOCK

VOLTAGE REFERENCE

DATA OUTPUTS

LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM)

LFCSP PCB SCHEMATICS

LFCSP PCB LAYERS

THERMAL CONSIDERATIONS

OUTLINE DIMENSIONS

ORDERING GUIDE