Analog Devices AD9238 Service Manual

12-Bit, 20 MSPS/40 MSPS/65 MSPS

FEATURES

Integrated dual 12-bit ADC
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 70 dB (to Nyquist, AD9238-65)
SFDR = 80.5 dBc (to Nyquist, AD9238-65)
Low power: 300 mW/channel at 65 MSPS
Differential input with 500 MHz, 3 dB bandwidth
Exceptional crosstalk immunity > 85 dB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
Output datamux option

APPLICATIONS

Ultrasound equipment
Direct conversion or IF sampling receivers

WB-CDMA, CDMA2000, WiMAX
Battery-powered instruments
Hand-held scopemeters
Low cost, digital oscilloscopes

GENERAL DESCRIPTION

The AD9238 is a dual, 3 V, 12-bit, 20 MSPS/40 MSPS/65 MSPS
analog-to-digital converter (ADC). It features dual high
performance sample-and-hold amplifiers (SHAs) and an
integrated voltage reference. The AD9238 uses a multistage
differential pipelined architecture with output error correction
logic to provide 12-bit accuracy and to guarantee no missing
codes over the full operating temperature range at up to
65 MSPS data rates. The wide bandwidth, differential SHA
allows for a variety of user-selectable input ranges and offsets,
including single-ended applications. It is suitable for various
applications, including multiplexed systems that switch full­scale voltage levels in successive channels and for sampling
inputs at frequencies well beyond the Nyquist rate.

Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available and can
compensate for wide variations in the clock duty cycle, allowing
the converter to maintain excellent performance. The digital
output data is presented in either straight binary or twos
complement format. Out-of-range signals indicate an overflow
condition, which can be used with the most significant bit to
determine low or high overflow.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

Dual A/D Converter

AD9238

FUNCTIONAL BLOCK DIAGRAM

AVDD

AGND

VIN+_A
VIN–_A

REFT_A

REFB_A

VREF

SENSE

AGND

REFT_B

REFB_B

VIN+_B
VIN–_B

SHA

0.5V

SHA

AD9238

ADC

ADC

DRVDD

Figure 1.

12

OUTPUT

BUFFERS

CLOCK

DUTY CYCLE

STABILIZER

CONTROL

12

OUTPUT

BUFFERS

DRGND

Fabricated on an advanced CMOS process, the AD9238 is
available in a Pb-free, space saving, 64-lead LQFP or LFCSP and
is specified over the industrial temperature range (−40°C to
+85°C).

PRODUCT HIGHLIGHTS

1. Pin-compatible with the AD9248, 14-bit 20MSPS/

40 MSPS/65 MSPS ADC.

2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS

allow flexibility between power, cost, and performance to suit
an application.

3. Low power consumption:

• AD9238-65: 65 MSPS = 600 mW

• AD9238-40: 40 MSPS = 330 mW

• AD9238-20: 20 MSPS = 180 mW

4. Typical channel isolation of 85 dB @ f

5. The clock duty cycle stabilizer (AD9238-20/AD9238-40/

AD9238-65) maintains performance over a wide range of
clock duty cycles.

6. Multiplexed data output option enables single-port operation

from either Data Port A or Data Port B.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] ©2005 Analog Devices, Inc. All rights reserved.

www.analog.com

MUX/

MODE

MUX/

= 10 MHz.

IN

12

12

OTR_A
D11_A TO D0_A

OEB_A

MUX_SELECT
CLK_A
CLK_B
DCS

SHARED_REF
PWDN_A
PWDN_B
DFS

OTR_B
D11_B TO D0_B

OEB_B

02640-001

AD9238

TABLE OF CONTENTS

Specifications..................................................................................... 4

Clock Circuitry ........................................................................... 21

DC Specifications ......................................................................... 4

AC Specifications.......................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications.............................................................. 6

Absolute Maximum Ratings............................................................ 7

Explanation of Test Levels ........................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Terminology .................................................................................... 10

Typical Performance Characteristics ........................................... 11

Equivalent Circuits......................................................................... 15

Theory of Operation ...................................................................... 16

Analog Input............................................................................... 16

Clock Input and Considerations .............................................. 17

Power Dissipation and Standby Mode..................................... 18

Analog Inputs ............................................................................. 21

Reference Circuitry .................................................................... 21

Digital Control logic .................................................................. 21

Outputs........................................................................................ 21

LQFP Evaluation Board Bill of Materials (BOM) .................. 23

LQFP Evaluation Board Schematics........................................ 24

LQFP PCB Layers....................................................................... 28

Dual ADC LFCSP PCB.................................................................. 34

Power Connector........................................................................ 34

Analog Inputs ............................................................................. 34

Optional Operational Amplifier .............................................. 34

Clock ............................................................................................ 34

Voltage Reference ....................................................................... 34

Data Outputs............................................................................... 34

LFCSP Evaluation Board Bill of Materials (BOM) ................ 35

Digital Outputs ........................................................................... 18

Timing.......................................................................................... 18

Data Format ................................................................................19

Voltage Reference....................................................................... 19

AD9238 LQFP Evaluation Board ................................................. 21

REVISION HISTORY

4/05—Rev. A to Rev. B

Changes to Format and Layout........................................ Universal

Added LFCSP..................................................................... Universal

Changes to Features and Applications...........................................1

Changes to General Description and Product Highlights ..........1

Changes to Figure 1..........................................................................1

Changes to Table 1............................................................................3

Changes to Table 2............................................................................5

Added Digital Specifications...........................................................6

Moved Switching Specifications to.................................................6

LFCSP PCB Schematics............................................................. 36

LFCSP PCB Layers..................................................................... 39

Thermal Considerations............................................................ 44

Outline Dimensions....................................................................... 45

Ordering Guide .......................................................................... 46

Changes to Pin Function Descriptions..........................................8

Changes to Terminology Section .................................................10

Changes to Figure 29......................................................................15

Changes to Clock Input and Considerations Section................17

Changes to Figure 33......................................................................18

Changes to Data Format Section..................................................19

Added AD9238 LQFP Evaluation Board Section ......................21

Added Dual ADC LFCSP PCB Section.......................................34

Added Thermal Considerations Section.....................................44

Updated Outline Dimensions.......................................................45

Changes to Ordering Guide.......................................................... 46

Rev. B | Page 2 of 48

AD9238

9/03—Rev. 0 to Rev. A

Changes to DC Specifications ........................................................2

Changes to Switching Specifications .............................................3

Changes to AC Specifications......................................................... 4

Changes to Figure 1..........................................................................4

Changes to Ordering Guide............................................................ 5

Changes to TPCs 2, 3, and 6 ........................................................... 8

Changes to Clock Input and Considerations Section................ 13

Added Text to Data Format Section ............................................15

Changes to Figure 9........................................................................16

Added Evaluation Board Diagrams Section............................... 17

Update Outline Dimensions ......................................................... 24

2/03—Revision 0: Initial Version

Rev. B | Page 3 of 48

AD9238

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 1.

Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full VI 12 12 12 Bits
ACCURACY

No Missing Codes Guaranteed Full VI 12 12 12 Bits
Offset Error Full VI ±0.30 ±1.2 ±0.50 ±1.1 ±0.50 ±1.1 % FSR
Gain Error1 Full IV ±0.30 ±2.2 ±0.50 ±2.4 ±0.50 ±2.5 % FSR
Differential Nonlinearity (DNL)2 Full V ±0.35 ±0.35 ±0.35 LSB
25°C I ±0.35 ±0.9 ±0.35 ±0.8 ±0.35 ±1.0 LSB
Integral Nonlinearity (INL)2 Full V ±0.45 ±0.60 ±0.70 LSB

25°C I ±0.40 ±1.4 ±0.50 ±1.4 ±0.55 ±1.75 LSB
TEMPERATURE DRIFT

Offset Error Full V ±4 ±4 ±6 µV/°C
Gain Error Full V ±12 ±12 ±12 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) Full VI ±5 ±35 ±5 ±35 ±5 ±35 mV
Load Regulation @ 1.0 mA Full V 0.8 0.8 0.8 mV
Output Voltage Error (0.5 V Mode) Full V ±2.5 ±2.5 ±2.5 mV
Load Regulation @ 0.5 mA Full V 0.1 0.1 0.1 mV

INPUT REFERRED NOISE

Input Span = 1 V 25°C V 0.54 0.54 0.54 LSB
Input Span = 2.0 V 25°C V 0.27 0.27 0.27 LSB

ANALOG INPUT

Input Span = 1.0 V Full IV 1 1 1 V p-p
Input Span = 2.0 V Full IV 2 2 2 V p-p
Input Capacitance3 Full V 7 7 7 pF

REFERENCE INPUT RESISTANCE Full V 7 7 7 kΩ
POWER SUPPLIES

Supply Voltages

Supply Current

PSRR Full V ±0.01 ±0.01 ±0.01 % FSR

POWER CONSUMPTION

DC Input4 Full V 180 330 600 mW
Sine Wave Input2 Full VI 190 212 360 397 640 698 mW
Standby Power5 Full V 2.0 2.0 2.0 mW

MATCHING CHARACTERISTICS

Offset Error 25°C V ±0.1 ±0.1 ±0.1 % FSR
Gain Error 25°C V ±0.05 ±0.05 ±0.05 % FSR

1

Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).

2

Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.

3

Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure for the equivalent analog input structure. 28

4

Measured with dc input at maximum clock rate.

5

Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).

, DCS enabled, unless otherwise noted.

MAX

Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65

rms

rms

AVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V
DRVDD Full IV 2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 V

IAVDD2 Full V 60 110 200 mA
IDRVDD2 Full V 4 10 14 mA

Rev. B | Page 4 of 48

AD9238

AC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 2.

Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)

f

INPUT

f

INPUT

25°C IV 69.7 70.4 dB
f

INPUT

25°C IV 69.7 70.3 dB
f

INPUT

25°C IV 68.7 70.0 dB
f

INPUT

SIGNAL-TO-NOISE AND DISTORTION

RATIO (SINAD)
f

INPUT

f

INPUT

25°C IV 69.3 70.2 dB
f

INPUT

25°C IV 69.4 70.1 dB
f

INPUT

25°C IV 68.1 69.1 dB
f

INPUT

EFFECTIVE NUMBER OF BITS (ENOB)

f

INPUT

f

INPUT

25°C IV 11.3 11.5 Bits
f

INPUT

25°C IV 11.3 11.4 Bits
f

INPUT

25°C IV 11.1 11.3 Bits
f

INPUT

WORST HARMONIC (SECOND or THIRD)

f

INPUT

f

INPUT

f

INPUT

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f

INPUT

f

INPUT

25°C I 76.1 86.0 dBc
f

INPUT

25°C I 76.7 86.0 dBc
f

INPUT

25°C I 72.5 80.5 dBc
f

INPUT

CROSSTALK Full V −85.0 −85.0 −85.0 dB

, DCS enabled, unless otherwise noted.

MAX

Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65

= 2.4 MHz 25°C V 70.4 70.4 70.3 dB
= 9.7 MHz Full V 70.2 dB

= 19.6 MHz Full V 70.1 dB

= 32.5 MHz Full V 69.3 dB

= 100 MHz 25°C V 68.7 68.3 67.6 dB

= 2.4 MHz 25°C V 70.2 70.2 70.1 dB
= 9.7 MHz Full V 70.1 dB

= 19.6 MHz Full V 69.9 dB

= 32.5 MHz Full V 68.9 dB

= 100 MHz 25°C V 67.9 67.9 66.6 dB

= 2.4 MHz 25°C V 11.5 11.5 11.4 Bits
= 9.7 MHz Full V 11.4 Bits

= 19.6 MHz Full V 11.4 Bits

= 32.5 MHz Full V 11.2 Bits

= 100 MHz 25°C V 11.1 11.1 10.9 Bits

= 9.7 MHz Full V −84.0 dBc
= 19.6 MHz Full V −85.0 dBc
= 35 MHz Full V −80.0 dBc

= 2.4 MHz 25°C V 86.0 86.0 86.0 dBc
= 9.7 MHz Full V 84.0 dBc

= 19.6 MHz Full V 85.0 dBc

= 32.5 MHz Full V 80.0 dBc

= 100 MHz 25°C V 75.0 dBc

Rev. B | Page 5 of 48

AD9238

DIGITAL SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 3.

Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
LOGIC INPUTS

High Level Input Voltage Full IV 2.0 2.0 2.0 V
Low Level Input Voltage Full IV 0.8 0.8 0.8 V
High Level Input Current Full IV −10 +10 −10 +10 −10 +10 µA
Low Level Input Current Full IV −10 +10 −10 +10 −10 +10 µA
Input Capacitance Full IV 2 2 2 pF

LOGIC OUTPUTS1

High Level Output Voltage Full IV

Low Level Output Voltage Full IV 0.05 0.05 0.05 V

1

Output voltage levels measured with capacitive load only on each output.

SWITCHING SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 4.

Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
SWITCHING PERFORMANCE

Maximum Conversion Rate Full VI 20 40 65 MSPS
Minimum Conversion Rate Full V 1 1 1 MSPS
CLK Period Full V 50.0 25.0 15.4 ns
CLK Pulse-Width High1 Full V 15.0 8.8 6.2 ns
CLK Pulse-Width Low1 Full V 15.0 8.8 6.2 ns

DATA OUTPUT PARAMETER

Output Delay2 (tPD) Full VI 2 3.5 6 2 3.5 6 2 3.5 6 ns
Pipeline Delay (Latency) Full V 7 7 7 Cycles
Aperture Delay (tA) Full V 1.0 1.0 1.0 ns
Aperture Uncertainty (tJ) Full V 0.5 0.5 0.5 pS rms
Wake-Up Time3 Full V 2.5 2.5 2.5 ms

OUT-OF-RANGE RECOVERY TIME Full V 2 2 2 Cycles

1

The AD9238-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 23).

2

Output delay is measured from clock 50% transition to data 50% transition, with a 5 pF load on each output.

3

Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.

, DCS enabled, unless otherwise noted.

MAX

, DCS enabled, unless otherwise noted.

MAX

N

ANALOG

INPUT

N–1

Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65

DRVDD −

0.05

DRVDD −

0.05

DRVDD −

0.05

V

Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65

N+1

N+2

N+3

N+4

N+5

N+6

N+7

N+8

CLOCK

DATA

OUT

N–9 N–8

N–7

N–6

N–5

N–4

N–3

N–2

N–1

N

t

PD

MIN 2.0ns,

=

MAX 6.0ns

02640-002

Figure 2. Timing Diagram

Rev. B | Page 6 of 48

AD9238

ABSOLUTE MAXIMUM RATINGS1

Table 5.

Parameter Rating
Pin Name With Respect To Min Max Unit

ELECTRICAL

AVDD AGND −0.3 +3.9 V
DRVDD DRGND −0.3 +3.9 V
AGND DRGND −0.3 +0.3 V
AVDD DRVDD −3.9 +3.9 V
Digital Outputs CLK, DCS, MUX_SELECT, SHARED_REF DRGND −0.3 DRVDD + 0.3 V
OEB, DFS AGND −0.3 AVDD + 0.3 V
VINA, VINB AGND −0.3 AVDD + 0.3 V
VREF AGND −0.3 AVDD + 0.3 V
SENSE AGND −0.3 AVDD + 0.3 V
REFB, REFT AGND −0.3 AVDD + 0.3 V
PDWN AGND −0.3 AVDD + 0.3 V

ENVIRONMENTAL2

Operating Temperature −45 +85 °C
Junction Temperature 150 °C
Lead Temperature (10 sec) 300 °C
Storage Temperature −65 +150 °C

1

Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is

not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.

2

Typical thermal impedances: 64-lead LQFP, θJA = 54°C/W; 64-lead LFCSP, θJA = 26.4°C/W with heat slug soldered to ground plane. These measurements were taken on a

4-layer board in still air, in accordance with EIA/JESD51-7.

EXPLANATION OF TEST LEVELS

I 100% production tested.
II 100% production tested at 25°C and sample tested at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI

100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production
tested at temperature extremes for military devices.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 7 of 48

AD9238

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK_A

AGND
VIN+_A
VIN–_A

AGND

AVDD

REFT_A

REFB_A

VREF

SENSE

REFB_B

REFT_B

AVDD

AGND
VIN–_B

VIN+_B

AGND

AVDD

SHARED_REF

64 63 62 61 60 55 54 53 52 51 50 4959 58 57 56

1

PIN 1

2

IDENTIFIER

3
4
5
6
7
8

9
10
11
12
13
14
15
16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

MUX_SELECT

OTR_A

OEB_A

PDWN_A

AD9238

64-LEAD LQFP

TOP VIEW

(Not to Scale)

D9_A

D8_A

D11_A (MSB)

D10_A

DRVDD

DRGND

D7_A

D6_A

D5_A

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

D4_A
D3_A

D2_A
D1_A
D0_A (LSB)
DNC
DNC
DRVDD
DRGND
OTR_B
D11_B (MSB)
D10_B
D9_B

D8_B
D7_B
D6_B

DFS

DCS

AVDD

CLK_B

PDWN_B

OEB_B

DNC = DO NOT CONNECT

Figure 3. 64-Lead LQFP and LFCSP Pin Configuration

DNC

DNC

D1_B

D2_B

D0_B (LSB)

DRVDD

DRGND

D3_B

D4_B

D5_B

02640-003

Rev. B | Page 8 of 48

AD9238

Table 6. Pin Function Descriptions (64-Lead LQFP and 64-Lead LFCSP)

Pin No. Mnemonic Description

1, 4, 13, 16 AGND Analog Ground.
2 VIN+_A Analog Input Pin (+) for Channel A.
3 VIN–_A Analog Input Pin (−) for Channel A.
5, 12, 17, 64 AVDD Analog Power Supply.
6 REFT_A Differential Reference (+) for Channel A.
7 REFB_A Differential Reference (−) for Channel A.
8 VREF Voltage Reference Input/Output.
9 SENSE Reference Mode Selection.
10 REFB_B Differential Reference (−) for Channel B.
11 REFT_B Differential Reference (+) for Channel B.
14 VIN−_B Analog Input Pin (−) for Channel B.
15 VIN+_B Analog Input Pin (+) for Channel B.
18 CLK_B Clock Input Pin for Channel B.
19 DCS Enable Duty Cycle Stabilizer (DCS) Mode (Tie High to Enable).
20 DFS Data Output Format Select Bit (Low for Offset Binary, High for Twos Complement).
21 PDWN_B Power-Down Function Selection for Channel B:

Logic 0 enables Channel B.

Logic 1 powers down Channel B. (Outputs static, not High-Z.)

22 OEB_B Output Enable Bit for Channel B:

Logic 0 enables Data Bus B.

Logic 1 sets outputs to High-Z.
23, 24, 42, 43 DNC Do Not Connect Pins. Should be left floating.
25 to 27,

30 to 38
28, 40, 53 DRGND Digital Output Ground.
29, 41, 52 DRVDD

39 OTR_B Out-of-Range Indicator for Channel B.
44 to 51,

54 to 57
58 OTR_A Out-of-Range Indicator for Channel A.
59 OEB_A Output Enable Bit for Channel A:

60 PDWN_A Power-Down Function Selection for Channel A:

61 MUX_SELECT Data Multiplexed Mode.

62 SHARED_REF Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared Reference Mode).
63 CLK_A Clock Input Pin for Channel A.

D0_B (LSB) to
D11_B (MSB)

D0_A (LSB) to
D11_A (MSB)

Channel B Data Output Bits.

Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor.
Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF.

Channel A Data Output Bits.

Logic 0 enables Data Bus A.

Logic 1 sets outputs to High-Z.

Logic 0 enables Channel A.

Logic 1 powers down Channel A. (Outputs static, not High-Z.)

(See Data Format section for how to enable; high setting disables output data multiplexed mode).

Rev. B | Page 9 of 48

AD9238

TERMINOLOGY

Aperture Delay

SHA performance measured from the rising edge of the clock
input to when the input signal is held for conversion.

Aperture Jitter

The variation in aperture delay for successive samples, which is
manifested as noise on the input to the ADC.

Integral Nonlinearity (INL)

Deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.

frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.

Effective Number of Bits (ENOB)

Using the following formula

ENOB = (SINAD − 1.76)/6.02

ENOB for a device for sine wave inputs at a given input
frequency can be calculated directly from its measured SINAD.

Signal-to-Noise Ratio (SNR)

The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in dB.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4,096
codes must be present over all operating ranges.

Offset Error

The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.

Gain Error

The first code transition should occur at an analog value ½ LSB
above negative full scale. The last transition should occur at an
analog value 1½ LSB below the nominal full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.

Temp er at u re D ri ft

The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at

or T

T

MIN

MAX

.

Power Supply Rejection
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.

Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal, expressed as a
percentage or in decibels relative to the peak carrier signal (dBc).

Signal-to-Noise and Distortion (SINAD) Ratio

The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist

Spurious-Free Dynamic Range (SFDR)
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal, which may or may not be a
harmonic.

Nyquist Sampling
When the frequency components of the analog input are below
the Nyquist frequency (f

/2), this is often referred to as

CLOCK

Nyquist sampling.

IF Sampling
Due to the effects of aliasing, an ADC is not limited to Nyquist
sampling. Higher sampled frequencies are aliased down into the
first Nyquist zone (DC − f

/2) on the output of the ADC.

CLOCK

The bandwidth of the sampled signal should not overlap
Nyquist zones and alias onto itself. Nyquist sampling
performance is limited by the bandwidth of the input SHA and
clock jitter (jitter adds more noise at higher input frequencies).

Two -Tone SFDR

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input
after a transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.

Crosstalk

Coupling onto one channel being driven by a (−0.5 dBFS) signal
when the adjacent interfering channel is driven by a full-scale
signal. Measurement includes all spurs resulting from both
direct coupling and mixing components.

Rev. B | Page 10 of 48

AD9238

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD, DRVDD = 3.0 V, T = 25°C, AIN differential drive, full scale = 2 V, unless otherwise noted.

0

–20

–40

MAGNITUDE (dBFS)

–60

–80

–100

–120

CROSSTALK

10 15 20 25 30

50

FREQUENCY (MHz)

SECOND
HARMONIC

Figure 4. Single-Tone FFT of Channel A Digitizing f

While Channel B Is Digitizing f

0

–20

–40

dB

–60

–80

–100

–120

SECOND
HARMONIC

10

CROSSTALK

15 20 25 3050

FREQUENCY (MHz)

Figure 5. Single-Tone FFT of Channel A Digitizing f

While Channel B Is Digitizing f

0

–20

–40

dB

CROSSTALK

–60

–80

–100

–120

SECOND
HARMONIC

15 20 25 3050

10

FREQUENCY (MHz)

Figure 6. Single-Tone FFT of Channel A Digitizing f

While Channel B is Digitizing f

IN

THIRD
HARMONIC

= 10 MHz

IN

= 76 MHz

IN

= 126 MHz

= 12.5 MHz

IN

= 70 MHz

IN

= 120 MHz

IN

02640-004

02640-005

02640-006

100

95

90

85

80

75

70

SFDR/SNR (dBc)

65

60
55
50

40

45 50 55 60 65

ADC SAMPLE RATE (MSPS)

SNR

SFDR

Figure 7. AD9238-65 Single-Tone SNR/SFDR vs. FS with f

100

95

90

85

80

75

70

SFDR/SNR (dBc)

65

60
55
50

ADC SAMPLE RATE (MSPS)

SFDR

SNR

SNR

SNR

35302520

Figure 8. AD9238-40 Single-Tone SNR/SFDR vs. FS with f

100

95

90

85

80

75

70

SFDR/SNR (dBc)

65

60
55
50

0

5101520

ADC SAMPLE RATE (MSPS)

SFDR

SNR

Figure 9. AD9238-20 Single-Tone SNR/SFDR vs. FS with f

= 32.5 MHz

IN

40

= 20 MHz

IN

= 10 MHz

IN

02640-007

02640-008

02640-009

Rev. B | Page 11 of 48

AD9238

100

95

90

80

70

SFDR/SNR (dBc)

60

50

40

–30 –25 –20 –15 –10 –5

–35

INPUT AMPLITUDE (dBFS)

SFDR

SNR

SNR

SNR

Figure 10. AD9238-65 Single-Tone SNR/SFDR vs. AIN with f

100

90

80

70

SFDR/SNR (dBc)

60

SNR

SFDR

SNR

SNR

0

= 32.5 MHz

IN

02640-010

90

85

80

SFDR/SNR (dBc)

75

70

65

20 40 60 80 100 120

0

Figure 13. AD9238-65 Single-Tone SNR/SFDR vs. f

SNR

SFDR

SNR

INPUT FREQUENCY (MHz)

02640-013

140

IN

95

90

85

80

SFDR/SNR (dBc)

75

SNR

SFDR

50

40

–30 –25 –20 –15 –10 –5

–35

INPUT AMPLITUDE (dBFS)

Figure 11. AD9238-40 Single-Tone SNR/SFDR vs. AIN with f

100

90

SNR

SFDR

80

70

SNR

SFDR/SNR (dBc)

60

50

40

–30 –25 –20 –15 –10 –5

–35

INPUT AMPLITUDE (dBFS)

SNR

Figure 12. AD9238-20 Single-Tone SNR/SFDR vs. AIN with f

0

= 20 MHz

IN

0

= 10 MHz

IN

02640-011

02640-012

SNR

70

65

20 40 60 80 100 120

0

Figure 14. AD9238-40 Single-Tone SNR/SFDR vs. f

SNR

INPUT FREQUENCY (MHz)

02640-014

140

IN

95

90

SFDR

85

80

SFDR/SNR (dBc)

75

70

65

20 40 60 80 100 120

0

Figure 15. AD9238-20 Single-Tone SNR/SFDR vs. f

SNR

SNR

SNR

INPUT FREQUENCY (MHz)

02640-015

140

IN

Rev. B | Page 12 of 48

AD9238

0

–20

–40

100

SNR

95

90

85

SFDR

–60

–80

MAGNITUDE (dBFS)

–100

–120

10

Figure 16. Dual-Tone FFT with f

0

–20

–40

–60

–80

MAGNITUDE (dBFS)

–100

–120

10 15 20 25 3050

Figure 17. Dual-Tone FFT with f

0

15 20 25 3050

FREQUENCY (MHz)

1 = 45 MHz and fIN2 = 46 MHz

IN

FREQUENCY (MHz)

1 = 70 MHz and fIN2 = 71 MHz

IN

02640-016

02640-017

80

75

SFDR/SNR (dBFS)

70

65

60

–24

SNR

SNR

–21 –18 –15 –12 –9 –6

INPUT AMPLITUDE (dBFS)

Figure 19. Dual-Tone SNR/SFDR vs. AIN with f

100

SNR

95

90

85

80

75

SFDR/SNR (dBFS)

70

65

60

–24

SFDR

SNR

SNR

–21 –18 –15 –12 –9 –6

INPUT AMPLITUDE (dBFS)

Figure 20. Dual-Tone SNR/SFDR vs. AIN with f

100

1 = 45 MHz and fIN2 = 46 MHz

IN

1 = 70 MHz and fIN2 = 71 MHz

IN

02640-019

02640-020

–20

–40

–60

–80

MAGNITUDE (dBFS)

–100

–120

10 15 20 25 3050

Figure 18. Dual-Tone FFT with f

FREQUENCY (MHz)

1 = 200 MHz and fIN2 = 201 MHz

IN

02640-018

Rev. B | Page 13 of 48

95

90

85

80

75

SFDR/SNR (dBFS)

70

65

60

–24

SNR

SFDR

SNR

–21 –18 –15 –12 –9 –6

INPUT AMPLITUDE (dBFS)

02640-021

Figure 21. Dual-Tone SNR/SFDR vs.

AIN with f

1 = 200 MHz and fIN2 = 201 MHz

IN

AD9238

74

12.0

600

–65

72

SINAD (dBc)

SINAD –20

70

SINAD –40

68

0

20 40 60

CLOCK FREQUENCY

Figure 22. SINAD vs. FS with Nyquist Input

95

90

85

80

75

70

65

SINAD/SFDR (dBc)

60

55

50

30

DCS OFF (SFDR)

35

40 45 50 55 60 65

DCS ON (SFDR)

DUTY CYCLE (%)

Figure 23. SINAD/SFDR vs. Clock Duty Cycle

84

82

80

78

76

74

72

SINAD/SFDR (dB)

70

68

66

–50

SFDR

SINAD

0 50 100

TEMPERATURE (°C)

Figure 24. SINAD/SFDR vs. Temperature with f

DCS ON (SINAD)

DCS OFF (SINAD)

IN

SINAD –65

= 32.5 MHz

11.5

11.0

02640-022

02640-023

02640-024

500

400

300

AVDD POWER (mW)

200

100

0102030405060

–40

–20

SAMPLE RATE (MSPS)

02640-025

Figure 25. Analog Power Consumption vs. FS

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2
–0.4

–0.6
–0.8
–1.0

150010005000 2000 2500 3000 3500 4000

CODE

02640-026

Figure 26. AD9238-65 Typical INL

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2
–0.4

–0.6
–0.8
–1.0

150010005000 2000 2500 3000 3500 4000

CODE

02640-027

Figure 27. AD9238-65 Typical DNL

Rev. B | Page 14 of 48

AD9238

V

V

EQUIVALENT CIRCUITS

AVDD

Figure 30. Equivalent Digital Input Circuit

IN+_A, VIN–_A,
IN+_B, VIN–_B

AVDD

Figure 28. Equivalent Analog Input Circuit

02640-062

CLK_A, CLK_B

DCS, DFS,

MUX_SELECT,

SHARED_REF

02640-064

DRVDD

02640-063

Figure 29. Equivalent Digital Output Circuit

Rev. B | Page 15 of 48