Analog Devices AD9236 Service Manual

12-Bit, 80 MSPS, 3 V A/D Converter

FEATURES

Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 70.4 dBc to Nyquist
SFDR = 87.8 dBc to Nyquist
Low power: 366 mW
Differential input with 500 MHz bandwidth
On-chip reference and sample-and-hold
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer

APPLICATIONS

High end medical imaging equipment
IF sampling in communications receivers

WCDMA, CDMA-One, CDMA-2000
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
DTV subsystems

GENERAL DESCRIPTION

The AD9236 is a monolithic, single 3 V supply, 12-bit, 80 MSPS
analog-to-digital converter featuring a high performance sample­and-hold amplifier (SHA) and voltage reference. The AD9236
uses a multistage differential pipelined architecture with output
error correction logic to provide 12-bit accuracy at 80 MSPS
and guarantee no missing codes over the full operating
temperature range.

The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and common modes, including
single-ended applications. It is suitable for multiplexed systems
that switch full-scale voltage levels in successive channels and
for sampling single-channel inputs at frequencies well beyond
the Nyquist rate. Combined with power and cost savings over
previously available analog-to-digital converters, the AD9236 is
suitable for applications in communications, imaging, and
medical ultrasound.

A single-ended clock input is used to control all internal
conversion cycles. A duty cycle stabilizer (DCS) compensates
for wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is

AD9236

FUNCTIONAL BLOCK DIAGRAM

DRVDDAVDD

AD9236

VIN+
VIN–

REFT
REFB

VREF

SENSE

SHA

REF

SELECT

A/D

AGND

MDAC1

4

0.5V

presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow. Fabricated on an advanced CMOS process, the
AD9236 is available in a 28-lead TSSOP and a 32-lead LFCSP
and is specified over the industrial temperature range
(−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. The AD9236 operates from a single 3 V power supply and

features a separate digital output driver supply to
accommodate 2.5 V and 3.3 V logic families.

2. Operating at 80 MSPS, the AD9236 consumes a low 366 mW.

3. The patented SHA input maintains excellent performance for

input frequencies up to 100 MHz, and can be configured for
single-ended or differential operation.

4. The AD9236 is pin compatible with the AD9215, AD9235,

and AD9245. This allows a simplified migration from 10 bits
to 14 bits and 20 MSPS to 80 MSPS.

5. The DCS maintains overall ADC performance over a wide

range of clock pulse widths.

6. The OTR output bit indicates when the signal is beyond the

selected input range.

8-STAGE

1 1/2-BIT PIPELINE

16

CORRECTION LOGIC

12

OUTPUT BUFFERS

CLOCK

DUTY CYCLE

STABILIZER

CLK PDWN MODE DGND

Figure 1.

MODE

SELECT

A/D

3

OTR

D11 (MSB)
D0 (LSB)

03066-0-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2006 Analog Devices, Inc. All rights reserved.

AD9236

TABLE OF CONTENTS

Features .............................................................................................. 1

Equivalent Circuits......................................................................... 10

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights........................................................................... 1

Revision History ............................................................................... 2

DC Specifications ............................................................................. 3

AC Specifications.............................................................................. 4

Digital Specifications........................................................................ 5

Switching Specifications .................................................................. 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Te r mi n ol o g y ...................................................................................... 8

Pin Configurations and Function Descriptions ........................... 9

Typical Perf or m an c e Charac t e r istics ........................................... 11

Theory of Operation ...................................................................... 14

Analog Input and Reference Overview ................................... 14

Clock Input Considerations...................................................... 15

Power Dissipation and Standby Mode .................................... 16

Digital Outputs........................................................................... 16

Timing ......................................................................................... 17

Volt a ge R e fer e nce ....................................................................... 17

Operational Mode Selection ..................................................... 18

Evaluation Board ........................................................................ 18

Outline Dimensions ....................................................................... 33

Ordering Guide .......................................................................... 34

REVISION HISTORY

1/06—Rev. A to Rev. B

Changes to Figure 29...................................................................... 15

Changes to Equation in Jitter Considerations Section ..............16

Changes to Internal Reference Connection Section, Figure 34,

and Table 10..................................................................................... 17

Changes to Figure 35...................................................................... 18

Changes to Figure 38...................................................................... 20

Changes to Figure 39...................................................................... 21

Changes to Figure 48...................................................................... 27

Changes to Figure 49...................................................................... 28

Changes to Figure 50...................................................................... 29

Changes to Table 12........................................................................ 32

Updated Outline Dimensions....................................................... 33

Changes to Ordering Guide.......................................................... 34

10/03—Rev. 0 to Rev. A

Changes to Figure 30...................................................................... 15

Changes to Figure 33 ..................................................................... 17

Changes to Figure 40...................................................................... 22

Changes to Figure 49...................................................................... 28

Changes to Figure 50...................................................................... 29

Changes to Table 11 ....................................................................... 32

Changes to Ordering Guide ......................................................... 33

Rev. B | Page 2 of 36

AD9236

DC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, unless otherwise noted.

Table 1.

AD9236BRU/AD9236BCP

Parameter Temp Test Level

Min Typ Max

RESOLUTION Full VI 12 Bits
ACCURACY

No Missing Codes Full VI Guaranteed
Offset Error

1

Full VI ±0.30 ±1.30 % FSR
Gain Error 25°C V ±0.10 % FSR
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)

1

2

2

Full VI ±0.30 ±4.34 % FSR

Full VI ±0.40 ±0.65 LSB

Full VI ±0.35 ±1.20 LSB

TEMPERATURE DRIFT

Offset Error

1

Full V ±6 ppm/°C
Gain Error Full V ±12 ppm/°C
Gain Error

1

Full V ±18 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V) Full VI ±2 ±35 mV
Load Regulation @ 1.0 mA 25°C V 0.8 mV
Output Voltage Error (0.5 V) 25°C V ±1 mV
Load Regulation @ 0.5 mA 25°C V 0.1 mV

INPUT REFERRED NOISE

VREF = 0.5 V 25°C V 0.55 LSB rms
VREF = 1.0 V 25°C V 0.28 LSB rms

ANALOG INPUT

Input Span, VREF = 0.5 V Full IV 1 V p-p
Input Span, VREF = 1.0 V Full IV 2 V p-p
Input Capacitance

3

Full V 7 pF

REFERENCE INPUT RESISTANCE Full V 7 kΩ
POWER SUPPLIES

Supply Voltage

AVDD Full IV 2.7 3.0 3.6 V
DRVDD Full IV 2.25 2.5 3.6 V

Supply Current

4

IAVDD
IDRVDD

4

Full VI 122 137 mA

25°C V 8 mA
PSRR 25°C V ±0.01 % FSR

POWER CONSUMPTION

Low Frequency Input
Standby Power

1

With a 1.0 V internal reference.

2

Measured at low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

3

Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure.

4

Measured at AC Specifications conditions without output drivers.

5

Measured with a dc input, CLK pin inactive (that is, set to AVDD or AGND).

4

5

25°C V 366 mW

25°C V 1.0 mW

Unit

Rev. B | Page 3 of 36

AD9236

AC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, AIN = –0.5 dBFS, DCS off,
unless otherwise noted.

Table 2.

AD9236BRU/AD9236BCP

Parameter Temp Test Level

SIGNAL-TO-NOISE-RATIO (SNR)

fIN = 2.4 MHz Full VI 68.6 dB

25°C V 70.9 dB

fIN = 40 MHz 25°C V 70.4 dB
fIN = 70 MHz Full IV 67.8 dB

25°C V 70.1 dB

fIN = 100 MHz 25°C V 69.0 dB

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 2.4 MHz Full VI 68.4 dB

25°C V 70.8 dB

fIN = 40 MHz 25°C V 70.2 dB
fIN = 70 MHz Full IV 67.4 dB

25°C V 69.8 dB

fIN = 100 MHz 25°C V 68.0 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.4 MHz Full VI 11.1 Bits

25°C V 11.5 Bits

fIN = 40 MHz 25°C V 11.4 Bits
fIN = 70 MHz Full IV 10.9 Bits

25°C V 11.3 Bits

fIN = 100 MHz 25°C V 11.0 Bits

WORST SECOND OR THIRD

fIN = 2.4 MHz Full VI –75.6 dBc
25°C V –91.3 dBc
fIN = 40 MHz 25°C V –87.8 dBc
fIN = 70 MHz Full VI –73.2 dBc
25°C V –81.4 dBc
fIN = 100 MHz 25°C V –76.4 dBc

SPURIOUS FREE DYNAMIC RANGE (SFDR)

fIN = 2.4 MHz Full VI 75.6 dBc

25°C V 91.3 dBc

fIN = 40 MHz 25°C V 87.8 dBc
fIN = 70 MHz Full IV 73.2 dBc

25°C V 81.4 dBc

fIN = 100 MHz 25°C V 76.4 dBc

Min Typ Max

Unit

Rev. B | Page 4 of 36

AD9236

DIGITAL SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, 1.0 V external reference, unless otherwise noted.

Table 3.

AD9236BRU/AD9236BCP

Parameter Temp Test Level

LOGIC INPUTS (CLK, PDWN)

High Level Input Voltage Full IV 2.0 V
Low Level Input Voltage Full IV 0.8 V
High Level Input Current Full IV –10 +10 μA
Low Level Input Current Full IV –10 +10 μA
Input Capacitance Full V 2 pF

DIGITAL OUTPUTS (D0–D11, OTR)

DRVDD = 3.3 V

High Level Output Voltage (IOH = 50 μA) Full IV 3.29 V
High Level Output Voltage (IOH = 0.5 mA) Full IV 3.25 V
Low Level Output Voltage (IOH = 1.6 mA) Full IV 0.2 V
Low Level Output Voltage (IOH = 50 μA) Full IV 0.05 V

DRVDD = 2.5 V

High Level Output Voltage (IOH = 50 μA) Full IV 2.49 V
High Level Output Voltage (IOH = 0.5 mA) Full IV 2.45 V
Low Level Output Voltage (IOH = 1.6 mA) Full IV 0.2 V
Low Level Output Voltage (IOH = 50 μA) Full IV 0.05 V

1

Output voltage levels measured with 5 pF load on each output.

1

Min Typ Max

Unit

Rev. B | Page 5 of 36

AD9236

SWITCHING SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted.

Table 4.

AD9236BRU/AD9236BCP

Parameter Temp Test Level

Min Typ Max

CLOCK INPUT PARAMETERS

Maximum Conversion Rate Full VI 80 MSPS
Minimum Conversion Rate Full V 1 MSPS
CLK Period Full V 12.5 ns
CLK Pulse Width High
CLK Pulse Width Low

1

1

Full V 4.0 ns
Full V 4.0 ns

DATA OUTPUT PARAMETERS

Output Propagation Delay (tPD)

2

Full V 3.5 ns
Pipeline Delay (Latency) Full V 7 Cycles
Aperture Delay (tA) Full V 1.0 ns
Aperture Uncertainty (Jitter, tJ) Full V 0.3 ps rms
Wake-Up Time

3

Full V 7 ms

OUT OF RANGE RECOVERY TIME Full V 2 Cycles

1

With duty cycle stabilizer (DCS) enabled.

2

Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

3

Wake-up time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.

Unit

N+1

ANALOG

INPUT

CLK

DATA

OUT

N

N–1

N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N

t

N+2

A

N+3

Figure 2. Timing Diagram

N+4

N+5

t

= 6.0ns MAX

PD

2.0ns MIN

N+6

N+7

N+8

03066-0-002

Table 5. Explanation of Test Levels

Test Level Definitions

I 100% production tested.
II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.

Rev. B | Page 6 of 36

AD9236

ABSOLUTE MAXIMUM RATINGS

Table 6.

With

Parameter Min Max Unit
ELECTRICAL

AVDD AGND –0.3 +3.9
DRVDD DGND –0.3 +3.9 V
AGND DGND –0.3 +0.3 V
AVDD DRVDD –3.9 +3.9 V
D0 to D11 DGND –0.3 DRVDD + 0.3 V
CLK, MODE AGND –0.3 AVDD + 0.3 V
VIN+, VIN– AGND –0.3 AVDD + 0.3
VREF AGND –0.3 AVDD + 0.3 V
SENSE AGND –0.3 AVDD + 0.3 V
REFT, REFB AGND –0.3 AVDD + 0.3 V
PDWN AGND –0.3 AVDD + 0.3 V

ENVIRONMENTAL

Storage Temperature –65 +125 °C
Operating Temperature Range –40 +85 °C
Lead Temperature

(Soldering 10 sec)

Junction Temperature 150 °C

Respect to

V

V

300 °C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θ

is specified for the worst-case conditions on a 4-layer board

JA

in still air, in accordance with EIA/JESD51-1.

Table 7.

Package Type Unit

RU-28 67.7 °C/W
CP-32-2 32.5 32.71 °C/W

θ

JA JC

Airflow increases heat dissipation effectively, reducing θ
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θ

. It is recommended that the exposed paddle be

JA

soldered to the ground plane for the LFCSP package. There is
an increased reliability of the solder joints, and maximum
thermal capability of the package is achieved with the exposed
paddle soldered to the customer board.

θ

. In

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 7 of 36

AD9236

(

−

TERMINOLOGY

Analog Bandwidth (Full Power Bandwidth)

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

Signal-to-Noise and Distortion (SINAD)

The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.

1

Aperture Delay (t

)

A

The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter, t

)

J

The sample-to-sample variation in aperture delay.

Integral Nonlinearity (INL)

The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes must be present over all operating ranges.

Offset Error

The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN–. Offset error is defined as the deviation
of the actual transition from that point.

Gain Error

The first code transition should occur at an analog value
½ LSB above negative full scale. The last transition should occur
at an analog value 1½ LSB below positive full scale. Gain error
is the deviation of the actual difference between first and last
code transitions and the ideal difference between first and last
code transitions.

Tem p er at u re Dr i ft

The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at T

MIN

or T

MAX

.

Power Supply Rejection Ratio

The change in full scale from the value with the supply at the
minimum limit to the value with the supply at its maximum limit.

Total Harmonic Distortion (THD)

1

The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.

Effective Number of Bits (ENOB)

The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured

SINAD using the following formula

SINAD

=

ENOB

Signal-to-Noise Ratio (SNR)

)

76.1

02.6

1

The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.

Spurious Free Dynamic Range (SFDR)

1

The difference in dB between the rms input signal amplitude
and the peak spurious signal. The peak spurious component
may or may not be a harmonic.

Two -Tone SFDR

1

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.

Clock Pulse Width and Duty Cycle

Pulse width high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.

Minimum Conversion Rate

The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The clock rate at which parametric testing is performed.

Output Propagation Delay (t

)

PD

The delay between the clock rising edge and the time when all
bits are within valid logic levels.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.

1

AC specifications may be reported in dBc (degrades as signal levels are

lowered) or in dBFS (always related back to converter full scale).

Rev. B | Page 8 of 36

AD9236

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

OTR 1

MODE 2

SENSE 3

VREF 4
REFB 5
REFT 6

AVDD 7

AGND 8

VIN+ 9
VIN– 10

AGND 11

AVDD 12

CLK 13

PDWN 14

AD9236

TOP VIEW

(Not to Scale)

03066-0-021

Figure 3. 28-Lead TSSOP

Table 8. Pin Function Descriptions—28-Lead TSSOP

D11 (MSB)28
D1027
D926
D825
DRVDD24
DGND23
D722
D621
D520
D419
D318
D217
D116
D0 (LSB)15

DNC 1
CLK 2
DNC 3

PDWN 4

DNC 5
DNC 6

(LSB) D0 7

D1 8

32 AVDD

31 AGND

(Not to Scale)

D2 9

D3 10

30 VIN–

29 VIN+

AD9236

CSP

TOP VIEW

D4 11

D5 12

28 AGND

27 AVDD

D6 13

D7 14

26 REFT

DGND 15

25 REFB

24 VREF
23 SENSE
22 MODE
21 OTR
20 D11 (MSB)
19 D10
18 D9
17 D8

DRVDD 16

Figure 4. 32-Lead LFCSP

Table 9. Pin Function Descriptions—32-Lead LFCSP

Pin No. Mnemonic Description Pin No. Mnemonic Description

1 OTR Out-of-Range Indicator 1, 3, 5, 6 DNC Do Not Connect
2 MODE

Data Format Select and DCS

Mode Selection
3 SENSE Reference Mode Selection
4 VREF Voltage Reference Input/Output
5 REFB Differential Reference (–)
6 REFT Differential Reference (+)
7, 12 AVDD Analog Power Supply
8, 11 AGND Analog Ground
9 VIN+ Analog Input Pin (+)
10 VIN– Analog Input Pin (–)
13 CLK Clock Input Pin
14 PDWN Power-Down Function Select
15 to 22,

25 to 28

D0 (LSB) to
D11 (MSB)

Data Output Bits

23 DGND Digital Output Ground
24 DRVDD Digital Output Driver Supply

2 CLK Clock Input Pin
4 PDWN Power-Down Function Select
7 to 14,

17 to 20

D0 (LSB) to
D11 (MSB)

Data Output Bits

15 DGND Digital Output Ground
16 DRVDD Digital Output Driver Supply
21 OTR Out-of-Range Indicator
22 MODE

Data Format Select and DCS

Mode Selection
23 SENSE Reference Mode Selection
24 VREF Voltage Reference Input/Output
25 REFB Differential Reference (–)
26 REFT Differential Reference (+)
27, 32 AVDD Analog Power Supply
28, 31 AGND Analog Ground
29 VIN+ Analog Input Pin (+)
30 VIN– Analog Input Pin (–)

03066-0-022

Rev. B | Page 9 of 36

AD9236

V

EQUIVALENT CIRCUITS

AVDD

DRVDD

IN+, VIN–

03600-0-003

Figure 5. Equivalent Analog Input Circuit

AVDD

MODE

20kΩ

03600-0-004

Figure 6. Equivalent MODE Input Circuit

D11-D0,
OTR

03600-0-005

Figure 7. Equivalent Digital Output Circuit

AVDD

CLK,

PDWN

03600-0-006

Figure 8. Equivalent Digital Input Circuit

Rev. B | Page 10 of 36

AD9236

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 3.0 V, DRVDD = 2.5 V, sample rate = 80 MSPS, DCS disabled, TA = 25°C, 2 V p-p differential input, AIN = –0.5 dBFS,
VREF = 1.0 V external, unless otherwise noted.

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120

0 5 10 15 20 25 30 35 40

FREQUENCY (MHz)

AIN = –0.5dBFS
SNR = 71.0dBc
ENOB = 11.5 BITS
SFDR = 93.6dBc

Figure 9. Single Tone 8K FFT @ 2.5 MHz

03066-0-031

100

90

80

70

60

SNR/SFDR (dBc AND dBFS)

50

40

–30 –25 –20 –15 –10 –5 0

SFDR (dBFS)

SFDR (dBc)

SNR (dBFS)

SNR (dBc)

INPUT AMPLITUDE (dBFS)

SFDR = 90dB

REFERENCE LINE

03066-0-048

Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 2.5 MHz

0

AIN = –0.5dBFS
SNR = 70.6dBc

–10

ENOB = 11.4 BITS
SFDR = 87.8dBc

–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120

0 5 10 15 20 25 30 35 40

FREQUENCY (MHz)

Figure 10. Single Tone 8K FFT @ 39 MHz

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120

0 5 10 15 20 25 30 35 40

FREQUENCY (MHz)

AIN = –0.5dBFS
SNR = 70.1dBc
ENOB = 11.3 BITS
SFDR = 81.9dBc

Figure 11. Single Tone 8K FFT @ 70 MHz Figure 14. SNR/SFDR vs. Sample Rate @ 10 MHz

100

90

80

70

60

SNR/SFDR (dBc AND dBFS)

50

40

–30 –25 –20 –15 –10 –5 0

03066-0-032

SFDR (dBFS)

SFDR (dBc)

REFERENCE LINE

SNR (dBFS)

INPUT AMPLITUDE (dBFS)

Figure 13. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 39 MHz

100

SFDR (DIFF)

90

SFDR (SE)

80

70

SNR/SFDR (dBc)

60

50

04020 60

03066-0-033

SAMPLE RATE (MSPS)

SFDR = 90dB

SNR (dBc)

03066-0-049

SNR (DIFF)

SNR (SE)

80 100

03066-0-042

Rev. B | Page 11 of 36