Analog Devices AD9236 Service Manual

12-Bit, 80 MSPS, 3 V A/D Converter

FEATURES

Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 70.4 dBc to Nyquist
SFDR = 87.8 dBc to Nyquist
Low power: 366 mW
Differential input with 500 MHz bandwidth
On-chip reference and sample-and-hold
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer

APPLICATIONS

High end medical imaging equipment
IF sampling in communications receivers

WCDMA, CDMA-One, CDMA-2000
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
DTV subsystems

GENERAL DESCRIPTION

The AD9236 is a monolithic, single 3 V supply, 12-bit, 80 MSPS
analog-to-digital converter featuring a high performance sample­and-hold amplifier (SHA) and voltage reference. The AD9236
uses a multistage differential pipelined architecture with output
error correction logic to provide 12-bit accuracy at 80 MSPS
and guarantee no missing codes over the full operating
temperature range.

The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and common modes, including
single-ended applications. It is suitable for multiplexed systems
that switch full-scale voltage levels in successive channels and
for sampling single-channel inputs at frequencies well beyond
the Nyquist rate. Combined with power and cost savings over
previously available analog-to-digital converters, the AD9236 is
suitable for applications in communications, imaging, and
medical ultrasound.

A single-ended clock input is used to control all internal
conversion cycles. A duty cycle stabilizer (DCS) compensates
for wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is

AD9236

FUNCTIONAL BLOCK DIAGRAM

DRVDDAVDD

AD9236

VIN+
VIN–

REFT
REFB

VREF

SENSE

SHA

REF

SELECT

A/D

AGND

MDAC1

4

0.5V

presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow. Fabricated on an advanced CMOS process, the
AD9236 is available in a 28-lead TSSOP and a 32-lead LFCSP
and is specified over the industrial temperature range
(−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. The AD9236 operates from a single 3 V power supply and

features a separate digital output driver supply to
accommodate 2.5 V and 3.3 V logic families.

2. Operating at 80 MSPS, the AD9236 consumes a low 366 mW.

3. The patented SHA input maintains excellent performance for

input frequencies up to 100 MHz, and can be configured for
single-ended or differential operation.

4. The AD9236 is pin compatible with the AD9215, AD9235,

and AD9245. This allows a simplified migration from 10 bits
to 14 bits and 20 MSPS to 80 MSPS.

5. The DCS maintains overall ADC performance over a wide

range of clock pulse widths.

6. The OTR output bit indicates when the signal is beyond the

selected input range.

8-STAGE

1 1/2-BIT PIPELINE

16

CORRECTION LOGIC

12

OUTPUT BUFFERS

CLOCK

DUTY CYCLE

STABILIZER

CLK PDWN MODE DGND

Figure 1.

MODE

SELECT

A/D

3

OTR

D11 (MSB)
D0 (LSB)

03066-0-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2006 Analog Devices, Inc. All rights reserved.

AD9236

TABLE OF CONTENTS

Features .............................................................................................. 1

Equivalent Circuits......................................................................... 10

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights........................................................................... 1

Revision History ............................................................................... 2

DC Specifications ............................................................................. 3

AC Specifications.............................................................................. 4

Digital Specifications........................................................................ 5

Switching Specifications .................................................................. 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Te r mi n ol o g y ...................................................................................... 8

Pin Configurations and Function Descriptions ........................... 9

Typical Perf or m an c e Charac t e r istics ........................................... 11

Theory of Operation ...................................................................... 14

Analog Input and Reference Overview ................................... 14

Clock Input Considerations...................................................... 15

Power Dissipation and Standby Mode .................................... 16

Digital Outputs........................................................................... 16

Timing ......................................................................................... 17

Volt a ge R e fer e nce ....................................................................... 17

Operational Mode Selection ..................................................... 18

Evaluation Board ........................................................................ 18

Outline Dimensions ....................................................................... 33

Ordering Guide .......................................................................... 34

REVISION HISTORY

1/06—Rev. A to Rev. B

Changes to Figure 29...................................................................... 15

Changes to Equation in Jitter Considerations Section ..............16

Changes to Internal Reference Connection Section, Figure 34,

and Table 10..................................................................................... 17

Changes to Figure 35...................................................................... 18

Changes to Figure 38...................................................................... 20

Changes to Figure 39...................................................................... 21

Changes to Figure 48...................................................................... 27

Changes to Figure 49...................................................................... 28

Changes to Figure 50...................................................................... 29

Changes to Table 12........................................................................ 32

Updated Outline Dimensions....................................................... 33

Changes to Ordering Guide.......................................................... 34

10/03—Rev. 0 to Rev. A

Changes to Figure 30...................................................................... 15

Changes to Figure 33 ..................................................................... 17

Changes to Figure 40...................................................................... 22

Changes to Figure 49...................................................................... 28

Changes to Figure 50...................................................................... 29

Changes to Table 11 ....................................................................... 32

Changes to Ordering Guide ......................................................... 33

Rev. B | Page 2 of 36

AD9236

DC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, unless otherwise noted.

Table 1.

AD9236BRU/AD9236BCP

Parameter Temp Test Level

Min Typ Max

RESOLUTION Full VI 12 Bits
ACCURACY

No Missing Codes Full VI Guaranteed
Offset Error

1

Full VI ±0.30 ±1.30 % FSR
Gain Error 25°C V ±0.10 % FSR
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)

1

2

2

Full VI ±0.30 ±4.34 % FSR

Full VI ±0.40 ±0.65 LSB

Full VI ±0.35 ±1.20 LSB

TEMPERATURE DRIFT

Offset Error

1

Full V ±6 ppm/°C
Gain Error Full V ±12 ppm/°C
Gain Error

1

Full V ±18 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V) Full VI ±2 ±35 mV
Load Regulation @ 1.0 mA 25°C V 0.8 mV
Output Voltage Error (0.5 V) 25°C V ±1 mV
Load Regulation @ 0.5 mA 25°C V 0.1 mV

INPUT REFERRED NOISE

VREF = 0.5 V 25°C V 0.55 LSB rms
VREF = 1.0 V 25°C V 0.28 LSB rms

ANALOG INPUT

Input Span, VREF = 0.5 V Full IV 1 V p-p
Input Span, VREF = 1.0 V Full IV 2 V p-p
Input Capacitance

3

Full V 7 pF

REFERENCE INPUT RESISTANCE Full V 7 kΩ
POWER SUPPLIES

Supply Voltage

AVDD Full IV 2.7 3.0 3.6 V
DRVDD Full IV 2.25 2.5 3.6 V

Supply Current

4

IAVDD
IDRVDD

4

Full VI 122 137 mA

25°C V 8 mA
PSRR 25°C V ±0.01 % FSR

POWER CONSUMPTION

Low Frequency Input
Standby Power

1

With a 1.0 V internal reference.

2

Measured at low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

3

Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure.

4

Measured at AC Specifications conditions without output drivers.

5

Measured with a dc input, CLK pin inactive (that is, set to AVDD or AGND).

4

5

25°C V 366 mW

25°C V 1.0 mW

Unit

Rev. B | Page 3 of 36

AD9236

AC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, AIN = –0.5 dBFS, DCS off,
unless otherwise noted.

Table 2.

AD9236BRU/AD9236BCP

Parameter Temp Test Level

SIGNAL-TO-NOISE-RATIO (SNR)

fIN = 2.4 MHz Full VI 68.6 dB

25°C V 70.9 dB

fIN = 40 MHz 25°C V 70.4 dB
fIN = 70 MHz Full IV 67.8 dB

25°C V 70.1 dB

fIN = 100 MHz 25°C V 69.0 dB

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 2.4 MHz Full VI 68.4 dB

25°C V 70.8 dB

fIN = 40 MHz 25°C V 70.2 dB
fIN = 70 MHz Full IV 67.4 dB

25°C V 69.8 dB

fIN = 100 MHz 25°C V 68.0 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.4 MHz Full VI 11.1 Bits

25°C V 11.5 Bits

fIN = 40 MHz 25°C V 11.4 Bits
fIN = 70 MHz Full IV 10.9 Bits

25°C V 11.3 Bits

fIN = 100 MHz 25°C V 11.0 Bits

WORST SECOND OR THIRD

fIN = 2.4 MHz Full VI –75.6 dBc
25°C V –91.3 dBc
fIN = 40 MHz 25°C V –87.8 dBc
fIN = 70 MHz Full VI –73.2 dBc
25°C V –81.4 dBc
fIN = 100 MHz 25°C V –76.4 dBc

SPURIOUS FREE DYNAMIC RANGE (SFDR)

fIN = 2.4 MHz Full VI 75.6 dBc

25°C V 91.3 dBc

fIN = 40 MHz 25°C V 87.8 dBc
fIN = 70 MHz Full IV 73.2 dBc

25°C V 81.4 dBc

fIN = 100 MHz 25°C V 76.4 dBc

Min Typ Max

Unit

Rev. B | Page 4 of 36

AD9236

DIGITAL SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, 1.0 V external reference, unless otherwise noted.

Table 3.

AD9236BRU/AD9236BCP

Parameter Temp Test Level

LOGIC INPUTS (CLK, PDWN)

High Level Input Voltage Full IV 2.0 V
Low Level Input Voltage Full IV 0.8 V
High Level Input Current Full IV –10 +10 μA
Low Level Input Current Full IV –10 +10 μA
Input Capacitance Full V 2 pF

DIGITAL OUTPUTS (D0–D11, OTR)

DRVDD = 3.3 V

High Level Output Voltage (IOH = 50 μA) Full IV 3.29 V
High Level Output Voltage (IOH = 0.5 mA) Full IV 3.25 V
Low Level Output Voltage (IOH = 1.6 mA) Full IV 0.2 V
Low Level Output Voltage (IOH = 50 μA) Full IV 0.05 V

DRVDD = 2.5 V

High Level Output Voltage (IOH = 50 μA) Full IV 2.49 V
High Level Output Voltage (IOH = 0.5 mA) Full IV 2.45 V
Low Level Output Voltage (IOH = 1.6 mA) Full IV 0.2 V
Low Level Output Voltage (IOH = 50 μA) Full IV 0.05 V

1

Output voltage levels measured with 5 pF load on each output.

1

Min Typ Max

Unit

Rev. B | Page 5 of 36

AD9236

SWITCHING SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted.

Table 4.

AD9236BRU/AD9236BCP

Parameter Temp Test Level

Min Typ Max

CLOCK INPUT PARAMETERS

Maximum Conversion Rate Full VI 80 MSPS
Minimum Conversion Rate Full V 1 MSPS
CLK Period Full V 12.5 ns
CLK Pulse Width High
CLK Pulse Width Low

1

1

Full V 4.0 ns
Full V 4.0 ns

DATA OUTPUT PARAMETERS

Output Propagation Delay (tPD)

2

Full V 3.5 ns
Pipeline Delay (Latency) Full V 7 Cycles
Aperture Delay (tA) Full V 1.0 ns
Aperture Uncertainty (Jitter, tJ) Full V 0.3 ps rms
Wake-Up Time

3

Full V 7 ms

OUT OF RANGE RECOVERY TIME Full V 2 Cycles

1

With duty cycle stabilizer (DCS) enabled.

2

Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

3

Wake-up time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.

Unit

N+1

ANALOG

INPUT

CLK

DATA

OUT

N

N–1

N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N

t

N+2

A

N+3

Figure 2. Timing Diagram

N+4

N+5

t

= 6.0ns MAX

PD

2.0ns MIN

N+6

N+7

N+8

03066-0-002

Table 5. Explanation of Test Levels

Test Level Definitions

I 100% production tested.
II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.

Rev. B | Page 6 of 36

AD9236

ABSOLUTE MAXIMUM RATINGS

Table 6.

With

Parameter Min Max Unit
ELECTRICAL

AVDD AGND –0.3 +3.9
DRVDD DGND –0.3 +3.9 V
AGND DGND –0.3 +0.3 V
AVDD DRVDD –3.9 +3.9 V
D0 to D11 DGND –0.3 DRVDD + 0.3 V
CLK, MODE AGND –0.3 AVDD + 0.3 V
VIN+, VIN– AGND –0.3 AVDD + 0.3
VREF AGND –0.3 AVDD + 0.3 V
SENSE AGND –0.3 AVDD + 0.3 V
REFT, REFB AGND –0.3 AVDD + 0.3 V
PDWN AGND –0.3 AVDD + 0.3 V

ENVIRONMENTAL

Storage Temperature –65 +125 °C
Operating Temperature Range –40 +85 °C
Lead Temperature

(Soldering 10 sec)

Junction Temperature 150 °C

Respect to

V

V

300 °C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θ

is specified for the worst-case conditions on a 4-layer board

JA

in still air, in accordance with EIA/JESD51-1.

Table 7.

Package Type Unit

RU-28 67.7 °C/W
CP-32-2 32.5 32.71 °C/W

θ

JA JC

Airflow increases heat dissipation effectively, reducing θ
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θ

. It is recommended that the exposed paddle be

JA

soldered to the ground plane for the LFCSP package. There is
an increased reliability of the solder joints, and maximum
thermal capability of the package is achieved with the exposed
paddle soldered to the customer board.

θ

. In

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 7 of 36

AD9236

(

−

TERMINOLOGY

Analog Bandwidth (Full Power Bandwidth)

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

Signal-to-Noise and Distortion (SINAD)

The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.

1

Aperture Delay (t

)

A

The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter, t

)

J

The sample-to-sample variation in aperture delay.

Integral Nonlinearity (INL)

The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes must be present over all operating ranges.

Offset Error

The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN–. Offset error is defined as the deviation
of the actual transition from that point.

Gain Error

The first code transition should occur at an analog value
½ LSB above negative full scale. The last transition should occur
at an analog value 1½ LSB below positive full scale. Gain error
is the deviation of the actual difference between first and last
code transitions and the ideal difference between first and last
code transitions.

Tem p er at u re Dr i ft

The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at T

MIN

or T

MAX

.

Power Supply Rejection Ratio

The change in full scale from the value with the supply at the
minimum limit to the value with the supply at its maximum limit.

Total Harmonic Distortion (THD)

1

The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.

Effective Number of Bits (ENOB)

The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured

SINAD using the following formula

SINAD

=

ENOB

Signal-to-Noise Ratio (SNR)

)

76.1

02.6

1

The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.

Spurious Free Dynamic Range (SFDR)

1

The difference in dB between the rms input signal amplitude
and the peak spurious signal. The peak spurious component
may or may not be a harmonic.

Two -Tone SFDR

1

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.

Clock Pulse Width and Duty Cycle

Pulse width high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.

Minimum Conversion Rate

The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The clock rate at which parametric testing is performed.

Output Propagation Delay (t

)

PD

The delay between the clock rising edge and the time when all
bits are within valid logic levels.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.

1

AC specifications may be reported in dBc (degrades as signal levels are

lowered) or in dBFS (always related back to converter full scale).

Rev. B | Page 8 of 36

AD9236

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

OTR 1

MODE 2

SENSE 3

VREF 4
REFB 5
REFT 6

AVDD 7

AGND 8

VIN+ 9
VIN– 10

AGND 11

AVDD 12

CLK 13

PDWN 14

AD9236

TOP VIEW

(Not to Scale)

03066-0-021

Figure 3. 28-Lead TSSOP

Table 8. Pin Function Descriptions—28-Lead TSSOP

D11 (MSB)28
D1027
D926
D825
DRVDD24
DGND23
D722
D621
D520
D419
D318
D217
D116
D0 (LSB)15

DNC 1
CLK 2
DNC 3

PDWN 4

DNC 5
DNC 6

(LSB) D0 7

D1 8

32 AVDD

31 AGND

(Not to Scale)

D2 9

D3 10

30 VIN–

29 VIN+

AD9236

CSP

TOP VIEW

D4 11

D5 12

28 AGND

27 AVDD

D6 13

D7 14

26 REFT

DGND 15

25 REFB

24 VREF
23 SENSE
22 MODE
21 OTR
20 D11 (MSB)
19 D10
18 D9
17 D8

DRVDD 16

Figure 4. 32-Lead LFCSP

Table 9. Pin Function Descriptions—32-Lead LFCSP

Pin No. Mnemonic Description Pin No. Mnemonic Description

1 OTR Out-of-Range Indicator 1, 3, 5, 6 DNC Do Not Connect
2 MODE

Data Format Select and DCS

Mode Selection
3 SENSE Reference Mode Selection
4 VREF Voltage Reference Input/Output
5 REFB Differential Reference (–)
6 REFT Differential Reference (+)
7, 12 AVDD Analog Power Supply
8, 11 AGND Analog Ground
9 VIN+ Analog Input Pin (+)
10 VIN– Analog Input Pin (–)
13 CLK Clock Input Pin
14 PDWN Power-Down Function Select
15 to 22,

25 to 28

D0 (LSB) to
D11 (MSB)

Data Output Bits

23 DGND Digital Output Ground
24 DRVDD Digital Output Driver Supply

2 CLK Clock Input Pin
4 PDWN Power-Down Function Select
7 to 14,

17 to 20

D0 (LSB) to
D11 (MSB)

Data Output Bits

15 DGND Digital Output Ground
16 DRVDD Digital Output Driver Supply
21 OTR Out-of-Range Indicator
22 MODE

Data Format Select and DCS

Mode Selection
23 SENSE Reference Mode Selection
24 VREF Voltage Reference Input/Output
25 REFB Differential Reference (–)
26 REFT Differential Reference (+)
27, 32 AVDD Analog Power Supply
28, 31 AGND Analog Ground
29 VIN+ Analog Input Pin (+)
30 VIN– Analog Input Pin (–)

03066-0-022

Rev. B | Page 9 of 36

AD9236

V

EQUIVALENT CIRCUITS

AVDD

DRVDD

IN+, VIN–

03600-0-003

Figure 5. Equivalent Analog Input Circuit

AVDD

MODE

20kΩ

03600-0-004

Figure 6. Equivalent MODE Input Circuit

D11-D0,
OTR

03600-0-005

Figure 7. Equivalent Digital Output Circuit

AVDD

CLK,

PDWN

03600-0-006

Figure 8. Equivalent Digital Input Circuit

Rev. B | Page 10 of 36

AD9236

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 3.0 V, DRVDD = 2.5 V, sample rate = 80 MSPS, DCS disabled, TA = 25°C, 2 V p-p differential input, AIN = –0.5 dBFS,
VREF = 1.0 V external, unless otherwise noted.

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120

0 5 10 15 20 25 30 35 40

FREQUENCY (MHz)

AIN = –0.5dBFS
SNR = 71.0dBc
ENOB = 11.5 BITS
SFDR = 93.6dBc

Figure 9. Single Tone 8K FFT @ 2.5 MHz

03066-0-031

100

90

80

70

60

SNR/SFDR (dBc AND dBFS)

50

40

–30 –25 –20 –15 –10 –5 0

SFDR (dBFS)

SFDR (dBc)

SNR (dBFS)

SNR (dBc)

INPUT AMPLITUDE (dBFS)

SFDR = 90dB

REFERENCE LINE

03066-0-048

Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 2.5 MHz

0

AIN = –0.5dBFS
SNR = 70.6dBc

–10

ENOB = 11.4 BITS
SFDR = 87.8dBc

–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120

0 5 10 15 20 25 30 35 40

FREQUENCY (MHz)

Figure 10. Single Tone 8K FFT @ 39 MHz

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120

0 5 10 15 20 25 30 35 40

FREQUENCY (MHz)

AIN = –0.5dBFS
SNR = 70.1dBc
ENOB = 11.3 BITS
SFDR = 81.9dBc

Figure 11. Single Tone 8K FFT @ 70 MHz Figure 14. SNR/SFDR vs. Sample Rate @ 10 MHz

100

90

80

70

60

SNR/SFDR (dBc AND dBFS)

50

40

–30 –25 –20 –15 –10 –5 0

03066-0-032

SFDR (dBFS)

SFDR (dBc)

REFERENCE LINE

SNR (dBFS)

INPUT AMPLITUDE (dBFS)

Figure 13. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 39 MHz

100

SFDR (DIFF)

90

SFDR (SE)

80

70

SNR/SFDR (dBc)

60

50

04020 60

03066-0-033

SAMPLE RATE (MSPS)

SFDR = 90dB

SNR (dBc)

03066-0-049

SNR (DIFF)

SNR (SE)

80 100

03066-0-042

Rev. B | Page 11 of 36

AD9236

0

AIN = –6.5dBFS
SNR = 71.3dBFS

–10

SFDR = 92.5dBc

–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90
–100
–110
–120

0 5 10 15 20 25 30 35 40

FREQUENCY (MHz)

Figure 15. Two-Tone 8K FFT @ 30 MHz and 31 MHz

03066-0-036

100

90

80

70

60

SNR/SFDR (dBc AND dBFS)

50

40

–30 –27 –24 –21 –18 –15 –12 –9 –6

SFDR = 90dB

REFERENCE LINE

Figure 18. Two-Tone SNR/SFDR vs. Input Amplitude @ 30 MHz and 31 MHz

SFDR (dBFS)

SFDR (dBc)

SNR (dBFS)

INPUT AMPLITUDE (dBFS)

SNR (dBc)

03066-0-039

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120

0 5 10 15 20 25 30 35 40

FREQUENCY (MHz)

AIN = –6.5dBFS
SNR = 71.0dBFS
SFDR = 79.3dBc

Figure 16. Two-Tone 8K FFT @ 69 MHz and 70 MHz

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 1024 2048 3072 4096

CODE

Figure 17. Typical INL Figure 20. Typical DNL

100

90

80

70

60

SNR/SFDR (dBc AND dBFS)

50

40

–30 –27 –24 –21 –18 –15 –12 –9 –6

03066-0-037

SFDR (dBc)

SFDR = 90dB
REFERENCE LINE

SFDR (dBFS)

SNR (dBFS)

INPUT AMPLITUDE (dBFS)

Figure 19. Two-Tone SNR/SFDR vs. Input Amplitude @ 69 MHz and 70 MHz

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

03066-0-038

0 1024 2048 3072 4096

CODE

SNR(dBc)

03066-0-040

03066-0-041

Rev. B | Page 12 of 36

AD9236

72.0

100

71.5

71.0

70.5

70.0

SNR (dBc)

69.5

69.0

68.5

68.0
0 25 50 75 100 125

INPUT FREQUENCY (MHz)

Figure 21. SNR vs. Input Frequency

95

SFDR (DCS ON)

90

85

80

75

70

SNR/SFDR (dBc)

65

60

55

30 35 40 45 50 55 60 65 70

SNR (DCS OFF)

DUTY CYCLE (%)

Figure 22. SNR/SFDR vs. Clock Duty Cycle

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120

0 7.68 15.36 23.04 30.72

FREQUENCY (MHz)

Figure 23. 32K FFT CDMA-2000 Carrier @ F

61.44 MSPS

–40°C

+25°C

+85°C

SFDR (DCS OFF)

SNR (DCS ON)

= 46.08 MHz, Sample Rate =

IN

03066-0-045

03066-0-046

03066-0-060

95

–40°C

90

85

SFDR (dBc)

80

75

70

0 25 50 75 100 125

+85°C

+25°C

INPUT FREQUENCY (MHz)

03066-0-047

Figure 24. SFDR vs. Input Frequency

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120

0 7.68 15.36 23.04 30.72

Figure 25. 32K FFT WCDMA Carrier @ F

FREQUENCY (MHz)

=76.8 MHz,

IN

03066-0-061

Sample Rate = 61.44 MSPS

Rev. B | Page 13 of 36

AD9236

THEORY OF OPERATION

The AD9236 architecture consists of a front-end sample-and­hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The pipelined ADC is divided into three sections,
consisting of a 4-bit first stage followed by eight 1.5-bit stages
and a final 3-bit flash. Each stage provides sufficient overlap to
correct for flash errors in the preceding stages. The quantized
outputs from each stage are combined into a final 12-bit result
in the digital correction logic. The pipelined architecture
permits the first stage to operate on a new input sample, while
the remaining stages operate on preceding samples. Sampling
occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.

The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The output­staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.

ANALOG INPUT AND REFERENCE OVERVIEW

The analog input to the AD9236 is a differential switched
capacitor SHA that has been designed for optimum
performance while processing a differential input signal. The
SHA input can support a wide common-mode range (VCM)
and maintain excellent performance, as shown in
input common-mode voltage of midsupply minimizes signal­dependant errors and provides optimum performance.

100

95

90

85

80

75

70

SNR/SFDR (dBc)

65

60

55

50

0.5 1.0 1.5 2.0 2.5 3.0

Figure 26. SNR, SFDR vs. Common-Mode Level

SNR (2.5MHz)

SNR (39MHz)

COMMON-MODE LEVEL (V)

SFDR (2.5MHz)

SFDR (39MHz)

Figure 26. An

03066-0-016

Referring to Figure 27, the clock signal alternately switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. In addition, a small shunt capacitor
can be placed across the inputs to provide dynamic charging
currents. This passive network creates a low-pass filter at the
ADC’s input; therefore, the precise values are dependant upon
the application. In IF undersampling applications, any shunt
capacitors should be reduced or removed. In combination with the
driving source impedance, they would limit the input bandwidth.

H

VIN+

VIN–

T

C

PAR

T

C

PAR

Figure 27. Switched-Capacitor SHA Input

5pF

5pF

T

T

H

03066-0-012

For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.

An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, that define the
span of the ADC core. The output common mode of the
reference buffer is set to midsupply, and the REFT and REFB
voltages and span are defined as follows:

REFT = ½(AVDD + VREF)

REFB = ½(AVDD + VREF)

Span = 2 × (REFT − REFB) = 2 × VREF

It can be seen from the previous equations that the REFT and
REFB voltages are symmetrical about the midsupply voltage and,
by definition, the input span is twice the value of the VREF voltage.

The internal voltage reference can be pin strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within the same range as
discussed in the

Internal Reference Connection section.
Maximum SNR performance is achieved with the AD9236 set
to the largest input span of 2 V p-p. The relative SNR degradation is
3 dB when changing from 2 V p-p mode to 1 V p-p mode.

Rev. B | Page 14 of 36

AD9236

The SHA can be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined as:

VCM

VCM

VREF

=

MIN

MAX

2

()

=

+

VREFAVDD

2

The minimum common-mode input level allows the AD9236 to
accommodate ground referenced inputs.

Although optimum performance is achieved with a differential
input, a single-ended source can be applied to VIN+ or VIN–.
In this configuration, one input accepts the signal, while the
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal can be
applied to VIN+ while a 1 V reference is applied to VIN–. The
AD9236 then accepts an input signal varying between 2 V and
0 V. In the single-ended configuration, distortion performance
can degrade significantly as compared to the differential case.
However, the effect is less noticeable at lower input frequencies.

Differential Input Configurations

As previously detailed, optimum performance is achieved while
driving the AD9236 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.

33Ω

2V p-p

Figure 29. Differential Transformer-Coupled Configuration

49.9Ω

0.1μF

20pF

33Ω

1kΩ

1kΩ

The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.

Single-Ended Input Configuration

A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, there is a
degradation in SFDR and distortion performance due to the
large input common-mode swing (see

Figure 14). However, if
the source impedances on each input are matched, there should
be little effect on SNR performance.

Figure 30 details a typical

single-ended input configuration.

1k

2V p-p

49.9

0.33μF

Ω

+

10μF 0.1μF

Ω

1k

Ω

33

Ω

20pF

1k

Ω

33

Ω

1k

Ω

AVDD

VIN+

AD9236

VIN–

AGND

VIN+

AD9236

VIN–

03600-0-014

AVDD

AGND

1V p-p

0.1μF

Figure 28. Differential Input Configuration Using the AD8138

1kΩ

1kΩ

49.9Ω

499Ω

523Ω

499Ω

AD8138

499Ω

33Ω

20pF

33Ω

AVDD

VIN+

AD9236

VIN–

AGND

03066-0-013

At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9236. This is especially true in IF
undersampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The value of the shunt capacitor is dependent
on the input frequency and source impedance and should be
reduced or removed. An example is shown in

Figure 29.

Rev. B | Page 15 of 36

03600-A-015

Figure 30. Single-Ended Input Configuration

CLOCK INPUT CONSIDERATIONS

Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result can be sensitive
to clock duty cycle. Commonly a 5% tolerance is required on
the clock duty cycle to maintain dynamic performance
characteristics. The AD9236 contains a clock
duty cycle stabilizer (DCS) that retimes the nonsampling edge,
providing an internal clock signal with a nominal 50% duty
cycle. This allows a wide range of clock input duty cycles
without affecting the performance of the AD9236. As shown in
Figure 22, noise and distortion performance is nearly flat for a
30% to 70% duty cycle with the DCS on.

The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 100 clock cycles to
allow the DLL to acquire and lock to the new rate.

AD9236

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input frequency

) due only to aperture jitter (tJ) can be calculated with the

(f

INPUT

following equation:

SNR

=

⎢

10

2

⎢

INPUT

⎣

⎡

log20

⎤

1

⎥

tf

×π

⎥

J

⎦

which is determined by the sample rate and the characteristics
of the analog input signal.

425

400

375

ANALOG CURRENT

TOTAL POWER

140

120

100

80

In the equation, the rms aperture jitter represents the root­mean square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification. IF
undersampling applications are particularly sensitive to jitter

Figure 31).

(see

The clock input should be treated as an analog signal in cases
where aperture jitter can affect the dynamic range of the
AD9236. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the last step.

75

70

65

60

55

SNR (dBc)

50

45

40

1 10 100 1000

Figure 31. SNR vs. Input Frequency and Jitter

INPUT FREQUENCY (MHz)

0.2ps

MEASURED
SNR

0.5ps

1.0ps

1.5ps

2.0ps

2.5ps

3.0ps

03066-0-043

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 32, the power dissipated by the AD9236 is
proportional to its sample rate. The digital power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The maximum DRVDD current

) can be calculated as

(I

DRVDD

= V

I

DRVDD

where

N is the number of output bits, 12 in the case of the

AD9236. This maximum current occurs when every output bit
switches on every clock cycle, that is, a full-scale square wave at
the Nyquist frequency,
established by the average number of output bits switching,

DRVDD

DRVDDDRVDD

× C

× f

LOAD

f

CLK

× N

CLK

NfCVI

×××=

CLKLOAD

/2. In practice, the DRVDD current is

03066-0-044

60

CURRENT (mA)

40

20

0

350

POWER (mW)

325

DIGITAL CURRENT

300

10 20 30 40 50 60 70 80 90 100

Figure 32. Power and Current vs. Sample Rate @ 2.5 MHz

SAMPLE RATE (MSPS)

Reducing the capacitive load presented to the output drivers
can minimize digital power consumption. The data in

Figure 32
was taken with the same operating conditions as the Typical
Performance Characteristics, and with a 5 pF load on each
output driver.

By asserting the PDWN pin high, the AD9236 is placed in
standby mode. In this state, the ADC typically dissipates
1 mW if the CLK and analog inputs are static. During
standby, the output drivers are placed in a high impedance
state. Reasserting the PDWN pin low returns the AD9236
to its normal operational mode.

Low power dissipation in standby mode is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 μF and 10 μF decoupling capacitors on REFT
and REFB, it takes approximately 1 second to fully discharge the
reference buffer decoupling capacitors and 7 ms to restore full
operation.

DIGITAL OUTPUTS

The AD9236 output drivers can be configured to interface with

2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies, which can affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts can require external buffers or latches.

As detailed in
either offset binary or twos complement.

Table 1 1, the data format can be selected for

Rev. B | Page 16 of 36

AD9236

TIMING

The AD9236 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propagation
delay (t

) after the rising edge of the clock signal. Refer to

PD

Figure 2 for a detailed timing diagram.

The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9236. These transients can degrade the converter’s dynamic
performance.

The lowest typical conversion rate of the AD9236 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance can degrade.

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into the
AD9236. The input range can be adjusted by varying the
reference voltage applied to the AD9236 using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly. The various reference modes are summarized in
and described in the following sections.

If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap
(common-mode voltage).

Internal Reference Connection

A comparator within the AD9236 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in

Tabl e 10 . If SENSE is
grounded, the reference amplifier switch is connected to the
internal resistor divider (see

Figure 33), setting VREF to 1 V.
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected as shown in

Figure 34, the switch is again set to the
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as follows:

Tabl e 10

In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.

VIN+

10μF+0.1μF

10μF+0.1μF

VIN–

ADC

CORE

VREF

SELECT

LOGIC

SENSE

0.5V

AD9236

Figure 33. Internal Reference Configuration

VIN+
VIN–

VREF

R2
SENSE

R1

SELECT

LOGIC

AD9236

03066-A-017

ADC

CORE

0.5V

REFT

0.1μF

0.1μF 10μF

REFB

0.1μF

REFT

0.1μF

REFB

0.1μF

+

0.1μF 10μF

+

VREF

⎛

+×=

15.0

⎟

⎜

R1

⎠

⎝

Figure 34. Programmable Reference Configuration

03066-0-018

R2

⎞

Table 10. Reference Configuration Summary

Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p)

External Reference AVDD N/A 2 × External Reference
Internal Fixed Reference VREF 0.5 1.0
Programmable Reference 0.2 V to VREF

R2

⎞

⎛

15.0

⎜
⎝

+×

⎟

R1

⎠

(See Figure 34)

2 × VREF

Internal Fixed Reference AGND to 0.2 V 1.0 2.0

Rev. B | Page 17 of 36

AD9236

If the internal reference of the AD9236 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered.

Figure 35 depicts
how the internal reference voltage is affected by loading. A
2 mA load is the maximum recommended load.

0.05

0

–0.05

–0.10

ERROR (%)

–0.15

–0.20

1.0V ERROR (%)

0.5V ERROR (%)

OPERATIONAL MODE SELECTION

As discussed in the Digital Outputs section, the AD9236 can
output data in either offset binary or twos complement format.
There is also a provision for enabling or disabling the clock duty
cycle stabilizer (DCS). The MODE pin is a multilevel input that
controls the data format and DCS state. The input threshold
values and corresponding mode selections are outlined in

Table 11. Mode Selection

MODE Voltage

Data Format

Duty Cycle
Stabilizer

AVDD Twos Complement Disabled
2/3 AVDD Twos Complement Enabled
1/3 AVDD Offset Binary Enabled
AGND (Default) Offset Binary Disabled

Tabl e 11 .

–0.25

0 0.5 1.0 1.5 2.0 2.5 3.0

Figure 35. VREF Accuracy vs. Load

LOAD (mA)

03066-0-019

External Reference Operation

The use of an external reference can be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift
characteristics. When multiple ADCs track one another, a
single reference (internal or external) can be necessary to
reduce gain matching errors to an acceptable level.

Figure 36
shows the typical drift characteristics of the internal reference
in both 1.0 V and 0.5 V modes.

When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1.0 V.

1.0

0.9

0.8

0.7

0.6
= 1.0V

0.5

ERROR (%)

0.4

REF

V

0.3

0.2

0.1

0
–40–30–20–100 1020304050607080

Figure 36. Typical VREF Drift

V

REF

V

= 0.5V

REF

TEMPERATURE (°C)

03066-0-011

EVALUATION BOARD

The AD9236 evaluation board provides all of the support
circuitry required to operate the ADC in its various modes and
configurations. Complete schematics and layout plots follow
and demonstrate the proper routing and grounding techniques
that should be applied at the system level.

It is critical that signal sources with very low phase noise (< 1 ps
rms jitter) be used to realize the ultimate performance of the
converter. Proper filtering of the input signal, to remove
harmonics and lower the integrated noise at the input, is also
necessary to achieve the specified noise performance.

TSSOP Evaluation Board

Figure 37 shows the typical bench setup used to evaluate the ac
performance of the AD9236. The AD9236 can be driven single­ended or differentially through an AD8138 driver or a
transformer. Separate power pins are provided to isolate the
DUT from the support circuitry. Each input configuration can
be selected by proper connection of various jumpers (refer to
the schematics).

The AUXCLK input should be selected in applications requiring
the lowest jitter and SNR performance (that is, IF undersampling
characterization). It allows the user to apply a clock input signal
that is 4× the target sample rate of the AD9236. A low jitter,
differential divide-by-4 counter, the MC100LVEL33D, provides
a 1× clock output that is subsequently returned back to the CLK
input via JP9. For example, a 260 MHz signal (sinusoid) is
divided down to a 65 MHz signal for clocking the ADC. Note
that R1 must be removed with the AUXCLK interface. Lower
jitter is often achieved with this interface since many RF signal
generators display improved phase noise at higher output
frequencies and the slew rate of the sinusoidal output signal is
4× that of a 1× signal of equal amplitude.

Rev. B | Page 18 of 36

AD9236

LFCSP Evaluation Board

The typical bench setup used to evaluate the ac performance of
the AD9236 is similar to the TSSOP evaluation board
connections. The AD9236 can be driven single-ended or
differentially through a transformer. Separate power pins are
provided to isolate the DUT from the support circuitry. Each
input configuration can be selected by proper connection of
various jumpers (see

Figure 48).

An alternative differential analog input path using an AD8351
op amp is included in the layout but is not populated in
production. Designers interested in evaluating the op amp with
the ADC should remove C15, R12, and R3 and populate the op
amp circuit. The passive network between the AD8351 outputs
and the AD9236 allows the user to optimize the frequency
response of the op amp for their application.

3V

–+

DVDD

J1

DATA

CAPTURE

AND

PROCESSING

03066-0-024

REFIN

SIGNAL SYNTHESIZER

10MHz
REFOUT

CLOCK SYNTHESIZER

HP8644, 2V p-p

HP8644, 2V p-p

BAND-PASS

FILTER

CLOCK

DIVIDER

3V

–+

AVDD DUT

S4
XFMR
INPUT

S1
CLOCK

3V

–+

GND GND DUT

AVDD

3V

–+

DRVDD

AD9236

EVALUATION BOARD

Figure 37. TSSOP Evaluation Board Connections

Rev. B | Page 19 of 36

AD9236

03066-0-007

μF

DUTDRVDD

1

0

0

DUTCLK

WHT

D11O

D10O

D9O

D8O

D7O

D6O

D5O

D4O

D3O

D2O

D1O

D0O

OTRO

TP6

4

.0

C

0

TP5

WHT

272625

28

D11

D10

OTRAVDD

AD9236

C39

0.001μF

0.1μF

C57

C36

10V

C22

10μF

JP24

JP25

C35

0.1μF

10V

C21

0.1μF

10μF

DUTAVDD

JP22

JP23

WHT

TP17

SENSE

AGND

71

8

3

21

22

D7

D8

D9

PDWN

REFB

VREF

4

5

14

C33

C34

10V

0.1μF

18

191716

D4

D5MODE

D3

D6

U1

VIN+

VIN–

REFT

220

6

9

10

VIN+

VIN–

C50

0.1μF

C32

C20

10μF

13

15

D0

D1

D2

CLK

AVDD

DGND

DRVDD

AGND

11

24

23

12

0.1μF

0.1μF

JP7

JP6

DUTAVDD

C37

0.1μF

C1

10V

10μF

C41

0.001μF

C38

0.1μF

10V

C23

10μF

JP2

JP1

8

22Ω

RP5

1

D8O D8

D0

817
22Ω

RP3

D0O

D9

765

22Ω

22Ω
RP5

RP5

2

3

D9O

D1

6

22Ω

22Ω

RP3

RP3

2

3

D1O

D10

22Ω
RP5

D10O

D2

22Ω
RP3 54

D2O

4

D11

D11O

D3

D3O

10kΩ

R3

10kΩ

OTR

8

7

6

22Ω

22Ω

22Ω

22Ω

RP62

D5

D5O

RP6 5

RP63

4

D7

D6

22Ω

22Ω

RP4 63

RP4 54

D7O

D6O

RP61

D4

8

22Ω

22Ω
RP4 72

RP4
1

D4O

JP12

RED

TP2

L1

OTRO

FBEAD

R4

DUTAVDD

AVDD

RED

TP1

12

F

C59

0.1μF

21

C58

22μF

2

TB1

DUTAVDDIN

25V

L2

FBEAD

TB1 3

AGND

TB1 1

AVDDIN



R20

1kΩ

AVDD

R27

5kΩ

JP13

AVDD

C52

0.1μF

C47

25V

22μF

RED

TP3

L3

FBEAD

R17

1kΩ

DUTDRVDD

JP11

12

C48

5

TB1

DRVDDIN

R42

1kΩ

BLK

TP16

BLK

BLK

TP14

BLKBLK

TP13

TP10 TP15

BLK BLK

TP12

TP9

DVDD

RED

TP4

L4

C53

0.1μF
21

FBEAD

25V

22μF

6

TB1 4

AGND

DVDDIN

TB1

BLK

TP11

C14

0.1μF

C6

25V

22μF

Figure 38. TSSOP Evaluation Board Schematic, DUT

Rev. B | Page 20 of 36

AD9236

864

2

16

14

12

10

24

22

20

18

32

30

28

26

40

38

36

34

HEADER RIGHT ANGLE MALE NO EJECTORS

957

3

1

DD0

16

22Ω

1

22Ω

DD1

15

22Ω

11

DD2

22Ω

13

DD3

DD4

121314

22Ω

15

17

DD5

22Ω

DD6

22Ω

RP17RP18RP16RP15RP14RP13RP12RP1

23

21

19

DD7

DD8

16

10911

22Ω

22Ω

RP2

1

31

29

27

25

DD9

DD10

DD11

DOTR

1514131211

22Ω

22Ω

22Ω

22Ω

RP22RP23RP24RP25RP26RP2

39

37

35

33

DACLK

9

10

22Ω

22Ω

22Ω

RP2

8

7

03066-0-008

J1

DVDD

182

15

16

10

U7

74VHC541

G2 GND

19

17

Y2Y3Y4Y5Y6Y7Y8

A2A3A4A5A6A7A8

A1 Y1

3

D9

D8

D11

D10

AVDD

R18

500Ω

R2

10kΩ

CW

20

10μF

VCC

21

10V

C12

C4

0.1μF

10μF

21

10V

20

10

VCC

182

14

15

16

17

Y2Y3Y4Y5Y6Y7Y8

C5

11

12

13

C11

0.1μF
G1

U6

74VHC541

G2 GND

A1 Y1

19

D0

R26

10kΩ

NC

MC100LVEL33D

VCC

8

A2A3A4A5A6A7A8

654

3

D6

D5

D4

D3

D2

D1

4

321

INA

INB

INCOM

U3

OUT

AVDD

VEE

REF

AVDD

657

C28

987

D7

10V

10μF

0.1μF

C24

U3 DECOUPLING

113Ω

R13

G1

1

AVDD

1N5712

D1

R25

10kΩ

D2

1N5712

2

1

T1-1T

6

T2

5

43

1

0.1μF

C26

90Ω

R15

11

12

13

14

987

654

OTR

R9

22Ω

DUTCLK

JP4

JP3

R7

22Ω

43

65

74VHC04

U8

AGND;7

AVDD ;1 4

74VHC04

U8

10V

10μF

C3

0.1μF

C10

U8 DECOUPLING

AVDD

1213

74VHC04

U8

89

1011

74VHC04

U8

74VHC04

U8

21

74VHC04

U8

WHT

TP7

R19

500Ω

C13

AVDD

C27

0.1μF

R11

AUXCLK

S5

49.9Ω

1

2

113Ω

R12



R14

90Ω

AVDD

JP9

CLOCK

0.1μF

R1

49.9Ω

1

2

S1

Figure 39. TSSOP Evaluation Board Schematic, Clock Inputs and Output Buffering

Rev. B | Page 21 of 36

AD9236

AVDD

VIN+

DNP

C44

R21

33Ω

JP42

JP40

JP45

C7

0.1μF

1kΩ

R23

R41

1kΩ

C44B

20pF

VIN–

DNP

C43

R22

33Ω

JP46

JP41

JP43

1kΩ

AVDD

R16

1

2

3

T1-1T

T1

6

5

4

03066-A-009

C16

0.1μF

C25

0.33μF

R8

1kΩ

JP5

40Ω

AD8138

5

VEE

2

S2

VAL C45

49.9Ω

R24

1

2

S4

XFMR INPUT

C17VAL

R36

499Ω

6

C18

R31

49.9Ω

10V

0.1μF

RED

TP8

ALT VEE

31

JP8

2

AB

C19

10μF

12

C9

0.33μF

49.9Ω

R5

C8

1

2

S3

SINGLE INPUT

R32

1kΩ

AVDD

21

10V10μF

+

C15

AVDD

0.1μF

1kΩ

R33

VAL

C69

0.33μF

C2

VAL C42

R6

R37

499Ω

3

R10

40Ω

2

VOC

4

VO+

VO–

U2

VCC

+IN

–IN

8

1

R34

R35

523Ω

499Ω

1

AMP INPUT

Figure 40. TSSOP Evaluation Board Schematic, Analog Inputs

Rev. B | Page 22 of 36

AD9236

DACLK

DD0
DD1

DD2
DD3
DD4
DD5
DD6
DD7
DD8

DD9
DD10
DD11

1
2

DB10

3

DB19

4

DB8

AD9762

5

DB7

6

DB6

7

DB5
DB4
DB3
DB2
DB1
DB0
NC1
NC2

U4

8

9
10
11
12

13
14

CLOCKMSB–DB11

DVDD

DCOM

NC3

AVDD

COMP2

IOUTA
IOUTB
ACOM

COMP1

FSADJ

REFIO

REFLO

SLEEP

28
27

26
25
24
23
22
21
20
19
18
17
16
15

C30

0.1μF

C49

0.01μF

C56

0.01μF

R30
2kΩ

C31

0.01μF

DVDD

C29

0.1μF

C51

0.01μF

C46

0.01μF
TP18

WHT

R29

49.9Ω

C55

22pF

R28

49.9Ω

C54

22pF

03066-0-010

S6

Figure 41. TSSOP Evaluation Board Schematic, Optional D/A Converter

Figure 42. TSSOP Evaluation Board Layout, Primary Side

Rev. B | Page 23 of 36

03066-0-025

AD9236

Figure 43. TSSOP Evaluation Board Layout, Secondary Side

03066-0-026

Figure 44. TSSOP Evaluation Board Layout, Ground Plane

Rev. B | Page 24 of 36

03066-0-027

AD9236

Figure 45. TSSOP Evaluation Board Layout, Power Plane

03066-0-028

Figure 46. TSSOP Evaluation Board Layout, Primary Silkscreen

Rev. B | Page 25 of 36

03066-0-029

AD9236

03066-0-030

Figure 47. TSSOP Evaluation Board Layout, Secondary Silkscreen

Rev. B | Page 26 of 36

AD9236

X

6

1
H

D
N
G

E
L
O
H
T

M

1

P6

AVDD

EXTREF

1V MAX E1

6
E
L
O
H
T

2
H

M

6

6

E

E

L

L

O

O

H

H

T

T

4

3

H

M

H

M

P2

6

45

123

MODE

2

2

Ω

5

k

R

1

F

2

μ

2

0

C

1

C13

0.10μF
P11

D

D
D

C

V
A

P8

B

P9

A

GND

P7

R1

10kΩ

5.0V

VAMP

VDL

2.5V

GND

2.5V

DRVDD

GND

3.0V

AVDD

C8

0.1μF

P5

7
R

GND

GND

Ω

k
1

p10

3

P3

Ω

6

k

R

1

C9

0.1μF

C12

R9

10kΩ

P1

E

IT
B

E
G
N
A
R
R
E
V
O

GND

0.10μF

GND GND

X
R
D

6
1

Ω

0
2

2
2
P
R

1

)
B
S

(M

4

P4

GND

0.1μF

C11

C29

10μF

D
N
G

X

X

X

1

2

3

1

1

1

D

D

D

5

3

4

1

1

1

2

3

4

17
18
19
20
21
22
23
24

C7

0.1μF

.
8
1

C
D
N

T

, A

U

6

P

, C

IN

2
4

D
E

, R

D

9

N

1

E

, R

E

8

L

1

G

R

IN

E

S

C

R

A
L

O

P

F

X

0

X

X

7

1

9

8

D

D

D

D

0

1

2

9

1

1

1

5

6

7

8

D8
D9

D10
D11

OTR

MODE

SENSE

VREF

25262728303132

E
B

D
L

GND

U
O
H

7
1

S
E

, C

N

2
4

O
Y

, R

L

2

.

N

1

7

O

R

2
C

D

2

N

4
R

, A
7
1

, C
5
1

, C
2
1

, R
3

R

6

E

C

V
O
M
E
R

D
D
V
R
D

6
1

D
D
V
R
D

REFB

D
N
G

D
D
V
A

.
E

IM
T
A

T
A

D
R
A
O

B
N
O

Ω

0

F

μ

.1
0

D
N
G

5
1

D
N
G
D

T
F
E
R

6
2
R

6
3
R

4
1

7

6

D

D

AD9236

D

D

N

D
V

G

A

A

D

D

D

N

V

G

A

Ω

k
1

Ω

k
1

2
1
R

IN
P
M
A

U4

X

X
6
D

6
1

1

2

3

1

1

5
D

+
IN

V

29

+
IN

V

X

X

X

X

4

5

D

D

5

4

1

1

2

3

0
1

11

4

3

D

D

D

–

N
G

IN

A

V

–

D
N

IN
V

G

1
2
C

Ω

4

3

R

3

OUT

X

3

2

D

D

2

3

1

1

4

5

9

2
D

D
D
V
A

D
D
V
A

F
p
0
1

6
2
C

0

Ω

1

6

R

3

6

T 1

ADT1–1WT

H
n
0

1
1
L

1
J

1
D

0

1

1

1

6

7

)
B
S

(L

D
N
G

F
p
0

1

5
4
E

CT

2

5

1

XFRIN1

5
1
C

X
0
D

9

8

D1

8

D0

7

DNC

6

DNC

5

PDWN

4

DNC

3

CLK

2

DNC

1

1
L
R
O

9

F

1

p
0

C

2

2

X

R

X

D

D

N

N

G

G

5
C

F

μ

6
1

.1

C

0

C
E
S

I
R

34

P

NC

D
N
G

F

μ

.1
0

P
M
A

D
N
G

Ω

0
2

2
1
P
R

R

D

E

N
G

ILT
F
R
O

F

F

μ

.1
0

1

Ω

1

6

R

3
D

N
G

OPTIONAL XFR

R
E

:

ID

R

IV

E
P

D

M

E

U

G
A

J

T

E

L

L

O

B
A

V

R

L

E

A

D

N

L

R

O

E
T

S

X

IN

E

P

:

E

A

S

O

N
E

T

S

E

3
2
C

B

OUT

X

T2

)
T
L
U
A
F
E

E

(D

C

E

N

C

E

E

N

C

R

E

N

E

R

E

F

E

E

R

F

E

E

R

F

V

R

E

V

.5

R

1

0

L

L

L

A

A

A

N

N

N

R

R

R

E

E

E

T

T

T

X

IN

E

IN

:

:

:

B

C

D

O

O

O

T

T

T

E

E

E

Ω

8

k

R

1

K
L
C

F
p
0
1

3

Ω

R

0

T

OUT

C

X

4

2

5

1

3

FT C1–1–13

IN
R
F
X

F
F

:

O
S

R
E

C

P

D

/

M

T

U

N
E

J
E

M

L

E

B

L

A

P

R

M

E

O

D

C

L

S

O

O

S

W

IN

T
:

P
E

1

D

O

O

T

M

5

P14

5

Ω

1

3

R

3

B
IN

P
M
A

B

OUT

X

D
N
G

N
O

F

S

F

N

C

O

O

/D

S

T

S

C

N

C

E

/D

/D

M

Y

Y

E

R

R

L

A

A

P

IN

IN

M
O

B

B

T

T

C

E

E

S

S

S

O

F

F

F

F

W

O

O

T

:

:

:

4

3

2

O

O

O

T

T

T

5

5

5

D
N
G

P13

D
D
V
A

D
N
G

D
D
V
A

F

μ

8
1
C

0.10

R SINGLE ENDED

R18

C
E
S
I
R
P

03066-A-050

5

Ω

2

k

R

1

3

Ω

1

k

R

1

D
N
G

Ω

5
2

R3, R16, C18

ONLY ONE SHOULD BE

ON BOARD AT A TIME

Figure 48. LFCSP Evaluation Board Schematic, Analog Inputs and DUT

Rev. B | Page 27 of 36

AD9236

GND

03066-A-051

135791113151719212325272931333537

135791113151719212325272931333537

P12

HEADER 40

2468101214161820222426283032343638

2468101214161820222426283032343638

GNDDRGND

MSB

39

39

40

40

AMPIN

AMPINB

DRY

GND

GND

GND

GND

C24

10μF

C45

0.1μF

R14

25Ω

R39

1kΩ

VAMP

VOCM

OPHI

R38

1kΩ

C44

0.1μF

VPOS

8

9

10

C27

R16

0.1μF

0Ω

OPLO
7

C17

R17

GND

COMM
6

0.1μF

0Ω

DRY

GND

GND

DRVDD

GND

24232221201918171615141312111098765432

CC

2Q4

2Q2

2Q3

GND

GND

GND

2Q6

2D6

D12X

2Q5

2D5

D11X

V

GND

CC

2D3

2D4

V

DRVDD

D10X

2D2

GND

D8X

D9X

GND

2Q7

2OE

2QB

U1

74LVTH162374

2CLK

2DB

2D7

2526272829303132333435363738394041424344454647

DRX

CLKAT/DAC

D13X

MSB

2Q1

2D1

D7X

1Q8

1D8

D6X

1Q7

1D7

D5X

GND

GND

GND

GND

1Q6

1D6

D4X

1Q5

1D5

D3X

Figure 49. LFCSP Evaluation Board Schematic, Digital Path

DRVDD

V

V

CC

DRVDD

TO USE AMPLIFIER

PLACE ALL COMPONENTS

SHOWN HERE (RIGHT)

GND

VAMP

EXCEPT R40 OR R41.

REMOVE R12, R3, R18, R42, C6,

R40

R41

U3

AD8351

C15, AND C18.

10kΩ

10kΩ

PWDN 1

INHI 3

RGP1 2

C28

0.1μF

AMP IN

AMP

VAMP

GND

GND

1

1Q4

1Q3

1Q2

GND

CC

1D4

1D3

GND

1D2

D2X

D1X

D0X

GND

LSB

1Q1

1OE
1

1D1

1CLK

48

CLKLAT/DAC

OUT

IN

GND

POWER DOWN

USE R40 OR R41

INLO 4

C35

R19

50Ω

R34

1.2kΩ

RPG2 5

R33

25Ω

0.10μF
R35

25Ω

GND

GND

GND

Rev. B | Page 28 of 36

AD9236

C40

0.001μF

03066-A-052

C37

C46

0.1μF

10μF

DRVDD

C20

10μF

VDL

C48

C41

C47

C1

C39

C38

C36

C34

C31

C30

GND

C49

0.001μF

0.001μF

0.1μF

0.1μF

0.001μF

0.001μF

0.1μF

0.1μF

0.1μF

0.001μF

C2

10μF

GND

0.1μF

VAMP

LATCH BYPASSING

GND

SCHEMATIC SHOWS TWO GATE DELAY SETUP.

FOR ONE DELAY, REMOVE R22 AND R37 AND

ATTACH Rx (Rx = 0Ω).

R23

367

1Y

A

B

1

1

1

245

R32

2Y

A

2

GND

1kΩ

ENCX

74VCX86

Rx

R37

0Ω

8

GND

B

2

DNP

25Ω

CLKLAT/DAC

R22

0Ω

DR

VDL

14

11

PWR

4Y

3Y

A

3
9

B

3
10

GND

U5

A

B

4

4

12

13

R20

1kΩ

GND

R21

1kΩ

GND

R24

1kΩ

GND

E51

CLK

R28

ENC

E50

R27

0Ω

ENCX

0Ω

ENC

C14

0.001μF

C33

0.1μF

C32

0.001μF

C25

10μF

AVDD

C3

10μF

DRVDD AVDD

C4

C10

10μF

10μF

VDL

GND

GND

ANALOG BYP AS SING DIGITAL BYPASSING LATCH BYPASSING

CLOCK TIMING ADJUSTMENTS

FOR A DIRECT ENCODE USE R27

FOR A BUFFERED ENCODE USE R28

DUT BYP AS SING

E52 E53

VDL

VDL

R31

1kΩ

VDL

C43

0.1μF

ENCODE

J2

E31 E35

R30

R29

VDL

E43 E44

1kΩ

GND

50Ω

GND

GND

VDL

Figure 50. LFCSP Evaluation Board Schematic, Clock Input

Rev. B | Page 29 of 36

AD9236

03066-0-055

03066-0-053

Figure 51. LFCSP Evaluation Board Layout, Primary Side

03066-0-054

Figure 52. LFCSP Evaluation Board Layout, Secondary Side

Figure 53. LFCSP Evaluation Board Layout, Ground Plane

03066-0-056

Figure 54. LFCSP Evaluation Board Layout, Power Plane

Rev. B | Page 30 of 36

AD9236

Figure 55. LFCSP Evaluation Board Layout, Primary Silkscreen

03066-0-057

Figure 56. LFCSP Evaluation Board Layout, Secondary Silkscreen

03066-0-058

Rev. B | Page 31 of 36

AD9236

Table 12. LFCSP Evaluation Board Bill of Materials

Recommended

Item Qty. Omit1Reference Designator Device Package Value

18 C1, C5, C7, C8, C9, C11, C12,

1

Chip Capacitors 0603 0.1 μF

Vendor/Part No.

C13, C15, C16, C31, C33, C34,
C36, C37, C41, C43, C47

8 C6, C18, C27, C17, C28,

C35, C45, C44

8 C2, C3, C4, C10, C20,

2

Tantalum Capacitors TAJC 10 μF

C22, C25, C29

2 C46, C24

3 8 C14, C30, C32, C38,

Chip Capacitors 0603 0.001 μF

C39, C40, C48, C49

4 1 C19 Chip Capacitor 0603 20 pF

1 C26

5

Chip Capacitors 0603 10 pF

2 C21, C23

9 E31, E35, E43, E44,

6

Headers EHOLE Jumper Blocks

E50, E51, E52, E53

2 E1, E45

7 2 J1, J2 SMA Connectors/50 Ω SMA

8 1 L1 Inductor 0603 10 nH Coilcraft/0603CS-

10NXGBU

9 1 P2 Terminal Block TB6 Wieland/25.602.2653.0,

z5-530-0625-0

10 1 P12 Header Dual 20-Pin RT Angle HEADER40 Digi-Key S2131-20-ND

5 R3, R12, R23, R28, RX 11

Chip Resistors 0603 0 Ω

6 R37, R22, R42, R16, R17, R27

12 2 R4, R15 Chip Resistors 0603 33 Ω

13 14 R5, R6, R7, R8, R13, R20,

Chip Resistors 0603 1 kΩ
R21, R24, R25, R26, R30,
R31, R32, R36

14 2 R10, R11 Chip Resistors 0603 36 Ω

1 R29 15

Chip Resistor 0603 50 Ω

1 R19

16 2 RP1, RP2 Resistor Pack R_742 220 Ω Digi-Key

CTS/742C163221JTR

17 1 T1 ADT1-1WT AWT1-1T Mini-Circuits

18 1 U1 74LVTH162374 CMOS Register TSSOP-48

19 1 U4 AD9236BCP ADC (DUT) CSP-32 Analog Devices, Inc. X

20 1 U5 74VCX86M SOIC-14 Fairchild

21 1 PCB AD92XXBCP/PCB PCB Analog Devices, Inc. X

22 1 U3 AD8351 Op Amp MSOP-8 Analog Devices, Inc. X

23 1 T2 M/A-COM Transformer ETC1-1-13 1-1 TX M/A-COM/ETC1-1-13

24 5 R9, R1, R2, R38, R39 Chip Resistors 0603 SELECT

25 4 R18, R14, R33, R35 Chip Resistors 0603 25 Ω

26 2 R40, R41 Chip Resistors 0603 10 kΩ

27 1 R34 Chip Resistor 1.2 kΩ

81 35

To ta l

1

These items are included in the PCB design, but are omitted at assembly.

Supplied
by ADI

Rev. B | Page 32 of 36

AD9236

C

Y

OUTLINE DIMENSIONS

9.80

9.70

9.60

PIN 1

0.15

0.05

OPLANARIT

0.10

28

0.65
BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AE

1.20 MAX

SEATING

PLANE

15

4.50

4.40

4.30

0.20

0.09

6.40 BSC

8°
0°

0.75

0.60

0.45

141

Figure 57. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

0.08

0.60 MAX

25

24

EXPOSED

PAD

(BOTTOM VIEW)

17

16

32

8

9

1

3.50 REF

PIN 1
INDICATOR

3.25

3.10 SQ

2.95

0.25 MIN

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING
PLANE

5.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

4.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

Figure 58. 32-Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

Rev. B | Page 33 of 36

AD9236

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9236BRU-80 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9236BRURL7-80 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9236BRUZ-80
AD9236BRUZRL7-80
AD9236BCP-80
AD9236BCPRL7-80
AD9236BCPZ-80
AD9236BCPZRL7-80
AD9236BRU-80EB TSSOP Evaluation Board
AD9236BCP-80EB

1

Z = Pb-free part.

2

It is recommended that the exposed paddle be soldered to the ground plane for the LFCSP. There is an increased reliability of the solder joints, and the maximum

thermal capability of the package is achieved with the exposed paddle soldered to the customer board.

1

1

2

2

1, 2

1, 2

2

–40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
–40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
–40°C to +85°C 32-Lead Lead Frame Chip Scale (LFCSP_VQ) CP-32-2
–40°C to +85°C 32-Lead Lead Frame Chip Scale (LFCSP_VQ) CP-32-2
–40°C to +85°C 32-Lead Lead Frame Chip Scale (LFCSP_VQ) CP-32-2
–40°C to +85°C 32-Lead Lead Frame Chip Scale (LFCSP_VQ) CP-32-2

LFCSP Evaluation Board

Rev. B | Page 34 of 36

AD9236

NOTES

Rev. B | Page 35 of 36

AD9236

NOTES

© 2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03066-0-1/06(B)

Rev. B | Page 36 of 36