12-Bit, 20/40/65 MSPS
FEATURES
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 70 dBc to Nyquist at 65 MSPS
SFDR = 85 dBc to Nyquist at 65 MSPS
Low power: 300 mW at 65 MSPS
Differential input with 500 MHz bandwidth
On-chip reference and SHA
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
IS-95, CDMA-One, IMT-2000
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
VIN+
VIN–
REFT
REFB
VREF
SENSE
3 V A/D Converter
FUNCTIONAL BLOCK DIAGRAM
DRVDD
8-STAGE
1 1/2-BIT
PIPELINE
12
MODE
SELECT
SHA
REF
SELECT
AVDD
A/D
AGND
MDAC1
4 16
CORRECTION LOGIC
OUTPUT BUFFERS
AD9235
CLOCK
DUTY CYCLE
STABILIZER
0.5V
CLK PDWN MODE
Figure 1.
AD9235
A/D
3
OTR
D11
D0
DGND
02461-001
GENERAL DESCRIPTION
The AD9235 is a family of monolithic, single 3 V supply, 12-bit,
20/40/65 MSPS analog-to-digital converters (ADCs). This
family features a high performance sample-and-hold amplifier
(SHA) and voltage reference. The AD9235 uses a multistage
differential pipelined architecture with output error correction
logic to provide 12-bit accuracy at 20/40/65 MSPS data rates
and guarantee no missing codes over the full operating
temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist
rate. Combined with power and cost savings over previously
available ADCs, the AD9235 is suitable for applications in
communications, imaging, and medical ultrasound.
A single-ended clock input is used to control all internal
conversion cycles. A duty cycle stabilizer (DCS) compensates
for wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
can be used with the most significant bit to determine low or
high overflow.
Fabricated on an advanced CMOS process, the AD9235 is available in a 28-lead TSSOP and a 32-lead LFCSP and is specified
over the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9235 operates from a single 3 V power supply and
features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families.
2. Operating at 65 MSPS, the AD9235 consumes a low 300 mW.
3. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz and can be configured for
single-ended or differential operation.
4. The AD9235 pinout is similar to the AD9214-65, a 10-bit,
65 MSPS ADC. This allows a simplified upgrade path from
10 bits to 12 bits for 65 MSPS systems.
5. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
6. The OTR output bit indicates when the signal is beyond the
selected input range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
AD9235
TABLE OF CONTENTS
Specifications..................................................................................... 3
Applying the AD9235 .................................................................... 15
DC Specifications ......................................................................... 3
Digital Specifications ................................................................... 4
Switching Specifications .............................................................. 4
AC Specifications.......................................................................... 5
Absolute Maximum Ratings............................................................ 7
Explanation of Test Levels........................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Definitions of Specifications........................................................... 9
Equivalent Circuits......................................................................... 10
Typical Performance Characteristics ........................................... 11
REVISION HISTORY
10/04—Data Sheet changed from Rev. B to Rev. C
Changes to Format ............................................................. Universal
Changes to Specifications.................................................................3
Changes to the Ordering Guide.................................................... 37
5/03—Data Sheet changed from Rev. A to Rev. B
Added CP-32 Package (LFCSP)........................................Universal
Changes to Several Pin Names .........................................Universal
Changes to Features...........................................................................1
Changes to Product Description .....................................................1
Changes to Product Highlights........................................................1
Changes to Specifications.................................................................2
Replaced Figure 1 ..............................................................................3
Changes to Absolute Maximum Ratings........................................5
Changes to Ordering Guide.............................................................5
Changes to Pin Function Descriptions...........................................6
New Definitions of Specifications Section .....................................7
Changes to TPCs 1 to 12...................................................................9
Changes to Theory of Operation Section.................................... 13
Theory of Operation.................................................................. 15
Analog Input............................................................................... 15
Clock Input Considerations...................................................... 16
Power Dissipation and Standby Mode .................................... 17
Digital Outputs ........................................................................... 18
Volt a ge R e fe r e nc e ....................................................................... 18
Operational Mode Selection ..................................................... 19
TSSOP Evaluation Board .......................................................... 19
LFCSP Evaluation Board........................................................... 20
Outline Dimensions....................................................................... 36
Ordering Guide .......................................................................... 37
Changes to Analog Input Section..................................................13
Changes to Single-ended Input Configuration Section .............14
Replaced Figure 8 ............................................................................14
Changes to Clock Input Considerations Section ........................14
Changes to Table I ...........................................................................15
Changes to Power Dissipation and Standby Mode Section .......15
Changes to Digital Outputs Section..............................................15
Changes to Timing Section............................................................15
Changes to Figure 13.......................................................................16
Changes to Figures 16 to 26...........................................................17
Added LFCSP Evaluation Board Section .....................................17
Inserted Figures 27 to 35 ................................................................25
Added Table III................................................................................30
Updated Outline Dimensions........................................................31
8/02—Data Sheet changed from Rev. 0 to Rev. A
Updated RU-28 Package................................................................ 24
Rev. C | Page 2 of 40
AD9235
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, T
unless otherwise noted.
Table 1.
Test
Parameter Temp
Level
AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65
Min Typ Max Min Typ Max Min Typ Max
RESOLUTION Full VI 12 12 12 Bits
ACCURACY
No Missing Codes Guaranteed Full VI 12 12 12 Bits
Offset Error Full VI ±0.30 ±1.20 ±0.50 ±1.20 ±0.50 ±1.20 % FSR
Gain Error
Differential Nonlinearity (DNL)
1
Full VI ±0.30 ±2.40 ±0.50 ±2.50 ±0.50 ±2.60 % FSR
2
Full IV ±0.35 ±0.65 ±0.35 ±0.75 ±0.40 ±0.80 LSB
25°C I ±0.35 ±0.35 ±0.35 LSB
Integral Nonlinearity (INL)2 Full IV ±0.45 ±0.80 ±0.50 ±0.90 ±0.70 ±1.30 LSB
25°C I ±0.40 ±0.40 ±0.45 LSB
TEMPERATURE DRIFT
Offset Error Full V ±2 ±2 ±3 ppm/°C
Gain Error Full V ±12 ±12 ±12 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) Full VI ±5 ±35 ±5 ±35 ±5 ±35 mV
Load Regulation @ 1.0 mA Full V 0.8 0.8 0.8 mV
Output Voltage Error (0.5 V Mode) Full V ±2.5 ±2.5 ±2.5 mV
Load Regulation @ 0.5 mA Full V 0.1 0.1 0.1 mV
INPUT REFERRED NOISE
VREF = 0.5 V 25°C V 0.54 0.54 0.54 LSB rms
VREF = 1.0 V 25°C V 0.27 0.27 0.27 LSB rms
ANALOG INPUT
Input Span, VREF = 0.5 V Full IV 1 1 1 V p-p
Input Span, VREF = 1.0 V Full IV 2 2 2 V p-p
Input Capacitance
3
Full V 7 7 7 pF
REFERENCE INPUT RESISTANCE Full V 7 7 7 kΩ
POWER SUPPLIES
Supply Voltages
AVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V
DRVDD Full IV 2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 V
Supply Current
IAVDD2 Full V 30 55 100 mA
IDRVDD2 Full V 2 5 7 mA
PSRR Full V ±0.01 ±0.01 ±0.01 % FSR
POWER CONSUMPTION
DC Input
4
Full V 90 165 300 mW
Sine Wave Input2 Full VI 95 110 180 205 320 350 mW
Standby Power
5
Full V 1.0 1.0 1.0 mW
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2
Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to for the equivalent analog input structure. Figure 5
4
Measured with dc input at maximum clock rate.
5
Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).
MIN
to T
MAX
,
Unit
Rev. C | Page 3 of 40
AD9235
DIGITAL SPECIFICATIONS
Table 2.
Test
Parameter Temp
Level
LOGIC INPUTS
High Level Input Voltage Full IV 2.0 2.0 2.0 V
Low Level Input Voltage Full IV 0.8 0.8 0.8 V
High Level Input Current Full IV –10 +10 –10 +10 –10 +10 µA
Low Level Input Current Full IV –10 +10 –10 +10 –10 +10 µA
Input Capacitance Full V 2 2 2 pF
LOGIC OUTPUTS
1
DRVDD = 3.3 V
High-Level Output Voltage Full IV 3.29 3.29 3.29 V
(IOH = 50 µA)
High-Level Output Voltage Full IV 3.25 3.25 3.25 V
(IOH = 0.5 mA)
Low-Level Output Voltage Full IV 0.2 0.2 0.2 V
(IOL = 1.6 mA)
Low-Level Output Voltage Full IV 0.05 0.05 0.05 V
(IOL = 50 µA)
DRVDD = 2.5 V
High-Level Output Voltage Full IV 2.49 2.49 2.49 V
(IOH = 50 µA)
High-Level Output Voltage Full IV 2.45 2.45 2.45 V
(IOH = 0.5 mA)
Low-Level Output Voltage Full IV 0.2 0.2 0.2 V
(IOL = 1.6 mA)
Low-Level Output Voltage Full IV 0.05 0.05 0.05 V
(IOL = 50 µA)
1
Output voltage levels measured with 5 pF load on each output.
SWITCHING SPECIFICATIONS
Table 3.
Test
Parameter Temp
CLOCK INPUT PARAMETERS
Maximum Conversion Rate Full VI 20 40 65 MSPS
Minimum Conversion Rate Full V 1 1 1 MSPS
CLK Period Full V 50.0 25.0 15.4 ns
CLK Pulse-Width High
1
Full V 15.0 8.8 6.2 ns
CLK Pulse-Width Low1 Full V 15.0 8.8 6.2 ns
DATA OUTPUT PARAMETERS
Output Delay2 (tPD) Full V 3.5 3.5 3.5 ns
Pipeline Delay (Latency) Full V 7 7 7 Cycles
Aperture Delay (tA) Full V 1.0 1.0 1.0 ns
Aperture Uncertainty Jitter (tJ) Full V 0.5 0.5 0.5 ps rms
Wake-Up Time
3
Full V 3.0 3.0 3.0 ms
OUT-OF-RANGE RECOVERY TIME Full V 1 1 2 Cycles
1
For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models.
2
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
3
Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Level
AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65
Min Typ Max Min Typ Max Min Typ Max
AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65
Min Typ Max Min Typ Max Min Typ Max
Unit
Unit
Rev. C | Page 4 of 40
AD9235
A
G
NALO
INPUT
DATA
CLK
OUT
N–1
N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N
N+1
N
N+2
t
A
N+3
N+4
t
PD
N+6
N+5
= 6.0ns MAX
2.0ns MIN
N+7
N+8
02461-002
Figure 2. Timing Diagram
AC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, AIN = –0.5 dBFS, 1.0 V internal reference, T
unless otherwise noted.
Table 4.
AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65
Parameter Temp Test Level Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO
f
= 2.4 MHz 25°C V 70.8 70.6 70.5 dBc
INPUT
f
= 9.7 MHz Full IV 70.0 70.4 dBc
INPUT
25°C I 70.6 dBc
f
= 19.6 MHz Full IV 69.9 70.3 dBc
INPUT
25°C I 70.4 dBc
f
= 32.5 MHz Full IV 68.7 69.7 dBc
INPUT
25°C I 70.1 dBc
f
= 100 MHz 25°C V 68.7 68.5 68.3 dBc
INPUT
SIGNAL-TO-NOISE RATIO
AND DISTORTION
f
= 2.4 MHz 25°C V 70.6 70.5 70.4 dBc
INPUT
f
= 9.7 MHz Full IV 69.9 70.3 dBc
INPUT
25°C I 70.5 dBc
f
= 19.6 MHz Full IV 69.7 70.2 dBc
INPUT
25°C I 70.3 dBc
f
= 32.5 MHz Full IV 68.3 69.5 dBc
INPUT
25°C I 69.9 dBc
f
= 100 MHz 25°C V 68.6 68.3 67.8 dBc
INPUT
TOTAL HARMONIC DISTORTION
f
= 2.4 MHz 25°C V –88.0 –89.0 –87.5 dBc
INPUT
f
= 9.7 MHz Full IV –86.0 –79.0 dBc
INPUT
25°C I –87.4 dBc
f
= 19.6 MHz Full IV –85.5 –79.0 dBc
INPUT
25°C I –86.0 dBc
f
= 32.5 MHz Full IV –81.8 –74.0 dBc
INPUT
25°C I –82.0 dBc
f
= 100 MHz 25°C V –84.0 –82.5 –78.0 dBc
INPUT
WORST HARMONIC
(SECOND OR THIRD)
f
= 9.7 MHz Full IV –90.0 –80.0 dBc
INPUT
f
= 19.6 MHz Full IV –90.0 –80.0 dBc
INPUT
f
= 32.5 MHz Full IV –83.5 –74.0 dBc
INPUT
MIN
to T
MAX
,
Rev. C | Page 5 of 40
AD9235
AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65
Parameter Temp Test Level Min Typ Max Min Typ Max Min Typ Max Unit
SPURIOUS-FREE DYNAMIC RANGE
f
= 2.4 MHz 25°C V 92.0 92.0 92.0 dBc
INPUT
f
= 9.7 MHz Full IV 80.0 88.5 dBc
INPUT
25°C I 91.0 dBc
f
= 19.6 MHz Full IV 80.0 89.0 dBc
INPUT
25°C I 90.0 dBc
f
= 32.5 MHz Full IV 74.0 83.0 dBc
INPUT
25°C I 85.0 dBc
f
= 100 MHz 25°C V 84.0 85.0 80.5 dBc
INPUT
Rev. C | Page 6 of 40
AD9235
ABSOLUTE MAXIMUM RATINGS
Table 5.
With
Pin Name
ELECTRICAL
AVDD AGND –0.3 +3.9 V
DRVDD DGND –0.3 +3.9 V
AGND DGND –0.3 +0.3 V
AVDD DRVDD –3.9 +3.9 V
Digital
Outputs
CLK, MODE AGND –0.3 AVDD + 0.3 V
VIN+, VIN– AGND –0.3 AVDD + 0.3 V
VREF AGND –0.3 AVDD + 0.3 V
SENSE AGND –0.3 AVDD + 0.3 V
REFB, REFT AGND –0.3 AVDD + 0.3 V
PDWN AGND –0.3 AVDD + 0.3 V
ENVIRONMENTAL
Operating Temperature –40 +85 °C
Junction Temperature 150 °C
Lead Temperature (10 sec) 300 °C
Storage Temperature –65 +150 °C
Respect to
DGND –0.3 DRVDD + 0.3 V
1
Min Max Unit
1
Typical thermal impedances (28-lead TSSOP), θJA = 67.7°C/W; (32-lead
LFCSP), θ
a 4-layer board in still air, in accordance with EIA/JESD51-1.
= 32.5°C/W, θJC = 32.71°C/W. These measurements were taken on
JA
Absolute maximum ratings are limiting values to be applied
individually and beyond which the serviceability of the circuit
may be impaired. Functional operability is not necessarily
implied. Exposure to absolute maximum rating conditions for
an extended period of time may affect device reliability.
EXPLANATION OF TEST LEVELS
Test
Levels Description
I 100% production tested.
II
III Sample tested only.
IV
V Parameter is a typical value only.
VI
100% production tested at 25°C and sample tested at
specified temperatures.
Parameter is guaranteed by design and characterization testing.
100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation
or loss of functionality.
Rev. C | Page 7 of 40
AD9235
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
OTR
2
MODE
3
SENSE
4
VREF
5
REFB
REFT
AVDD
AGND
VIN+
VIN–
AGND
AVDD
CLK D1
PDWN
6
(Not to Scale)
7
8
9
10
11
12
13
14
AD9235
TOP VIEW
Figure 3. 28-Lead TSSOP Pin Configuration
28
D11 (MSB)
27
D10
26
D9
25
D8
24
DRVDD
23
DGND
22
D7
21
D6
20
D5
19
D4
18
D3
17
D2
16
15
D0 (LSB)
02461-003
AVDD
VIN+
VIN–
AGND
32
31302928272625
1
DNC
CLK
DNC
PDWN
DNC
DNC
(LSB)D0
D1
DNC = DO NOT CONNECT
2
3
4
5
6
7
8
PIN 1
INDICATOR
AD9235
TOP VIEW
(Not to Scale)
9
101112
D5
D4
D3
D2
Figure 4. 32-Lead LFCSP Pin Configuration
AVDD
AGND
141516
13
D7
D6
REFB
REFT
DGND
DRVDD
VREF
24
23
SENSE
22
MODE
21
OTR
20
D11(MSB)
19
D10
18
D9
17
D8
02461-004
Table 6. Pin Function Descriptions
Pin No.
28-Lead TSSOP
Pin No.
32-Lead LFCSP
Mnemonic Description
1 21 OTR Out-of-Range Indicator.
2 22 MODE Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection.
3 23 SENSE Reference Mode Selection.
4 24 VREF Voltage Reference Input/Output.
5 25 REFB Differential Reference (−).
6 26 REFT Differential Reference (+).
7, 12 27, 32 AVDD Analog Power Supply.
8, 11 28, 31 AGND Analog Ground.
9 29 VIN+ Analog Input Pin (+).
10 30 VIN– Analog Input Pin (−).
13 2 CLK Clock Input Pin.
14 4 PDWN Power-Down Function Selection (Active High).
15 to 22, 25 to 28 7 to 14, 17 to 20 D0 (LSB) to D11 (MSB) Data Output Bits.
23 15 DGND Digital Output Ground.
24 16 DRVDD Digital Output Driver Supply. Must be decoupled to DGND with a minimum.
0.1 µF capacitor. Recommended decoupling is 0.1 µF in parallel with 10 µF.
1, 3, 5, 6 DNC Do Not Connect.
Rev. C | Page 8 of 40
AD9235
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay (t
)
A
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Aperture Jitter (t
)
J
The sample-to-sample variation in aperture delay.
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1 ½ LSBs beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed no
missing codes to 12-bit resolution indicates that all 4096 codes
must be present over all operating ranges.
Offset Error
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN–. Offset error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value ½ LSB
above negative full scale. The last transition should occur at an
analog value 1 ½ LSB below the positive full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at T
MIN
or T
MAX
.
Power Supply Rejection Ratio
The change in full scale from the value with the supply
at the minimum limit to the value with the supply at its
maximum limit.
1
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal.
Signal-to-Noise and Distortion (SINAD)1
The ratio of the rms signal amplitude (set 0.5 dB below full
scale) to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but
excluding dc.
Effective Number of Bits (ENOB)
The ENOB for a device for sine wave inputs at a given input
frequency can be calculated directly from its measured SINAD
using the following formula
N = (SINAD − 1.76)/6.02
1
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude (set at 0.5 dB below full
scale) to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six
harmonics and dc.
1
Spurious-Free Dynamic Range (SFDR)
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
1
Two -Ton e SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Clock Pulse Width and Duty Cycle
Pulse-width high is the minimum amount of time that the
clock pulse should be left in the Logic 1 state to achieve rated
performance. Pulse-width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the
guaranteed limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Output Propagation Delay (t
)
PD
The delay between the clock logic threshold and the time when
all bits are within valid logic levels.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
1
AC specifications may be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
Rev. C | Page 9 of 40
AD9235
EQUIVALENT CIRCUITS
AVDD
DRVDD
VIN+, VIN–
02461-005
Figure 5. Equivalent Analog Input Circuit
AVDD
MODE
20kΩ
Figure 6. Equivalent MODE Input Circuit
02461-006
Figure 7. Equivalent Digital Output Circuit
AVDD
CLK,
PDWN
Figure 8. Equivalent Digital Input Circuit
D11–D0,
OTR
02461-007
02461-008
Rev. C | Page 10 of 40
AD9235
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V, f
unless otherwise noted.
0
–20
–40
–60
–80
MAGNITUDE (dBFS)
–100
–120
FREQUENCY (MHz)
Figure 9. Single Tone 8K FFT with f
0
–20
–40
–60
–80
MAGNITUDE (dBFS)
–100
–120
FREQUENCY (MHz)
Figure 10. Single Tone 8K FFT with f
0
–20
–40
–60
–80
MAGNITUDE (dBFS)
–100
–120
FREQUENCY (MHz)
Figure 11. Single Tone 8K FFT with f
= 65 MSPS with DCS disabled, TA = 25°C, 2 V differential input, AIN = −0.5 dBFS, VREF = 1.0 V,
SAMPLE
SNR = 70.3dBc
SINAD = 70.2dBc
ENOB = 11.4 BITS
THD = –86.3dBc
SFDR = 89.9dBc
= 10 MHz
IN
SNR = 69.4dBc
SINAD = 69.1dBc
ENOB = 11.2 BITS
THD = –81.0dBc
SFDR = 83.8dBc
= 70 MHz
IN
SNR = 68.5dBc
SINAD = 66.5dBc
ENOB = 10.8 BITS
THD = –71.0dBc
SFDR = 71.2dBc
= 100 MHz
IN
32.50 6.5 13.0 19.5 26.0
02461-009
91.065.0 71.5 78.0 84.5
02461-010
130.097.5 104.0 110.5 117.0 123.5
02461-011
100
SFDR (2V DIFF)
95
90
85
SNR/SFDR (dBc)
80
75
70
65
60
55
50
SNR (2V DIFF)
SFDR (2V SE)
SAMPLE RATE (MSPS)
SNR (2V SE)
Figure 12. AD9235-65: Single Tone SNR/SFDR vs.
with fIN = Nyquist (32.5 MHz)
f
CLK
100
95
90
85
80
75
70
SNR/SFDR (dBc)
65
60
55
50
SFDR (2V DIFF)
SNR (2V SE)
SFDR (2V SE)
SNR (2V DIFF)
SAMPLE RATE (MSPS)
Figure 13. AD9235-40: Single Tone SNR/SFDR vs. f
100
SFDR (2V DIFF)
95
90
85
80
75
SNR (2V SE)
70
SNR/SFDR (dBc)
65
SNR (2V DIFF)
60
55
50
SFDR (2V SE)
SAMPLE RATE (MSPS)
Figure 14. AD9235-20: Single Tone SNR/SFDR vs. f
with fIN = Nyquist (20 MHz)
CLK
with fIN = Nyquist (10 MHz)
CLK
6540 45 50 55 60
02461-012
4020 25 30 35
02461-013
200 5 10 15
02461-014
Rev. C | Page 11 of 40
AD9235
100
90
80
SFDR
SINGLE-ENDED (dBFS)
SFDR
SNR
DIFFERENTIAL (dBFS)
DIFFERENTIAL (dBc)
SFDR
DIFFERENTIAL (dBFS)
95
90
SFDR
85
70
60
SNR/SFDR (dBFS and dBc)
50
40
SFDR
SINGLE-ENDED (dBc)
SNR
SINGLE-ENDED (dBFS)
SNR
DIFFERENTIAL (dBc)
AIN (dBFS)
Figure 15. AD9235-65: Single Tone SNR/SFDR vs.
with fIN = Nyquist (32.5 MHz)
A
IN
100
SFDR
DIFFERENTIAL (dBFS)
90
SFDR
DIFFERENTIAL
(dBc)
SNR
SINGLE-ENDED
(dBFS)
SNR
SINGLE-ENDED (dBc)
AIN (dBFS)
SINGLE-ENDED (dBc)
SNR/SFDR (dBFS and dBc)
SNR
80
DIFFERENTIAL
(dBFS)
70
60
SNR
DIFFERENTIAL (dBc)
50
40
Figure 16. AD9235-40: Single Tone SNR/SFDR vs. A
100
SFDR DIFFERENTIAL (dBFS)
90
SINGLE-ENDED (dBFS)
80
SNR
DIFFERENTIAL (dBFS)
70
60
DIFFERENTIAL(dBc)
SNR/SFDR (dBFS and dBc)
50
40
SFDR
DIFFERENTIAL (dBc)
SFDR
SINGLE-ENDED(dBc)
SNR
SINGLE-ENDED (dBFS)
SNR
SNR
SINGLE-ENDED (dBc)
AIN (dBFS)
Figure 17. AD9235-20: Single Tone SNR/SFDR vs. A
SNR
SINGLE-ENDED (dBc)
0–30 –25 –20 –15 –10 –5
SFDR
SINGLE-ENDED
(dBFS)
SFDR
0–30 –25 –20 –15 –10 –5
with fIN = Nyquist (20 MHz)
IN
SFDR
0–30 –25 –20 –15 –10 –5
with fIN = Nyquist (10 MHz)
IN
02461-015
02461-016
02461-017
80
75
SNR/SFDR (dBc)
70
65
95
90
85
80
75
SNR/SFDR (dBc)
70
65
95
90
85
80
75
SNR/SFDR (dBc)
70
65
SNR
INPUT FREQUENCY (MHz)
Figure 18. AD9235-65: SNR/SFDR vs. f
SFDR
SNR
INPUT FREQUENCY (MHz)
Figure 19. AD9235-40: SNR/SFDR vs. f
SFDR
SNR
INPUT FREQUENCY (MHz)
Figure 20. AD9235-20: SNR/SFDR vs. f
1250 25 50 75 100
02461-018
IN
1250 25 50 75 100
02461-019
IN
1250 25 50 75 100
02461-020
IN
Rev. C | Page 12 of 40
AD9235
MAGNITUDE (dBFS)
–20
–40
–60
–80
–100
0
SNR = 64.6dBFS
SFDR = 81.6dBFS
95
90
85
80
75
SNR/SFDR (dBFS)
70
65
2V SFDR
1V SFDR
2V SNR
1V SNR
–120
FREQUENCY (MHz)
Figure 21. Dual Tone 8K FFT with f
0
–20
–40
–60
–80
MAGNITUDE (dBFS)
–100
–120
FREQUENCY (MHz)
Figure 22. Dual Tone 8K FFT with f
0
–20
–40
–60
–80
MAGNITUDE (dBFS)
–100
= 45 MHz and f
IN1
= 69 MHz and f
IN1
= 46 MHz
IN2
SNR = 64.3dBFS
SFDR = 81.1dBFS
= 70 MHz
IN2
SNR = 62.5dBFS
SFDR = 75.6dBFS
65.032.5 39.0 45.5 52.0 58.5
02461-021
97.565.0 71.5 78.0 84.5 91.0
02461-022
60
AIN (dBFS)
Figure 24. Dual Tone SNR/SFDR vs. A
95
90
85
80
75
SNR/SFDR (dBFS)
70
65
60
2V SFDR
1V SFDR
2V SNR
1V SNR
AIN (dBFS)
Figure 25. Dual Tone SNR/SFDR vs. A
95
90
85
80
75
SNR/SFDR (dBFS)
70
65
2V SFDR
1V SFDR
2V SNR
1V SNR
with f
IN
with f
IN
= 45 MHz and f
IN1
= 69 MHz and f
IN1
–6–24 –21 –18 –15 –12 –9
= 46 MHz
IN2
–6–24 –21 –18 –15 –12 –9
= 70 MHz
IN2
02461-024
02461-025
–120
FREQUENCY (MHz)
Figure 23. Dual Tone 8K FFT with f
= 144 MHz and f
IN1
= 145 MHz
IN2
162.0130.0 136.5 143.0 149.5 156.0
02461-023
Rev. C | Page 13 of 40
60
Figure 26. Dual Tone SNR/SFDR vs. A
AIN (dBFS)
with f
IN
= 144 MHz and f
IN1
–6–24 –21 –18 –15 –12 –9
= 145 MHz
IN2
02461-026
AD9235
75
12.2
20
AD9235-20:
72
2V SINAD
69
66
SINAD (dBc)
63
60
AD9235-40:
2V SINAD
AD9235-20:
1V SINAD
AD9235-65:
1V SINAD
SAMPLE RATE (MSPS)
Figure 27. SINAD vs. f
90
80
70
60
50
SINAD/SFDR (dBc)
40
30
SFDR: DCS OFF
SINAD: DCS OFF
DUTY CYCLE (%)
Figure 28. SINAD/SFDR vs. Clock Duty Cycle
90
SFDR 2V DIFF
85
80
75
70
65
SINAD/SFDR (dBc)
60
55
50
SFDR 1V DIFF
SINAD 1V DIFF
SAMPLE RATE (MSPS)
Figure 29. SINAD/SFDR vs. Temperature with f
AD9235-40:
1V SINAD
with fIN = Nyquist
CLK
SFDR: DCS ON
SINAD: DCS ON
SINAD 2V DIFF
AD9235-65:
2V SINAD
60010203040 50
= 32.5 MHz
IN
15
11.7
11.2
10.7
10.2
9.7
ENOB (Bits)
02461-027
10
5
0
–5
GAIN DRAFT (ppm/°C)
–10
–15
–20
TEMPERATURE (°C)
80–40 0–20 204060
02461-030
Figure 30. A/D Gain vs. Temperature Using an External Reference
1.0
0.8
0.6
0.4
0.2
0
–0.2
INL (LSB)
–0.4
–0.6
–0.8
6535 40 45 50 55 60
02461-028
–1.0
CODE
40000 500 1000 1500 2000 2500 3000 3500
02461-031
Figure 31. Typical INL
1.0
0.8
0.6
0.4
0.2
0
–0.2
DNL (LSB)
–0.4
–0.6
–0.8
80–40–30–20–100 10203040506070
02461-029
–1.0
CODE
40000 500 1000 1500 2000 2500 3000 3500
02461-032
Figure 32. Typical DNL
Rev. C | Page 14 of 40
AD9235
APPLYING THE AD9235
THEORY OF OPERATION
The AD9235 architecture consists of a front end SHA followed
by a pipelined switched capacitor ADC. The pipelined ADC is
divided into three sections, consisting of a 4-bit first stage
followed by eight 1.5-bit stages and a final 3-bit flash. Each stage
provides sufficient overlap to correct for flash errors in the
preceding stages. The quantized outputs from each stage are
combined into a final 12-bit result in the digital correction logic.
The pipelined architecture permits the first stage to operate on a
new input sample while the remaining stages operate on
preceding samples. Sampling occurs on the rising edge
of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The outputstaging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT
The analog input to the AD9235 is a differential switched
capacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA
input can support a wide common-mode range and maintain
excellent performance, as shown in Figure 34. An input
common-mode voltage of midsupply minimizes signaldependent errors and provides optimum performance.
Referring to Figure 33, the clock signal alternatively switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s
input; therefore, the precise values are dependent upon the
application. In IF undersampling applications, any shunt
capacitors should be removed. In combination with the driving
source impedance, they would limit the input bandwidth.
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
H
T
T
H
02461-033
VIN+
VIN–
T
5pF
C
PAR
T
5pF
C
PAR
Figure 33. Switched-Capacitor SHA Input
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as:
REFT = ½(AV D D + VREF)
REFB = ½(AV D D − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the
VREF voltage.
90
85
80
75
70
SNR (dBc)
65
60
55
50
Figure 34. AD9235-65: SNR, THD vs. Common-Mode Level
SNR 35MHz 2V DIFF
THD 35MHz 2V DIFF
SNR 2.5MHz 2V DIFF
COMMON-MODE LEVEL (V)
THD 2.5MHz 2V DIFF
–90
–85
–80
–75
–70
–65
–60
–55
–50
3.00 0.5 1.0 1.5 2.0 2.5
THD (dBc)
02461-034
Rev. C | Page 15 of 40
AD9235
2
2
The internal voltage reference can be pin-strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within the same range as
discussed in the Internal Reference Connection section. Maximum SNR performance is achieved with the AD9235 set to the
largest input span of 2 V p-p. The relative SNR degradation is
3 dB when changing from 2 V p-p mode to 1 V p-p mode.
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels
are defined as:
VCM
VCM
The minimum common-mode input level allows the AD9235 to
accommodate ground-referenced inputs.
Although optimum performance is achieved with a differential
input, a single-ended source may be driven into VIN+ or VIN–.
In this configuration, one input accepts the signal, while the
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal may be
applied to VIN+ while a 1 V reference is applied to VIN–. The
AD9235 then accepts an input signal varying between 2 V and
0 V. In the single-ended configuration, distortion performance
may degrade significantly as compared to the differential case.
However, the effect is less noticeable at lower input frequencies and
in the lower speed grade models (AD9235-40 and AD9235-20).
Differential Input Configurations
As previously detailed, optimum performance is achieved while
driving the AD9235 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9235. This is especially true in IF
undersampling applications where frequencies in the 70 MHz to
100 MHz range are being sampled. For these applications,
= VREF/2
MIN
= (AV D D + VREF)/2
MAX
1Vp-p
49.9Ω
1kΩ
1kΩ0.1µF
Figure 35. Differential Input Configuration Using the AD8138
499Ω
523Ω
499Ω
AD8138
499Ω
22Ω
15pF
22Ω
15pF
AVDD
VIN+
AD9235
VIN–
AGND
02461-035
differential transformer coupling is the recommended input
configuration, as shown in Figure 36.
22Ω
15pF
Vp-p
49.9Ω
0.1µF
Figure 36. Differential Transformer-Coupled Configuration
1kΩ
1kΩ
22Ω
15pF
AVDD
VIN+
AD9235
VIN–
AGND
02461-036
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is degradation in SFDR and in distortion performance due to the large
input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance. Figure 37 details a typical singleended input configuration.
1kΩ
0.33µF
Vp-p
49.9Ω
0.1µF10µF
Figure 37. Single-Ended Input Configuration
1kΩ
1kΩ
1kΩ
22Ω
15pF
22Ω
15pF
AVDD
VIN+
AD9235
VIN–
AGND
02461-037
CLOCK INPUT CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result, may be sensitive to clock duty cycle. Commonly a 5% tolerance is required
on the clock duty cycle to maintain dynamic performance characteristics. The AD9235 contains a clock duty cycle stabilizer
(DCS) that retimes the nonsampling edge, providing an internal
clock signal with a nominal 50% duty cycle. This allows a wide
range of clock input duty cycles without affecting the performance of the AD9235. As shown in Figure 30, noise and distortion performance are nearly flat over a 30% range of duty cycle.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 100 clock cycles to
allow the DLL to acquire and lock to the new rate.
Rev. C | Page 16 of 40
AD9235
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (f
) due only to aperture jitter (tJ) can be
INPUT
calculated by
SNR Degradation = −20 × log
In the equation, the rms aperture jitter, t
[2π × f
10
× tJ]
INPUT
, represents the root-
J
sum square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9235. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 38, the power dissipated by the AD9235 is
proportional to its sample rate. The digital power dissipation
does not vary substantially between the three speed grades
because it is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current can be calculated as
= V
I
DRVDD
where N is the number of output bits, 12 in the case of the
AD9235. This maximum current occurs when every output bit
switches on every clock cycle, i.e., a full-scale square wave at the
Nyquist frequency, f
established by the average number of output bits switching,
which is determined by the encode rate and the characteristics
of the analog input signal.
DRVDD
× C
× f
CLK
× N
LOAD
/2. In practice, the DRVDD c urrent is
CLK
325
300
275
250
225
200
175
150
TOTAL POWER (mW)
125
100
75
AD9235-20
50
Figure 38. Total Power vs. Sample Rate with f
AD9235-65
AD9235-40
SAMPLE RATE (MSPS)
= 10 MHz
IN
600 1020304050
02461-038
For the AD9235-20 speed grade, the digital power consumption
can represent as much as 10% of the total dissipation. Digital
power consumption can be minimized by reducing the capacitive load presented to the output drivers. The data in Figure 38
was taken with a 5 pF load on each output driver.
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases linearly with the clock
frequency.
By asserting the PDWN pin high, the AD9235 is placed in
standby mode. In this state, the ADC typically dissipates 1 mW
if the CLK and analog inputs are static. During standby, the
output drivers are placed in a high impedance state. Reasserting
the PDWN pin low returns the AD9235 into its normal
operational mode.
Low power dissipation in standby mode is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 µF and 10 µF decoupling capacitors on REFT
and REFB, it takes approximately 1 sec to fully discharge the
reference buffer decoupling capacitors and 3 ms to restore full
operation.
Rev. C | Page 17 of 40
AD9235
Table 7. Reference Configuration Summary
Selected Mode SENSE Voltage Internal Switch Position Resulting VREF (V) Resulting Differential Span (V p-p)
External Reference AVDD N/A N/A 2 × External Reference
Internal Fixed Reference VREF SENSE 0.5 1.0
Programmable Reference 0.2 V to VREF SENSE 0.5 × (1 + R2/R1) 2 × VREF (See Figure 40)
Internal Fixed Reference AGND to 0.2 V Internal Divider 1.0 2.0
DIGITAL OUTPUTS
The AD9235 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.
As detailed in Table 8, the data format can be selected for either
offset binary or twos complement.
Timing
The AD9235 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propagation delay (t
Figure 2 for a detailed timing diagram.
) after the rising edge of the clock signal. Refer to
PD
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as
VREF = 0.5 × (1 + R2/R1)
VIN+
+
10µF 0.1µF
SENSE
VIN–
VREF
SELECT
LOGIC
ADC
CORE
0.5V
REFT
0.1µF
0.1µF10µF
REFB
0.1µF
+
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9235;
these transients can detract from the converter’s dynamic
performance.
The lowest typical conversion rate of the AD9235 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance may degrade.
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9235. The input range can be adjusted by varying the reference voltage applied to the AD9235, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly.
If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap
(common-mode voltage).
Internal Reference Connection
A comparator within the AD9235 detects the potential at the
SENSE pin and configures the reference into one of four possible states, which are summarized in Table 7. If SENSE is
grounded, the reference amplifier switch is connected to the
internal resistor divider (see Figure 39), setting VREF to 1 V.
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected as shown in Figure 40, the switch is again set to the
AD9235
Figure 39. Internal Reference Configuration
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
VIN+
+
10µF 0.1µF
R2
SENSE
Figure 40. Programmable Reference Configuration
VIN–
VREF
R1
SELECT
LOGIC
ADC
CORE
AD9235
0.5V
REFT
0.1µF
0.1µF10µF
REFB
0.1µF
+
02461-039
02461-040
Rev. C | Page 18 of 40
AD9235
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift
characteristics. When multiple ADCs track one another, a single
reference (internal or external) may be necessary to reduce gain
matching errors to an acceptable level. A high precision external
reference may also be selected to provide lower gain and offset
temperature drift. Figure 41 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes.
1.2
1.0
0.8
0.6
0.4
VREF ERROR (%)
0.2
0
TEMPERATURE (°C)
Figure 41. Typical VREF Drift
VREF = 1.0V
VREF = 0.5V
80–40–30–20–100 10203040506070
02461-041
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1 V.
If the internal reference of the AD9235 is used to drive multiple
converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 42
depicts how the internal reference voltage is affected by loading.
0.05
0
–0.05
–0.10
ERROR (%)
–0.15
–0.20
1V ERROR (%)
0.5V ERROR (%)
OPERATIONAL MODE SELECTION
As discussed earlier, the AD9235 can output data in either offset
binary or twos complement format. There is also a provision for
enabling or disabling the clock DCS. The MODE pin is a multilevel input that controls the data format and DCS state. The
input threshold values and corresponding mode selections are
outlined in Table 8.
Table 8. Mode Selection
MODE Voltage Data Format Duty Cycle Stabilizer
AVDD Twos Complement Disabled
2/3 AVDD Twos Complement Enabled
1/3 AVDD Offset Binary Enabled
AGND (Default) Offset Binary Disabled
The MODE pin is internally pulled down to AGND by a 20 kΩ
resistor.
TSSOP EVALUATION BOARD
The AD9235 evaluation board provides the support circuitry
required to operate the ADC in its various modes and configurations. The converter can be driven differentially, through an
AD8138 driver or a transformer, or single-ended. Separate
power pins are provided to isolate the DUT from the support
circuitry. Each input configuration can be selected by proper
connection of various jumpers (refer to the schematics). Figure 43
shows the typical bench characterization setup used to evaluate
the ac performance of the AD9235. It is critical that signal
sources with very low phase noise (<1 ps rms jitter) be used to
realize the ultimate performance of the converter. Proper filtering of the input signal, to remove harmonics and lower the integrated noise at the input, is also necessary to achieve the specified noise performance.
The AUXCLK input should be selected in applications requiring
the lowest jitter and SNR performance, i.e., IF undersampling
characterization. It allows the user to apply a clock input signal
that is 4× the target sample rate of the AD9235. A low-jitter,
differential divide-by-4 counter, the MC100LVEL33D, provides
a 1× clock output that is subsequently returned back to the CLK
input via JP9. For example, a 260 MHz signal (sinusoid) is
divided down to a 65 MHz signal for clocking the ADC. Note
that R1 must be removed with the AUXCLK interface. Lower
jitter is often achieved with this interface since many RF signal
generators display improved phase noise at higher output
frequencies and the slew rate of the sinusoidal output signal is
4× that of a 1× signal of equal amplitude.
Complete schematics and layout plots follow and demonstrate
the proper routing and grounding techniques that should be
applied at the system level.
–0.25
LOAD (mA)
Figure 42. VREF Accuracy vs. Load
3.00 0.5 1.0 1.5 2.0 2.5
02461-042
Rev. C | Page 19 of 40
AD9235
LFCSP EVALUATION BOARD
The typical bench setup used to evaluate the ac performance
of the AD9235 is similar to the TSSOP Evaluation Board
connections (refer to the schematics for connection details).
The AD9235 can be driven single-ended or differentially
through a transformer. Separate power pins are provided to
isolate the DUT from the support circuitry. Each input
configuration can be selected by proper connection of
various jumpers (refer to the schematics).
An alternative differential analog input path using an AD8351
op amp is included in the layout but is not populated in production. Designers interested in evaluating the op amp with the
ADC should remove C15, R12, and R3 and populate the op amp
circuit. The passive network between the AD8351 outputs and
the AD9235 allows the user to optimize the frequency response
of the op amp for the application.
REFIN
10MHz
REFOUT
HP8644, 2V p-p
SIGNAL SYNTHESIZER
HP8644, 2V p-p
CLOCK SYNTHESIZER
BAND-PASS
FILTER
CLOCK
DIVIDER
3V
–
S4
XFMR
INPUT
S1
CLOCK
3V
+
–
AVDD DUT
GND GND DUT
TSSOP EVALUATION BOARD
+
AVDD
AD9235
–
3V
DRVDD
+
Figure 43. TSSOP Evaluation Board Connections
3V
+
–
DVDD
DATA
J1
CAPTURE
AND
PROCESSING
02461-043
Rev. C | Page 20 of 40
AD9235
D0O
O
D1
D2O
O
D3
D4O
O
D5
D6O
O
D7
DUTAVDDIN
TB1
N
AG
TB1
AVDDIN
TB1
DDIN
DRV
TB1
AGND
TB1
P3 22
R
1
RP3 22
2
P3 22
R
3
RP3 22
4
P4 22
R
1
RP4 22
2
P4 22
R
3
P4 22
R
4
2
D
3
1
5
4
Ω
8
Ω
7
Ω
6
Ω
5
Ω
8
Ω
7
Ω
6
Ω
5
C58
22µ
25V
C47
22µF
25V
C4
22µF
25V
F
8
D0
D1
D2
D10O
D3
D
D4
D5
D6
OTRO
D7
FBEAD
L1
21
+
FBEAD
L2
21
+
FBEAD
L3
21
+
D8O
D9
11O
0.1
0.1
0.1
O
C5
C52
C53
µF
µ
µF
9
F
P5 22
R
1
RP5 22
2
P5 22
R
3
P5 22
R
4
RP6 22
1
P6 22
R
2
RP6 22
3
RP6 22
4
TP2
RED
TP1
D
RE
TP3
D
RE
Ω
8
Ω
7
Ω
6
Ω
5
Ω
8
Ω
7
Ω
6
Ω
5
JP12
JP11
D8
D9
D10
D11
OTR
DUTA
D
D
AV
D
D
AV
DUTDRV
VDD
JP13
DD
R3
10k
R4
10k
R27
5kΩ
Ω
Ω
10µF
C34
0.1
C20
10
10V
AVDD
C5
0.1
C21
10V
µF
µF
R2
1k
R17
1kΩ
R4
1kΩ
WHT
TP5
7
µF
+
5
C3
µF
0.1
C33
µF
0.1
+
C32
µF
0.1
JP7
0
Ω
JP6
JP1
2
JP2
10µF
JP22
JP23
JP25
JP24
C22
10µF
10V
+
C36
0.1
0.001
DUTA
µF
C3
µF
VDD
9
AD9235
14
10
11
12
23
24
C1
10µF
10V
7
8
3
4
5
6
2
9
D
AVD
AGN
SENSE
VREF
PDWN
FB
RE
REFT
MODE
VIN+
VIN–
AGN
D
D
AV
DGND
DD
DRV
0.1
D
U1
D
C3
WHT
TP17
SHEET 3
C50
µF
0.1
VDD
DUTA
C23
++
C38
µF
0.1
10V
0.001
C41
VIN+
VIN–
µF
1
OTR
28
1
D1
27
D10
26
D9
25
D8
22
D7
21
D6
20
D5
19
D4
18
D3
17
D2
16
D1
15
D0
13
CLK
WHT
TP6
DUTDRV
7
µF
C40
0.001
OTRO
O
D0
D1O
D2O
O
D3
D4O
O
D5
D6O
D7O
D8O
D9O
10O
D
11O
D
DUTCLK
DD
µF
DVDDIN
TB1
C14
TP4
RED
TP11
BLK
F
µ
FBEAD
L4
22
25V
C6
µF
21
+
0.1
6
DV
DD
TP9
BLK
TP12
BLK
TP10
BLK
TP13
BLK
TP15
BLK
TP14
BLK
TP16
BLK
02461-044
Figure 44. TSSOP Evaluation Board Schematic, DUT
Rev. C | Page 21 of 40
AD9235
C12
0.1µF
C4
10µF
10V
21
1
G1
19
G2 GND
A1 Y1
3
A2
4
A3
U6
5
74VHC541
A4
6
A5
7
A6
8
A7
9
A8
C11
0.1µF
C5
10µF
10V
21
1
G1
19
G2 GND
A1 Y1
3
A2
4
A3
U7
5
74VHC541
A4
6
A5
7
A6
8
A7
9
A8
+
+
AUXCLK
S5
AVDD
R12
113Ω
R14
90Ω
CLOCK
S1
R25
10kΩ
1
2
R11
49.9Ω
6
5
T1–1T
T2
1
1N5712
2
34
AVDD
1N5712
D2
D1
D0
D1
D2
D3
D4
D5
D6
D7
C27
0.1µF
AVDD
MC100LVEL33D
8
VCC
7
OUT
6
REF
5
VEE
AVDD
AVDD
R13
113Ω
R15
90Ω
U3
NC
INA
INB
INCOM
U8 DECOUPLING
C26
0.1µF
1
2
3
4
C24
0.1µF
R26
10kΩ
+
C28
10µF
10V
JP9
D8
DUTCLK
D9
D10
D11
OTR
R9
22Ω
R19
500ΩR210Ω
CW
C13
1
2
0.1µF
R1
49.9Ω
R18
500Ω
AVDD
WHT
TP7
1256
74VHC04U874VHC04
U8
U8
34
AVDD; 14
AVDD; 7
R7
22Ω
74VHC04
JP4
JP3
VCC
VCC
DVDD
2
0
DOTR
DACLK
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
HDR40RAM
HEADER RIGHT ANGLE MALE NO EJECTORS
J1
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
20
10
182
17
Y2
16
Y3
15
Y4
14
Y5
13
Y6
12
Y7
11
Y8
20
10
182
17
Y2
16
Y3
15
Y4
14
Y5
13
Y6
12
Y7
11
Y8
RP2 22
1
R
2
R
3
RP2 22
4
R
5
RP2 22
6
R
7
RP2 22
8
R
1
RP2 22
2
R
3
R
4
RP2 22
5
R
6
RP2 22
7
R
8
P2 22
P2 22
P2 22
P2 22
P2 22
P2 22
P2 22
P2 22
P2 22
Ω
DD0
16
Ω
DD1
15
Ω
DD2
14
Ω
DD3
13
Ω
DD4
12
Ω
DD5
11
Ω
DD6
10
Ω
DD7
9
Ω
DD8
16
Ω
DD9
15
Ω
DD1
14
Ω
DD11
13
Ω
12
Ω
11
Ω
10
Ω
9
U8
13 12
74VHC04
U8
11 10
AVDD
U9 DECOUPLING
C10
0.1µF
C8
10µF
10V
U8
98
74VHC04
02461-045
Figure 45. TSSOP Evaluation Board Schematic, Clock Inputs and Output Buffering
Rev. C | Page 22 of 40
AD9235
AVDD
C7
R23
1kΩ
R41
1kΩ
T2
0.1µF
JP42
JP40
JP45
R21
22Ω
C44
15pF
VIN+
C44B
R22
JP46
22Ω
JP41
JP43
C43
15pF
VIN–
AVDD
1
34
R16
1kΩ
R8
1kΩ
C25
0.33µF
C16
0.1µF
AMP INPUT
S2
1
2
C18
0.1µF
+
523Ω
499Ω
R31
49.9Ω
C19
10µF
10V
21
R34
R35
2
AB
JP8
AVDD
–IN
1
8
+IN
ALT VEE
TP8
RED
31
VCC
3
AD8138
U2
6
VEE
C15
10µF
10V
C69
0.1µF
C2
VAL
R37
499Ω
4
5
R36
499Ω
C17
VAL
21
VO+
VO–
AVDD
2
VOC
SINGLE INPUT
S3
R32
1kΩ
C8
R33
0.1µF
1kΩ
R6
40Ω
R10
40Ω
XFMR INPUT
1
S4
2
1
2
49.9Ω
JP5
C9
R5
0.33µF
C42
VAL
C45
VAL
6
T1–1T
R24
49.9Ω
52
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
Figure 46. TSSOP Evaluation Board Schematic, Analog Inputs
DACLK
AD9762
DB10
DB19
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC1
NC2
U4
CLOCKMSB-DB11
DVDD
DCOM
NC3
AVDD
COMP2
IOUTA
IOUTB
ACOM
COMP1
FSADJ
REFIO
REFLO
SLEEP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C30
0.1µF
C49
0.1µF
0.01µF
C56
0.1µF
R30
2kΩ
C31
C51
0.1µF
DVDD
C29
0.1µF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Figure 47. TSSOP Evaluation Board Schematic, Optional DAC
C46
0.01µF
WHT
TP18
R29
49.9Ω
C55
22pF
R28
49.9Ω
C54
22pF
02461-046
S6
02461-047
Rev. C | Page 23 of 40
AD9235
Figure 48. TSSOP Evaluation Board Layout, Primary Side
02461-048
Rev. C | Page 24 of 40
AD9235
Figure 49. TSSOP Evaluation Board Layout, Secondary Side
02461-049
Rev. C | Page 25 of 40
AD9235
Figure 50. TSSOP Evaluation Board Layout, Ground Plane
02461-050
Rev. C | Page 26 of 40
AD9235
_
Figure 51. TSSOP Evaluation Board Power Plane
02461-051
Rev. C | Page 27 of 40
AD9235
Figure 52. TSSOP Evaluation Board Layout, Primary Silkscreen
02461-052
Rev. C | Page 28 of 40
AD9235
Figure 53. TSSOP Evaluation Board Layout, Secondary Silkscreen
02461-053
Rev. C | Page 29 of 40
AD9235
G
10kΩ
R9
GND
R1
10kΩ
GND
C12
0.1µF
P7
EXTREF
1V MAX E1
B
A
P9
E
GND
AVDDGND
C
P10
C9
0.10µF
P8
GND
P11
D
C7
0.1µF
+
GND
C29
10µF
C13
0.10µF
GND
C11
0.1µF
C22
10µF
AVDD
GND
P6
R5
1kΩ
P1
R7
1kΩ
P3
R6
1kΩ
P4
1
123456
MODE
22
P5
C8
0.1µF
3
GND
4
AVDD
3.0V
OVERRANGE BIT
(MSB)
GND
DRVDD
2.5V
GND
VDL
2.5V
GND
P2
VAMP
5.0V
H1
MTHOLE6
H2
MTHOLE6
H3
MTHOLE6
H4
MTHOLE6
GND
(LSB)
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
24 23 22 21 20 19 18 17
D9
C6
0.1µF
C15
J1
0.1µF
L1
10nH
XFRIN1
AMP
ND
OPTIONAL XFR
FT C1–1–13
125
X FRIN
PRI SEC
ADT 1–1 WT
NC
GND
T2
43
T1
1
6
52
43
PRI SEC
X
OUT
CT
B
X
OUT
GND
R3, R17, R18
ONLY ONE SHOULD BE
ON BOARD AT A TIME
CT
GND
X
AMPIN
X
OUT
E 45
OUT
R10
36Ω
C16
0.1µF
R11
36Ω
B
R42
0Ω
R12
0Ω
C26
10pF
C5
0.1µF
R3
0Ω
AMPINB
R18
R SINGLE ENDED
25Ω
GND
GND
GND
C18
0.1µF
AVDD
R2
XX
R36
1kΩ
R4
33kΩ
C19
15pF
R15
33Ω
R26
1kΩ
OR L1
FOR FILTER
GND
AVDD
GND
R13
1kΩ
GND
C21
10pF
C23
10pF
AVDD
GND
VIN+
VIN–
GND
AVDD
R25
1kΩ
VREF
MODE
SENSE
25
REFB
26
R
E
F
T
27
A
V
D
D
28
29
30
31
32
AD9235
AGND
VIN+
VIN–
AGND
AVDD
DNC
CLK
DNC
1 2 3 4 5 6 7 8
CLK
P14
AVDD
P13
GND
D11
OTR
U4
DNC
PDWN
R8
1kΩ
SENSE PIN SOLDERABLE JUMPER
E TO A EXTERNAL VOLTAGE DIVIDER
E TO B INTERNAL 1V REFERENCE (DEFAULT)
E TO C EXTERNAL REFERENCE
E TO D INTERNAL 0.5V REFERENCE
D10
DRVDD
DGND
D7
D6
D5
D4
D3
D2
DNCD0D1
GND
D8
16
DRVDD
15
14
13
12
11
10
9
RP2 220Ω
RP1 220Ω
16
DRX
15
D13X
14
D12X
13
D11X
12
D10X
11
D9X
10
D8X
9
D7X
16
D6X
15
D5X
14
D4X
13
D3X
12
D2X
11
D1X
10
D0X
9
MODE PIN SOLDERABLE JUMPER
5 TO 1 TWOS COMPLEMENT/DCS OFF
5 TO 2 TWOS COMPLEMENT/DCS OFF
5 TO 3 OFFSET BINARY/DCS ON
5 TO 4 OFFSET BINARY/DCS OFF
02461-054
Figure 54. LFCSP Evaluation Board Schematic, Analog Inputs and DUT
Rev. C | Page 30 of 40
AD9235
C
74LVTH162374
CLKAT/DAC
DRX
D13X
GND
D12X
D11X
DRVDD
D10X
GND
GND
DRVDD
GND
LSB
CLKLAT/DA
D9X
D8X
D7X
D6X
D5X
D4X
D3X
D2X
D1X
D0X
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
AMP IN
AMP
U1
2CLK
2DB
2D7
GND
2D6
2D5
V
CC
2D4
2D3
GND
2D2
2D1
1D8
1D7
GND
1D6
1D5
V
CC
1D4
1D3
GND
1D2
1D1
1CLK
1
IN OUT
VAMP
R41
10kΩ
R19
R35
50Ω
25Ω
GND GND
24
2OE
23
2QB
22
2Q7
21
GND
20
2Q6
19
2Q5
18
V
CC
17
2Q4
16
2Q3
15
GND
14
2Q2
13
2Q1
12
1Q8
11
1Q7
10
GND
9
1Q6
8
1Q5
7
V
CC
6
1Q4
5
1Q3
4
GND
3
1Q2
2
1Q1
1
1OE
POWER DOWN
USE R40 OR R41
R41
R40
10kΩ
10kΩ
C28
0.1µF
C35
0.10µF
GND
DRYMSB
GND
MSB
DRVDD
GND
GND
DRVDD
GND
GND
R38
R39
1kΩ
C44
0.1µF
1kΩ
VAMP
VAMP
GND
GND
R33
25Ω
PWDN
RGP1
INHI
INLO
RPG2
1
2
3
4
5
AD8351
U3
R34
1.2kΩ
10
9
8
7
6
VOCM
VPOS
OPH1
OPLO
COMM
GND
R14
25Ω
Figure 55. LFCSP Evaluation Board Schematic, Digital Path
GND
C24
10µF
+
C45
0.1µF
R16
0Ω
R17
0Ω
GND
GND
GND
GND
HEADER 40
2
2
4
DR
DRY
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
GND GND
C27
0.1µF
C17
0.1µF
AMPINB
AMPIN
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
02461-055
Rev. C | Page 31 of 40
AD9235
C40
0.001µF
C37
0.1µF
C46
10µF
+
C20
10µF
+++++
Rx
ATTACH Rx (Rx = 0Ω)
1Y
6
B
1
2
DNP
R37
CLKAT/DAC
0Ω
R23
GND
7811
GND
2Y
A
B
2
2
4
5
25Ω
A
3
9
VDL
GND
C49
0.001µF
C48
0.001µF
C47
0.1µF
C1
0.1µF
C39
0.001µF
C38
0.001µF
C36
0.1µF
C34
0.1µF
C31
0.1µF
C30
0.001µF
VAMP
LATCH BYPASSING
GND
74VCX86
SCHEMATIC SHOWS TWO GATE DELAY SETUP
ENCX
FOR ONE DELAY REMOVE R22 AND R37 AND
3
A
1
1
DR
0Ω
R22
VDL
14
PWR
3Y
4Y
B
B
A
3
4
4
12
13
10
C2
22µF
DIGITAL BYPASSINGANALOG BYPASSING
VDL DRVDD AVDD
DRVDD
AVDD
GND
C41
0.1µF
C14
0.001µF
CLK
C33
0.1µF
C32
0.001µF
C25
10µF
GND
C3
10µF
C4
10µF
GND
C10
22µF
DUT BYPASSING
CLOCK TIMING ADJUSTMENTS
FOR A BUFFERED ENCODE USE R28
0Ω
R28
FOR A DIRECT ENCODE USE R27
ENC
ENCX
R32
1kΩ
E50 E51
VDL GND
0Ω
R27
ENC
R20
1kΩ
E52 E53
VDL GND
R31
1kΩ
VDL
C43
0.1µF
ENCODE
R21
1kΩ
E31 E35
R30
1kΩ
GND
R29
50Ω
GND
GND
J2
R24
1kΩ
E43 E44
VDL GND
VDL GND
02461-056
Figure 56. LFCSP Evaluation Board Schematic, Clock Input
Rev. C | Page 32 of 40
AD9235
02461-057
Figure 57. LFCSP Evaluation Board Layout, Primary Side
02461-058
Figure 58. LFCSP Evaluation Board Layout, Secondary Side
02461-059
Figure 59. LFCSP Evaluation Board Layout, Ground Plane
02461-060
Figure 60. LFCSP Evaluation Board Layout, Power Plane
Rev. C | Page 33 of 40
AD9235
Figure 61. LFCSP Evaluation Board Layout, Primary Silkscreen
02461-061
02461-062
Figure 62. LFCSP Evaluation Board Layout, Secondary Silkscreen
Rev. C | Page 34 of 40
AD9235
Table 9. LFCSP Evaluation Board Bill of Materials (BOM)
Recommended Vendor/
Item Qty. Omit1Reference Designator Device Package Value
18
1
8
8
2
2 C46, C24
3 8
4 3 C19, C21, C23 Chip Capacitor 0603 10 pF
5 1 C26 Chip Capacitor 0603 10 pF
9
6
2 E1, E45
7 2 J1, J2 SMA Connector/50 Ω SMA
8 1 L1 Inductor 0603 10 nH
9 1 P2 Terminal Block TB6
10 1 P12 Header Dual 20-Pin RT Angle HEADER40 Digi-Key S2131-20-ND
5 R3, R12, R23, R28, RX 11
6 R37, R22, R42, R16, R17, R27
12 2 R4, R15 Chip Resistor 0603 33 Ω
13 14
14 2 R10, R11 Chip Resistor 0603 36 Ω
1 R29 15
1 R19
16 2 RP1, RP2 Resistor Pack R_742 220 Ω
17 1 T1 ADT1-1WT AWT1-1T Mini-Circuits
18 1 U1
19 1 U4 AD9235BCP ADC (DUT) LFCSP-32 Analog Devices, Inc. X
20 1 U5 74VCX86M SOIC-14 Fairchild
21 1 PCB AD92XXBCP/PCB PCB Analog Devices, Inc. X
22 1 U3 AD8351 Op Amp MSOP-8 Analog Devices, Inc. X
23 1 T2 MACOM Transformer ETC1-1-13 1-1 TX M/A-COM/ETC1-1-13
24 5 R9, R1, R2, R38, R39 Chip Resistor 0603 SELECT
25 3 R18, R14, R35 Chip Resistor 0603 25 Ω
26 2 R40, R41 Chip Resistor 0603 10 k Ω
27 1 R34 Chip Resistor 1.2 k Ω
28 1 R33 Chip Resistor 100 Ω
Total 82 34
C1, C5, C7, C8, C9, C11,
C12, C13, C15, C16, C31, C33,
C34, C36, C37, C41, C43, C47
C6, C18, C27, C17,
C28, C35, C45, C44
C2, C3, C4, C10, C20,
C22, C25, C29
C14, C30, C32, C38,
C39, C40, C48, C49
E31, E35, E43, E44,
E50, E51, E52, E53
R5, R6, R7, R8, R13, R20,
R21, R24, R25, R26,
R30, R31, R32, R36
Chip Capacitor 0603 0.1 µF
Tantalum Capacitor TAJD 10 µF
Chip Capacitor 0603 0.001 µF
Header EHOLE Jumper Blocks
Chip Resistor 0603 0 Ω
Chip Resistor 0603 1 k Ω
Chip Resistor 0603 50 Ω
74LVTH162374
CMOS Register
TSSOP-48
Part Number
Coilcraft/
0603CS-10NXGBU
Wieland/25.602.2653.0,
z5-530-0625-0
Digi-Key
CTS/742C163220JTR
1
These items are included in the PCB design but are omitted at assembly.
Supplied
by ADI
Rev. C | Page 35 of 40
AD9235
R
OUTLINE DIMENSIONS
9.80
9.70
9.60
PIN 1
INDICATO
1.00
0.85
0.80
28
PIN 1
0.15
0.05
COPLANARITY
0.10
0.65
BSC
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153AE
1.20 MAX
SEATING
PLANE
15
4.50
4.40
4.30
0.20
0.09
6.40 BSC
141
Figure 63. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
5.00
12° MAX
SEATING
PLANE
BSC SQ
TOP
VIEW
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
4.75
BSC SQ
0.20 REF
0.05 MAX
0.02 NOM
0.60 MAX
0.50
BSC
0.50
0.40
0.30
COPLANARITY
0.08
25
24
17
16
Figure 64. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body (CP-32-2)
Dimensions shown in millimeters
8°
0°
0.60 MAX
EXPOSED
PAD
(BOTTOM VIEW)
0.75
0.60
0.45
32
1
8
9
3.50 REF
PIN 1
INDICATOR
3.25
3.10 SQ
2.95
0.25 MIN
Rev. C | Page 36 of 40
AD9235
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9235BRU-20 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9235BRURL7-20 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9235BRUZ-20
AD9235BRUZRL7-201 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9235BRU-40 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9235BRURL7-40 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9235BRUZ-401 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9235BRUZRL7-401 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9235BRU-65 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9235BRURL7-65 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9235BRUZ-651 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9235BRUZRL7-651 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9235BCP-20
AD9235BCPRL7-202 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2
AD9235BCPZ-20
AD9235BCPZRL7-20
AD9235BCP-402 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2
AD9235BCPRL7-402 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2
AD9235BCPZ-40
AD9235BCPZRL7-40
AD9235BCP-652 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2
AD9235BCPRL7-652 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2
AD9235BCPZ-65
AD9235BCPZRL7-65
AD9235-20PCB TSSOP Evaluation Board
AD9235-40PCB TSSOP Evaluation Board
AD9235-65PCB TSSOP Evaluation Board
AD9235BCP-20EB LFCSP Evaluation Board
AD9235BCP-40EB LFCSP Evaluation Board
AD9235BCP-65EB LFCSP Evaluation Board
1
Z = Pb-free part.
2
It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of
the package is achieved with exposed paddle soldered to the customer board.
1
2
1, 2
1, 2
–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2
1, 2
–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2
–40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2
–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2
1, 2
–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2
1, 2
–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2
1, 2
–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2
Rev. C | Page 37 of 40
AD9235
NOTES
Rev. C | Page 38 of 40
AD9235
NOTES
Rev. C | Page 39 of 40
AD9235
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02461–0–10/04(C)
Rev. C | Page 40 of 40
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