Analog Devices AD9233 Service Manual

12-Bit, 80 MSPS/105 MSPS/125 MSPS,

A

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply SNR = 69.5 dBc (70.5 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.15 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Clock duty cycle stabilizer Data output clock Serial port control

Built-in selectable digital test pattern generation Programmable clock and data alignment

APPLICATIONS

Ultrasound equipment IF sampling in communications receivers

IS-95, CDMA-One, IMT-2000 Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes

GENERAL DESCRIPTION

The AD9233 is a monolithic, single 1.8 V supply, 12-bit, 80 MSPS/ 105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring a high performance sample-and-hold amplifier (SHA) and onchip voltage reference. The product uses a multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range.

1.8 V Analog-to-Digital Converter AD9233

FUNCTIONAL BLOCK DIAGRAM

MODE

SELECT

DRVDD

A/D

3

OR

DCO

D11 (MSB)

D0 (LSB)

SCLK/DFS

SDIO/DCS

CSB

VDD

AD9233

VIN+

VIN–

REFT

REFB

VREF

SENSE

SHA

REF

SELECT

A/D

AGND

MDAC1

4

0.5V

8-STAGE

1 1/2-BIT PIPEL INE

8

CORRECTION L OGIC

13

OUTPUT BUFFERS

CLOCK

DUTY CYCLE

STABILIZER

CLK– PDWN DRGND

CLK+

Figure 1.

The digital output data is presented in offset binary, Gray code, or twos complement formats. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic.

The AD9233 is available in a 48-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. The AD9233 operates from a single 1.8 V power supply

and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.

2. The patented SHA input maintains excellent performance

for input frequencies up to 225 MHz.

05492-001

The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and offsets, including single-ended

3. The clock DCS maintains overall ADC performance over a

wide range of clock pulse widths.

applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9233 is suitable for applications in communications, imaging, and medical ultrasound.

A differential clock input controls all internal conversion cycles. A

4. A standard serial port interface supports various product

features and functions, such as data formatting (offset binary, twos complement, or Gray coding), enabling the clock DCS, power-down, and voltage reference mode.

5. The AD9233 is pin compatible with the AD9246, allowing

a simple migration from 12 bits to 14 bits.

duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9233

REVISION HISTORY

8/06—Rev. 0 to Rev. A

Updated Format.................................................................. Universal

Added 80 MSPS.................................................................. Universal

Deleted Figure 19, Figure 20, Figure 22, and Figure 23;

Renumbered Sequentially ..............................................................11

Deleted Figure 24, Figure 25, and Figure 27 to Figure 29;

Renumbered Sequentially ..............................................................12

Deleted Figure 31 and Figure 34; Renumbered Sequentially....13

Deleted Figure 37, Figure 38, Figure 40, and Figure 41;

Renumbered Sequentially ..............................................................14

Deleted Figure 46; Renumbered Sequentially.............................15

Deleted Figure 52; Renumbered Sequentially.............................16

Changes to Figure 40 ......................................................................16

Changes to Figure 46 ......................................................................18

Inserted Figure 54; Renumbered Sequentially ............................20

Changes to Digital Outputs Section .............................................21

Changes to Timing Section............................................................22

Added Data Clock Output (DCO) Section..................................22

Changes to Configuration Using the SPI Section and

Configuration Without the SPI Section.......................................23

Changes to Table 15 ........................................................................25

Changes to Table 16 ........................................................................39

Changes to Ordering Guide...........................................................42

4/06—Revision 0: Initial Version

Rev. A | Page 3 of 44

AD9233

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled, unless otherwise noted.

Table 1.

AD9233BCPZ-80 AD9233BCPZ-105 AD9233BCPZ-125 Parameter Te mp Min Typ Max Min Typ Max Min Typ Max Unit

RESOLUTION Full 12 12 12 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.3 ±0.5 ±0.3 ±0.8 ±0.3 ±0.8 % FSR Gain Error Full ±0.2 ±4.7 ±0.2 ±4.9 ±0.2 ±3.9 % FSR Differential Nonlinearity (DNL) 25°C ±0.2 ±0.2 ±0.2 LSB Integral Nonlinearity (INL) 25°C ±0.5 ±0.5 ±0.5 LSB

TEMPERATURE DRIFT

Offset Error Full ±15 ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ±95 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) Full ±5 ±20 ±5 ±35 ±5 ±35 mV Load Regulation @ 1.0 mA Full 7 7 7 mV

INPUT REFERRED NOISE

VREF = 1.0 V 25°C 0.34 0.34 0.34 LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V Full 2 2 2 V p-p Input Capacitance

2

REFERENCE INPUT RESISTANCE Full 6 6 6 kΩ POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 3.3 3.6 1.7 3.3 3.6 1.7 3.3 3.6 V

Supply Current

1

IAVDD IDRVDD1 (DRVDD = 1.8 V) Full 7 8 10 mA IDRVDD1 (DRVDD = 3.3 V) Full 12 14 17 mA

POWER CONSUMPTION

DC Input Full 248 279 320 350 395 425 mW Sine Wave Input1 (DRVDD = 1.8 V) Full 261 335 415 mW Sine Wave Input1 (DRVDD = 3.3 V) Full 288 365 452 mW Standby

3

Power-Down Full 1.8 1.8 1.8 mW

1

Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.

3

Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).

1

Full ±0.3 ±0.5 ±0.5 LSB

Full ±1.2 ±1.2 ±1.2 LSB

Full 8 8 8 pF

Full 138 155 178 194 220 236 mA

Full 40 40 40 mW

Rev. A | Page 4 of 44

AD9233

AC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled, unless otherwise noted.

Table 2.

AD9233BCPZ-80 AD9233BCPZ-105 AD9233BCPZ-125 Parameter

SIGNAL-TO-NOISE-RATIO (SNR)

fIN = 2.4 MHz 25°C 69.5 69.5 69.5 dBc fIN = 70 MHz 25°C 69.5 69.5 69.5 dBc Full 68.9 68.3 68.3 dBc fIN = 100 MHz 25°C 69.4 69.4 69.4 dBc fIN = 170 MHz 25°C 68.9 68.9 68.9 dBc

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 2.4 MHz 25°C 69.2 69.2 69.2 dBc fIN = 70 MHz 25°C 69.2 69.2 69.2 dBc Full 68.5 67.3 67.3 dBc fIN = 100 MHz 25°C 69.1 69.1 69.1 dBc fIN = 170 MHz 25°C 68.6 68.6 68.6 dBc

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.4 MHz 25°C 11.4 11.4 11.4 Bits fIN = 70 MHz 25°C 11.4 11.4 11.4 Bits fIN = 100 MHz 25°C 11.4 11.4 11.4 Bits fIN = 170 MHz 25°C 11.3 11.3 11.3 Bits

WORST SECOND OR THIRD HARMONIC

fIN = 2.4 MHz 25°C −90.0 −90.0 −90.0 dBc fIN = 70 MHz 25°C −85.0 −85.0 −85.0 dBc Full −76.0 −73.0 −73.0 dBc fIN = 100 MHz 25°C −85.0 −85.0 −85.0 dBc fIN = 170 MHz 25°C −83.5 −83.5 −83.5 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.4 MHz 25°C 90.0 90.0 90.0 dBc fIN = 70 MHz 25°C 85.0 85.0 85.0 dBc Full 76.0 73.0 73.0 dBc fIN = 100 MHz 25°C 85.0 85.0 85.0 dBc fIN = 170 MHz 25°C 83.5 83.5 83.5 dBc

WORST OTHER (HARMONIC OR SPUR)

fIN = 2.4 MHz 25°C −90.0 −90.0 −90.0 dBc fIN = 70 MHz 25°C −90.0 −90.0 −90.0 dBc Full −85.0 −81.0 −81.0 dBc fIN = 100 MHz 25°C −90.0 −90.0 −90.0 dBc fIN = 170 MHz 25°C −90.0 −90.0 −90.0 dBc

TWO-TONE SFDR

fIN = 30 MHz (−7 dBFS), 31 MHz (−7 dBFS) 25°C 87 87 85 dBFS fIN = 170 MHz (−7 dBFS), 171 MHz (−7 dBFS) 25°C 83 83 84 dBFS

ANALOG INPUT BANDWIDTH 25°C 650 650 650 MHz

1

See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

1

Te mp Min Typ Max Min Typ Max Min Typ Max Unit

Rev. A | Page 5 of 44

AD9233

DIGITAL SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled, unless otherwise noted.

Table 3.

AD9233BCPZ-80/105/125 Parameter Te mp Min Typ Max Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 V Differential Input Voltage Full 0.2 Input Voltage Range Full AVDD − 0.3 Input Common-Mode Range Full 1.1 High Level Input Voltage (VIH) Full 1.2 3.6 V Low Level Input Voltage (VIL) Full 0 High Level Input Current (IIH) Full −10 +10 µA Low Level Input Current (IIL) Full −10 +10 µA Input Resistance Full 8 10 12 kΩ Input Capacitance Full

LOGIC INPUTS (SCLK/DFS, OE, PWDN)

High Level Input Voltage (VIH) Full 1.2 3.6 V Low Level Input Voltage (VIL) Full 0 High Level Input Current (IIH) Full −50 Low Level Input Current (IIL) Full −10 +10 µA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF

LOGIC INPUTS (CSB)

High Level Input Voltage (VIH) Full 1.2 3.6 V Low Level Input Voltage (VIL) Full 0 High Level Input Current (IIH) Full −10 Low Level Input Current (IIL) Full +40 Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUTS (SDIO/DCS)

High Level Input Voltage (VIH) Full 1.2 DRVDD + 0.3 V Low Level Input Voltage (VIL) Full 0 High Level Input Current (IIH) Full −10 Low Level Input Current (IIL) Full +40 Input Resistance Full Input Capacitance Full 5 pF

DIGITAL OUTPUTS

DRVDD = 3.3 V

High Level Output Voltage (VOH, IOH = 50 µA) Full 3.29 V High Level Output Voltage (VOH, IOH = 0.5 mA) Full 3.25 V Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (VOL, IOL = 50 µA) Full 0.05 V

DRVDD = 1.8 V

High Level Output Voltage (VOH, IOH = 50 µA) Full 1.79 V High Level Output Voltage (VOH, IOH = 0.5 mA) Full 1.75 V Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (VOL, IOL = 50 µA) Full 0.05 V

4

26

6 V p-p AVDD + 1.6 V AVDD V

0.8 V

−75 µA

0.8 V +10 µA +135 µA

0.8 V +10 µA +130 µA

pF

kΩ

Rev. A | Page 6 of 44

AD9233

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.

Table 4.

AD9233BCPZ-80 AD9233BCPZ-105 AD9233BCPZ-125 Parameter

CLOCK INPUT PARAMETERS

Conversion Rate, DCS Enabled Full 20 80 20 105 20 125 MSPS Conversion Rate, DCS Disabled Full 10 80 10 105 10 125 MSPS CLK Period Full 12.5 9.5 8 ns CLK Pulse Width High, DCS Enabled Full 3.75 6.25 8.75 2.85 4.75 6.65 2.4 4 5.6 ns CLK Pulse Width High, DCS Disabled Full 5.63 6.25 6.88 4.28 4.75 5.23 3.6 4 4.4 ns

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD) DCO Propagation Delay (t Setup Time (tS) Full 4.9 5.7 3.4 4.3 2.6 3.5 ns Hold Time (tH) Full 5.9 6.8 4.4 5.3 3.7 4.5 ns Pipeline Delay (Latency) Full 12 12 12 cycles Aperture Delay (tA) Full 0.8 0.8 0.8 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms

Wake-Up Time OUT-OF-RANGE RECOVERY TIME Full 2 2 3 cycles SERIAL PORT INTERFACE

SCLK Period (t

SCLK Pulse Width High Time (tHI) Full 16 16 16 ns

SCLK Pulse Width Low Time (tLO) Full 16 16 16 ns

SDIO to SCLK Setup Time (tDS) Full 5 5 5 ns

SDIO to SCLK Hold Time (tDH) Full 2 2 2 ns

CSB to SCLK Setup Time (tS) Full 5 5 5 ns

CSB to SCLK Hold Time (tH) Full 2 2 2 ns

1

See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

3

Wake-up time is dependant on the value of the decoupling capacitors, values shown with 0.1 µF capacitor across REFT and REFB.

4

See Figure 57 and the Serial Port Interface (SPI) section.

1

2

) Full 4.4 4.4 4.4 ns

DCO

3

4

) Full 40 40 40 ns

CLK

Te mp Min Typ Max Min Typ Max Min Typ Max Unit

Full 3.1 3.9 4.8 3.1 3.9 4.8 3.1 3.9 4.8 ns

Full 350 350 350 ms

TIMING DIAGRAM

CLK+

CLK–

DATA

DCO

N+2

N+ 1

N

t

A

t

CLK

t

PD

N – 12 N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4

N – 13

t

S

t

H

N+ 3

t

DCO

N+ 4

N+ 5

N+ 6

t

CLK

N+ 7

Figure 2. Timing Diagram

Rev. A | Page 7 of 44

N+ 8

05492-083

AD9233

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

ELECTRICAL

AVDD to AGND −0.3 V to +2.0 V DRVDD to DRGND −0.3 V to +3.9 V AGND to DRGND −0.3 V to +0.3 V AVDD to DRVDD −3.9 V to +2.0 V D0 through D11 to DRGND −0.3 V to DRVDD + 0.3 V DCO to DRGND −0.3 V to DRVDD + 0.3 V OR to DRGND −0.3 V to DRVDD + 0.3 V CLK+ to AGND −0.3 V to +3.9 V CLK− to AGND −0.3 V to +3.9 V VIN+ to AGND −0.3 V to AVDD + 1.3 V VIN− to AGND −0.3 V to AVDD + 1.3 V VREF to AGND −0.3 V to AVDD + 0.2 V SENSE to AGND −0.3 V to AVDD + 0.2 V REFT to AGND −0.3 V to AVDD + 0.2 V REFB to AGND −0.3 V to AVDD + 0.2 V SDIO/DCS to DRGND −0.3 V to DRVDD + 0.3 V PDWN to AGND −0.3 V to +3.9 V CSB to AGND −0.3 V to +3.9 V SCLK/DFS to AGND −0.3 V to +3.9 V OEB to AGND −0.3 V to +3.9 V

ENVIRONMENTAL

Storage Temperature Range –65°C to +125°C Operating Temperature Range –40°C to +85°C Lead Temperature

(Soldering 10 Sec)

Junction Temperature 150°C

300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package.

Table 6.

Package Type θ

48-lead LFCSP (CP-48-3) 26.4 2.4 °C/W

JA

Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θ addition, metal in direct contact with the package leads from metal traces, and through holes, ground, and power planes, reduces the θ

.

JA

θ

JC

Unit

JA

. In

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 8 of 44

AD9233

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DRVDD

DRGNDNCNC

DCO

OEB

AVDD

AGND

AVDD

CLK–

CLK+

4847464544434241403938

AGND

37

AVDD

35 34 33

32 31 30

29

28 27

26 25

PDWN36

RBIAS CML AVDD

AGND VIN– VIN+

AGND

REFT REFB

VREF SENSE

05492-003

(LSB) D0

DRGND

DRVDD

1 2

D1

3

D2

4

D3

5

D4

6

D5

7

8

9

D6

10

D7

11

D8

12

D9

PIN 1 INDICATO R

AD9233

TOP VIEW

(Not to Scale)

PIN 0 (EXPOS ED PADDLE): AGND

13141516171819

OR

D10

DRGND

(MSB) D11

NC = NO CONNECT

DRVDD

SDIO/DCS

SCLK/DFS

2021222324

CSB

AVDD

AGND

Figure 3. Pin Configuration

Table 7. Pin Function Description

Pin No. Mnemonic Description

0, 21, 23, 29,

AGND Analog Ground. (Pin 0 is the exposed thermal pad on the bottom of the package.)

32, 37, 41 1 to 6, 9 to 14 D0 (LSB) to D11 (MSB) Data Output Bits. 7, 16, 47 DRGND Digital Output Ground. 8, 17, 48 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 15 OR Out-of-Range Indicator. 18 SDIO/DCS

Serial Port Interface (SPI)® Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select (External Pin Mode). See

Table 10. 19 SCLK/DFS SPI Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). See Tab le 10. 20 CSB SPI Chip Select (Active Low). 22, 24, 33, 40, 42 AVDD Analog Power Supply.

25 SENSE Reference Mode Selection. See Table 9. 26 VREF Voltage Reference Input/Output. 27 REFB Differential Reference (−). 28 REFT Differential Reference (+). 30 VIN+ Analog Input Pin (+). 31 VIN– Analog Input Pin (−). 34 CML Common-Mode Level Bias Output. 35 RBIAS

External Bias Resister Connection. A 10 kΩ resister must be connected between this pin and

analog ground (AGND). 36 PDWN Power-Down Function Select. 38 CLK+ Clock Input (+). 39 CLK– Clock Input (−). 43 OEB Output Enable (Active Low). 44 DCO Data Clock Output. 45, 46 NC No Connection.

Rev. A | Page 9 of 44

AD9233

C

S

A

V

EQUIVALENT CIRCUITS

VDD

26kΩ

1kΩ

30kΩ

1kΩ

05492-008

05492-010

LK+

VIN

05492-004

Figure 4. Equivalent Analog Input Circuit

AVDD

1.2V

10kΩ 10kΩ

Figure 5. Equivalent Clock Input Circuit

DRVDD

CLK–

CLK/DFS

OEB

PDWN

Figure 8. Equivalent SCLK/DFS, OEB, PDWN Input Circuit

CSB

05492-005

Figure 9. Equivalent CSB Input Circuit

SENSE

DIO/DCS

Figure 6. Equivalent SDIO/DCS Input Circuit

1kΩ

DRVDD

05492-011

05492-006

Figure 10. Equivalent SENSE Circuit

DD

VREF

6kΩ

05492-012

DRGND

Figure 7. Equivalent Digital Output Circuit

05492-007

Figure 11. Equivalent VREF Circuit

Rev. A | Page 10 of 44

AD9233

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V; DRVDD = 2.5 V; maximum sample rate, DCS enabled, 1 V internal reference; 2 V p-p differential input; AIN =

−1.0 dBFS; 64k sample; T

0

–20

–40

= 25°C, unless otherwise noted. All figures show typical performance for all speed grades.

A

125MSPS

2.3MHz @ –1dBF S SNR = 69.5dBc (70. 5dBFS) ENOB = 11.2 BITS SFDR = 90.0d Bc

0

–20

–40

125MSPS

100.3MHz @ –1dBF S SNR = 69.4dBc (70. 4dBFS) ENOB = 11.2 BITS SFDR = 85.0dBc

–60

–80

AMPLITUDE ( dBFS)

–100

–120

–140

0 15.625 31.250 46.875 62.500

Figure 12. AD9233-125 Single-Tone FFT with F

FREQUENCY (MHz)

IN

0

–20

–40

–60

–80

AMPLI TUDE (d BFS)

–100

–120

–140

0 15.625 31.250 46.875 62.500

FREQUENCY (MHz )

Figure 13. AD9233-125 Single-Tone FFT with F

125MSPS

30.3MHz @ –1dBF S SNR = 69.5dBc (70.5dBFS) ENOB = 11.2 BI TS SFDR = 88.8dBc

IN

0

125MSPS

70.3MHz @ –1dBFS SNR = 69.5dBc (70. 5dBFS)

–20

ENOB = 11.2 BITS SFDR = 85.0d Bc

–40

= 2.3 MHz

= 30.3 MHz

–60

–80

AMPLITUDE (dBFS)

–100

–120

05492-013

–140

0 15.625 31.250 46.875 62.500

Figure 15. AD9233-125 Single-Tone FFT with F

FREQUENCY (MHz)

= 100.3 MHz

IN

05492-016

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

05492-014

–140

0 15.625 31.250 46.875 62.500

FREQUENCY (MHz)

Figure 16. AD9233-125 Single-Tone FFT with F

125MSPS

140.3MHz @ –1dBF S SNR = 69.0dBc ( 70.0dBFS) ENOB = 11.1 BIT S SFDR = 85.0dBc

= 140.3 MHz

IN

05492-017

0

125MSPS

170.3MHz @ –1dBFS SNR = 68.9dBc (69. 9dBFS)

–20

ENOB = 11.1 BITS SFDR = 83.5d Bc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 15.625 31.250 46.875 62.500

Figure 14. AD9233-125 Single-Tone FFT with F

FREQUENCY (MHz)

IN

= 70.3 MHz

05492-015

Rev. A | Page 11 of 44

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 15.625 31.250 46.875 62.500

Figure 17. AD9233-125 Single-Tone FFT with F

FREQUENCY (MHz)

= 170.3 MHz

IN

05492-018

AD9233

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 15.625 31.250 46.875 62.500

FREQUENCY ( MHz)

Figure 18. AD9233-125 Single-Tone FFT with F

0

125MSPS

300.3MHz @ –1dBF S

–20

SNR = 67.8dBc (68.8dBFS) ENOB = 10.8 BI TS SFDR = 77.4d Bc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 15.625 31.250 46.875 62.500

FREQUENCY (MHz)

Figure 19. AD9233-125 Single-Tone FFT with F

120

100

80

SFDR (dBFS)

SNR (dBFS)

125MSPS

225.3MHz @ –1dBF S SNR = 68.5dBc ( 69.5dBFS ) ENOB = 11.0 BITS SFDR = 80.4d Bc

= 225.3 MHz

IN

= 300.3 MHz

IN

100

95

90

85

80

75

SNR/SFDR (d Bc)

05492-019

SNR = +25°C

70

SNR = +85°C

65

60

0 15050 100 200 250

SFDR = –40°C

SFDR = +85°C

SNR = –40°C

INPUT FREQ UENCY (MHz)

SFDR = +25°C

05492-021

Figure 21. AD9233 Single-Tone SNR/SFDR vs.

Input Frequency (F

100

95

90

85

80

75

SNR/SFDR (d Bc)

70

SNR = +25°C

65

05492-029

SNR = +85°C

60

0 15050 100 200 250

) and Temperature with 2 V p-p Full Scale

IN

SFDR = +85°C

SFDR = –40°C

SNR = –40°C

INPUT FREQ UENCY (MHz)

SFDR = +25°C

05492-022

Figure 22. AD9233 Single-Tone SNR/SFDR vs.

Input Frequency (F

1.0

0.8

0.5

0.3

) and Temperature with 1 V p-p Full Scale

IN

OFFSET ERROR

60

40

SFDR (dBc)

SNR/SFDR (d Bc and dBF S)

20

SNR (dBc)

0

–90 0

–80 –70 –60 –50 –40 –30 –20 –10

INPUT AM PLITUDE (d BFS)

85dB REFERENCE L INE

Figure 20. AD9233 Single-Tone SNR/SFDR vs.

Input Amplitude (AIN) with F

= 2.4 MHz

IN

05492-091

Rev. A | Page 12 of 44

0

–0.3

–0.5

GAIN/OF FSET ERROR (%FSR)

–0.8

–1.0

–20 0 20 40 60

–40 80

GAIN ERROR

TEMPERATURE ( °C)

Figure 23. AD9233 Gain and Offset vs. Temperature

05492-031

AD9233

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 15.625 31.250 46.875 62.500

FREQUENCY (MHz)

Figure 24. AD9233-125 Two-Tone FFT with F

0

125MSPS

169.1MHz @ –7dBF S

–20

172.1MHz @ –7dBF S SFDR = 84dBc (91d BFS)

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 15.625 31.250 46.875 62.500

FREQUENCY ( MHz)

Figure 25. AD9233-125 Two-Tone FFT with F

0

–20

–40

125MSPS

29.1MHz @ –7dBF S

32.1MHz @ –7dBF S SFDR = 85dBc (92d BFS)

= 29.1 MHz, F

IN1

= 169.1 MHz, F

IN1

= 32.1 MHz

IN2

= 172.1 MHz

IN2

05492-024

05492-025

0

–20

–40

IMD3 (d Bc)

–60

–80

SFDR/IMD3 (dBc and d BFS)

–100

–120

–90 –6–78 –66 –54 –42 –30 –18

SFDR (dBc)

SFDR (dBFS)

IMD3 (d BFS)

ANALOG INPUT LEVEL (dB FS)

Figure 27. AD9233 Two-Tone SFDR/IMD vs.

Input Amplitude (AIN) with F

0

–20

–40

IMD3 (d BFS)

–60

–80

SFDR (dBFS)

SFDR/IMD3 (dBc and d BFS)

–100

–120

–90 –78 –66 –54 –42 –30 –18 –6

IMD3 (d BFS)

INPUT AMPLI TUDE (dBFS)

= 29.1 MHz, F

IN1

SFDR (dBc)

IN2

Figure 28. AD9233 Two-Tone SFDR/IMD vs.

Input Amplitude (AIN) with F

0

–20

–40

= 169.1 MHz, F

IN1

NOTCH @ 18.5MHz

NOTCH WIDT H = 3MHz

IN2

NPR = 61.9dBc

= 32.1 MHz

= 172.1 MHz

05492-035

05492-080

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 15.36 30.72 46. 08 61.44

FREQUENCY (MHz )

Figure 26. AD9233-125 Two 64k WCDMA Carriers

= 215.04 MHz, FS = 122.88 MSPS

with F

IN

05492-086

Rev. A | Page 13 of 44

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 15.625 31.250 46.875 62. 500

FREQUENCY (MHz)

Figure 29. AD9233-125 Noise Power Ratio

05492-090

AD9233

NUMBER OF HIT S (1M)

INL ERROR (LSB)

10

8

6

4

2

0

N–1 N N+1

OUTPUT CODE

Figure 33. AD9233 Grounded Input Histogram

0.35

0.25

0.15

0.05

–0.05

–0.15

0.34 LSB rms

05492-085

100

95

90

85

80

SNR/SFDR (dBc)

75

70

65

5 254565851051

SFDR

SNR

CLOCK FREQUENCY (MSPS)

Figure 30. AD9233 Single-Tone SNR/SFDR vs.

) with FIN = 2.4 MHz

S

SNR DCS = ON

100

SNR/SFDR (d Bc)

Clock Frequency (F

SFDR DCS = ON

90

SFDR DCS = OFF

80

70

60

05492-027

25

50

40

20 40 60 80

DUTY CYCLE (%)

SNR DCS = OFF

Figure 31. AD9233 SNR/SFDR vs. Duty Cycle with F

90

85

80

75

SNR/SFDR (dBc)

70

65

0.5 0. 7 0. 9 1.1 1.3

SFDR

SNR

INPUT COMMON-MODE VOLTAGE (V)

Figure 32. AD9233 SNR/SFDR vs.

Input Common Mode (V

) with FIN = 30 MHz

CM

= 10.3 MHz

IN

–0.25

05492-026

–0.35

0 1024 2048 3072 4096

Figure 34. AD9233 INL with F

OUTPUT CODE

IN

= 10.3 MHz

05492-023

0.15

0.10

0.05

0

–0.05

DNL ERROR (LSB)

–0.10

05492-028

–0.15

0 1024 2048 3072 4096

Figure 35. AD9233 DNL with F

OUTPUT CODE

= 10.3 MHz

IN

05492-020

Rev. A | Page 14 of 44

Analog Devices AD9233 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING DIAGRAM

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

EQUIVALENT CIRCUITS

TYPICAL PERFORMANCE CHARACTERISTICS