Analog Devices AD9230 Service Manual

12-Bit, 170 MSPS/210 MSPS/250 MSPS,

FEATURES

SNR = 64.9 dBFS @ fIN up to 70 MHz @ 250 MSPS ENOB of 10.4 @ f SFDR = −79 dBc @ f Excellent linearity

DNL = ±0.3 LSB typical

INL = ±0.5 LSB typical LVDS at 250 MSPS (ANSI-644 levels) 700 MHz full power analog bandwidth On-chip reference, no external decoupling required Integrated input buffer and track-and-hold Low power dissipation

434 mW @ 250 MSPS—LVDS SDR mode

400 mW @ 250 MSPS—LVDS DDR mode Programmable input voltage range

1.0 V to 1.5 V, 1.25 V nominal

1.8 V analog and digital supply operation Selectable output data format (offset binary, twos

complement, Gray code) Clock duty cycle stabilizer Integrated data capture clock

up to 70 MHz @ 250 MSPS (−1.0 dBFS)

IN

up to 70 MHz @ 250 MSPS (−1.0 dBFS)

IN

1.8 V Analog-to-Digital Converter AD9230

CML

VIN+

VIN–

CLK+

CLK–

FUNCTIONAL BLOCK DIAGRAM

REFERENCE

TRACK-AND-HOLD

CLOCK

MANAGEMENT

RESET

Figure 1. Functional Block Diagram

AGNDPWDNRBIAS AVDD (1.8V)

12 12

ADC 12-BIT CORE

SERIAL PORT

SCLK SDIO CSB

AD9230

OUTPUT

STAGING

LVDS

DRVDD

DRGND

D11 TO D0

OR+

OR–

DCO+

DCO–

06002-001

APPLICATIONS

Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

GENERAL DESCRIPTION

The AD9230 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 250 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.

The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.

Fabricated on an advanced CMOS process, the AD9230 is available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. High Performance—Maintains 64.9 dBFS SNR @ 250 MSPS

with a 70 MHz input.

2. Low Power—Consumes only 434 mW @ 250 MSPS.

3. Ease of Use—LVDS output data and output clock signal

allow interface to current FPGA technology. The on-chip reference and sample and hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design.

4. Serial Port Control—Standard serial port interface supports

various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation.

5. Pin-Compatible Family—10-bit pin-compatible family

offered as AD9211.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9230

REVISION HISTORY

2/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD9230

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 1.

Parameter

1

RESOLUTION 12 12 12 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error 25°C 4.2 4.3 4.5 mV Full −12 12 −12 12 −12 12 mV Gain Error 25°C 0.89 1.0 1.1 mV Full −1.5 3.5 −1.5 3.5 −1.5 3.5 % FS Differential Nonlinearity 25°C ±0.3 ±0.3 ±0.3 LSB (DNL) Full −0.5 0.5 −0.5 0.5 −0.6 0.6 LSB Integral Nonlinearity (INL) 25°C ±0.5 ±0.4 ±0.5 LSB Full −0.75 0.75 −0.75 0.75 −1.0 +1.0 LSB

TEMPERATURE DRIFT

Offset Error Full Gain Error Full 0.019 0.021 0.018 %/°C

ANALOG INPUTS (VIN+, VIN−)

Differential Input Voltage Range2Full 0.98 1.25 1.5 0.98 1.25 1.5 0.98 1.25 1.5 V p-p Input Common-Mode Voltage Full 1.4 1.4 1.4 V Input Resistance (Differential) Full 4.3 4.3 4.3 kΩ Input Capacitance 25°C 2 2 2 pF

POWER SUPPLY

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Currents

3

I

AVDD

3

I

/SDR Mode

DRVDD

3

I

/DDR Mode

DRVDD

Power Dissipation

SDR Mode DDR Mode

1

See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.

2

The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section.

3

I

and I

AVDD

4

Single data rate mode; this is the default mode of the AD9230.

5

Double data rate mode; user-programmable feature. See the Memory Map section.

are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate.

DRVDD

4

5

3

4

5

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

MAX

AD9230-170 AD9230-210 AD9230-250

Temp Min Typ Max Min Typ Max Min Typ Max Unit

±9

±8

±7

μV/°C

Full 136 145 154 164 181 194 mA Full 58 61 59 62 60 63 mA Full 39 40 41 mA Full mW Full 349 371 383 407 434 463 mW Full 315 349 400 mW

Rev. 0 | Page 3 of 32

AD9230

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

1

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

MAX

Table 2.

AD9230-170 AD9230-210 AD9230-250

Parameter2 Temp Min Typ Max Min Typ Max Min Typ Max Unit

SNR

fIN = 10 MHz 25°C 63.8 64.6 63.7 64.5 63.3 64.1 dB

Full 63.5 63.4 62.5 dB

fIN = 70 MHz 25°C 63.5 64.3 63.3 64.2 63.0 63.9 dB

Full 63.3 63.1 62.3 dB

fIN = 170 MHz

3

25°C 63.5 63.4 63.3 dB

fIN = 225 MHz 25°C 63.0 61.5 63.3 dB SINAD

fIN = 10 MHz 25°C 63.7 64.5 63.6 64.4 63.3 64.0 dB

Full 63.4 63.4 62.4 dB

fIN = 70 MHz 25°C 63.3 64.1 63.2 64.0 62.9 63.7 dB

Full 63.1 63.0 62.2 dB

fIN = 170 MHz

3

25°C 63.3 63.1 63.0 dB

fIN = 225 MHz 25°C 61.8 61.1 62.8 dB EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 10 MHz 25°C 10.6 10.6 10.5 Bits

fIN = 70 MHz 25°C 10.5 10.5 10.4 Bits

fIN = 170 MHz

3

25°C 10.4 10.4 10.3 Bits

fIN = 225 MHz 25°C 10.1 10.0 10.3 Bits WORST HARMONIC (Second or Third)

fIN = 10 MHz 25°C −82 −78 −86 −80 −84 −79 dBc

Full −78 −78 −76 dBc

fIN = 70 MHz 25°C −78 −76 −80 −77 −79 −76 dBc

Full −75 −75 −75 dBc

fIN = 170 MHz

3

25°C −78 −79 −78 dBc

fIN = 225 MHz 25°C −68 −70 −75 dBc WORST OTHER

(SFDR Excluding Second and Third)

fIN = 10 MHz 25°C −89 −84 −89 −84 −84 −79 dBc

Full −83 −83 −76 dBc

fIN = 70 MHz 25°C −89 −83 −86 −81 −83 −79 dBc

Full −83 −81 −75 dBc

fIN = 170 MHz

3

25°C −89 −79 −83 dBc

fIN = 225 MHz 25°C −80 −79 −80 dBc TWO-TONE IMD

140.2 MHz/141.3 MHz @ −7 dBFS 25°C 73 75 78 dBc

170.2 MHz/171.3 MHz @ −7 dBFS 25°C 67 73 dBc

ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz

1

All ac specifications tested by driving CLK+ and CLK− differentially.

2

See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.

3

140 MHz for the AD9230-170 speed grade, 170 MHz for the AD9230-210 and AD9230-250 speed grades.

Rev. 0 | Page 4 of 32

AD9230

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 3.

AD9230-170 AD9230-210 AD9230-250 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit

CLOCK INPUTS

Logic Compliance Full CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 1.2 1.2 V Differential Input Voltage Full 0.2 6 0.2 6 0.2 6 V p-p Input Voltage Range Full

Input Common-Mode Range Full 1.1 AVDD 1.1 AVDD 1.1 AVDD V High Level Input Voltage (VIH) Full 1.2 3.6 1.2 3.6 1.2 3.6 V Low Level Input Voltage (VIL) Full 0 0.8 0 0.8 0 0.8 V High Level Input Current (IIH) Full −10 +10 −10 +10 −10 +10 μA Low Level Input Current (IIL) Full −10 +10 −10 +10 −10 +10 μA Input Resistance

(Differential) Input Capacitance Full 4 4 4 pF

LOGIC INPUTS

Logic 1 Voltage Full

Logic 0 Voltage Full

Logic 1 Input Current (SDIO) Full 0 0 0 μA Logic 0 Input Current (SDIO) Full −60 −60 −60 μA Logic 1 Input Current

(SCLK, PDWN, CSB, RESET) Logic 0 Input Current

(SCLK, PDWN, CSB, RESET) Input Capacitance 25°C 4 4 4 pF

LOGIC OUTPUTS2

VOD Differential Output Voltage Full 247 454 247 454 247 454 mV VOS Output Offset Voltage Full 1.125 1.375 1.125 1.375 1.125 1.375 V Output Coding Twos complement, Gray code, or offset binary (default)

1

See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.

2

LVDS R

TERMINATION

= 100 Ω.

= −40°C, T

MIN

AVDD −

0.3

= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

MAX

AVDD +

1.6

AVDD −

0.3

AVDD +

1.6

AVDD −

0.3

AVDD +

1.6

V

Full 16 20 24 16 20 24 16 20 24 kΩ

0.8 × VDD

0.2 × AVDD

0.8 × VDD

0.2 × AVDD

0.8 ×

V

VDD

0.2 × AVDD

V

Full 55 55 50 μA

Full 0 0 0 μA

Rev. 0 | Page 5 of 32

AD9230

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 4.

AD9230-170 AD9230-210 AD9230-250 Parameter (Conditions) Temp Min Typ Max Min Typ Max Unit

Maximum Conversion Rate Full 170 Minimum Conversion Rate Full CLK+ Pulse Width High (tCH) Full 2.65 2.9 2.15 2.4 1.8 2.0 ns CLK+ Pulse Width Low (tCL) Full 2.65 2.9 2.15 2.4 1.8 2.0 ns Output (LVDS − SDR Mode)

1

Data Propagation Delay (tPD) Full 3.0 3.0 3.0 ns

Rise Time (tR) (20% to 80%) 25°C 0.2 0.2 0.2 ns

Fall Time (tF) (20% to 80%) 25°C 0.2 0.2 0.2 ns

DCO Propagation Delay (t

Data to DCO Skew (t

CPD

) Full −0.3 0.1 0.5 −0.3 0.1 0.5 −0.3 0.1 0.5 ns

SKEW

Latency Full 7 7 7 Cycles Output (LVDS − DDR Mode)

2

Data Propagation Delay (tPD) Full 3.8 3.8 3.8 ns

Rise Time (tR) (20% to 80%) 25°C 0.2 0.2 0.2 ns

Fall Time (tF) (20% to 80%) 25°C 0.2 0.2 0.2 ns

DCO Propagation Delay (t

Data to DCO Skew (t

CPD

) Full −0.5 0.1 0.3 −0.5 0.1 0.3 −0.5 0.1 0.3 ns

SKEW

Latency Full 7 7 7 Cycles Aperture Uncertainty (Jitter, tJ) 25°C 0.2 0.2 ps rms

1

See Figure 2.

2

See Figure 3.

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

MAX

40

210

250 40

40 MSPS

MSPS

) Full 3.9 3.9 3.9 ns

Rev. 0 | Page 6 of 32

AD9230

TIMING DIAGRAMS

VIN

N – 1

t

A

N

N + 3

N + 4

N + 5

CLK+

CLK–

DCO+

DCO–

DX+

DX–

VIN

CLK+

CLK–

DCO+

DCO–

D0/D6+

D0/D6–

t

CH

N – 1

N + 1

t

CL

t

CPD

1/

f

S

t

SKEW

t

PD

N – 7 N – 6 N – 5 N – 4 N – 3

N + 2

06002-002

Figure 2. Single Data Rate Mode

t

A

N

N + 3

N + 1

t

CH

CL

t

CPD

1/

f

S

t

SKEW

t

PD

D6

N – 8D0N – 7D6N – 7D0N – 6D6N – 6D0N – 5D6N – 5D0N – 4D6N – 4D0N – 3

N + 2

N + 4

N + 5

D5/D11+

D5/D11–

D11

N – 8D5N – 7

6 MSBs

6 LSBs

D11

N – 7D5N – 6

D11

N – 6D5N – 5

D11

N – 5D5N – 4

D11

N – 4D5N – 3

06002-003

Figure 3. Double Data Rate Mode

Rev. 0 | Page 7 of 32

AD9230

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

ELECTRICAL

AVDD to AGND −0.3 V to +2.0 V

DRVDD to DRGND −0.3 V to +2.0 V

AGND to DRGND −0.3 V to +0.3 V

AVDD to DRVDD −2.0 V to +2.0 V

D0+/D0− through D13+/D13−

to DRGND DCO to DRGND −0.3 V to DRVDD + 0.3 V OR to DGND −0.3 V to DRVDD + 0.3 V CLK+ to AGND −0.3 V to +3.9 V CLK− to AGND −0.3 V to +3.9 V VIN+ to AGND −0.3 V to AVDD + 0.2 V VIN− to AGND −0.3 V to AVDD + 0.2 V SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V PDWN to AGND −0.3 V to +3.9 V CSB to AGND −0.3 V to +3.9 V SCLK/DFS to AGND −0.3 V to +3.9 V

ENVIRONMENTAL

Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature

(Soldering 10 sec) Junction Temperature 150°C

−0.3 V to DRVDD + 0.3 V

300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package.

Table 6.

Package Type θJA θ

56-Lead LFCSP (CP-48-3) 30.4 2.9 °C/W

Unit

JC

Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θ

JA

. In addition, metal in direct contact with the package leads from metal traces, and through holes, ground, and power planes reduces the θ

.

JA

ESD CAUTION

Rev. 0 | Page 8 of 32

AD9230

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

)

D2–

D2+

55

56

1D3– 2D3+ 3D4– 4D4+ 5D5– 6D5+ 7DRVDD 8DRG ND

9D6– 10D6+ 11D7– 12D7+ 13D8– 14D8+

PIN 1 INDICATO R

PIN 0 (EXPOSED PADDLE) = AGND

16

15

D9–

D9+

Figure 4. Single Data Rate Mode

D0+ (LSB

D1–

D1+

52

53

54

AD9230

TOP VIEW

(Not to Scale)

17

19

18

D10–

D10+

(MSB) D11–

DCO+

D0– (LSB)

50

51

21

20

OR–

(MSB) D11+

Table 7. Single Data Rate Mode Pin Function Descriptions

Pin No. Mnemonic Description

30, 32 to 34, 37 to 39,

AVDD 1.8 V Analog Supply.

41 to 43, 46 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 0 AGND 8, 23, 48 DRGND

1

Analog Ground.

Digital Output Ground. 35 VIN+ Analog Input—True. 36 VIN− Analog Input—Complement. 40 CML

Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the

optimized internal bias voltage for VIN+/VIN−. 44 CLK+ Clock Input—True. 45 CLK− Clock Input—Complement. 31 RBIAS Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V. 28 RESET CMOS-Compatible Chip Reset (Active Low). 25 SDIO/DCS

Serial Port Interface (SPI®) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select

(External Pin Mode). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 29 PWDN Chip Power-Down. 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 51 D0− D0 Complement Output Bit (LSB). 52 D0+ D0 True Output Bit (LSB). 53 D1− D1 Complement Output Bit. 54 D1+ D1 True Output Bit. 55 D2− D2 Complement Output Bit. 56 D2+ D2 True Output Bit. 1 D3− D3 Complement Output Bit. 2 D3+ D3 True Output Bit. 3 D4− D4 Complement Output Bit. 4 D4+ D4 True Output Bit.

CLK–

AVDD

DRVDD

DRGND

DCO–

48

49

22

23

ND

OR+

DRG

AVDD

CLK+

44

43

45

46

47

42 AVDD 41 AVDD 40 CML 39 AVDD 38 AVDD 37 AVDD 36 VIN– 35 VIN+ 34 AVDD 33 AVDD 32 AVDD 31 RBIAS 30 AVDD 29 PWDN

24

25

26

27

28

CSB

ESET R

DRVDD

SDIO/DCS

SCLK/DFS

06002-004

Rev. 0 | Page 9 of 32

AD9230

Pin No. Mnemonic Description

5 D5− D5 Complement Output Bit. 6 D5+ D5 True Output Bit. 9 D6− D6 Complement Output Bit. 10 D6+ D6 True Output Bit. 11 D7− D7 Complement Output Bit. 12 D7+ D7 True Output Bit. 13 D8− D8 Complement Output Bit. 14 D8+ D8 True Output Bit. 15 D9− D9 Complement Output Bit. 16 D9+ D9 True Output Bit. 17 D10− D10 Complement Output Bit. 18 D10+ D10 True Output Bit. 19 D11− D11 Complement Output Bit (MSB). 20 D11+ D11 True Output Bit (MSB). 21 OR− Overrange Complement Output Bit. 22 OR+ Overrange True Output Bit.

1

AGND and DRGND should be tied to a common quiet ground plane.

Rev. 0 | Page 10 of 32

Analog Devices AD9230 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS