Analog Devices AD9228 Service Manual

Quad, 12-Bit, 40/65 MSPS

A

V

FEATURES

4 ADCs integrated into 1 package
119 mW ADC power per channel at 65 MSPS
SNR = 70 dB (to Nyquist)
ENOB = 11.3 bits
SFDR = 82 dBc (to Nyquist)
Excellent linearity

DNL = ±0.3 LSB (typical)
INL = ±0.4 LSB (typical)

Serial LVDS (ANSI-644, default)

Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
315 MHz full-power analog bandwidth
2 V p-p input voltage range

1.8 V supply operation
Serial port control

Full-chip and individual-channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

APPLICATIONS

Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tap e dr ive s
Optical networking
Test equipment

GENERAL DESCRIPTION

The AD9228 is a quad, 12-bit, 40/65 MSPS analog-to-digital con­verter (ADC) with an on-chip sample-and-hold circuit designed
for low cost, low power, small size, and ease of use. The product
operates at a conversion rate of up to 65 MSPS and is optimized for
outstanding dynamic performance and low power in applications
where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.

The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

Serial LVDS 1.8 V A/D Converter

AD9228

FUNCTIONAL BLOCK DIAGRAM

+
–

AGND

PDWN

AD9228

0.5V

SERIAL PORT

INTERFACE

SDIO/ODMRBIAS

CSB

PIPELINE

ADC

PIPELINE

ADC

PIPELINE

ADC

PIPELINE

ADC

Figure 1.

DRVDD

12

12

12

12

SCLK/DTP

DRGND

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

DATA RATE

MULTI PLI ER

CLK+

CLK–

DD

VIN + A

VIN – A

VIN + B

VIN – B

VIN + C

VIN – C

VIN + D

VIN – D

VREF

SENSE

REFT

REFB

REF

SELECT

capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual­channel power-down is supported and typically consumes less
than 2 mW when all channels are disabled.

The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user­defined test patterns entered via the serial port interface (SPI).

The AD9228 is available in a RoHS compliant, 48-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Small Footprint. Four ADCs are contained in a small, space-

saving package.

2. Low power of 119 mW/channel at 65 MSPS.

3. Ease of Use. A data clock output (DCO) is provided that

operates at frequencies of up to 390 MHz and supports
double data rate operation (DDR).

4. User Flexibility. The SPI control offers a wide range of flexible

features to meet specific system requirements.

5. Pin-Compatible Family. This includes the AD9287 (8-bit),

AD9219 (10-bit), and AD9259 (14-bit).

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2007 Analog Devices, Inc. All rights reserved.

D + A
D – A

D + B
D – B

D + C
D – C

D + D
D – D

FCO+

FCO–

DCO+
DCO–

5727-001

AD9228

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Diagrams.............................................................................. 7

Absolute Maximum Ratings............................................................ 9

Thermal Impedance..................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Analog Input Considerations ................................................... 19

Clock Input Considerations...................................................... 22

Serial Port Interface (SPI).............................................................. 30

Hardware Interface..................................................................... 30

Memory Map .................................................................................. 32

Reading the Memory Map Table.............................................. 32

Reserved Locations .................................................................... 32

Default Values............................................................................. 32

Logic Levels................................................................................. 32

Evaluation Board ............................................................................ 36

Power Supplies ............................................................................ 36

Input Signals................................................................................ 36

Output Signals ............................................................................ 36

Default Operation and Jumper Selection Settings................. 37

Alternative Analog Input Drive Configuration...................... 38

Equivalent Circuits......................................................................... 12

Typical Performance Characteristics ........................................... 14

Theory of Operation ...................................................................... 19

REVISION HISTORY

5/07—Rev. 0 to Rev. A

Changes to Features.......................................................................... 1

Change to Effective Number of Bits (ENOB) ............................... 4

Changes to Logic Output (SDIO/ODM) Section......................... 5

Added Endnote 3 to Table 3 ............................................................ 5

Changes to Pipeline Latency ........................................................... 6

Added Endnote 2 to Table 4 ............................................................ 6

Changes to Figure 2 to Figure 4...................................................... 7

Changes to Figure 10...................................................................... 12

Changes to Figure 15, Figure 17 to Figure 19, Figure 37, and

Figure 39 .....................................................................................14

Changes to Figure 23 to Figure 26 Captions............................... 15

Change to Figure 35 Caption........................................................ 17

Added Figure 46 and Figure 47..................................................... 20

Changes to Figure 51...................................................................... 21

Changes to Clock Duty Cycle Considerations Section.............. 22

Changes to Power Dissipation and Power-Down Mode Section ...23

Changes to Figure 61 to Figure 63 Captions............................... 25

Changes to Table 9 Endnote.......................................................... 26

Changes to Digital Outputs and Timing Section ....................... 27

Rev. A | Page 2 of 52

Outline Dimensions ....................................................................... 52

Ordering Guide .......................................................................... 52

Added Table 10 ............................................................................... 27

Changes to RBIAS Pin Section ..................................................... 28

Deleted Figure 62 and Figure 63 .................................................. 27

Changes to Figure 67...................................................................... 29

Changes to Hardware Interface Section ...................................... 30

Added Figure 68 ............................................................................. 31

Changes to Table 15 ....................................................................... 31

Changes to Reading the Memory Map Table Section ............... 32

Change to Input Signals Section................................................... 36

Changes to Output Signals Section.............................................. 36

Changes to Figure 71...................................................................... 36

Changes to Default Operation and

Jumper Selection Settings Section........................................... 37

Changes to Alternative Analog Input

Drive Configuration Section.................................................... 38

Changes to Figure 74...................................................................... 40

Changes to Table 17 ....................................................................... 48

Changes to Ordering Guide.......................................................... 52

4/06—Revision 0: Initial Version

AD9228

SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 1.

AD9228-40 AD9228-65
Parameter

RESOLUTION 12 12 Bits
ACCURACY

No Missing Codes Full Guaranteed Guaranteed
Offset Error Full ±1 ±8 ±1 ±8 mV
Offset Matching Full ±2 ±8 ±2 ±8 mV
Gain Error Full ±0.4 ±1.2 ±2 ±3.5 % FS
Gain Matching Full ±0.3 ±0.7 ±0.3 ±0.7 % FS
Differential Nonlinearity (DNL) Full ±0.25 ±0.5 ±0.3 ±0.65 LSB
Integral Nonlinearity (INL) Full ±0.4 ±1 ±0.4 ±1 LSB

TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ppm/°C
Gain Error Full ±17 ±17 ppm/°C
Reference Voltage (1 V Mode) Full ±21 ±21 ppm/°C

REFERENCE

Output Voltage Error (V
Load Regulation at 1.0 mA (V
Input Resistance Full 6 6 kΩ

ANALOG INPUTS

Differential Input Voltage (V
Common-Mode Voltage Full AVDD/2 AVDD/2 V
Differential Input Capacitance Full 7 7 pF
Analog Bandwidth, Full Power Full 315 315 MHz

POWER SUPPLY

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
I

AVDD

I

DRVDD

Total Power Dissipation (Including Output Drivers) Full 335 367 478 510 mW
Power-Down Dissipation Full 2 5.8 2 5.8 mW

Standby Dissipation
CROSSTALK Full −100 −100 dB
CROSSTALK (Overrange Condition)

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Can be controlled via the SPI.

3

Overrange condition is specific with 6 dB of the full-scale input range.

1

= 1 V) Full ±2 ±30 ±2 ±30 mV

REF

= 1 V) Full 3 3 mV

REF

= 1 V) Full 2 2 V p-p

REF

Temperature Min Typ Max Min Typ Max Unit

Full 155 170 232 245 mA
Full 31 34 34 38 mA

2

3

Full 72 72 mW

Full −100 −100 dB

Rev. A | Page 3 of 52

AD9228

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 2.

AD9228-40 AD9228-65
Parameter

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 2.4 MHz Full 70.5 70.2 dB
fIN = 19.7 MHz Full 68.5 70.2 70.0 dB
fIN = 35 MHz Full 70.2 68.5 70.0 dB
fIN = 70 MHz Full 70.0 69.5 dB

SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)

fIN = 2.4 MHz Full 70.3 70.0 dB
fIN = 19.7 MHz Full 68.0 69.8 70.0 dB
fIN = 35 MHz Full 69.7 68.0 69.8 dB
fIN = 70 MHz Full 69.5 69.0 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.4 MHz Full 11.42 11.37 Bits
fIN = 19.7 MHz Full 11.1 11.37 11.33 Bits
fIN = 35 MHz Full 11.37 11.1 11.33 Bits
fIN = 70 MHz Full 11.33 11.25 Bits

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.4 MHz Full 85 85 dBc
fIN = 19.7 MHz Full 72 82 85 dBc
fIN = 35 MHz Full 80 73 84 dBc

fIN = 70 MHz Full 80 74 dBc
WORST HARMONIC (Second or Third)
fIN = 2.4 MHz Full −85 −85 dBc
fIN = 19.7 MHz Full −82 −72 −85 dBc
fIN = 35 MHz Full −80 −84 −73 dBc
fIN = 70 MHz Full −80 −74 dBc
WORST OTHER (Excluding Second or Third)
fIN = 2.4 MHz Full −90 −90 dBc
fIN = 19.7 MHz Full −90 −80 −90 dBc
fIN = 35 MHz Full −90 −90 −79 dBc
fIN = 70 MHz Full −90 −88 dBc
TWO-TONE INTERMODULATION DISTORTION (IMD)—

AIN1 AND AIN2 = −7.0 dBFS

f

IN1

f

IN2

f

IN1

f

IN2

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

1

= 15 MHz,
= 16 MHz

= 70 MHz,
= 71 MHz

Temperature Min Typ Max Min Typ Max Unit

25°C 80.8 77.8 dBc

25°C 75.0 77.0 dBc

Rev. A | Page 4 of 52

AD9228

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 3.

AD9228-40 AD9228-65
Parameter

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL
Differential Input Voltage
Input Common-Mode Voltage Full 1.2 1.2 V
Input Resistance (Differential) 25°C 20 20 kΩ
Input Capacitance 25°C 1.5 1.5 pF

LOGIC INPUTS (PDWN, SCLK/DTP)

Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V
Logic 0 Voltage Full 0 0.3 0.3 V
Input Resistance 25°C 30 30 kΩ
Input Capacitance 25°C 0.5 0.5 pF

LOGIC INPUT (CSB)

Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V
Logic 0 Voltage Full 0 0.3 0.3 V
Input Resistance 25°C 70 70 kΩ
Input Capacitance 25°C 0.5 0.5 pF

LOGIC INPUT (SDIO/ODM)

Logic 1 Voltage Full 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 V
Logic 0 Voltage Full 0 0.3 0 0.3 V
Input Resistance 25°C 30 30 kΩ
Input Capacitance 25°C 2 2 pF

LOGIC OUTPUT (SDIO/ODM)

Logic 1 Voltage (IOH = 800 μA) Full 1.79 1.79 V
Logic 0 Voltage (IOL = 50 μA) Full 0.05 0.05 V

DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)

Logic Compliance LVDS LVDS
Differential Output Voltage (VOD) Full 247 454 247 454 mV
Output Offset Voltage (VOS) Full 1.125 1.375 1.125 1.375 V
Output Coding (Default) Offset binary Offset binary

DIGITAL OUTPUTS (D + x, D − x),

(Low Power, Reduced Signal Option)
Logic Compliance LVDS LVDS
Differential Output Voltage (VOD) Full 150 250 150 250 mV
Output Offset Voltage (VOS) Full 1.10 1.30 1.10 1.30 V
Output Coding (Default) Offset binary Offset binary

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

This is specified for LVDS and LVPECL only.

3

This is specified for 13 SDIO pins sharing the same connection.

1

2

3

Temperature Min Typ Max Min Typ Max Unit

Full 250 250 mV p-p

Rev. A | Page 5 of 52

AD9228

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 4.

AD9228-40 AD9228-65

Parameter

CLOCK

OUTPUT PARAMETERS

APERTURE

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured on standard FR-4 material.

3

Can be adjusted via the SPI.

4

t

SAMPLE

1, 2

3

Temp

Min Typ Max Min Typ Max Unit

Maximum Clock Rate Full 40 65 MSPS

Minimum Clock Rate Full 10 10 MSPS

Clock Pulse Width High (tEH) Full 12.5 7.7 ns

Clock Pulse Width Low (tEL) Full 12.5 7.7 ns

3

Propagation Delay (tPD) Full 2.0 2.7 3.5 2.0 2.7 3.5 ns

Rise Time (tR) (20% to 80%) Full 300 300 ps

Fall Time (tF) (20% to 80%) Full 300 300 ps

FCO Propagation Delay (t

DCO Propagation Delay (t

DCO to Data Delay (t

DCO to FCO Delay (t

Data to Data Skew

(t

− t

DATA-MAX

DATA-MIN

) Full 2.0 2.7 3.5 2.0 2.7 3.5 ns

FCO

)4Full t

CPD

DATA

FRAME

4

)

)

4

Full (t

Full (t

/24) − 300 (t

SAMPLE

/24) − 300 (t

SAMPLE

FCO

(t

+

SAMPLE

SAMPLE

SAMPLE

t

/24)
/24) (t

/24) (t

/24) + 300 (t

SAMPLE

/24) + 300 (t

SAMPLE

/24) − 300 (t

SAMPLE

/24) − 300 (t

SAMPLE

FCO

(t

SAMPLE

SAMPLE

SAMPLE

+

/24)
/24) (t

/24) (t

ns

/24) + 300 ps

SAMPLE

/24) + 300 ps

SAMPLE

Full ±50 ±150 ±50 ±150 ps

)
Wake-Up Time (Standby) 25°C 600 600 ns
Wake-Up Time (Power-Down) 25°C 375 375 μs
Pipeline Latency Full 8 8 CLK

cycles

Aperture Delay (tA) 25°C 500 500 ps
Aperture Uncertainty (Jitter) 25°C <1 <1 ps rms
Out-of-Range Recovery Time 25°C 1 2 CLK

cycles

/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.

Rev. A | Page 6 of 52

AD9228

TIMING DIAGRAMS

N – 1

AIN

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D – x

D + x

N – 1

t

A

N

t

EH

t

CPD

t

FCO

t

PD

t

FRAME

MSB

D10

N – 9

N – 9D9N – 9D8N – 9D7N – 9D6N – 9D5N – 9D4N – 9D3N – 9D2N – 9D1N – 9D0N – 9

t

EL

t

DATA

D10

MSB

N – 8

N – 8

05727-039

Figure 2. 12-Bit Data Serial Stream, MSB First (Default)

AIN

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D – x

D + x

t

A

N

D6

N – 9

t

D5

N – 9

EL

t

DATA

D4

N – 9

D3

N – 9

D2

N – 9

D1

N – 9

D0

N – 9

MSB
N – 8

D8

N – 8D7N – 8

D6

N – 8

D5

N – 8

05727-040

t

EH

t

CPD

MSB
N – 9

t

FRAME

D8

N – 9D7N – 9

t

FCO

t

PD

Figure 3. 10-Bit Data Serial Stream, MSB First

Rev. A | Page 7 of 52

AD9228

N – 1

AIN

t

A

N

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D – x

D + x

t

EH

t

CPD

t

FCO

t

PD

t

FRAME

LSB

N – 9D0N – 9D1N – 9D2N – 9D3N – 9D4N – 9D5N – 9D6N – 9D7N – 9D8N – 9D9N – 9

t

EL

t

DATA

D10

N – 9

LSB

N – 8

D0

N – 8

05727-041

Figure 4. 12-Bit Data Serial Stream, LSB First

Rev. A | Page 8 of 52

AD9228

ABSOLUTE MAXIMUM RATINGS

Table 5.

With

Parameter

ELECTRICAL

AVDD AGND −0.3 V to +2.0 V
DRVDD DRGND −0.3 V to +2.0 V
AGND DRGND −0.3 V to +0.3 V
AVDD DRVDD −2.0 V to +2.0 V
Digital Outputs

(D + x, D − x, DCO+,

DCO−, FCO+, FCO−)
CLK+, CLK− AGND −0.3 V to +3.9 V
VIN + x, VIN − x AGND −0.3 V to +2.0 V
SDIO/ODM AGND −0.3 V to +2.0 V
PDWN, SCLK/DTP, CSB AGND −0.3 V to +3.9 V
REFT, REFB, RBIAS AGND −0.3 V to +2.0 V
VREF, SENSE AGND −0.3 V to +2.0 V

ENVIRONMENTAL

Operating Temperature

Range (Ambient)
Maximum Junction

Temperature
Lead Temperature

(Soldering, 10 sec)
Storage Temperature

Range (Ambient)

Respect To

DRGND −0.3 V to +2.0 V

−40°C to +85°C

150°C

300°C

−65°C to +150°C

Rating

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL IMPEDANCE

Table 6.

Air Flow Velocity (m/sec) θ

0.0 24 °C/W

1.0 21 12.6 1.2 °C/W

2.5 19 °C/W

1

θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad

soldered to PCB.

1

θ

JA

θ

JB

Unit

JC

ESD CAUTION

Rev. A | Page 9 of 52

AD9228

C

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD

AVDD

VIN – D

VIN + D

AVDD

AVDD

CLK–

CLK+

AVDD

AVDD

DRGND

DRVDD

VIN –

VIN + C

47

48

PIN 1
INDICATOR

1

2

3

4

5

6

7

8

9

10

11

12

14

13

D – D

D + D

REFT

REFB

43

44

AD9228

TOP VIEW

17

18

D – B

D + B

VREF

42

19

D – A

AVDD

AVDD

45

46

EXPOSED PADDLE, PIN 0
(BOTTO M OF PACKAGE)

16

15

D – C

D + C

SENSE

41

20

D + A

RBIAS

40

VIN + B

VIN – B

AVDD

37

38

39

36

AVDD

35

AVDD

34

VIN – A

33

VIN + A

32

AVDD

31

PDWN

30

CSB

29

SDIO/ODM

28

SCLK/DTP

27

AVDD

26

DRGND

25

DRVDD

222123

24

FCO–

FCO+

DCO–

DCO+

Figure 5. 48-Lead LFCSP Pin Configuration, Top View

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

0 AGND Analog Ground (Exposed Paddle)
1, 2, 5, 6, 9, 10, 27, 32,

35, 36, 39, 45, 46
11, 26
12, 25
3
4
7

AVDD 1.8 V Analog Supply

DRGND Digital Output Driver Ground
DRVDD 1.8 V Digital Output Driver Supply
VIN − D ADC D Analog Input Complement
VIN + D ADC D Analog Input True

CLK− Input Clock Complement
8 CLK+ Input Clock True
13
14
15
16
17
18

D − D ADC D Digital Output Complement

D + D ADC D Digital Output True

D − C ADC C Digital Output Complement

D + C ADC C Digital Output True

D − B ADC B Digital Output Complement

D + B ADC B Digital Output True
19 D − A ADC A Digital Output Complement
20 D + A ADC A Digital Output True
21
22
23
24

FCO− Frame Clock Output Complement

FCO+ Frame Clock Output True

DCO− Data Clock Output Complement

DCO+ Data Clock Output True
28 SCLK/DTP Serial Clock/Digital Test Pattern
29
30

SDIO/ODM Serial Data IO/Output Driver Mode

CSB Chip Scale Bar
31 PDWN Power-Down
33
34

VIN + A ADC A Analog Input True

VIN − A ADC A Analog Input Complement

Rev. A | Page 10 of 52

05727-003

AD9228

Pin No. Mnemonic Description

37
38
40
41
42
43
44
47
48

VIN − B ADC B Analog Input Complement
VIN + B ADC B Analog Input True
RBIAS External resistor sets the internal ADC core bias current
SENSE Reference Mode Selection
VREF Voltage Reference Input/Output
REFB Differential Reference (Negative)
REFT Differential Reference (Positive)
VIN + C ADC C Analog Input True
VIN − C ADC C Analog Input Complement

Rev. A | Page 11 of 52

AD9228



C

S

EQUIVALENT CIRCUITS

DRVDD

VIN ± x

Figure 6. Equivalent Analog Input Circuit

LK+

CLK–

10

10k

1.25V

10k

10

V

D– D+

V

05727-030

DRGND

V

V

05727-005

Figure 9. Equivalent Digital Output Circuit

SCLK/DTP

AND

PDWN

1k

30k

Figure 7. Equivalent Clock Input Circuit

DIO/ODM

350

30k

Figure 8. Equivalent SDIO/ODM Input Circuit

05727-032

5727-033

Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit

RBIAS

05727-035

100

05727-031

Figure 11. Equivalent RBIAS Circuit

Rev. A | Page 12 of 52

AD9228

A

V

DD

70k

CSB

1k

VREF

05727-037

Figure 12. Equivalent CSB Input Circuit

SENSE

1k

6k

05727-034

Figure 14. Equivalent VREF Circuit

05727-036

Figure 13. Equivalent SENSE Circuit

Rev. A | Page 13 of 52

AD9228

TYPICAL PERFORMANCE CHARACTERISTICS

–20

0

AIN = –0.5dBFS

SNR = 70.51dB

ENOB = 11.42 BITS

SFDR = 86.00dBc

–20

0

AIN = –0.5dBFS

SNR = 69.62dB

ENOB = 11.27 BITS

SFDR = 72.48dBc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 2 4 6 8 101214161820

Figure 15. Single-Tone 32k FFT with f

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

FREQUENCY (MHz )

= 2.4 MHz, f

IN

SAMPLE

AIN = –0.5dBFS

SNR = 70.38dB

ENOB = 11.40 BITS

SFDR = 81.13d Bc

= 40 MSPS

–40

–60

–80

AMPLITUDE (dBFS)

–100

05727-052

–120

0 5 10 15 20 25 30

Figure 18. Single-Tone 32k FFT with f

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

FREQUENCY (MHz )

= 70 MHz, f

IN

= 65 MSPS

SAMPLE

AIN = –0.5dBF S

SNR = 68.74dB

ENOB = 11.12 BITS

SFDR = 72.99dBc

05727-054

–120

01412108642116 20

Figure 16. Single-Tone 32k FFT with f

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 5 10 15 20 25 30

Figure 17. Single-Tone 32k FFT with f

FREQUENCY (MHz)

= 35 MHz, f

IN

FREQUENCY (MHz )

= 2.3 MHz, f

IN

AIN = –0.5dBFS

ENOB = 11.42 BITS

SFDR = 86.04d Bc

05727-085

8

= 40 MSPS

SAMPLE

SNR = 70.53dB

05727-053

= 65 MSPS

SAMPLE

–120

0 5 10 15 20 25 30

Figure 19. Single-Tone 32k FFT with f

0

AIN = –0.5dBF S
SNR = 67.68dB
ENOB = 10.95 BI TS

–20

SFDR = 62.23d Bc

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

0 5 10 15 20 25 30

Figure 20. Single-Tone 32k FFT with f

FREQUENCY (MHz )

= 120 MHz, f

IN

FREQUENCY (MHz)

= 170 MHz, f

IN

SAMPLE

SAMPLE

05727-055

= 65 MSPS

05727-056

= 65 MSPS

Rev. A | Page 14 of 52

AD9228

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 5 10 15 20 25 30

Figure 21. Single-Tone 32k FFT with f

0

–20

–40

FREQUENCY (MHz )

= 190 MHz, f

IN

AIN = –0.5dBF S

SNR = 67.58dB

ENOB = 10.93 BI TS

SFDR = 68.39d Bc

= 65 MSPS

SAMPLE

AIN = –0.5dBF S

SNR = 65.56dB

ENOB = 10.6 BI TS

SFDR = 62.72d Bc

84

82

80

78

76

74

SNR/SFDR (dB)

72

70

05727-057

68

10 15 20 25 30 35 40

Figure 24. SNR/SFDR vs. Encode, f

90

85

80

2V p-p, SFDR

2V p-p, SNR

ENCODE (MSPS)

= 35 MHz, f

IN

2V p-p, SFDR

SAMPLE

05727-061

= 40 MSPS

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 5 10 15 20 25 30

Figure 22. Single-Tone 32k FFT with f

90

85

80

75

SNR/SFDR (dB)

70

65

60

10 15 20 25 30 35 40

Figure 23. SNR/SFDR vs. Encode, f

FREQUENCY (MHz)

= 250 MHz, f

IN

2V p-p, SF DR

2V p-p, SNR

ENCODE (MSPS)

= 10.3 MHz, f

IN

SAMPLE

= 65 MSPS

SAMPLE

= 40 MSPS

75

SNR/SFDR (dB)

70

65

05727-058

60

10 20 30 40 50 60

Figure 25. SNR/SFDR vs. Encode, f

84

82

80

78

76

74

SNR/SFDR (dB)

72

70

05727-059

68

10 20 30 40 50 60

Figure 26. SNR/SFDR vs. Encode, f

2V p-p, SNR

ENCODE (MSPS)

= 10.3 MHz, f

IN

2V p-p, SFDR

2V p-p, SNR

ENCODE (MSPS)

= 35 MHz, f

IN

SAMPLE

SAMPLE

05727-062

= 65 MSPS

05727-064

= 65 MSPS

Rev. A | Page 15 of 52

AD9228

100

f

= 10.3MHz

IN

90

f

=40MSPS

SAMPLE

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0
–60 –50 –40 –30 –20 –10 0

REFERENCE

2V p-p, SFDR

80dB

ANALOG INPUT L EVEL (dBFS)

Figure 27. SNR/SFDR vs. Analog Input Level, f

2V p-p, SNR

= 10.3 MHz, f

IN

SAMPLE

05727-065

= 40 MSPS

100

f

= 35MHz

IN

90

f

= 65MSPS

SAMPLE

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0
–60 –50 –40 –30 –20 –10 0

ANALOG INPUT LEVEL (dBFS)

Figure 30. SNR/SFDR vs. Analog Input Level, f

2V p-p, SFDR

80dB

REFERENCE

= 35 MHz, f

IN

2V p-p, SNR

= 65 MSPS

SAMPLE

05727-070

100

f

= 35MHz

IN

90

f

= 40MSPS

SAMPLE

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0

–60 –50 –40 –30 –20 –10 0

REFERENCE

2V p-p, SFDR

80dB

ANALOG INPUT L EVEL (dBFS)

Figure 28. SNR/SFDR vs. Analog Input Level, f

100

f

= 10.3MHz

IN

90

f

= 65MSPS

SAMPLE

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0

–60 –5 0 –40 –30 –20 –10 0

80dB

REFERENCE

ANALOG INPUT LEVEL (dBFS)

Figure 29. SNR/SFDR vs. Analog Input Level, f

2V p-p, SNR

= 35 MHz, f

IN

2V p-p, SFDR

2V p-p , SNR

= 10.3 MHz, f

IN

SAMPLE

SAMPLE

05727-066

= 40 MSPS

05727-068

= 65 MSPS

0

AIN1 AND AIN2 = –7dBFS
SFDR = 80.75dBc
IMD2 = 85.53dBc

–20

IMD3 = 80.83dBc

–40

–60

–80

AMPLITUDE (d BFS)

–100

–120

0 2 4 6 8 101214161820

Figure 31. Two-Tone 32k FFT with f

0

AIN1 AND AIN2 = –7dBFS
SFDR = 74.76dBc
IMD2 = 81.03dBc

–20

IMD3 = 75.00dBc

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

0 2 4 6 8 101214161820

Figure 32. Two-Tone 32k FFT with f

FREQUENCY (MHz)

IN1

= 40 MSPS

f

SAMPLE

FREQUENCY (MHz)

SAMPLE

IN1

= 40 MSPS

f

= 15 MHz and f

= 70 MHz and f

IN2

IN2

05727-049

= 16 MHz,

05727-050

= 71 MHz,

Rev. A | Page 16 of 52