Analog Devices AD9221, AD9223, AD9220 Service Manual

Complete 12-Bit 1.5/3.0/10.0 MSPS

Monolithic A/D Converters

AD9221/AD9223/AD9220

FEATURES Monolithic 12-Bit A/D Converter Product Family Family Members Are: AD9221, AD9223, and AD9220 Flexible Sampling Rates: 1.5 MSPS, 3.0 MSPS, and

10.0 MSPS Low Power Dissipation: 59 mW, 100 mW, and 250 mW Single 5 V Supply Integral Nonlinearity Error: 0.5 LSB Differential Nonlinearity Error: 0.3 LSB Input Referred Noise: 0.09 LSB Complete On-Chip Sample-and-Hold Amplifier and

Voltage Reference Signal-to-Noise and Distortion Ratio: 70 dB Spurious-Free Dynamic Range: 86 dB Out-of-Range Indicator Straight Binary Output Data 28-Lead SOIC and 28-Lead SSOP

GENERAL DESCRIPTION

The AD9221, AD9223, and AD9220 are a generation of high performance, single supply 12-bit analog-to-digital converters. Each device exhibits true 12-bit linearity and temperature drift performance

as well as 11.5-bit or better ac performance.2 The AD9221/AD9223/AD9220 share the same interface options, package, and pinout. Thus, the product family provides an upward or downward component selection path based on performance, sample rate and power. The devices differ with respect to their specified sampling rate, and power consumption, which is reflected in their dynamic performance over frequency.

The AD9221/AD9223/AD9220 combine a low cost, high speed CMOS process and a novel architecture to achieve the resolution and speed of existing hybrid and monolithic implementations at a fraction of the power consumption and cost. Each device is a complete, monolithic ADC with an on-chip, high performance, low noise sample-and-hold amplifier and programmable voltage reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. The devices use a multistage differential pipelined architecture with digital output error correction logic to provide 12-bit accuracy at the specified data rates and to guarantee no missing codes over the full operating temperature range.

The input of the AD9221/AD9223/AD9220 is highly flexible, allowing for easy interfacing to imaging, communications, medical, and data-acquisition systems. A truly differential input structure allows for both single-ended and differential input interfaces of varying input spans. The sample-and-hold

NOTES

Excluding internal voltage reference.

Depends on the analog input configuration.

REV. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

FUNCTIONAL BLOCK DIAGRAM

DVDDAVDD

MDAC3

GAIN = 4

A/D

DVSSAVSS

CML

A/D

OTR

BIT 1 (MSB)

BIT 12 (LSB)

VINA

VINB

CAPT

CAPB

VREF

SENSE

SHA

MODE

SELECT

MDAC1

GAIN = 16

REFCOM

CLK

MDAC2

GAIN = 8

A/DA/D

DIGITAL CORRECTION LOGIC

OUTPUT BUFFERS

AD9221/AD9223/AD9220

amplifier (SHA) is equally suited for both multiplexed systems that switch full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the Nyquist rate. Also, the AD9221/AD9223/AD9220 is well suited for communication systems employing DirectIF down conversion since the SHA in the differential input mode can achieve excellent dynamic performance far beyond its specified Nyquist frequency.

A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range (OTR) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow.

PRODUCT HIGHLIGHTS

The AD9221/AD9223/AD9220 family offers a complete singlechip sampling 12-bit, analog-to-digital conversion function in pin compatible 28-lead SOIC and SSOP packages.

Flexible Sampling Rates—The AD9221, AD9223, and AD9220 offer sampling rates of 1.5 MSPS, 3.0 MSPS, and 10.0 MSPS, respectively.

Low Power and Single Supply—The AD9221, AD9223, and AD9220 consume only 59 mW, 100 mW, and 250 mW, respectively, on a single 5 V power supply.

Excellent DC Performance Over Temperature—The AD9221/ AD9223/AD9220 provide 12-bit linearity and temperature drift performance.

Excellent AC Performance and Low Noise—The AD9221/ AD9223/AD9220 provide better than 11.3 ENOB performance and have an input referred noise of 0.09 LSB rms.

Flexible Analog Input Range—The versatile on-board sampleand-hold (SHA) can be configured for either single-ended or differential inputs of varying input spans.

AD9221/AD9223/AD9220–SPECIFICATIONS

DC SPECIFICATIONS

(AVDD = 5 V, DVDD = 5 V, f otherwise noted.)

= Max Conversion Rate, V

SAMPLE

= 2.5 V, VINB = 2.5 V, T

REF

MIN

to T

MAX

, unless

Parameter AD9221 AD9223 AD9220 Unit

RESOLUTION 12 12 12 Bits min

MAX CONVERSION RATE 1.5 3 10 MHz min

INPUT REFERRED NOISE (TYP)

= 1 V 0.23 0.23 0.23 LSB rms typ

REF

= 2.5 V 0.09 0.09 0.09 LSB rms typ

REF

ACCURACY

Integral Nonlinearity (INL) ±0.4 ± 0.5 ± 0.5 LSB typ

± 1.25 ± 1.25 ± 1.25 LSB max

Differential Nonlinearity (DNL) ± 0.3 ± 0.3 ± 0.3 LSB typ

± 0.75 ± 0.75 ± 0.75 LSB max ± 0.6 ± 0.6 ± 0.7 LSB typ ± 0.3 ± 0.3 ± 0.35 LSB typ

INL DNL

No Missing Codes 12 12 12 Bits Guaranteed Zero Error (@ 25°C) ± 0.3 ± 0.3 ± 0.3 % FSR max Gain Error (@ 25°C) Gain Error (@ 25°C)

± 1.5 ± 1.5 ± 1.5 % FSR max ± 0.75 ± 0.75 ± 0.75 % FSR max

TEMPERATURE DRIFT

Zero Error ± 2 ±2 ± 2 ppm/°C typ Gain Error Gain Error

± 26 ± 26 ± 26 ppm/°C typ ± 0.4 ± 0.4 ± 0.4 ppm/°C typ

POWER SUPPLY REJECTION

AVDD, DVDD (+5 V ± 0.25 V) ± 0.06 ± 0.06 ± 0.06 % FSR max

ANALOG INPUT

Input Span (with V Input Span (with V

= 1.0 V) 222V p-p min

REF

= 2.5 V) 555V p-p max

REF

Input (VINA or VINB) Range 000V min

AVDD AVDD AVDD V max

Input Capacitance 16 16 16 pF typ

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode) 111V typ Output Voltage Tolerance (1 V Mode) ±14 ±14 ±14 mV max Output Voltage (2.5 V Mode) 2.5 2.5 2.5 V typ Output Voltage Tolerance (2.5 V Mode) ±35 ±35 ±35 mV max Load Regulation

2.0 2.0 2.0 mV max

REFERENCE INPUT RESISTANCE 555kΩ typ

POWER SUPPLIES

Supply Voltages

AVDD 555V (± 5% AVDD Operating) DVDD 2.7 to 5.25 2.7 to 5.25 2.7 to 5.25 V

Supply Current

IAVDD 14.0 26 58 mA max

11.8 20 51 mA typ

IDVDD 0.5 0.5 4.0 mA max

0.02 0.02 <1.0 mA typ

POWER CONSUMPTION 59.0 100 254 mW typ

70.0 130 310 mW max

NOTES

= 1 V.

REF

Including internal reference.

Excluding internal reference.

Load regulation with 1 mA load current (in addition to that required by the AD9221/AD9223/AD9220).

Specification subject to change without notice.

REV. E–2–

AD9221/AD9223/AD9220

AC SPECIFICATIONS

(AVDD = 5 V, DVDD= 5 V, f Ended Input T

MIN

to T

MAX

= Max Conversion Rate, V

SAMPLE

, unless otherwise noted.)

= 1.0 V, VINB = 2.5 V, DC Coupled/Single-

REF

Parameter AD9221 AD9223 AD9220 Unit

MAX CONVERSION RATE 1.5 3.0 10.0 MHz min

DYNAMIC PERFORMANCE Input Test Frequency 1 (VINA = –0.5 dBFS) 100 500 1000 kHz

Signal-to-Noise and Distortion (SINAD) 70.0 70.0 70 dB typ

69.0 68.5 68.5 dB min

Effective Number of Bits (ENOBs) 11.3 11.3 11.3 dB typ

11.2 11.1 11.1 dB min

Signal-to-Noise Ratio (SNR) 70.2 70.0 70.2 dB typ

69.0 68.5 69.0 dB min

Total Harmonic Distortion (THD) –83.4 –83.4 –83.7 dB typ

–77.5 –76.0 –76.0 dB max

Spurious Free Dynamic Range (SFDR) 86.0 87.5 88.0 dB typ

79.0 77.5 77.5 dB max

Input Test Frequency 2 (VINA = –0.5 dBFS) 0.50 1.50 5.0 MHz

Signal-to-Noise and Distortion (SINAD) 69.9 69.4 67.0 dB typ

69.0 68.0 65.0 dB min

Effective Number of Bits (ENOBs) 11.3 11.2 10.8 dB typ

11.2 11.1 10.5 dB min

Signal-to-Noise Ratio (SNR) 70.1 69.7 68.8 dB typ

69.0 68.5 67.5 dB min

Total Harmonic Distortion (THD) –83.4 –82.9 –72.0 dB typ

–77.5 –75.0 –68.0 dB max

Spurious Free Dynamic Range (SFDR) 86.0 85.7 75.0 dB typ

79.0 76.0 69.0 dB max Full Power Bandwidth 25 40 60 MHz typ Small Signal Bandwidth 25 40 60 MHz typ Aperture Delay 111ns typ Aperture Jitter 444ps rms typ Acquisition to Full-Scale Step 125 43 30 ns typ

Specifications subject to change without notice.

DIGITAL SPECIFICATIONS

(AVDD = 5 V, DVDD = 5 V, T

MIN

to T

, unless otherwise noted.)

MAX

Parameter Symbol Unit

CLOCK INPUT

High Level Input Voltage V Low Level Input Voltage V High Level Input Current (V Low Level Input Current (V

= DVDD) I

= 0 V) I

Input Capacitance C

3.5 V min

1.0 V max

± 10 µA max ± 10 µA max

5 pF typ

LOGIC OUTPUTS

DVDD = 5 V High Level Output Voltage (I High Level Output Voltage (I Low Level Output Voltage (I Low Level Output Voltage (I

= 50 µA) V

= 0.5 mA) V = 1.6 mA) V = 50 µA) V

4.5 V min

2.4 V min

0.4 V max

0.1 V max DVDD = 3 V High Level Output Voltage (I High Level Output Voltage (I Low Level Output Voltage (I Low Level Output Voltage (I

= 50 µA) V

= 0.5 mA) V

= 1.6 mA) V

= 50 µA) V

Output Capacitance C

Specifications subject to change without notice.

REV. E

OUT

–3–

2.95 V min

2.80 V min

0.4 V max

0.05 V max

5 pF typ

AD9221/AD9223/AD9220

SWITCHING SPECIFICATIONS

to T

MIN

with AVDD = 5 V, DVDD = 5 V, CL = 20 pF)

MAX

Parameter Symbol AD9221 AD9223 AD9220 Unit

Clock Period* t CLOCK Pulsewidth High t CLOCK Pulsewidth Low t Output Delay t

667 333 100 ns min 300 150 45 ns min 300 150 45 ns min 888ns min 13 13 13 ns typ 19 19 19 ns max

Pipeline Delay (Latency) 333Clock Cycles

*The clock period may be extended to 1 ms without degradation in specified performance @ 25 °C.

Specifications subject to change without notice.

ANALOG

INPUT

CLOCK

DATA

OUTPUT

DATA 1

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS*

With Respect

Parameter to Min Max Unit

AVDD AVSS –0.3 +6.5 V DVDD DVSS –0.3 +6.5 V AVSS DVSS –0.3 +0.3 V AVDD DVDD –6.5 +6.5 V

THERMAL CHARACTERISTICS

Thermal Resistance 28-Lead SOIC

= 71.4°C/W

␪

= 23°C/W

28-Lead SSOP

= 63.3°C/W

␪

= 23°C/W

REFCOM AVSS –0.3 +0.3 V CLK AVSS –0.3 AVDD + 0.3 V Digital Outputs DVSS –0.3 DVDD + 0.3 V VINA, VINB AVSS –0.3 AVDD + 0.3 V VREF AVSS –0.3 AVDD + 0.3 V SENSE AVSS –0.3 AVDD + 0.3 V CAPB, CAPT AVSS –0.3 AVDD + 0.3 V Junction Temperature 150 °C Storage Temperature –65 +150 °C Lead Temperature

(10 sec) 300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.

Model Range Description Option

AD9221AR –40°C to +85°C 28-Lead SOIC R-28 AD9223AR –40°C to +85°C 28-Lead SOIC R-28 AD9220AR –40°C to +85°C 28-Lead SOIC R-28 AD9221ARS –40°C to +85°C 28-Lead SSOP RS-28 AD9223ARS –40°C to +85°C 28-Lead SSOP RS-28 AD9220ARS –40°C to +85°C 28-Lead SSOP RS-28 AD9221-EB Evaluation Board AD9223-EB Evaluation Board AD9220-EB Evaluation Board

ORDERING GUIDE

Temperature Package Package

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9221/AD9223/AD9220 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. E–4–

AD9221/AD9223/AD9220

PIN CONFIGURATION

CLK

(LSB) BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

(MSB) BIT 1

OTR

AD9221/

AD9223/

AD9220

TOP VIEW

(Not to Scale)

DVDD

DVSS

AVDD

AVSS

VINB

VINA

CML

CAPT

CAPB

REFCOM

VREF

SENSE

AVSS

AVDD

PIN FUNCTION DESCRIPTIONS

Pin Number Mnemonic Description

1 CLK Clock Input Pin 2BIT 12 Least Significant Data Bit (LSB) 3–12 BITS 11–2 Data Output Bit 13 BIT 1 Most Significant Data Bit (MSB) 14 OTR Out of Range 15, 26 AVDD 5 V Analog Supply 16, 25 AVSS Analog Ground 17 SENSE Reference Select 18 VREF Reference I/O 19 REFCOM Reference Common 20 CAPB Noise Reduction Pin 21 CAPT Noise Reduction Pin 22 CML Common-Mode Level (Midsupply) 23 VINA Analog Input Pin (+) 24 VINB Analog Input Pin (–) 27 DVSS Digital Ground 28 DVDD 3 V to 5 V Digital Supply

DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity (INL)

INL refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating ranges.

Zero Error

The major carry transition should occur for an analog value 1/2 LSB below VINA = VINB. Zero error is defined as the deviation of the actual transition from that point.

Gain Error

The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.

Temperature Drift

The temperature drift for zero error and gain error specifies the maximum change from the initial (25°C) value to the value at

or T

MIN

MAX

Power Supply Rejection

The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit.

Aperture Jitter

Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D.

Aperture Delay

Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion.

Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio

S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.

Effective Number of Bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,

N SINAD=

()

–. /.176 602

it is possible to get a measure of performance expressed as N, the effective number of bits.

Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.

Spurious Free Dynamic Range (SFDR)

SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.

REV. E

–5–

AD9221/AD9223/AD9220

AD9221–Typical Performance Characteristics

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

DNL – LSBs

–0.4

–0.6

–0.8

–1.0

0 4095

CODE

TPC 1. Typical DNL

SINAD – dB

0.1 1.0

–0.5dB

–6.0dB

–20.0dB

FREQUENCY – MHz

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

INL – LSBs

–0.4

–0.6

–0.8

–1.0

0 4095

CODE

TPC 2. Typical INL

–50

–55

–60

–20.0dB

–65

–70

–6.0dB

–75

–80

THD – dB

–85

–0.5dB

–90

–95

–100

0.1 1.0 FREQUENCY – MHz

(AVDD = 5 V, DVDD = 5 V, f

HITS

TPC 3. “Grounded-Input” Histogram (Input Span = 2 V p-p)

SINAD – dB

= 1.5 MSPS, TA = 25C)

SAMPLE

8,180,388

121,764

N–1 N N+1

–0.5dB

–6.0dB

–20.0dB

0.1 1.0

CODE

FREQUENCY – MHz

85,895

TPC 4. SINAD vs. Input Frequency (Input Span = 2.0 V p-p, VCM = 2.5 V)

–50

–55

–60

–65

–70

THD– dB

–75

–80

–85

–90

0.1 1.0 FREQUENCY – MHz

–20.0dB

–0.5dB

–6.0dB

TPC 7. THD vs. Input Frequency (Input Span = 5.0 V p-p, V

= 2.5 V)

TPC 5. THD vs. Input Frequency (Input Span = 2.0 V p-p, VCM = 2.5 V)

–60

–65

–70

–75

–80

THD – dB

–85

–90

–95

–100

0.2 1 2

0.4 0.6

SAMPLE RATE – MSPS

5V p-p

2V p-p

TPC 8. THD vs. Sample Rate (AIN = –0.5 dB, fIN = 500 kHz, VCM = 2.5 V)

TPC 6. SINAD vs. Input Frequency (Input Span = 5.0 V p-p, VCM = 2.5 V)

100

SNR/SFDR – dB

30.3 0.8

–60 –50 –30–40

SFDR

SNR

AIN – dBFS

–20 –10 0

TPC 9. SNR/SFDR vs. AIN (Input Amplitude) (fIN = 500 kHz, Input Span = 2 V p-p, VCM = 2.5 V)

REV. E–6–

AD9221/AD9223/AD9220

AD9223–Typical Performance Characteristics

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

DNL – LSBs

–0.4

–0.6

–0.8

–1.0

0 4095

CODE

TPC 10. Typical DNL

SINAD – dB

0.1 1.0 10.0 FREQUENCY – MHz

–0.5dB

–6.0dB

–20.0dB

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

INL – LSBs

–0.4

–0.6

–0.8

–1.0

0 4095

CODE

TPC 11. Typical INL

–50

–55

–60

–65

–70

–75

THD – dB

–80

–85

–90

–95

–100

0.1 1.0 FREQUENCY – MHz

–20.0dB

–0.5dB

(AVDD = 5 V, DVDD = 5 V, f

TPC 12. “Grounded-Input” Histogram (Input Span = 2 V p-p)

–6.0dB

10.0

SINAD – dB

0.1 1.0 10.0

= 3.0 MSPS, TA = 25C)

SAMPLE

8,123,672

HITS

96,830

N–1 N N+1

–0.5dB

–6.0dB

–20.0dB

FREQUENCY – MHz

130,323

CODE

TPC 13. SINAD vs. Input Frequency (Input Span = 2.0 V p-p, VCM = 2.5 V)

–50

–55

–60

–65

–20.0dB

–70

–75

–6.0dB

–80

THD – dB

–0.5dB

–85

–90

–95

–100

0.1 1.0 10.0 FREQUENCY – MHz

TPC 16. THD vs. Input Frequency (Input Span = 5.0 V p-p, VCM = 2.5 V)

TPC 14. THD vs. Input Frequency (Input Span = 2.0 V p-p, VCM = 2.5 V)

–60

–65

–70

–75

–80

THD – dB

–85

–90

–95

–100

0.6 1 2 3 5 6

0.4 0.8 4 SAMPLE RATE – MSPS

5V p-p

2V p-p

TPC 17. THD vs. Sample Rate (AIN = –0.5 dB, fIN = 500 kHz, VCM = 2.5 V)

TPC 15. SINAD vs. Input Frequency (Input Span = 5.0 V p-p, VCM = 2.5 V)

100

SNR/SFDR – dB

–60 –40

SFDR

SNR

–50 –30 –10

AIN – dBFS

–20

TPC 18. SNR/SFDR vs. AIN (Input Amplitude) (fIN = 1.5 MHz, Input Span = 2 V p-p, V

= 2.5 V)

REV. E

–7–

AD9221/AD9223/AD9220

AD9220–Typical Performance Characteristics

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

DNL – LSBs

–0.4

–0.6

–0.8

–1.0

1 4095

CODE

TPC 19. Typical DNL

SINAD – dB

0.1 1.0

–0.5dB

–6dB

–20dB

FREQUENCY – MHz

10.0

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

INL – LSBs

–0.4

–0.6

–0.8

–1.0

1 4095

CODE

TPC 20. Typical INL

–50

–55

–60

–65

–70

–75

THD – dB

–80

–85

–90

–95

–100

0.5 1.0 10.0

–20dB

–6dB

–0.5dB

FREQUENCY – MHz

(AVDD = 5 V, DVDD = 5 V, f

HITS

TPC 21. “Grounded-Input” Histogram (Input Span = 2 V p-p)

SINAD – dB

0.1 1.0 10.0

= 10 MSPS, TA = 25C)

SAMPLE

8,123,672

134,613

N–1 N N+1

–0.5dB

–6.0dB

–20.0dB

CODE

FREQUENCY – MHz

130,323

TPC 22. SINAD vs. Input Frequency (Input Span = 2.0 V p-p, V

–50

–55

–60

–65

–70

THD – dB

–75

–80

–85

–90

0.1 1.0 10.0

–20.0dB

–0.5dB

FREQUENCY – MHz

= 2.5 V)

–6.0dB

TPC 25. THD vs. Input Frequency (Input Span = 5.0 V p-p, VCM = 2.5 V)

TPC 23. THD vs. Input Frequency (Input Span = 2.0 V p-p, VCM = 2.5 V)

–60

–65

–70

–75

–80

THD – dB

–85

–90

–95

–100

5V p-p

2V p-p

110

SAMPLE RATE – MSPS

TPC 26. THD vs. Clock Frequency (AIN = –0.5 dB, fIN = 1.0 MHz, VCM = 2.5 V)

TPC 24. SINAD vs. Input Frequency (Input Span = 5.0 V p-p, VCM = 2.5 V)

SNR/SFDR – dB

–50 –30 –10

–60 –40

AIN – dBFS

–20

SFDR

SNR

TPC 27. SNR/SFDR vs. AIN (Input Amplitude) (fIN = 5.0 MHz, Input Span = 2 V p-p, V

= 2.5 V)

REV. E–8–

AD9221/AD9223/AD9220

FREQUENCY – MHz

–3

–12

1 10010

AMPLITUDE – dB

–6

–9

AD9221

AD9220

AD9223

SETTLING TIME – ns

CODE

4000

3000

6010 20 30 40 50

2000

1000

AD9220

AD9223

AD9221

INTRODUCTION

The AD9221/AD9223/AD9220 are members of a high performance, complete single-supply 12-bit ADC product family based on the same CMOS pipelined architecture. The product family allows the system designer an upward or downward component selection path based on dynamic performance, sample rate, and power. The analog input range of the AD9221/AD9223/AD9220 is highly flexible, allowing for both single-ended or differential inputs of varying amplitudes that can be ac or dc coupled. Each device shares the same interface options, pinout, and package offering.

The AD9221/AD9223/AD9220 utilize a four-stage pipeline architecture with a wideband input sample-and-hold amplifier (SHA) implemented on a cost-effective CMOS process. Each stage of the pipeline, excluding the last stage, consists of a low resolution flash A/D connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier amplifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash A/D.

The pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. This means that while the converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the conversion to be fully processed and appear at the output. This latency is not a concern in most applications. The digital output, together with the out-of-range indicator (OTR), is latched into an output buffer to drive the output pins. The output drivers can be configured to interface with 5 V or 3.3 V logic families.

The AD9221/AD9223/AD9220 use both edges of the clock in their internal timing circuitry (see Figure 1 and Specifications for exact timing requirements). The A/D samples the analog input on the rising edge of the clock input. During the clock low time (between the falling edge and rising edge of the clock), the input SHA is in the sample mode; during the clock high time, it is in hold. System disturbances just prior to the rising edge of the clock and/or excessive clock jitter may cause the input SHA to acquire the wrong value, and should be minimized.

The internal circuitry of both the input SHA and individual pipeline stages of each member of the product family are optimized for both power dissipation and performance. An inherent trade-off exists between the input SHA’s dynamic performance and its power dissipation. Figures 2 and 3 show this trade-off by comparing the full-power bandwidth and settling time of the AD9221/AD9223/AD9220. Both figures reveal that higher fullpower bandwidths and faster settling times are achieved at the expense of an increase in power dissipation. Similarly, a tradeoff exists between the sampling rate and the power dissipated in each stage.

As previously stated, the AD9221, AD9223, and AD9220 are similar in most aspects except for the specified sampling rate, power consumption, and dynamic performance. The product family is highly flexible, providing several different input ranges and interface options. As a result, many of the application issues and trade-offs associated with these resulting configurations are

also similar. The data sheet is structured such that the designer can make an informed decision in selecting the proper A/D and optimizing its performance to fit the specific application.

Figure 2. Full-Power Bandwidth

Figure 3. Settling Time

ANALOG INPUT AND REFERENCE OVERVIEW

Figure 4, a simplified model of the AD9221/AD9223/AD9220, highlights the relationship between the analog inputs, VINA, VINB, and the reference voltage, VREF. Like the voltage applied to the top of the resistor ladder in a flash A/D converter, the value VREF defines the maximum input voltage to the A/D core. The minimum input voltage to the A/D core is automatically defined to be –VREF.

AD9221/AD9223/AD9220

VINA

CORE

VINB

REF

A/D

CORE

–V

REF

Figure 4. AD9221/AD9223/AD9220 Equivalent Functional Input Circuit

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AD9221/AD9223/AD9220

The addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily configure the inputs for either single-ended operation or differential operation. The A/D’s input structure allows the dc offset of the input signal to be varied independently of the input span of the converter. Specifically, the input to the A/D core is the difference of the voltages applied at the VINA and VINB input pins. Therefore, the equation,

VVINAVINB

= –

CORE

(1)

defines the output of the differential input stage and provides the input to the A/D core.

The voltage, V

–VREF V VREF

, must satisfy the condition,

CORE

≤≤

CORE

(2)

where VREF is the voltage at the VREF pin.

While an infinite combination of VINA and VINB inputs exist that satisfy Equation 2, there is an additional limitation placed on the inputs by the power supply voltages of the AD9221/ AD9223/AD9220. The power supplies bound the valid operating range for VINA and VINB. The condition,

AVSS V VINA AVDD V

–. .

03 03

<< +

AVSS V VINB AVDD V

–. .

03 03

<< +

(3)

where AVSS is nominally 0 V and AVDD is nominally 5 V, defines this requirement. Thus, the range of valid inputs for VINA and VINB is any combination that satisfies both Equations 2 and 3.

For additional information showing the relationship between VINA, VINB, VREF and the digital output of the AD9221/ AD9223/AD9220, see Table IV.

Refer to Table I and Table II at the end of this section for a summary of both the various analog input and reference configurations.

ANALOG INPUT OPERATION

Figure 5 shows the equivalent analog input of the AD9221/ AD9223/AD9220, which consists of a differential sample-andhold amplifier (SHA). The differential input structure of the SHA is highly flexible, allowing the devices to be easily configured for either a differential or single-ended input. The dc offset, or common-mode voltage, of the input(s) can be set to accommodate either single-supply or dual-supply systems. Also, note that the analog inputs, VINA and VINB, are interchangeable with the exception that reversing the inputs to the VINA and VINB pins results in a polarity inversion.

VINA

VINB

PAR

–

PAR

Figure 5. AD9221/AD9223/AD9220 Simplified Input Circuit

The SHA’s optimum distortion performance for a differential or single-ended input is achieved under the following two conditions: (1) the common-mode voltage is centered around midsupply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input signal voltage span of the SHA is set at its lowest (i.e., 2 V input span). This is due to the sampling switches, Q whose R

resistance is very low but has some signal depen-

, being CMOS switches

dency that causes frequency dependent ac distortion while the SHA is in the track mode. The R

resistance of a CMOS

switch is typically lowest at its midsupply but increases symmetrically as the input signal approaches either AVDD or AVSS. A lower input signal voltage span centered at midsupply reduces the degree of R

modulation.

Figure 6 compares the AD9221/AD9223/AD9220’s THD vs. frequency performance for a 2 V input span with a commonmode voltage of 1 V and 2.5 V. Note how each A/D with a common-mode voltage of 1 V exhibits a similar degradation in THD performance at higher frequencies (i.e., beyond 750 kHz). Similarly, note how the THD performance at lower frequencies becomes less sensitive to the common-mode voltage. As the input frequency approaches dc, the distortion will be dominated by static nonlinearities such as INL and DNL. It is important to note that these dc static nonlinearities are independent of any RON modulation.

–50

AD9220

2.5V

AD9221 1V

AD9220

2.5V

–60

–70

THD – dB

–80

–90

0.1 101

AD9223

AD9221

2.5V

FREQUENCY – MHz

Figure 6. AD9221/AD9223/AD9220 THD vs. Frequency for VCM = 2.5 V and 1.0 V (AIN = –0.5 dB, Input Span = 2.0 V p-p)

Due to the high degree of symmetry within the SHA topology, a significant improvement in distortion performance for differential input signals with frequencies up to and beyond Nyquist can be realized. This inherent symmetry provides excellent cancellation of both common-mode distortion and noise. Also, the required input signal voltage span is reduced by a half, which further reduces the degree of R

modulation and its effects

on distortion.

The optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 5 V input span) and matched input impedance for VINA and VINB. Note that only a slight degradation in dc linearity performance exists between the 2 V and 5 V input span as specified in the AD9221/AD9223/ AD9220 DC Specifications.

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