Analog Devices AD9218 Service Manual

10-Bit, 40/65/80/105 MSPS

3 V Dual Analog-to-Digital Converter

FEATURES

Dual 10-bit, 40 MSPS, 65 MSPS, 80 MSPS, and 105 MSPS ADC
Low power: 275 mW at 105 MSPS per channel
On-chip reference and track-and-hold
300 MHz analog bandwidth each channel
SNR = 57 dB @ 41 MHz, Encode = 80 MSPS
1 V p-p or 2 V p-p analog input range each channel

3.0 V single-supply operation (2.7 V to 3.6 V)
Power-down mode for single-channel operation
Twos complement or offset binary output mode
Output data alignment mode
Pin compatible with the 8-bit AD9288
–75 dBc crosstalk between channels

APPLICATIONS

Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
I and Q communications
Ultrasound equipment

A

IN

AINA

REF

IN

REF

OUT

REF

IN

A

IN

A

IN

ENCODE B

FUNCTIONAL BLOCK DIAGRAM

ADC

REF

ADC

V

Figure 1.

AD9218

/

REGISTER

10

/

REGISTER

10

D

OUTPUT

OUTPUT

GND

TIMINGENCODE A

A

A

B

B

B

T/H

T/H

TIMING

AD9218

D9

/

10

/

10

V

DD

TO D0

A

USER
SELECT NO. 1

USER
SELECT NO. 2

DATA
FORMAT/
GAIN

D9

TO D0

B

A

B

02001-001

GENERAL DESCRIPTION

The AD9218 is a dual 10-bit monolithic sampling analog-to­digital converter with on-chip track-and-hold circuits. The
product is low cost, low power, and is small and easy to use. The
AD9218 operates at a 105 MSPS conversion rate with
outstanding dynamic performance over its full operating range.
Each channel can be operated independently.

The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and a clock for full operation. No external reference or
driver components are required for many applications. The
digital outputs are TTL/CMOS compatible and a separate
output power supply pin supports interfacing with 3.3 V or

2.5 V logic.

The clock input is TTL/CMOS compatible and the 10-bit digital
outputs can be operated from 3.0 V (2.5 V to 3.6 V) supplies.
User-selectable options offer a combination of power-down
modes, digital data formats, and digital data timing schemes.
In power-down mode, the digital outputs are driven to a high
impedance state.

PRODUCT HIGHLIGHTS

1. Low Power. Only 275 mW power dissipation per channel

at 105 MSPS. Other speed grades proportionally scaled
down while maintaining high ac performance.

2. Pin Compatibility Upgrade. Allows easy migration from 8-bit

to 10-bit devices. Pin compatible with the 8-bit AD9288
dual ADC.

3. Easy to Use. On-chip reference and user controls provide

flexibility in system design.

4. High Performance. Maintains 54 dB SNR at 105 MSPS

with a Nyquist input.

5. Channel Crosstalk. Very low at –75 dBc.

6. Fabricated on an Advanced CMOS Process. Available in a

48-lead low profile quad flat package (7 mm × 7 mm
LQFP) specified over the industrial temperature range
(−40°C to +85°C).

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD9218

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

Digital Specifications ................................................................... 4

AC Specifications.......................................................................... 5

Switching Specifications.............................................................. 6

Timing Diagrams.......................................................................... 6

Absolute Maximum Ratings............................................................ 8

Explanation of Test Levels........................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Terminology .................................................................................... 10

Equivalent Circuits......................................................................... 12

Typical Performance Characteristics ........................................... 13

Theory of Operation ...................................................................... 18

Using the AD9218 ENCODE Input......................................... 18

Digital Outputs........................................................................... 18

Analog Input............................................................................... 18

Voltage Reference....................................................................... 19

Timing ......................................................................................... 19

User Select Options.................................................................... 19

Application Information ........................................................... 19

AD9218/AD9288 Customer PCB BOM...................................... 20

Evaluation Board............................................................................ 21

Power Connector........................................................................ 21

Analog Inputs ............................................................................. 21

Voltage Reference....................................................................... 21

Clocking....................................................................................... 21

Data Outputs............................................................................... 21

Data Format/Gain...................................................................... 21

Timing ......................................................................................... 21

Troubleshooting.......................................................................... 21

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

REVISION HISTORY

12/06—Rev. B to Rev. C

Updated Format..................................................................Universal

Changes to DC Specifications......................................................... 3

1/04—Rev. A. to Rev. B

Updated format...................................................................Universal

Changes to General Description .................................................... 1

Changes to DC Specifications......................................................... 3

Changes to Switching Specifications.............................................. 6

Added AD9218/AD9288 Customer PCB BOM section ........... 20

Added Evaluation Board section.................................................. 21

7/03—Rev. 0 to Rev. A

Updated Ordering Guide................................................................. 6

Changes to Terminology section................................................... .8

Changes to Figure 17b.................................................................... 19

Updated Outline Dimensions....................................................... 24

Rev. C | Page 2 of 28

AD9218

SPECIFICATIONS

DC SPECIFICATIONS

VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.

Table 1.

AD9218BST-40/-65 AD9218BST-80/-105
Parameter Temp

RESOLUTION 10 10 Bits
ACCURACY

No Missing Codes1 Full VI Guaranteed, not tested Guaranteed, not tested
Offset Error2 25°C I –18 2 18 –18 2 18 LSB
Gain Error2 25°C I –2 3 8 –2 3.5 8 % FS
Differential Nonlinearity

25°C I –1 ±0.3/±0.6 1/1.3 –1 ±0.5/±0.8 1.2/1.7 LSB

(DNL)

Full VI ±0.8 ±0.6/±0.9 LSB

Integral Nonlinearity

25°C I –1/–1.6 ±0.3/±1 1/1.6 –1.35/–2.7 ±0.75/±2 +1.35/2.7 LSB

(INL)
Full VI ±1 ±1/±2.3 LSB
TEMPERATURE DRIFT

Offset Error Full V 10 4 ppm/°C

Gain Error2 Full V 80 100 ppm/°C

Reference Full V 40 40 ppm/°C
REFERENCE

Internal Reference Voltage 25°C I 1.18 1.24 1.28 1.18 1.24 1.28 V

(REF

)

OUT

Input Resistance (REFINA,

REF

B)

IN

Full VI 9 11 13 9 11 13 kΩ

ANALOG INPUTS

Differential Input Voltage

Range (A

IN, AIN

)3

Full V 1 or 2 1 V

Common-Mode Voltage3Full V VD/3 VD/3 V

Input Resistance Full VI 8 10 14 8 10 14 kΩ

Input Capacitance 25°C V 3 3 pF
POWER SUPPLY

VD Full IV 2.7 3 3.6 2.7 3 3.6 V

VDD Full IV 2.7 3 3.6 2.7 3 3.6 V

Supply Currents

IVD (VD = 3.0 V)

4

Full VI 108/117 113/130 172/183 175/188 mA

IVDD (VDD = 3.0 V)4 25°C V 7/11 13/17 mA
Power Dissipation DC5 Full VI 325/350 340/390 515/550 525/565 mW
IVD Power-Down Current6 Full VI 20 22 mA
Power Supply Rejection

25°C I

Ratio

1

No missing codes across industrial temperature range guaranteed for 40 MSPS, 65 MSPS, and 80 MSPS grades. No missing codes at room temperature guaranteed for

105 MSPS grade.

2

Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.25 V external reference) 65 grade in 2 V p-p range, 40, 80, 105 grades in 1 V p-p range.

3

A

IN

(AIN –

externally by a low impedance source by ±300 mV (differential drive, gain = 1) or ±150 mV (differential drive, gain = 2).

4

AC power dissipation measured with rated encode and a 10.3 MHz analog input @ 0.5 dBFS, C

5

DC power dissipation measured with rated encode and a dc analog input (outputs static, IVDD = 0).

6

In power-down state, IVDD = ±10 μA typical (all grades).

) = ±0.5 V in 1 V range (full scale), (AIN –

Test
Level

A

IN

Min Typ Max Min Typ Max Unit

) = ±1 V in 2 V range (full scale). The analog inputs self-bias to VD/3. This common-mode voltage can be overdriven

±1 ±1 mV/V

= 5 pF.

LOAD

Rev. C | Page 3 of 28

AD9218

DIGITAL SPECIFICATIONS

VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.

Table 2.

Test AD9218BST-40/-65 AD9218BST-80/-105
Parameter Temp Level Min Typ Max Min Typ Max Unit

DIGITAL INPUTS

Encode Input Common

Mode
Encode 1 Voltage Full VI 2 2 V
Encode 0 Voltage Full VI 0.8 0.8 V
Encode Input Resistance Full VI 1.8 2.0 2.3 1.8 2.0 2.3 kΩ
Logic 1 Voltage—S1, S2,

DFS
Logic 0 Voltage—S1, S2,

DFS
Logic 1 Current—S1 Full VI –50 ±0 50 –50 ±0 50 μA
Logic 0 Current—S1 Full VI –400 –230 –50 –400 –230 –50 μA
Logic 1 Current—S2 Full VI 50 230 400 50 230 400 μA
Logic 0 Current—S2 Full VI –50 ±0 50 –50 ±0 50 μA
Logic 1 Current—DFS Full VI 30 100 200 30 100 200 μA
Logic 0 Current—DFS Full VI –400 –230 –50 –400 –230 –50 μA
Input Capacitance—S1,

S2, Encode Inputs
Input Capacitance DFS 25°C V 4.5 4.5 pF

DIGITAL OUTPUTS

Logic 1 Voltage Full VI 2.45 2.45 V
Logic 0 Voltage Full VI 0.05 0.05 V
Output Coding Twos complement or offset binary Twos complement or offset binary

Full V VD/2 VD/2 V

Full VI 2 2 V

Full VI 0.8 0.8 V

25°C V 2 2 pF

Rev. C | Page 4 of 28

AD9218

AC SPECIFICATIONS

VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.

Table 3.

Test AD9218BST-40/-65 AD9218BST-80/-105
Parameter Temp Level Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE1

Signal-to-Noise Ratio (SNR)

(Without Harmonics)
fIN = 10.3 MHz 25°C I 58/55 59/57 57/53 58/55 dB
fIN = Nyquist

Signal-to-Noise and Distortion (SINAD)

(With Harmonics)
fIN = 10.3 MHz 25°C I 58/54 59/56 56/52 58/53 dB
fIN = Nyquist2 25°C I –/53 59/55 55/51 57/53 dB

Effective Number of Bits

fIN = 10.3 MHz 25°C I 9.4/8.8 9.6/9.1 9.1/8.4 9.4/8.6 Bits
fIN = Nyquist2 25°C I –/8.6 9.6/8.9 9/8.3 9.3/8.6 Bits

Second Harmonic Distortion

f

= 10.3 MHz 25°C I –72/–66 –89/–77 –69/–60 –77/–68 dBc

IN

fIN = Nyquist2 25°C I –/–63 –89/–72 –65/–57 –76/–66 dBc

Third Harmonic Distortion

fIN = 10.3 MHz 25°C I –68/–62 –79/–68 –62/–57 –71/–63 dBc
fIN = Nyquist

Spurious Free Dynamic Range (SFDR)

fIN = 10.3 MHz 25°C I –68/–62 –79/–67 –62/–57 –69/–62 dBc
fIN = Nyquist2 25°C I –/–60 –78/–64 –63/–57 –70/–63 dBc

Two-Tone Intermodulation Distortion (IMD)

f

= 10 MHz, f

IN1

f

= 30 MHz, f

IN1

Analog Bandwidth, Full Power 25°C V 300 300 MHz
Crosstalk 25°C V –75 –75 dBc

1

AC specifications based on an analog input voltage of –0.5 dBFS at 10.3 MHz, unless otherwise noted. AC specifications for 40, 80, 105 grades are tested in 1 V p-p

range and driven differentially. AC specifications for 65 grade are tested in 2 V p-p range and driven differentially.

2

The 65, 80, and 105 grades are tested close to Nyquist for that grade: 31 MHz, 39 MHz, and 51 MHz for the 65, 80, and 105 grades, respectively.

2

2

= 11 MHz at –7 dBFS 25°C V –74/–73 dBc

IN2

= 31 MHz at –7 dBFS 25°C V –73/–73 –77/–67 dBc

IN2

25°C I –/54 59/56 55/52 57/54 dB

25°C I –/–60 –78/–64 –63/–57 –73/–69 dBc

Rev. C | Page 5 of 28

AD9218

SWITCHING SPECIFICATIONS

VDD = 3.0 V, V = 3.0 V; external reference, unless otherwise noted.

Table 4.

Test AD9218BST-40/-65 AD9218BST-80/-105
Parameter Temp Level Min Typ Max Min Typ Max Unit

ENCODE INPUT PARAMETERS

Maximum Encode Rate Full VI 40/65 80/105 MSPS
Minimum Encode Rate Full IV 20/20 20/20 MSPS
Encode Pulse Width High (tEH) Full IV 7/6 5/3.8 ns
Encode Pulse Width Low (tEL) Full IV 7/6 5/3.8 ns
Aperture Delay (tA) 25°C V 2 2 ns
Aperture Uncertainty (Jitter) 25°C V 3 3 ps rms

DIGITAL OUTPUT PARAMETERS

Output Valid Time (tV) Full VI 2.5 2.5 ns
Output Propagation Delay (tPD)1 Full VI 4.5 7 4.5 6 ns
Output Rise Time (tR) 25°C V 1 1.0 ns
Output Fall Time (tF) 25°C V 1.2 1.2 ns
Out-of-Range Recovery Time 25°C V 5 5 ns
Transient Response Time 25°C V 5 5 ns
Recovery Time from Power-Down 25°C V 10 10 Cycles
Pipeline Delay Full IV 5 5 Cycles

1

t and t

V PD

an ac load of 5 pF or a dc current of ±40 μA. Rise and fall times are measured from 10% to 90%.

D

1

are measured from the 1.5 level of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed

TIMING DIAGRAMS

AINA
A

B

IN

ENCODE A
ENCODE B

D9

TO D0

A

A

D9BTO D0

B

SAMPLE N

t

A

t

EH

SAMPLE

N + 1

SAMPLE

t

EL

DATA N – 5 DATA N – 4 DATA N – 3 DATA N – 2 DATA N – 1 DATA N

DATA N – 5 DATA N – 4 DATA N – 3 DATA N – 2 DATA N – 1 DATA N

1/f

S

N + 2

SAMPLE

N + 3

SAMPLE

N + 4

SAMPLE

N + 5

t

PD

Figure 2. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing

SAMPLE

N + 6

t

V

02001-002

Rev. C | Page 6 of 28

AD9218

AINA
A

ENCODE A

ENCODE B

D9

TO D0

A

D9BTO D0

SAMPLE

B

IN

t

A

t

EH

A

B

SAMPLE

N

DATA N – 10 DATA N – 8 D ATA N – 6 DATA N – 4 DATA N – 2 DATA N DATA N + 2

SAMPLE

N + 1

N + 2

t

EL

SAMPLE

1/f

DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 D ATA N + 1

N + 3

S

SAMPLE

N + 4

SAMPLE

N + 5

SAMPLE

N + 7

SAMPLE

N + 6

SAMPLE

N + 8

t

PD

t

V

02001-003

Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing

AINA
A

B

IN

ENCODE A

SAMPLE

t

A

t

EH

SAMPLE

N

N + 1

t

EL

SAMPLE

N + 2

SAMPLE

N + 3

1/f

SAMPLE

SAMPLE

S

N + 4

SAMPLE

N + 5

SAMPLE

N + 6

N + 7

SAMPLE

N + 8

t

V

DATA N + 2

02001-004

ENCODE B

D9

TO D0

A

D9BTO D0

t

PD

A

B

DATA N – 10 DATA N – 8 DATA N – 6 DATA N – 4 DATA N – 2 DATA N

DATA N – 11 DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1

Figure 4. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing

Rev. C | Page 7 of 28

AD9218

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

VD, V 4 V

DD

Analog Inputs –0.5 V to VD + 0.5 V
Digital Inputs –0.5 V to V + 0.5 V
REFIN Inputs –0.5 V to VD + 0.5 V
Digital Output Current 20 mA
Operating Temperature –55°C to +125°C
Storage Temperature –65°C to +150°C
Maximum Junction Temperature 150°C
Maximum Case Temperature 150°C
θA (measured on a 4-layer board with

solid ground plane)

57°C/W

DD

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

EXPLANATION OF TEST LEVELS

I. 100% production tested.

II. 100% production tested at 25°C and sample tested at

specified temperatures.

III. Sample tested only.

IV. Parameter is guaranteed by design and characterization

testing.

V. Parameter is a typical value only.

VI. 100% production tested at 25°C; guaranteed by design

and characterization testing for industrial temperature
range.

100% production tested at temperature extremes for
military devices.

Table 6. User Select Modes

S1 S2 Power-Down and Data Alignment Settings

0 0 Power down both Channel A and Channel B.
0 1 Power down Channel B only.
1 0 Normal operation (data align disabled).
1 1

Data align enabled (data from both channels
available on rising edge of Clock A. Channel B data is
delayed by a ½ clock cycle.)

ESD CAUTION

Rev. C | Page 8 of 28

AD9218

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

(MSB)

A

VDENCAVDDGND

4847464544434241403938

1

GND

2

A

A

IN

A

A

3

IN

DFS/GAIN

REF

REF

REF

IN

OUT

IN

A

IN

A

IN

GND

4

A

5

6

B

7

8

S1

S2

9

B

10

11

B

12

1314151617181920212223

D

B

V

ENC

Figure 5. Pin Configuration

AD7AD6AD5AD4AD3AD2A

D9

D8

AD9218

TOP VIEW

(Not to Scale)

BD8BD7BD6BD5BD4BD3BD2B

DD

V

GND

(MSB) D9

37

36

D1

A

35

D0

A

GND

34

33

V

DD

GND

32

31

V

D

V

30

D

29

GND

V

28

DD

GND

27

26

D0

B

D1

25

B

24

2001-005

Table 7. Pin Function Descriptions

Pin Number Mnemonic Description

1, 12, 16, 27, 29,

GND Ground.

32, 34, 45
2 AINA Analog Input for Channel A.

3

AA

IN

4 DFS/GAIN

Analog Input for Channel A (Complementary).

Data Format Select and Analog Input Gain Mode. Low = offset binary output available, 1 V p-p supported;
high = twos complement output available, 1 V p-p supported; floating = offset binary output available,
2 V p-p supported; set to V

= twos complement output available, 2 V p-p supported.

REF

5 REFINA Reference Voltage Input for Channel A.
6 REF

Internal Reference Voltage.

OUT

7 REFINB Reference Voltage Input for Channel B.
8 S1 User Select No. 1. See Tabl e 6.
9 S2 User Select No. 2. See Tabl e 6.
10

BA

IN

Analog Input for Channel B (Complementary).

11 AINB Analog Input for Channel B.
13, 30, 31, 48 VD Analog Supply (3 V).
14 ENC
15, 28, 33, 46 V
17 to 26 D9 to D0

B

DD

B B

Clock Input for Channel B.
Digital Supply (2.5 V to 3.6 V).
Digital Output for Channel B (D9 = MSB).

B

35 to 44 D0A to D9A Digital Output for Channel A (D9A = MSB).
47 ENCA Clock Input for Channel A.

Rev. C | Page 9 of 28

AD9218

TERMINOLOGY

Analog Bandwidth

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

Aperture Delay

The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Crosstalk

Coupling onto one channel being driven by a low level signal
(–40 dBFS) when the adjacent interfering channel is driven by a
full-scale signal.

Differential Analog Input Resistance,
Differential Analog Input Capacitance,
Differential Analog Input Impedance

The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180
degrees out of phase. Peak-to-peak differential is computed by
rotating the input phase 180 degrees and again taking the peak
measurement. The difference is then computed between both
peak measurements.

Differential Nonlinearity

The deviation of any code width from an ideal 1 LSB step.

Effective Number of Bits (ENOB)

The effective number of bits is calculated from the measured
SNR based on the equation

ENOB

SNR

MEASURED

=

76.1 dB−

02.6

ENCODE Pulse Width/Duty Cycle

Pulse width high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve rated
performance; pulse width low is the minimum time ENCODE
pulse should be left in low state. See timing implications of
changing t

in text. At a given clock rate, these specifications

ENCH

define an acceptable ENCODE duty cycle.

Full-Scale Input Power

Expressed in dbm. Computed using the following equation:

2

ScaleFull

INPUT

001.0

⎞

rmsV

⎟
⎟
⎟
⎟
⎟

⎠

⎛

−

⎜
⎜

Z

log10

Power

=

ScaleFull

−

⎜
⎜
⎜

⎝

Gain Error

Gain error is the difference between the measured and the ideal
full-scale input voltage range of the ADC.

Harmonic Distortion, Second

The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.

Harmonic Distortion, Third

The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.

Integral Nonlinearity

The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least-square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between the 50% level crossing of ENCODE A or
ENCODE B and the 50% level crossing of the respective
channel’s output data bit.

Noise (for Any Range Within the ADC)

NOISE

ZV

⎛

××=

10001.0

⎜
⎝

−−

10

⎞

dBFSdBcdBm

⎟
⎠

SignalSNRFS

where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value for the particular
input level, and Signal is the signal level within the ADC
reported in dB below full scale. This value includes both
thermal and quantization noise.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in
power supply voltage.

Rev. C | Page 10 of 28

AD9218

Signal-to-Noise and Distortion (SINAD)

The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.

Signal-to-Noise Ratio (without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component
may or may not be a harmonic. Reported in dBc (that is,
degrades as signal level is lowered) or dBFS (always related back
to converter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value
of the worst third-order intermodulation product; reported in dBc.

Two -Tone SFDR

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. Reported in dBc (that is,
degrades as signal level is lowered) or in dBFS (always related
back to converter full scale).

Worst Other Spur

The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonics) reported in dBc.

Transi ent Res p ons e Ti me

Transient response is defined as the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
negative full scale to 10% below positive full scale.

Out-of-Range Recovery Time

Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale or from 10%
below negative full scale to 10% below positive full scale.

Rev. C | Page 11 of 28

AD9218

V

A

S2V

V

V

V

V

V

EQUIVALENT CIRCUITS

V

D

D

30kΩ

40kΩ

IN

15kΩ

30kΩ

15kΩ

40kΩ

A

IN

02001-B-006

REF

10kΩ

02001-010

Figure 6. Analog Input Stage Figure 10. Reference Inputs

D

02001-011

D

ENCODE

2.6kΩ

600kΩ

2.6kΩ

Figure 7. Encode Inputs

D

OUT

D

10kΩ

02001-007

Figure 11. S2 Input

10kΩ

S1

02001-012

02001-008

Figure 8. Reference Output Stage

DD

40kΩ

DX

02001-009

Figure 9. Digital Output Stage

Figure 12. S1 Input

DFS/GAIN

Figure 13. DFS/Gain Input

15kΩ

15kΩ

V

REF

D

02001-013

Rev. C | Page 12 of 28

AD9218

TYPICAL PERFORMANCE CHARACTERISTICS

0

ENCODE = 105MSP S

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

Figure 14. FFT: FS = 105 MSPS, A

= 50.1MHz AT –0.5dBFS

A

IN

SNR = 53.8dB
SINAD = 53.4d B
H2 = –69dB
H3 = –65.8dB

052.5

= 50.1 MHz @ –0.5 dBFS, Differential,

IN

02001-014

1 V p-p Input Range

0

ENCODE = 40MSPS

–10

A

= 19.75MHz AT –0.5dBFS

IN

SNR = 58.4dB

–20

SINAD = 58.3d B
H2 = –87dB

–30

H3 = –81dB

–40

–50

(dB)

–60

–70

–80

–90

–100

020

Figure 17. FFT: FS = 40 MSPS, A

= 19.75 MHz @ –0.5 dBFS, Differential,

IN

02001-017

1 V p-p Input Range

0

ENCODE = 80MSPS

–10

A

= 39MHz AT –0.5dBFS

IN

SNR = 56.1dB

–20

SINAD = 55.5d B
H2 = –71.8dB

–30

H3 = –66.2dB

–40

–50

(dB)

–60

–70

–80

–90

–100

040

Figure 15. FFT: FS = 80 MSPS, A

= 39 MHz @ –0.5 dBFS, Differential,

IN

02001-015

0

ENCODE = 105MSPS

–10

A

= 70MHz AT –0.5dBFS

IN

SNR = 51.9dB

–20

SINAD = 51.8d B
H2 = –70.5dB

–30

H3 = –76.3dB

–40

–50

(dB)

–60

–70

–80

–90

–100

040

Figure 18. FFT: FS = 105 MSPS A

1 V p-p Input Range

0

ENCODE = 65MSPS

–10

A

= 30.3MHz AT –0. 5dBFS

IN

SNR = 56.1dB

–20

SINAD = 55.9d B
SFDR = 72dB

–30

H2 = –83.2dB
H3 = –79dB

–40

–50

(dB)

–60

–70

–80

–90

–100

032.5

Figure 16. FFT: FS = 65 MSPS, A

= 30.3 MHz @ –0.5 dBFS, Differential,

IN

02001-016

0

ENCODE = 65MSP S

–10

A

= 15MHz AT –0.5dBFS

IN

SNR = 56.4dB

–20

SINAD = 55.9d B
H2 = –73.9dB

–30

H3 = –71.7dB

–40

–50

(dB)

–60

–70

–80

–90

–100

032.5

Figure 19. FFT: FS = 65 MSPS, A

2 V p-p Input Range

= 70 MHz @ –0.5 dBFS, Differential,

IN

1 V p-p Input Range

= 15 MHz @ – 0.5 dBFS; with AD8138 Driving

IN

ADC Inputs, 1 V p-p Input Range

02001-018

02001-019

Rev. C | Page 13 of 28

AD9218

0

ENCODE = 31MSPS

–10

A

= 8MHz AT –0.5dBF S

IN

SNR = 59.23dB

–20

SINAD = 59.1d B
H2 = –87dB

–30

H3 = –81dB

–40

–50

(dB)

–60

–70

–80

–90

–100

015.5

Figure 20. FFT: FS = 31 MSPS, A

= 8 MHz @ –0.5 dBFS, Differential,

IN

02001-020

1 V p-p Input Range

80

75

70

65

60

55

(dB)

50

45

40

35

30

0 50 100 150 200 250

SECOND

SFDR

A

THIRD

FREQUENCY (MHz)

IN

02001-021

Figure 21. Harmonic Distortion (Second and Third) and

SFDR vs. A

Frequency (1 V p-p, FS = 105 MSPS)

IN

0

ENCODE = 31MSPS

–10

A

= 8MHz AT –0.5dBF S

IN

SNR = 59dB

–20

SINAD = 58.8d B
H2 = –78.7dB

–30

H3 = –72.9dB

–40

–50

(dB)

–60

–70

–80

–90

–100

015.5

Figure 23. FFT: FS = 31 MSPS, A

= 8 MHz @ –0.5 dBFS, Differential, with

IN

02001-023

AD8138 Driving ADC Inputs,1 V p-p Input Range

0

ENCODE = 105MSPS

–10

A

1 = 30.1MHz AT –7dBFS

IN

A

2 = 31.1MHz AT –7dBFS

IN

–20

SFDR = –67dBFS

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

052.5

02001-024

Figure 24. Two-Tone Intermodulation Distortion

(30.1 MHz and 31.1 MHz; 1 V p-p, FS = 105 MSPS)

80

75

70

SECOND

65

60

55

(dB)

50

45

40

35

30

0 50 100 150 200 250

SFDR

THIRD

A

FREQUENCY (MHz)

IN

Figure 22. Harmonic Distortion (Second and Third) and

SFDR vs. A

Frequency (1 V p-p, FS = 80 MSPS)

IN

02001-022

Rev. C | Page 14 of 28

0

ENCODE = 80MSPS

–10

A

1 = 29.3MHz AT –7dBFS

IN

A

2 = 30.3MHz AT –7dBFS

IN

–20

SFDR = –77dBFS

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

040

02001-025

Figure 25. Two-Tone Intermodulation Distortion

(29.3 MHz and 30.3 MHz; 1 V p-p, FS = 80 MSPS)

AD9218

90

80

H3 1V

70

SFDR 1V

60

50

(dB)

40

SFDR 2V

30

20

10

0 20 40 60 80 100 120 140 160 180

H2 1V

H2 2V

2V SINGLE-ENDED DRIVE

1V DIFFERENT IAL DRIVE

FREQUENCY (MHz )

A

IN

H3 2V

0

ENCODE = 65MSPS

–10

A

1 = 28.1MHz AT –7dBFS

IN

A

2 = 29.1MHz AT –7dBFS

IN

–20

SFDR = –72.9d BFS

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

02001-026

03

02001-029

2.5

Figure 26. Harmonic Distortion (Second and Third) and

SFDR vs. A

90

85

80

75

70

(dB)

65

60

55

50

SFDR

Frequency (FS = 65 MSPS)

IN

THIRD

30 4010 20 50 60 70

FREQUENCY (M Hz)

A

IN

Figure 27. Harmonic Distortion (Second and Third) and

SFDR vs. A

75

70

65

60

(dB)

55

50

Frequency (1 V p-p, FS = 40 MSPS)

IN

SFDR

SINAD

SECOND

Figure 29. Two-Tone Intermodulation Distortion

(28 MHz, 29 MHz; 1 V p-p, FS = 65 MSPS)

0

ENCODE = 40MSPS

–10

A

1 = 10MHz AT –7dBFS

IN

A

2 = 11MHz AT –7dBFS

IN

–20

SFDR = 74dBc

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

02001-027

02

02001-030

0

Figure 30. Two-Tone Intermodulation Distortion

(10 MHz, 11 MHz; 1 V p-p, FS = 40 MSPS)

80

75

70

65

(dB)

60

55

50

SFDR

SNR

SINAD

45

40 60020 80100120

ENCODE RATE (MSPS)

Figure 28. SINAD and SFDR vs. Encode Rate (A

Grade) A

= –0.5 dBFS Differential, 1 V p-p Analog Input Range )

IN

= 10.3 MHz, 105 MSPS

IN

02001-028

Figure 31. SINAD and SFDR vs. Encode Rate (A

Rev. C | Page 15 of 28

45

= –0.5 dBFS Differential, 1 V p-p Analog Input Range

A

IN

403010 2005060

ENCODE RATE (MHz)

= 10.3 MHz, 65 MSPS Grade)

IN

7080

02001-031

AD9218

75

70

65

60

55

(dB)

50

45

40

35

30

SINAD

ENCODE POSITIVE PULSEWIDTH (ns)

SFDR

4312056

Figure 32. SINAD and SFDR vs. Encode Pulse Width High, A

Single-Ended, 1 V p-p Analog Input Range 105 MSPS

200

180

IVD – 105

160

140

(mA)

IV

– 65

120

100

80

0 20 40 60 80 100 120 140

Figure 33. IV

D

ENCODE CLOCK R ATE (MSPS)

and IVDD vs. Encode Rate (AIN = 10.3 MHz, @ –0.5 dBFS),

D

–65/–105 IV

DD

–65 MSPS/–105 MSPS Grade CI = 5 pF

1.131

1.129

1.127

1.125

(V)

1.123

1.121

1.119

020–40 –20 40 60 80

TEMPERATURE (°C)

Figure 34. V

Output Voltage vs. Temperature (I

REF

LOAD

78

02001-032

= –0.5 dBFS

IN

50

45

40

35

30

(mA)

25

DD

IV

20

15

10

5

0

02001-033

02001-034

= 300 μA)

75

70

65

60

(dB)

55

50

45

40

02468101214

SFDR

SINAD

ENCODE POSITIVE PULSEWIDTH (ns)

Figure 35. SINAD and SFDR vs. Encode Pulse Width High, A

Single-Ended, 1 V p-p Analog Input Range 65 MSPS

4.5

4.0

3.5

(%)

3.0

2.5

2.0

Figure 36. Gain Error vs. Temperature, A

GAIN –105

GAIN –65

020–40 –20 40 60 80

TEMPERATURE (°C)

= 10.3 MHz, –65 MSPS Grade,

IN

–105 MSPS Grade, 1 V p-p

68

66

64

62

60

(dB)

58

56

54

52

SFDR –65

SNR –65

SNR –105

SINAD –105

020–40 –20 40 60 80

TEMPERATURE (°C)

SFDR –105

SINAD –65

Figure 37. SNR, SINAD, SFDR vs. Temperature, A

= 10.3 MHz,

IN

–65 MSPS Grade, –105 MSPS Grade, 1 V p-p

= –0.5 dBFS

IN

02001-035

02001-036

02001-037

Rev. C | Page 16 of 28

AD9218

1.50

1.45

1.40

1.35

1.30

1.25

(V)

1.20

1.15

1.10

1.05

1.00
–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5

I

(mA)

LOAD

Figure 38. V

2.0

1.5

1.0

0.5

0

(LSB)

–0.5

–1.0

–1.5

–2.0

0 1024

REF

CODES

vs. I

LOAD

Figure 39. Typical INL Plot, 10.3 MHz A

@ 80 MSPS

IN

90

SFDR – dBFS

80

70

60

50

(dB)

40

30

20

10

0

02001-038

Figure 40. SFDR vs. A

1.0

0.8

0.6

0.4

0.2

0

(LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 1024

02001-039

Figure 41. Typical DNL Plot, 10.3 MHz A

SFDR – dBc

70dB REF LI NE

SNR – dBc

–40 –30–60 –50 –20 –10 0

A

INPUT LEVEL (dBFS)

IN

Input Level, 10.3 MHz AIN @ 80 MSPS

IN

CODES

@ 80 MSPS

IN

02001-040

02001-041

Rev. C | Page 17 of 28

AD9218

THEORY OF OPERATION

The AD9218 ADC architecture is a bit-per-stage pipeline-type
converter utilizing switch capacitor techniques. These stages
determine the 7 MSBs and drive a 3-bit flash. Each stage
provides sufficient overlap and error correction, allowing
optimization of comparator accuracy. The input buffers are
differential, and both sets of inputs are internally biased. This
allows the most flexible use of ac-coupled or dc-coupled and
differential or single-ended input modes. The output staging
block aligns the data, carries out the error correction, and feeds
the data to output buffers. The set of output buffers are powered
from a separate supply, allowing adjustment of the output
voltage swing. There is no discernible difference in performance
between the two channels.

USING THE AD9218 ENCODE INPUT

Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer. Any noise, distortion, or timing jitter on the
clock is combined with the desired signal at the analog-to­digital output. For that reason, considerable care has been taken
in the design of the ENCODE input of the AD9218, and the
user is advised to give commensurate thought to the clock
source. The ENCODE input is fully TTL/CMOS compatible.

DIGITAL OUTPUTS

The digital outputs are TTL/CMOS compatible for lower power
consumption. During power-down, the output buffers transition to
a high impedance state. A data format selection option supports
either twos complement (set high) or offset binary output (set
low) formats.

ANALOG INPUT

The analog input to the AD9218 is a differential buffer. For best

A

IN

dynamic performance, impedance at A
Special care was taken in the design of the analog input section
of the AD9218 to prevent damage and data corruption when
the input is overdriven. The nominal input range is 1.024 V p-p.
Optimum performance is obtained when the part is driven
differentially where common-mode noise is minimized and
even-order harmonics are reduced.
of the AD9218 being driven differentially via a wideband RF
transformer for ac-coupled applications. As shown in
applications that require dc-coupled differential drives can be
accommodated using the AD8138 differential output op amp.

50Ω

ANALOG

SIGNAL

SOURCE

Figure 42. Using a Wideband Transformer to Drive the AD9218

50Ω

ANALOG

SIGNAL

SOURCE

AV

DD

10kΩ

5kΩ

Figure 43. Using the AD8138 to Drive the AD9218

1:1

500Ω

VOCM

0.1µF

25Ω

25Ω

AD8138

525Ω

and IN should match.

Figure 42 shows an example

Figure 43,

A

IN

0.1µF

500Ω

500Ω

AD9218

A

IN

25Ω

15pF

25Ω

02001-042

AD9218

A

IN

A

IN

02001-043

Rev. C | Page 18 of 28

AD9218

VOLTAGE REFERENCE APPLICATION INFORMATION

A stable and accurate 1.25 V voltage reference is built into the
AD9218 (VREF OUT). Typically, the internal reference is used
by strapping Pin 5 (REF
(REF

). The input range for each channel can be adjusted

OUT

A) and Pin 7 (REF

IN IN

B) to Pin 6

independently by varying the reference voltage inputs applied to
the AD9218. No appreciable degradation in performance
occurs when the reference is adjusted ±5%. The full-scale range
of the ADC tracks reference voltage, which changes linearly
(a 5% change in VREF results in a 5% change in full scale).

TIMING

The AD9218 provides latched data outputs, with five pipeline
delays. Data outputs are available one propagation delay (t

)

PD

after the rising edge of the encode command (see Figure 2
through Figure 4). The length of the output data lines and loads
placed on them should be minimized to reduce transients
within the AD9218. These transients can detract from the
dynamic performance of the converter.

The minimum guaranteed conversion rate is 20 MSPS. At clock
rates below 20 MSPS, dynamic performance degrades.

USER SELECT OPTIONS

Two pins are available for a combination of operational modes,
enabling the user to power down both channels, excluding the
reference, or just the B channel. Both modes place the output
buffers in a high impedance state. Recovery from a power-down
state is accomplished in 10 clock cycles following power-on.

The other option allows the user to skew the B channel output
data by one-half a clock cycle. In other words, if two clocks are
fed to the AD9218 and are 180 degrees out of phase, enabling
the data align allows Channel B output data to be available at
the rising edge of Clock A. If the same encode clock is provided
to both channels and the data align pin is enabled, output data
from Channel B is 180 degrees out of phase with respect to
Channel A. If the same encode clock is provided to both
channels and the data align pin is disabled, both outputs are
delivered on the same rising edge of the clock.

The wide analog bandwidth of the AD9218 makes it very
attractive for a variety of high performance receiver and
encoder applications.

Figure 44 shows the dual ADC in a
typical low cost I and Q demodulator implementation for cable,
satellite, or wireless LAN modem receivers. The excellent
dynamic performance of the ADC at higher analog input
frequencies and encode rates lets users employ direct IF
sampling techniques. IF sampling eliminates or simplifies analog
mixer and filter stages to reduce total system cost and power.

AD9218

Q

ADC

ADC

I

02001-044

IF IN

BPF

90°

BPF

VCO VCO

Figure 44. Typical I/Q Demodulation Scheme

Rev. C | Page 19 of 28

AD9218

AD9218/AD9288 CUSTOMER PCB BOM

Table 8. Bill of Materials

No. Qty Reference Designator Device Package Value Comments

1 29 C1, C3 to C15, C20, C21, C24,

C25, C27, C30 to C35, C39 to C42
2 2 C2, C36 Capacitor 0603 15 pF 8138 out
3 7 C16–C19, C26, C37, C38 Capacitor TAJD 10 μF
4 28 E1, E2, E3, E4, E12 to E30,

E34 to E38
5 4 H1, H2, H3, H4 MTHOLE MTHOLE
6 5 J1, J2, J3, J4, J5 SMA SMA J2, J3 not placed
7 3 P1, P4, P11 4-lead power connector Post Z5.531.3425.0 Wieland
8 3 P1, P4, P11 4-lead power connector Detachable

9 1 P2, P31 80-lead rt. angle male TSW-140-08-

10 4 R1, R2, R32, R34 Resistor 0603 36 Ω R1, R2, R32, R34,

11 9 R3, R7, R11, R14, R22, R23, R24,

R30, R51

12 17 R4, R5, R8, R9, R10, R12, R13,

R20, R33, R35, R36, R37, R40,

R42, R43, R50, R53
13 2 R6, R38 Resistor 0603 25 Ω R6, R38

14 6 R15, R16, R18, R26, R29, R31 Resistor 0603 500 Ω R16, R29

15 2 R17, R25 Resistor 0603 525 Ω
16 2 R19, R27 Resistor 0603 4 kΩ
17 12 R21, R28, R39, R41, R44,

R46 to R49, R52, R54, R55

18 2 T1, T2 Transformer ADT1-1WT Minicircuits
19 1 U1 AD9288 or AD92182 LQFP48
20 2 U2, U3 74LCX821
21 2 U5, U6 SN74VCX86
22 4 U7, U8, U9, U10 Resistor array CTS 47 Ω 768203470G
23 2 U11, U12 AD8138 op amp3

1

P2, P3 are implemented as one physical 80-lead connector SAMTEC TSW-140-08-L-D-RA.

2

AD9288/PCB populated with AD9288-100, AD9218-65/PCB populated with AD9218-65, AD9218-105/PCB populated with AD9218-105.

3

To use optional amp place R22, R23, R30, R24, R16, R29, remove R4, R36.

Capacitor 0603 0.1 μF

W-HOLE W-HOLE

25.602.5453.0 Wieland

connector

Samtec

L-D-RA

not placed

Resistor 0603 50 Ω R11, R22, R23,

R24, R30, R51
not placed

Resistor 0603 0 Ω R43, R50

not placed

not placed

not placed

Resistor 0603 1 kΩ

Rev. C | Page 20 of 28

AD9218

EVALUATION BOARD

The AD9218/AD9288 customer evaluation board offers an easy
way to test the AD9218 or the AD9288. The compatible pinout
of the two parts facilitates the use of one PCB for testing either
part. The PCB requires power supplies, a clock source, and a
filtered analog source for most ADC testing required.

POWER CONNECTOR

Power is supplied to the board via a detachable 12-lead power
strip. The minimum 3 V supplies required to run the board are
V

, VDL, and VDD. To allow the use of the optional amplifier

D

path, ±5 V supplies are required.

ANALOG INPUTS

Each channel has an independent analog path that uses a
wideband transformer to drive the ADC differentially from a
single-ended sine source at the input SMAs. The transformer
paths can be bypassed to allow the use of a dc-coupled path
using two AD8138 op amps with a simple board modification.
The analog input should be band-pass filtered to remove any
harmonics in the input signal and to minimize aliasing.

VOLTAGE REFERENCE

The AD9218 has an internal 1.25 V voltage reference; an
external reference for each channel can be employed instead
by connecting two external voltage references at the power
connector and setting jumpers at E18 and E19. The evaluation
board is shipped configured for internal reference mode.

CLOCKING

Each channel can be clocked by a common clock input at SMA
inputs ENCODE A and ENCODE B. The channels can also be
clocked independently by a simple board modification. The
clock input should be a low jitter sine source for maximum
performance.

DATA OUTPUTS

The data outputs are latched on board by two 10-bit latches
and drive an 8-lead connector, which is compatible with the dual­channel FIFO board that is available from Analog Devices, Inc.
This board, together with ADC analyzer software, can greatly
simplify ADC testing.

DATA FORMAT/GAIN

The DFS/GAIN pin can be biased for desired operation at the
DFS jumper located at the S1, S2 jumpers.

TIMING

Timing on each channel can be controlled, if needed, on the
PCB. Clock signals at the latches or the data ready signals that
go to the output 80-lead connector can be inverted if required.
Jumpers also allow for biasing of Pin S1 and Pin S2 for power­down and timing alignment control.

TROUBLESHOOTING

If the board does not seem to be working correctly, try the
following:

• Ver if y p o w er a t th e IC p i ns .

• Check that all jumpers are in the correct position for the

desired mode of operation.

• Ver if y t h at V

• Try running encode clock and analog inputs at low speeds

(20 MSPS/1 MHz) and monitor the LCX821 outputs, DAC
outputs, and ADC outputs for toggling.

The AD9218 evaluation board is provided as a design example
for customers of Analog Devices. Analog Devices makes no
warranties, express, statutory, or implied, regarding
merchantability or fitness for a particular purpose.

is at 1.23 V.

REF

Rev. C | Page 21 of 28

AD9218

B
B

VDL

VDL

E16

ENC

ENCX

**DUT CLOCK SELEC TABLE* *

**TO BE DI RECT OR BUF FERED**

R530ΩR50

GND

**DUT CLO CK SELEC TABLE**

**TO BE DI RECT OR BUF FERED**

U5

U6

VDL

TIEB

SN74VCX86

SN74VCX86

C25

0Ω

ENCODE B

0.1µF

ENCXA ENCA

E34

R48

DRB

0Ω

R12

GND

R13

76543

2Y

2A

2B

GND

3Y83A93B104Y114A

E36E35

R49

ENCXB

VDL

R52

1kΩ

R54

1kΩ

C42

0.1µF

R51

51Ω

J2

VDL

E12

GND

E13

R46

1kΩ

VDL

DRA

R10

0Ω

1413121110

4Y

4A

4B

VCC

1A11B21Y32A42B

R420ΩR43

0Ω

R39

1kΩ

VDL

C40

0.1µF

TIEA

J3

ENCODE A

E38

TIEA

0Ω

ENC

0.1µF

J1

TIEB

R40

0Ω

R14

50Ω

GND

H3

MTHOLE6H1MTHOLE6H2MTHOLE6H4MTHOLE6

GND

B

GND

GND

GND

(MSB) D9

C6

0.1µF

D

V

IN

REF

C24

0.1µF

A

IN

REF

C27

0.1µF

GND

B

REF

DD

C26

AV

REF

V

C19

DL

V

C18

DD

V

C17

D

C16

10µF

10µF

10µF

10µF

10µF

V

++++++

C38

10µF

+

–5V +5V V

C37

10µF

0.1µF

GND

–5V

+5V

123

0Ω

B

36Ω

AMPOUTB

0Ω

R35

C15

0.1µF

0.1µF

R7

50Ω

GND

A

REF

REF

V

V

123

DLVDD

V

GND

GND

AIN B

GND

1

234

GND

GND

E37

R55

1kΩ

1kΩ

D

V

CLKLATB

C3

0Ω

2

1

1Y

1A

1B

4B

VCC

12

13

14

GND

1kΩ

GND

GND

GND

VDL

GND

C41

0.1µF

VDL

A

D2

A

D3

A

D4

A

D5

A

D6

A

GND

C8

0.1µF

DD

V

D7

A

D8

D9A(MSB)

GND

A

ENC

D

V

C7

0.1µF

GND

A

37

D2

A

38

D3

A

D4

39

A

40

D5

A

D6

41

A

D7

42

A

D8

43

A

D9

44

GND

45

DD

V

46

A

ENC

47

D

V

48

E15

0.1µF

GND

DD

V

C4

0.1µF

D1AD0AGND

3635343332313029282726

D1AD0

GND

A

DD

V

GND

GND

DVD

V

DD

V

C1

GND

GND

DD

V

GND

GND

U1

AD9218

A

B

IN

OUT

A

A

IN

IN

A

GND

A

123456789

IN

B

REF

S1S2A

IN

101112

REF

DFS/GAIN

REF

0.1µF

D0BD1

BD1B

D0

B

IN

A

B

25

GND

GND

GND

E14

R47

1kΩ

CLKLATA

R9

0Ω

9

8

3Y

3A

3B

2Y

GND

6

7

5

GND

ENCXA

GND

E4E3

R44

1kΩ

0Ω

R33

C9

C10

0.1µF

0.1µF

R4

0Ω

GND

R1

36Ω

AMPOUTA

VDL

C11

0.1µF

R41

1kΩ

GND

C14

0.1µF

R3

50Ω

E1

E19

E17

GND

E18

GND

E20

GND

E22

E24

VREFA

E27

REFOUT

0Ω

5

34

2

GND

VD E29

GND

GND

GND

R6

25Ω

AMPOUTAB

R SINGLE- ENDED

T2

C30

0.1µF

E26

E23

VD E28

R38

25Ω

AMPOUTBB

R SINGLE- ENDED

GND

C12

E30E2

E25

VD

R5

GND

R2

36Ω

6

1

C31

0.1µF

GND

AMPINA

GND

B

0.1µF

B

B

B

B

B

B

B

B

DD

D

R37

R34

6

1

GND

TO TIE CLO CKS TOGETHER

D2

24

D3

23

D4

22

D5

21

D6

20

D7

19

D8

18

D9

17

GND

16

V

15

ENC

14

V

13

0Ω

36Ω

5

34

2

B

ENC

R20

R8

0Ω

A

J5

ENC

B

D2

B

D3

B

D4

B

D5

B

D6

B

D7

B

D8

B

GND

B

C5

GND

C39

R36

GND

GND

R32

T1

C13

AMPINB

GND

GND

R11

50Ω

AIN A

J4

GND

GND

Figure 45. PCB Schematic

02001-045

GND

DDVDVDL

V

P6P5P7

GND

4

P11

GND

4

P4

D

V

P1

Rev. C | Page 22 of 28

AD9218

GND

DRA

GND

D9P

D8P

D7P

D6P

D5P

D4P

D3P

D2P

D1P

D0P

GND

GND

GND

GND

GND

GND

GND

97531

3937353331

39373533312927252321191715

2927252321

191715

11

13

11

13

97531

P3

HEADER40

40383634323028262422201816141210864

4038363432

D9P

D8P

2019181716

201918171615141312

U9

CTS20

VALU E = 50

123456789

D9X 1

D8X 2

VDL

D9X

C21

0.1µF

GND

2423222120

Y0Y1Y2Y3Y4Y5Y6Y7Y8

VCC

D7P

D7X 3

D8X

D6P

D6X4D5X 5

D7X

D5P

D6X

3028262422

D4P

D3P

D2P

D1P

151413

12

D4X 6

D3X 7

D2X 8

D1X9D0X

D5X

D4X

D3X

D2X

1918171615

2018161412

D0P

11

11

10

10

D1X

D0X

CLKLATA

14

13

10

864

2
2

GND

GND

U2

74LCX821

OEX0X1X2X3X4X5X6X7

X8

X9 Y9

GND CL K

10

12

GND

DRB

GND

D9Q

D8Q

D7Q

D6Q

D5Q

D4Q

D3Q

D2Q

D1Q

D0Q

3937353331

39373533312927252321191715

2927252321

191715

P2

HEADER40

40383634323028262422201816141210864

4038363432

D0Q

D1Q

2019181716

201918171615141312

U10

CTS20

VALU E = 50

123456789

D0Y1D1Y 2

VDL

D0Y

C20

0.1µF

2423222120

Y0Y1Y2Y3Y4Y5Y6Y7Y8

VCC

D2Q

D2Y 3

D1Y

D3Q

D4Q

D3Y 4

D4Y 5

D2Y

D3Y

3028262422

D5Q

D6Q

D7Q

D8Q

151413

12

D5Y6D6Y 7

D7Y 8

D8Y 9

D4Y

D5Y

D6Y

D7Y

1918171615

2018161412

D9Q

11

11

10

D9Y 10

D8Y

D9Y

CLKLATB

14

13

U3

74LCX821

OEX0X1X2X3X4X5X6X7

1

X8

X9 Y9

GND CLK

GND

GND

11

13

11

13

GND

GND

97531
97531

864

10

02001-046

GND

GND

GND

2

2

GND

D9M 2

D8M 3

GND 1

D9M

D8M

D7M

2019181716

201918171615141312

U7

CTS20

VALU E = 50

123456789

1

D8A 2

D7A 3

D9A

R17

525Ω

AMPINA

OPAMP INPUT OFF PIN ONE OF TRANSFORMER

GND

R16

500Ω

D7M4D6M 5

D6M

D6A4D5A 5

+5V

D5M

AD8138

D5M 6

D4M 7

D4M

D3M

151413

D4A 6

D3A 7

R19

4kΩ

123

–IN

VOCM

+IN8

NC7V–6

D0N 2

D1N 3

D2N 4

D3N 5

D4N6D5N 7

D6N 8

D7N 9

D8N 10

D3M 8

D2M9D1M

D0M 11

GND

D2M

D1M

D0M

11

12

11

10

10

D2A 8

D1A9D0A

R18

500Ω

R21

1kΩ

GND

+5V

C32

0.1µF

GND

R22

50Ω

4

U11

V+

+OUT

C2

AMPOUTAAMPO UTAB

15pF

–OUT5

R23

50Ω

C33

0.1µF

–5V

GND

D0N

D1N

D2N

2019181716

201918171615141312

U8

CTS20

VALU E = 50

123456789

D0B1D1B 2

D2B 3

R25

525Ω

GND

AMPINB

R29

500Ω

D3N

D4N

D5N

D6N

151413

D3B 4

D4B 5

D5B6D6B 7

R26

R27

4kΩ

+5V

123

–IN

VOCM

AD8138

+IN

8NC7

D9N 11

GND 12

D7N

D8N

D9N

11

12

11

10

D7B 8

D8B 9

D9B 10

500Ω

R28

1kΩ

GND

+5V

C35

0.1µF

GND

R30

50Ω

4

V+

V–6

–5V

U12

+OUT

C36

–OUT5

C34

0.1µF

AMPOUTBBAMPOUT B

15pF

R24

50Ω

R15

500Ω

R31

500Ω

NC = NO CO NNECT

Figure 46. PCB Schematic (Continued)

Rev. C | Page 23 of 28

AD9218

Figure 47. Top Silkscreen

Figure 48. Top Routing

02001-047

02001-050

Figure 50. Split Power Plane

02001-048

02001-051

Figure 51. Bottom Routing

Figure 49. Ground Plane

02001-049

Rev. C | Page 24 of 28

Figure 52. Bottom Silkscreen

02001-052

AD9218

OUTLINE DIMENSIONS

9.20

1

12

0.50

BSC

48

13

9.00 SQ

8.80

PIN 1

TOP VIEW

(PINS DO WN)

37

36

7.20

7.00 SQ

6.80

25

24

0.27

0.22

0.17

051706-A

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0.75

0.60

0.45

0.20

0.09
7°

3.5°
0°

0.08
COPLANARIT Y

COMPLIANT TO JEDEC STANDARDS MS-026-BBC

1.60
MAX

VIEW A

LEAD PITCH

Figure 53. 48-Lead Low Profile Quad Flat Package [LQFP]

(ST-48)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9218BST-40 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BST-RL40 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BSTZ-40 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BSTZ-RL40 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BST-65 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BST-RL65 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BSTZ-65 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BSTZ-RL65 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BST-80 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BST-RL80 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BSTZ-80 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BSTZ-RL80 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BST-105 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BST-RL105 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BSTZ-105 –40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218BSTZ-RL105 −40°C to +85°C 48-Lead Low Profile Quad Flat Pack (LQFP) ST-48
AD9218-65PCB Evaluation Board (Supports -40/-65 Grade)
AD9218-105PCB Evaluation Board (Supports -80/-105 Grade)

1

Z = Pb-free part.

1

1

1

1

1

1

1

1

Rev. C | Page 25 of 28

AD9218

NOTES

Rev. C | Page 26 of 28

AD9218

NOTES

Rev. C | Page 27 of 28

AD9218

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02001-0-12/06(C)

Rev. C | Page 28 of 28