Analog Devices AD9216 Datasheet

10-Bit, 105 MSPS

FEATURES

Integrated dual 10-bit ADC Single 3 V supply operation (2.85 V to 3.15 V) SNR = 57 dBc (to Nyquist, AD9216-105) SFDR = 75 dBc (to Nyquist, AD9216-105) Low power: 300 mW at 105 MSPS Differential input with 300 MHz 3 dB bandwidth Exceptional crosstalk immunity > 80 dB Offset binary or twos complement data format Clock duty cycle stabilizer

APPLICATIONS

Ultrasound equipment IF sampling in communications receivers

3G, radio point-to-point, LMDS, MMDS Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes

GENERAL DESCRIPTION

The AD9216 is a dual, 3 V, 10-bit, 105 MSPS analog-to-digital converter (ADC). It features dual high performance sample-and hold amplifiers (SHAs) and an integrated voltage reference. The AD9216 uses a multistage differential pipelined architecture with output error correction logic to provide 10-bit accuracy and guarantee no missing codes over the full operating temperature range at up to 105 MSPS data rates. The wide bandwidth, differential SHA allows for a variety of userselectable input ranges and offsets, including single-ended applications. The AD9216 is suitable for various applications, including multiplexed systems that switch full-scale voltage levels in successive channels and for sampling inputs at frequencies well beyond the Nyquist rate.

Dual A/D Converter

AD9216

FUNCTIONAL BLOCK DIAGRAM

AVDD AGND

VIN+_A

VIN–_A

REFT_A

REFB_A

VREF

SENSE

AGND

REFT_B

REFB_B

VIN+_B

VIN–_B

SHA

0.5V

SHA

AD9216

ADC

DRVDD

Figure 1.

10

OUTPUT

BUFFERS

CLOCK

DUTY CYCLE

STABILIZER

CONTROL

10

OUTPUT

BUFFERS

DRGND

Fabricated on an advanced CMOS process, the AD9216 is available in a space saving, Pb-free, 64-lead LFCSP (9 mm × 9 mm) and is specified over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. Pin compatible with AD9238, dual 12-bit 20 MSPS/40 MSPS/

65 MSPS ADC and AD9248, dual 14-bit 20 MSPS/40 MSPS/ 65 MSPS ADC.

2. 105 MSPS capability allows for demanding high frequency

applications.

MUX/

MODE

MUX/

10

D9_A–D0_A OEB_A

MUX_SELECT CLK_A CLK_B DCS

SHARED_REF PWDN_A PWDN_B DFS

D9_B–D0_B OEB_B

04775-001

Dual single-ended clock inputs are used to control all internal conversion cycles. A duty cycle stabilizer is available on the AD9216 and can compensate for wide variations in the clock duty cycle, allowing the converters to maintain excellent performance. The digital output data is presented in either straight binary or twos complement format.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

3. Low power consumption: AD9216-105: 105 MSPS = 300 mW.

4. The patented SHA input maintains excellent performance for

input frequencies up to 200 MHz and can be configured for single-ended or differential operation.

5. Typical channel crosstalk of > 80 dB @ f

up to 70 MHz.

IN

6. The clock duty cycle stabilizer maintains performance over a

wide range of clock duty cycles.

www.analog.com

AD9216

DC SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 1.

Parameter Temp Test Level Min Typ Max Unit RESOLUTION Full VI 10 Bits ACCURACY

No Missing Codes Full VI Guaranteed

Offset Error Full VI −3.6 ±0.7 +3.6 % FSR

Gain Error

Differential Nonlinearity (DNL)

25°C I −0.65 ±0.5 +1.0 LSB

Integral Nonlinearity (INL)2 Full V −2.8 ±1.0 +2.8 LSB 25°C I −1.8 ±1.0 +1.8 LSB TEMPERATURE DRIFT

Offset Error Full V ±10 µV/°C

Gain Error1 Full V ±75 ppm/°C

Reference Voltage Full V ±15 ppm/°C INTERNAL VOLTAGE REFERENCE

Output Voltage Error Full VI ±2 ±35 mV

Load Regulation @ 1.0 mA 25°C V 1.0 mV INPUT REFERRED NOISE

Input Span = 2.0 V 25°C V 0.5 LSB rms ANALOG INPUT

Input Span, VREF = 1.0 V Full IV 2 V p-p

Input Capacitance REFERENCE INPUT RESISTANCE Full V 7 kΩ POWER SUPPLIES

Supply Voltages

Supply Current

PSRR Full V ±0.1 % FSR POWER CONSUMPTION

P

AVDD

P

DRVDD

Standby Power MATCHING CHARACTERISTICS

Offset Matching Error

Gain Matching Error (Shared Reference Mode) 25°C I −0.6 ±0.1 +0.6 % FSR

Gain Matching Error (Nonshared Reference Mode) 25°C I −1.6 ±0.3 +1.6 % FSR

1

Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).

2

Measured with low frequency ramp at maximum clock rate.

3

Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure for the equivalent analog input structure. 24

4

Measured with low frequency analog input at maximum clock rate with approximately 5 pF loading on each output bit.

5

Standby power is measured with the CLK_A and CLK_B pins inactive (i.e., set to AVDD or AGND).

6

Shared reference mode or nonshared reference mode.

, DCS enabled, unless otherwise noted.

MAX

AD9216BCPZ-105

1

2

3

25°C VI −1.6 ±0.7 +1.6 % FSR Full V −1.0 ±0.5 +1.66 LSB

Full V 2 pF

AVDD Full IV 2.85 3.0 3.15 V DRVDD Full IV 2.85 3.0 3.15 V

4

IAVDD

Full VI 100 110 mA

IDRVDD4 Full VI 24 mA

4

5

6

25°C I 300 330 mW 25°C V 72 mW 25°C V 3.0 mW

25°C I −6.0 ±1.0 +6.0 % FSR

Rev. 0 | Page 3 of 36

AD9216

AC SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 2.

Parameter Temp Test Level Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR)

f

INPUT

25°C I 56.6 57.8 dB f

INPUT

25°C I 56.4 57.6 dB f

INPUT

f

INPUT

SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)

f

INPUT

25°C I 56.5 57.7 dB f

INPUT

25°C I 56.1 57.4 dB f

INPUT

f

INPUT

EFFECTIVE NUMBER OF BITS (ENOB)

f

INPUT

25°C I 9.2 9.4 Bits f

INPUT

25°C I 9.1 9.3 Bits f

INPUT

f

INPUT

WORST HARMONIC (SECOND OR THIRD)

f

INPUT

25°C I −76.0 −68.0 dBc f

INPUT

25°C I −74.0 −65.0 dBc f

INPUT

f

INPUT

WORST OTHER (EXCLUDING SECOND OR THIRD) f

INPUT

25°C I −75.0 −66.0 dBc f

INPUT

25°C I −75.0 −63.0 dBc f

INPUT

f

INPUT

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f

INPUT

25°C I 66.0 75.0 dBc f

INPUT

25°C I 63.0 74.0 dBc f

INPUT

f

INPUT

, DCS enabled, unless otherwise noted.

MAX

AD9216BCPZ-105

= 2.4 MHz Full IV 55.0 57.8 dB

= 50 MHz Full IV 54.8 57.6 dB

= 69 MHz 25°C V 57.4 dB = 100 MHz 25°C V 57.3 dB

= 2.4 MHz Full IV 54.9 57.7 dB

= 50 MHz Full IV 54.3 57.4 dB

= 69 MHz 25°C V 56.8 dB = 100 MHz 25°C V 56.7 dB

= 2.4 MHz Full IV 8.9 9.4 Bits

= 50 MHz Full IV 8.8 9.3 Bits

= 69 MHz 25°C V 9.2 Bits = 100 MHz 25°C V 9.2 Bits

= 2.4 MHz Full IV −76.0 −64.6 dBc

= 50 MHz Full IV −74.0 −58.4 dBc

= 69 MHz 25°C V −74.0 dBc = 100 MHz 25°C V −74.0 dBc

= 2.4 MHz Full IV −75.0 −65.0 dBc

= 50 MHz Full IV −75.0 −62.0 dBc

= 69 MHz 25°C V −77.0 dBc = 100 MHz 25°C V −77.0 dBc

= 2.4 MHz Full IV 64.6 75.0 dBc

= 50 MHz Full IV 58.4 74.0 dBc

= 69 MHz 25°C V 74.0 dBc = 100 MHz 25°C V 74.0 dBc

Rev. 0 | Page 4 of 36

AD9216

AD9216BCPZ-105

Parameter Temp Test Level Min Typ Max Unit

TWO-TONE SFDR (AIN = −7 dBFS)

f

= 69.1 MHz, f

IN1

f

= 100.1 MHz, f

IN1

= 70.1 MHz 25°C V 70 dBc

IN2

= 101.1 MHz 25°C V 69 dBc

IN2

ANALOG BANDWIDTH 25°C V 300 MHz CROSSTALK 25°C V −80.0 dB

Rev. 0 | Page 5 of 36

AD9216

LOGIC SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 3.

Parameter Temp Test Level Min Typ Max Unit LOGIC INPUTS

High Level Input Voltage Full IV 2.0 V Low Level Input Voltage Full IV 0.8 V High Level Input Current Full IV −10 +10 µA Low Level Input Current Full IV −10 +10 µA Input Capacitance Full IV 2 pF

LOGIC OUTPUTS

DRVDD = 3.0 V

1

Output voltage levels measured with 5 pF load on each output.

, DCS enabled, unless otherwise noted.

MAX

AD9216BCPZ-105

1

High Level Output Voltage Full IV 2.95 V Low Level Output Voltage Full IV 0.05 V

Rev. 0 | Page 6 of 36

AD9216

SWITCHING SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 4.

Parameter Temp Test Level Min Typ Max Unit SWITCHING PERFORMANCE

Maximum Conversion Rate Full VI 105 MSPS

Minimum Conversion Rate Full V 10 MSPS

CLK Period Full V 9.5 ns OUTPUT PARAMETERS

Output Propagation Delay2 (tPD) 25°C I 3.75 4.6 ns

Valid Time3 (tV) 25°C I 2.0

Output Rise Time (10% to 90%) 25°C V 1.0 ns

Output Fall Time (10% to 90%) 25°C V 1.0 ns

Output Enable Time

Output Disable Time4 25°C V 1 Cycle

Pipeline Delay (Latency) Full V 6 Cycles APERTURE

Aperture Delay (tA) Full V 1.5 ns

Aperture Uncertainty (tJ) Full V 0.5 ps rms

Wake-Up Time OUT-OF-RANGE RECOVERY TIME Full V 1 Cycle

1

C

LOAD

2

Output delay is measured from clock 50% transition to data 50% transition.

3

Valid time is approximately equal to the minimum output propagation delay.

4

Output enable time is OEB_A, OEB_B falling to respective channel outputs coming out of high impedance. Output disable time is OEB_A, OEB_B rising to respective

channel outputs going into high impedance.

5

Wake-up time is dependent on value of decoupling capacitors; typical values shown for 0.1 µF and 10 µF capacitors on REFT and REFB.

, DCS enabled, unless otherwise noted.

MAX

1

4

5

equals 5 pF maximum for all output switching parameters.

AD9216BCPZ-105

25°C V 1 Cycle

Full V 7 ms

Rev. 0 | Page 7 of 36

AD9216

TIMING DIAGRAM

ANALOG

INPUT

CLK

N–1

N+1

N

t

A

N+2

N+3

N+4

N+5

N+8

N+7

N+6

DATA

OUT

N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1

t

PD

04775-002

Figure 2.

Rev. 0 | Page 8 of 36

AD9216

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating Pin Name With Respect To Min Max Unit

ELECTRICAL

ENVIRONMENTAL

1

2

1

AVDD AGND −0.3 +3.9 V

DRVDD DRGND −0.3 +3.9 V

AGND DRGND −0.3 +0.3 V

AVDD DRVDD −3.9 +3.9 V

Digital Outputs CLK, DCS, MUX_SELECT, SHARED_REF DRGND −0.3 DRVDD + 0.3 V

OEB, DFS AGND −0.3 AVDD + 0.3 V

VINA, VINB AGND −0.3 AVDD + 0.3 V

VREF AGND −0.3 AVDD + 0.3 V

SENSE AGND −0.3 AVDD + 0.3 V

REFB, REFT AGND −0.3 AVDD + 0.3 V

PDWN AGND −0.3 AVDD + 0.3 V

2

Operating Temperature −45 +85 °C

Junction Temperature 150 °C

Lead Temperature (10 sec) 300 °C

Storage Temperature −65 +150 °C

Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is

not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.

Typical thermal impedances (64-lead LFCSP); θ

EIA/JESD51-7.

= 26.4°C/W. These measurements were taken on a 4-layer board (with thermal via array) in still air, in accordance with

JA

EXPLANATION OF TEST LEVELS

Table 6.

Test Level Description

I 100% production tested. II 100% production tested at 25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI

100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 9 of 36

AD9216

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD

CLK_A

SHARED_REF

MUX_SELECT

PDWN_A

OEB_A

DNC

D9_A (MSB)

D8_A

D7_A

D6_A

DRGND

DRVDD

D5_A

D4_A

AGND VIN+_A VIN–_A

AGND

AVDD REFT_A REFB_

VREF

SENSE REFB_B REFT_B

AVDD

AGND VIN–_B VIN+_B

AGND

646362616059585756555453525150

PIN 1

1

INDICATOR

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

AD9216

TOP VIEW

(Not to Scale)

D3_A 49

D2_A

48

D1_A

47

D0_A (LSB)

46

DNC

45

DNC

44

DNC

43

DNC

42

DRVDD

41

DRGND

40

DNC

39

D9_B (MSB)

38

D8_B

37

D7_B

36

D6_B

35

D5_B

34

D4_B

33

DNC = DO NOT CONNECT

171819202122232425262728293031

DFS

DCS

DNC

AVDD

CLK_B

PDWN_B

OEB_B

DNC

D0_B (LSB)

DRVDD

DRGND

D1_B

D2_B

32

D3_B

04775-003

Figure 3. Pin Configuration

Rev. 0 | Page 10 of 36

AD9216

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1, 4, 13, 16 AGND Analog Ground. 2 VIN+_A Analog Input Pin (+) for Channel A. 3 VIN−_A Analog Input Pin (−) for Channel A. 5, 12, 17, 64 AVDD Analog Power Supply. 6 REFT_A Differential Reference (+) for Channel A. 7 REFB_A Differential Reference (−) for Channel A. 8 VREF Voltage Reference Input/Output. 9 SENSE Reference Mode Selection. 10 REFB_B Differential Reference (−) for Channel B. 11 REFT_B Differential Reference (+) for Channel B. 14 VIN−_B Analog Input Pin (−) for Channel B. 15 VIN+_B Analog Input Pin (+) for Channel B. 18 CLK_B Clock Input Pin for Channel B. 19 DCS Duty Cycle Stabilizer (DCS) Mode Pin (Active High). 20 DFS Data Output Format Select Pin (Low for Offset Binary, High for Twos Complement). 21 PDWN_B Power-Down Function Selection for Channel B (Active High). 22 OEB_B

23 to 26, 39, 42 to 45, 58

27, 30 to 38

28, 40, 53 DRGND Digital Output Ground. 29, 41, 52 DRVDD

46 to 51, 54 to 57

59 OEB_A

60 PDWN_A Power-Down Function Selection for Channel A (Active High). 61 MUX_SELECT Data Multiplexed Mode. (See Data Format section for how to enable). 62 SHARED_REF Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared Reference Mode). 63 CLK_A Clock Input Pin for Channel A.

DNC Do Not Connect Pins. Should be left floating.

D0_B (LSB) to D9_B (MSB)

D0_A (LSB) to D9_A (MSB)

Output Enable for Channel B (Low Setting Enables Channel B Output Data Bus). Outputs are high impedance when OEB_B is set high.

Channel B Data Output Bits.

Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor. Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF.

Channel A Data Output Bits.

Output Enable for Channel A (Low Setting Enables Channel A Output Data Bus). Outputs are high impedance when OEB_A is set high.

Rev. 0 | Page 11 of 36

Analog Devices AD9216 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

DC SPECIFICATIONS

AC SPECIFICATIONS

LOGIC SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING DIAGRAM

ABSOLUTE MAXIMUM RATINGS

EXPLANATION OF TEST LEVELS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS